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radeon_legacy_encoders.c
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1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  * Alex Deucher
25  */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 #include "atom.h"
31 #include <linux/backlight.h>
32 #ifdef CONFIG_PMAC_BACKLIGHT
33 #include <asm/backlight.h>
34 #endif
35 
36 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
37 {
38  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
39  struct drm_encoder_helper_funcs *encoder_funcs;
40 
41  encoder_funcs = encoder->helper_private;
42  encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
43  radeon_encoder->active_device = 0;
44 }
45 
46 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
47 {
48  struct drm_device *dev = encoder->dev;
49  struct radeon_device *rdev = dev->dev_private;
50  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
51  uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
52  int panel_pwr_delay = 2000;
53  bool is_mac = false;
54  uint8_t backlight_level;
55  DRM_DEBUG_KMS("\n");
56 
57  lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
58  backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
59 
60  if (radeon_encoder->enc_priv) {
61  if (rdev->is_atom_bios) {
62  struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
63  panel_pwr_delay = lvds->panel_pwr_delay;
64  if (lvds->bl_dev)
65  backlight_level = lvds->backlight_level;
66  } else {
67  struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
68  panel_pwr_delay = lvds->panel_pwr_delay;
69  if (lvds->bl_dev)
70  backlight_level = lvds->backlight_level;
71  }
72  }
73 
74  /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
75  * Taken from radeonfb.
76  */
77  if ((rdev->mode_info.connector_table == CT_IBOOK) ||
78  (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
79  (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
80  (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
81  is_mac = true;
82 
83  switch (mode) {
84  case DRM_MODE_DPMS_ON:
85  disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
86  disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
87  WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
88  lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
89  lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
90  WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
91  mdelay(1);
92 
93  lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
94  lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
95  WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
96 
97  lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
98  RADEON_LVDS_BL_MOD_LEVEL_MASK);
99  lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
100  RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
101  (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
102  if (is_mac)
103  lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
104  mdelay(panel_pwr_delay);
105  WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106  break;
107  case DRM_MODE_DPMS_STANDBY:
108  case DRM_MODE_DPMS_SUSPEND:
109  case DRM_MODE_DPMS_OFF:
110  pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
111  WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
112  lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
113  if (is_mac) {
114  lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
115  WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
116  lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
117  } else {
118  WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
119  lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
120  }
121  mdelay(panel_pwr_delay);
122  WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
123  WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
124  mdelay(panel_pwr_delay);
125  break;
126  }
127 
128  if (rdev->is_atom_bios)
129  radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
130  else
131  radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
132 
133 }
134 
135 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
136 {
137  struct radeon_device *rdev = encoder->dev->dev_private;
138  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
139  DRM_DEBUG("\n");
140 
141  if (radeon_encoder->enc_priv) {
142  if (rdev->is_atom_bios) {
143  struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
144  lvds->dpms_mode = mode;
145  } else {
146  struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
147  lvds->dpms_mode = mode;
148  }
149  }
150 
151  radeon_legacy_lvds_update(encoder, mode);
152 }
153 
154 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
155 {
156  struct radeon_device *rdev = encoder->dev->dev_private;
157 
158  if (rdev->is_atom_bios)
159  radeon_atom_output_lock(encoder, true);
160  else
161  radeon_combios_output_lock(encoder, true);
162  radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
163 }
164 
165 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
166 {
167  struct radeon_device *rdev = encoder->dev->dev_private;
168 
169  radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
170  if (rdev->is_atom_bios)
171  radeon_atom_output_lock(encoder, false);
172  else
173  radeon_combios_output_lock(encoder, false);
174 }
175 
176 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
177  struct drm_display_mode *mode,
178  struct drm_display_mode *adjusted_mode)
179 {
180  struct drm_device *dev = encoder->dev;
181  struct radeon_device *rdev = dev->dev_private;
182  struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
183  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
184  uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
185 
186  DRM_DEBUG_KMS("\n");
187 
188  lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
189  lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
190 
191  lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
192  if (rdev->is_atom_bios) {
193  /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
194  * need to call that on resume to set up the reg properly.
195  */
196  radeon_encoder->pixel_clock = adjusted_mode->clock;
197  atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
198  lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
199  } else {
200  struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
201  if (lvds) {
202  DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
203  lvds_gen_cntl = lvds->lvds_gen_cntl;
204  lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
205  (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
206  lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
207  (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
208  } else
209  lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
210  }
211  lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
212  lvds_gen_cntl &= ~(RADEON_LVDS_ON |
213  RADEON_LVDS_BLON |
214  RADEON_LVDS_EN |
215  RADEON_LVDS_RST_FM);
216 
217  if (ASIC_IS_R300(rdev))
218  lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
219 
220  if (radeon_crtc->crtc_id == 0) {
221  if (ASIC_IS_R300(rdev)) {
222  if (radeon_encoder->rmx_type != RMX_OFF)
223  lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
224  } else
225  lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
226  } else {
227  if (ASIC_IS_R300(rdev))
228  lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
229  else
230  lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
231  }
232 
233  WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
234  WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
235  WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
236 
237  if (rdev->family == CHIP_RV410)
238  WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
239 
240  if (rdev->is_atom_bios)
241  radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
242  else
243  radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
244 }
245 
246 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
247  const struct drm_display_mode *mode,
248  struct drm_display_mode *adjusted_mode)
249 {
250  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
251 
252  /* set the active encoder to connector routing */
253  radeon_encoder_set_active_device(encoder);
254  drm_mode_set_crtcinfo(adjusted_mode, 0);
255 
256  /* get the native mode for LVDS */
257  if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
258  radeon_panel_mode_fixup(encoder, adjusted_mode);
259 
260  return true;
261 }
262 
263 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
264  .dpms = radeon_legacy_lvds_dpms,
265  .mode_fixup = radeon_legacy_mode_fixup,
266  .prepare = radeon_legacy_lvds_prepare,
267  .mode_set = radeon_legacy_lvds_mode_set,
268  .commit = radeon_legacy_lvds_commit,
269  .disable = radeon_legacy_encoder_disable,
270 };
271 
272 u8
273 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
274 {
275  struct drm_device *dev = radeon_encoder->base.dev;
276  struct radeon_device *rdev = dev->dev_private;
277  u8 backlight_level;
278 
279  backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
280  RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
281 
282  return backlight_level;
283 }
284 
285 void
286 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
287 {
288  struct drm_device *dev = radeon_encoder->base.dev;
289  struct radeon_device *rdev = dev->dev_private;
290  int dpms_mode = DRM_MODE_DPMS_ON;
291 
292  if (radeon_encoder->enc_priv) {
293  if (rdev->is_atom_bios) {
294  struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
295  if (lvds->backlight_level > 0)
296  dpms_mode = lvds->dpms_mode;
297  else
298  dpms_mode = DRM_MODE_DPMS_OFF;
299  lvds->backlight_level = level;
300  } else {
301  struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
302  if (lvds->backlight_level > 0)
303  dpms_mode = lvds->dpms_mode;
304  else
305  dpms_mode = DRM_MODE_DPMS_OFF;
306  lvds->backlight_level = level;
307  }
308  }
309 
310  radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
311 }
312 
313 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
314 
315 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
316 {
317  struct radeon_backlight_privdata *pdata = bl_get_data(bd);
318  uint8_t level;
319 
320  /* Convert brightness to hardware level */
321  if (bd->props.brightness < 0)
322  level = 0;
323  else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
324  level = RADEON_MAX_BL_LEVEL;
325  else
326  level = bd->props.brightness;
327 
328  if (pdata->negative)
329  level = RADEON_MAX_BL_LEVEL - level;
330 
331  return level;
332 }
333 
334 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
335 {
336  struct radeon_backlight_privdata *pdata = bl_get_data(bd);
337  struct radeon_encoder *radeon_encoder = pdata->encoder;
338 
339  radeon_legacy_set_backlight_level(radeon_encoder,
340  radeon_legacy_lvds_level(bd));
341 
342  return 0;
343 }
344 
345 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
346 {
347  struct radeon_backlight_privdata *pdata = bl_get_data(bd);
348  struct radeon_encoder *radeon_encoder = pdata->encoder;
349  struct drm_device *dev = radeon_encoder->base.dev;
350  struct radeon_device *rdev = dev->dev_private;
351  uint8_t backlight_level;
352 
353  backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
354  RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
355 
356  return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
357 }
358 
359 static const struct backlight_ops radeon_backlight_ops = {
360  .get_brightness = radeon_legacy_backlight_get_brightness,
361  .update_status = radeon_legacy_backlight_update_status,
362 };
363 
364 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
365  struct drm_connector *drm_connector)
366 {
367  struct drm_device *dev = radeon_encoder->base.dev;
368  struct radeon_device *rdev = dev->dev_private;
369  struct backlight_device *bd;
370  struct backlight_properties props;
371  struct radeon_backlight_privdata *pdata;
372  uint8_t backlight_level;
373  char bl_name[16];
374 
375  if (!radeon_encoder->enc_priv)
376  return;
377 
378 #ifdef CONFIG_PMAC_BACKLIGHT
379  if (!pmac_has_backlight_type("ati") &&
380  !pmac_has_backlight_type("mnca"))
381  return;
382 #endif
383 
384  pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
385  if (!pdata) {
386  DRM_ERROR("Memory allocation failed\n");
387  goto error;
388  }
389 
390  memset(&props, 0, sizeof(props));
391  props.max_brightness = RADEON_MAX_BL_LEVEL;
392  props.type = BACKLIGHT_RAW;
393  snprintf(bl_name, sizeof(bl_name),
394  "radeon_bl%d", dev->primary->index);
395  bd = backlight_device_register(bl_name, &drm_connector->kdev,
396  pdata, &radeon_backlight_ops, &props);
397  if (IS_ERR(bd)) {
398  DRM_ERROR("Backlight registration failed\n");
399  goto error;
400  }
401 
402  pdata->encoder = radeon_encoder;
403 
404  backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
405  RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
406 
407  /* First, try to detect backlight level sense based on the assumption
408  * that firmware set it up at full brightness
409  */
410  if (backlight_level == 0)
411  pdata->negative = true;
412  else if (backlight_level == 0xff)
413  pdata->negative = false;
414  else {
415  /* XXX hack... maybe some day we can figure out in what direction
416  * backlight should work on a given panel?
417  */
418  pdata->negative = (rdev->family != CHIP_RV200 &&
419  rdev->family != CHIP_RV250 &&
420  rdev->family != CHIP_RV280 &&
421  rdev->family != CHIP_RV350);
422 
423 #ifdef CONFIG_PMAC_BACKLIGHT
424  pdata->negative = (pdata->negative ||
425  of_machine_is_compatible("PowerBook4,3") ||
426  of_machine_is_compatible("PowerBook6,3") ||
427  of_machine_is_compatible("PowerBook6,5"));
428 #endif
429  }
430 
431  if (rdev->is_atom_bios) {
432  struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
433  lvds->bl_dev = bd;
434  } else {
435  struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
436  lvds->bl_dev = bd;
437  }
438 
439  bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
440  bd->props.power = FB_BLANK_UNBLANK;
441  backlight_update_status(bd);
442 
443  DRM_INFO("radeon legacy LVDS backlight initialized\n");
444 
445  return;
446 
447 error:
448  kfree(pdata);
449  return;
450 }
451 
452 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
453 {
454  struct drm_device *dev = radeon_encoder->base.dev;
455  struct radeon_device *rdev = dev->dev_private;
456  struct backlight_device *bd = NULL;
457 
458  if (!radeon_encoder->enc_priv)
459  return;
460 
461  if (rdev->is_atom_bios) {
462  struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
463  bd = lvds->bl_dev;
464  lvds->bl_dev = NULL;
465  } else {
466  struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
467  bd = lvds->bl_dev;
468  lvds->bl_dev = NULL;
469  }
470 
471  if (bd) {
472  struct radeon_backlight_privdata *pdata;
473 
474  pdata = bl_get_data(bd);
475  backlight_device_unregister(bd);
476  kfree(pdata);
477 
478  DRM_INFO("radeon legacy LVDS backlight unloaded\n");
479  }
480 }
481 
482 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
483 
484 void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
485 {
486 }
487 
488 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
489 {
490 }
491 
492 #endif
493 
494 
495 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
496 {
497  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
498 
499  if (radeon_encoder->enc_priv) {
500  radeon_legacy_backlight_exit(radeon_encoder);
501  kfree(radeon_encoder->enc_priv);
502  }
503  drm_encoder_cleanup(encoder);
504  kfree(radeon_encoder);
505 }
506 
507 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
508  .destroy = radeon_lvds_enc_destroy,
509 };
510 
511 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
512 {
513  struct drm_device *dev = encoder->dev;
514  struct radeon_device *rdev = dev->dev_private;
515  uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
516  uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
517  uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
518 
519  DRM_DEBUG_KMS("\n");
520 
521  switch (mode) {
522  case DRM_MODE_DPMS_ON:
523  crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
524  dac_cntl &= ~RADEON_DAC_PDWN;
525  dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
526  RADEON_DAC_PDWN_G |
527  RADEON_DAC_PDWN_B);
528  break;
529  case DRM_MODE_DPMS_STANDBY:
530  case DRM_MODE_DPMS_SUSPEND:
531  case DRM_MODE_DPMS_OFF:
532  crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
533  dac_cntl |= RADEON_DAC_PDWN;
534  dac_macro_cntl |= (RADEON_DAC_PDWN_R |
535  RADEON_DAC_PDWN_G |
536  RADEON_DAC_PDWN_B);
537  break;
538  }
539 
540  /* handled in radeon_crtc_dpms() */
541  if (!(rdev->flags & RADEON_SINGLE_CRTC))
542  WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
543  WREG32(RADEON_DAC_CNTL, dac_cntl);
544  WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
545 
546  if (rdev->is_atom_bios)
547  radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
548  else
549  radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
550 
551 }
552 
553 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
554 {
555  struct radeon_device *rdev = encoder->dev->dev_private;
556 
557  if (rdev->is_atom_bios)
558  radeon_atom_output_lock(encoder, true);
559  else
560  radeon_combios_output_lock(encoder, true);
561  radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
562 }
563 
564 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
565 {
566  struct radeon_device *rdev = encoder->dev->dev_private;
567 
568  radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
569 
570  if (rdev->is_atom_bios)
571  radeon_atom_output_lock(encoder, false);
572  else
573  radeon_combios_output_lock(encoder, false);
574 }
575 
576 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
577  struct drm_display_mode *mode,
578  struct drm_display_mode *adjusted_mode)
579 {
580  struct drm_device *dev = encoder->dev;
581  struct radeon_device *rdev = dev->dev_private;
582  struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
583  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
584  uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
585 
586  DRM_DEBUG_KMS("\n");
587 
588  if (radeon_crtc->crtc_id == 0) {
589  if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
590  disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
591  ~(RADEON_DISP_DAC_SOURCE_MASK);
592  WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
593  } else {
594  dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
595  WREG32(RADEON_DAC_CNTL2, dac2_cntl);
596  }
597  } else {
598  if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
599  disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
600  ~(RADEON_DISP_DAC_SOURCE_MASK);
601  disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
602  WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
603  } else {
604  dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
605  WREG32(RADEON_DAC_CNTL2, dac2_cntl);
606  }
607  }
608 
609  dac_cntl = (RADEON_DAC_MASK_ALL |
610  RADEON_DAC_VGA_ADR_EN |
611  /* TODO 6-bits */
612  RADEON_DAC_8BIT_EN);
613 
614  WREG32_P(RADEON_DAC_CNTL,
615  dac_cntl,
616  RADEON_DAC_RANGE_CNTL |
617  RADEON_DAC_BLANKING);
618 
619  if (radeon_encoder->enc_priv) {
620  struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
621  dac_macro_cntl = p_dac->ps2_pdac_adj;
622  } else
623  dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
624  dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
625  WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
626 
627  if (rdev->is_atom_bios)
628  radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
629  else
630  radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
631 }
632 
633 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
634  struct drm_connector *connector)
635 {
636  struct drm_device *dev = encoder->dev;
637  struct radeon_device *rdev = dev->dev_private;
638  uint32_t vclk_ecp_cntl, crtc_ext_cntl;
639  uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
640  enum drm_connector_status found = connector_status_disconnected;
641  bool color = true;
642 
643  /* save the regs we need */
644  vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
645  crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
646  dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
647  dac_cntl = RREG32(RADEON_DAC_CNTL);
648  dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
649 
650  tmp = vclk_ecp_cntl &
651  ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
652  WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
653 
654  tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
655  WREG32(RADEON_CRTC_EXT_CNTL, tmp);
656 
657  tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
658  RADEON_DAC_FORCE_DATA_EN;
659 
660  if (color)
661  tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
662  else
663  tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
664 
665  if (ASIC_IS_R300(rdev))
666  tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
667  else if (ASIC_IS_RV100(rdev))
668  tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
669  else
670  tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
671 
672  WREG32(RADEON_DAC_EXT_CNTL, tmp);
673 
674  tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
675  tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
676  WREG32(RADEON_DAC_CNTL, tmp);
677 
678  tmp = dac_macro_cntl;
679  tmp &= ~(RADEON_DAC_PDWN_R |
680  RADEON_DAC_PDWN_G |
681  RADEON_DAC_PDWN_B);
682 
683  WREG32(RADEON_DAC_MACRO_CNTL, tmp);
684 
685  mdelay(2);
686 
687  if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
688  found = connector_status_connected;
689 
690  /* restore the regs we used */
691  WREG32(RADEON_DAC_CNTL, dac_cntl);
692  WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
693  WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
694  WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
695  WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
696 
697  return found;
698 }
699 
700 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
701  .dpms = radeon_legacy_primary_dac_dpms,
702  .mode_fixup = radeon_legacy_mode_fixup,
703  .prepare = radeon_legacy_primary_dac_prepare,
704  .mode_set = radeon_legacy_primary_dac_mode_set,
705  .commit = radeon_legacy_primary_dac_commit,
706  .detect = radeon_legacy_primary_dac_detect,
707  .disable = radeon_legacy_encoder_disable,
708 };
709 
710 
711 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
712  .destroy = radeon_enc_destroy,
713 };
714 
715 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
716 {
717  struct drm_device *dev = encoder->dev;
718  struct radeon_device *rdev = dev->dev_private;
719  uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
720  DRM_DEBUG_KMS("\n");
721 
722  switch (mode) {
723  case DRM_MODE_DPMS_ON:
724  fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
725  break;
726  case DRM_MODE_DPMS_STANDBY:
727  case DRM_MODE_DPMS_SUSPEND:
728  case DRM_MODE_DPMS_OFF:
729  fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
730  break;
731  }
732 
733  WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
734 
735  if (rdev->is_atom_bios)
736  radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
737  else
738  radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
739 
740 }
741 
742 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
743 {
744  struct radeon_device *rdev = encoder->dev->dev_private;
745 
746  if (rdev->is_atom_bios)
747  radeon_atom_output_lock(encoder, true);
748  else
749  radeon_combios_output_lock(encoder, true);
750  radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
751 }
752 
753 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
754 {
755  struct radeon_device *rdev = encoder->dev->dev_private;
756 
757  radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
758 
759  if (rdev->is_atom_bios)
760  radeon_atom_output_lock(encoder, true);
761  else
762  radeon_combios_output_lock(encoder, true);
763 }
764 
765 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
766  struct drm_display_mode *mode,
767  struct drm_display_mode *adjusted_mode)
768 {
769  struct drm_device *dev = encoder->dev;
770  struct radeon_device *rdev = dev->dev_private;
771  struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
772  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
773  uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
774  int i;
775 
776  DRM_DEBUG_KMS("\n");
777 
778  tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
779  tmp &= 0xfffff;
780  if (rdev->family == CHIP_RV280) {
781  /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
782  tmp ^= (1 << 22);
783  tmds_pll_cntl ^= (1 << 22);
784  }
785 
786  if (radeon_encoder->enc_priv) {
787  struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
788 
789  for (i = 0; i < 4; i++) {
790  if (tmds->tmds_pll[i].freq == 0)
791  break;
792  if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
793  tmp = tmds->tmds_pll[i].value ;
794  break;
795  }
796  }
797  }
798 
799  if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
800  if (tmp & 0xfff00000)
801  tmds_pll_cntl = tmp;
802  else {
803  tmds_pll_cntl &= 0xfff00000;
804  tmds_pll_cntl |= tmp;
805  }
806  } else
807  tmds_pll_cntl = tmp;
808 
809  tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
810  ~(RADEON_TMDS_TRANSMITTER_PLLRST);
811 
812  if (rdev->family == CHIP_R200 ||
813  rdev->family == CHIP_R100 ||
814  ASIC_IS_R300(rdev))
815  tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
816  else /* RV chips got this bit reversed */
817  tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
818 
819  fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
820  (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
821  RADEON_FP_CRTC_DONT_SHADOW_HEND));
822 
823  fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
824 
825  fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
826  RADEON_FP_DFP_SYNC_SEL |
827  RADEON_FP_CRT_SYNC_SEL |
828  RADEON_FP_CRTC_LOCK_8DOT |
829  RADEON_FP_USE_SHADOW_EN |
830  RADEON_FP_CRTC_USE_SHADOW_VEND |
831  RADEON_FP_CRT_SYNC_ALT);
832 
833  if (1) /* FIXME rgbBits == 8 */
834  fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
835  else
836  fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
837 
838  if (radeon_crtc->crtc_id == 0) {
839  if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
840  fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
841  if (radeon_encoder->rmx_type != RMX_OFF)
842  fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
843  else
844  fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
845  } else
846  fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
847  } else {
848  if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
849  fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
850  fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
851  } else
852  fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
853  }
854 
855  WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
856  WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
857  WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
858 
859  if (rdev->is_atom_bios)
860  radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
861  else
862  radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
863 }
864 
865 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
866  .dpms = radeon_legacy_tmds_int_dpms,
867  .mode_fixup = radeon_legacy_mode_fixup,
868  .prepare = radeon_legacy_tmds_int_prepare,
869  .mode_set = radeon_legacy_tmds_int_mode_set,
870  .commit = radeon_legacy_tmds_int_commit,
871  .disable = radeon_legacy_encoder_disable,
872 };
873 
874 
875 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
876  .destroy = radeon_enc_destroy,
877 };
878 
879 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
880 {
881  struct drm_device *dev = encoder->dev;
882  struct radeon_device *rdev = dev->dev_private;
883  uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
884  DRM_DEBUG_KMS("\n");
885 
886  switch (mode) {
887  case DRM_MODE_DPMS_ON:
888  fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
889  fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
890  break;
891  case DRM_MODE_DPMS_STANDBY:
892  case DRM_MODE_DPMS_SUSPEND:
893  case DRM_MODE_DPMS_OFF:
894  fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
895  fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
896  break;
897  }
898 
899  WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
900 
901  if (rdev->is_atom_bios)
902  radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
903  else
904  radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
905 
906 }
907 
908 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
909 {
910  struct radeon_device *rdev = encoder->dev->dev_private;
911 
912  if (rdev->is_atom_bios)
913  radeon_atom_output_lock(encoder, true);
914  else
915  radeon_combios_output_lock(encoder, true);
916  radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
917 }
918 
919 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
920 {
921  struct radeon_device *rdev = encoder->dev->dev_private;
922  radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
923 
924  if (rdev->is_atom_bios)
925  radeon_atom_output_lock(encoder, false);
926  else
927  radeon_combios_output_lock(encoder, false);
928 }
929 
930 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
931  struct drm_display_mode *mode,
932  struct drm_display_mode *adjusted_mode)
933 {
934  struct drm_device *dev = encoder->dev;
935  struct radeon_device *rdev = dev->dev_private;
936  struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
937  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
938  uint32_t fp2_gen_cntl;
939 
940  DRM_DEBUG_KMS("\n");
941 
942  if (rdev->is_atom_bios) {
943  radeon_encoder->pixel_clock = adjusted_mode->clock;
944  atombios_dvo_setup(encoder, ATOM_ENABLE);
945  fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
946  } else {
947  fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
948 
949  if (1) /* FIXME rgbBits == 8 */
950  fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
951  else
952  fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
953 
954  fp2_gen_cntl &= ~(RADEON_FP2_ON |
955  RADEON_FP2_DVO_EN |
956  RADEON_FP2_DVO_RATE_SEL_SDR);
957 
958  /* XXX: these are oem specific */
959  if (ASIC_IS_R300(rdev)) {
960  if ((dev->pdev->device == 0x4850) &&
961  (dev->pdev->subsystem_vendor == 0x1028) &&
962  (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
963  fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
964  else
965  fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
966 
967  /*if (mode->clock > 165000)
968  fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
969  }
970  if (!radeon_combios_external_tmds_setup(encoder))
971  radeon_external_tmds_setup(encoder);
972  }
973 
974  if (radeon_crtc->crtc_id == 0) {
975  if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
976  fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
977  if (radeon_encoder->rmx_type != RMX_OFF)
978  fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
979  else
980  fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
981  } else
982  fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
983  } else {
984  if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
985  fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
986  fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
987  } else
988  fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
989  }
990 
991  WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
992 
993  if (rdev->is_atom_bios)
994  radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
995  else
996  radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
997 }
998 
999 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1000 {
1001  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1002  /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1003  kfree(radeon_encoder->enc_priv);
1004  drm_encoder_cleanup(encoder);
1005  kfree(radeon_encoder);
1006 }
1007 
1008 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1009  .dpms = radeon_legacy_tmds_ext_dpms,
1010  .mode_fixup = radeon_legacy_mode_fixup,
1011  .prepare = radeon_legacy_tmds_ext_prepare,
1012  .mode_set = radeon_legacy_tmds_ext_mode_set,
1013  .commit = radeon_legacy_tmds_ext_commit,
1014  .disable = radeon_legacy_encoder_disable,
1015 };
1016 
1017 
1018 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1019  .destroy = radeon_ext_tmds_enc_destroy,
1020 };
1021 
1022 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1023 {
1024  struct drm_device *dev = encoder->dev;
1025  struct radeon_device *rdev = dev->dev_private;
1026  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1027  uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1028  uint32_t tv_master_cntl = 0;
1029  bool is_tv;
1030  DRM_DEBUG_KMS("\n");
1031 
1032  is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1033 
1034  if (rdev->family == CHIP_R200)
1035  fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1036  else {
1037  if (is_tv)
1038  tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1039  else
1040  crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1041  tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1042  }
1043 
1044  switch (mode) {
1045  case DRM_MODE_DPMS_ON:
1046  if (rdev->family == CHIP_R200) {
1047  fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1048  } else {
1049  if (is_tv)
1050  tv_master_cntl |= RADEON_TV_ON;
1051  else
1052  crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1053 
1054  if (rdev->family == CHIP_R420 ||
1055  rdev->family == CHIP_R423 ||
1056  rdev->family == CHIP_RV410)
1057  tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1058  R420_TV_DAC_GDACPD |
1059  R420_TV_DAC_BDACPD |
1060  RADEON_TV_DAC_BGSLEEP);
1061  else
1062  tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1063  RADEON_TV_DAC_GDACPD |
1064  RADEON_TV_DAC_BDACPD |
1065  RADEON_TV_DAC_BGSLEEP);
1066  }
1067  break;
1068  case DRM_MODE_DPMS_STANDBY:
1069  case DRM_MODE_DPMS_SUSPEND:
1070  case DRM_MODE_DPMS_OFF:
1071  if (rdev->family == CHIP_R200)
1072  fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1073  else {
1074  if (is_tv)
1075  tv_master_cntl &= ~RADEON_TV_ON;
1076  else
1077  crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1078 
1079  if (rdev->family == CHIP_R420 ||
1080  rdev->family == CHIP_R423 ||
1081  rdev->family == CHIP_RV410)
1082  tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1083  R420_TV_DAC_GDACPD |
1084  R420_TV_DAC_BDACPD |
1085  RADEON_TV_DAC_BGSLEEP);
1086  else
1087  tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1088  RADEON_TV_DAC_GDACPD |
1089  RADEON_TV_DAC_BDACPD |
1090  RADEON_TV_DAC_BGSLEEP);
1091  }
1092  break;
1093  }
1094 
1095  if (rdev->family == CHIP_R200) {
1096  WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1097  } else {
1098  if (is_tv)
1099  WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1100  /* handled in radeon_crtc_dpms() */
1101  else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1102  WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1103  WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1104  }
1105 
1106  if (rdev->is_atom_bios)
1107  radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1108  else
1109  radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1110 
1111 }
1112 
1113 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1114 {
1115  struct radeon_device *rdev = encoder->dev->dev_private;
1116 
1117  if (rdev->is_atom_bios)
1118  radeon_atom_output_lock(encoder, true);
1119  else
1120  radeon_combios_output_lock(encoder, true);
1121  radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1122 }
1123 
1124 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1125 {
1126  struct radeon_device *rdev = encoder->dev->dev_private;
1127 
1128  radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1129 
1130  if (rdev->is_atom_bios)
1131  radeon_atom_output_lock(encoder, true);
1132  else
1133  radeon_combios_output_lock(encoder, true);
1134 }
1135 
1136 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1137  struct drm_display_mode *mode,
1138  struct drm_display_mode *adjusted_mode)
1139 {
1140  struct drm_device *dev = encoder->dev;
1141  struct radeon_device *rdev = dev->dev_private;
1142  struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1143  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1144  struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1145  uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1146  uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1147  bool is_tv = false;
1148 
1149  DRM_DEBUG_KMS("\n");
1150 
1151  is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1152 
1153  if (rdev->family != CHIP_R200) {
1154  tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1155  if (rdev->family == CHIP_R420 ||
1156  rdev->family == CHIP_R423 ||
1157  rdev->family == CHIP_RV410) {
1158  tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1159  RADEON_TV_DAC_BGADJ_MASK |
1160  R420_TV_DAC_DACADJ_MASK |
1161  R420_TV_DAC_RDACPD |
1162  R420_TV_DAC_GDACPD |
1163  R420_TV_DAC_BDACPD |
1164  R420_TV_DAC_TVENABLE);
1165  } else {
1166  tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1167  RADEON_TV_DAC_BGADJ_MASK |
1168  RADEON_TV_DAC_DACADJ_MASK |
1169  RADEON_TV_DAC_RDACPD |
1170  RADEON_TV_DAC_GDACPD |
1171  RADEON_TV_DAC_BDACPD);
1172  }
1173 
1174  tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1175 
1176  if (is_tv) {
1177  if (tv_dac->tv_std == TV_STD_NTSC ||
1178  tv_dac->tv_std == TV_STD_NTSC_J ||
1179  tv_dac->tv_std == TV_STD_PAL_M ||
1180  tv_dac->tv_std == TV_STD_PAL_60)
1181  tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1182  else
1183  tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1184 
1185  if (tv_dac->tv_std == TV_STD_NTSC ||
1186  tv_dac->tv_std == TV_STD_NTSC_J)
1187  tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1188  else
1189  tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1190  } else
1191  tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1192  tv_dac->ps2_tvdac_adj);
1193 
1194  WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1195  }
1196 
1197  if (ASIC_IS_R300(rdev)) {
1198  gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1199  disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1200  } else if (rdev->family != CHIP_R200)
1201  disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1202  else if (rdev->family == CHIP_R200)
1203  fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1204 
1205  if (rdev->family >= CHIP_R200)
1206  disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1207 
1208  if (is_tv) {
1209  uint32_t dac_cntl;
1210 
1211  dac_cntl = RREG32(RADEON_DAC_CNTL);
1212  dac_cntl &= ~RADEON_DAC_TVO_EN;
1213  WREG32(RADEON_DAC_CNTL, dac_cntl);
1214 
1215  if (ASIC_IS_R300(rdev))
1216  gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1217 
1218  dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1219  if (radeon_crtc->crtc_id == 0) {
1220  if (ASIC_IS_R300(rdev)) {
1221  disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1222  disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1223  RADEON_DISP_TV_SOURCE_CRTC);
1224  }
1225  if (rdev->family >= CHIP_R200) {
1226  disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1227  } else {
1228  disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1229  }
1230  } else {
1231  if (ASIC_IS_R300(rdev)) {
1232  disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1233  disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1234  }
1235  if (rdev->family >= CHIP_R200) {
1236  disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1237  } else {
1238  disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1239  }
1240  }
1241  WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1242  } else {
1243 
1244  dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1245 
1246  if (radeon_crtc->crtc_id == 0) {
1247  if (ASIC_IS_R300(rdev)) {
1248  disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1249  disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1250  } else if (rdev->family == CHIP_R200) {
1251  fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1252  RADEON_FP2_DVO_RATE_SEL_SDR);
1253  } else
1254  disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1255  } else {
1256  if (ASIC_IS_R300(rdev)) {
1257  disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1258  disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1259  } else if (rdev->family == CHIP_R200) {
1260  fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1261  RADEON_FP2_DVO_RATE_SEL_SDR);
1262  fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1263  } else
1264  disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1265  }
1266  WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1267  }
1268 
1269  if (ASIC_IS_R300(rdev)) {
1270  WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1271  WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1272  } else if (rdev->family != CHIP_R200)
1273  WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1274  else if (rdev->family == CHIP_R200)
1275  WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1276 
1277  if (rdev->family >= CHIP_R200)
1278  WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1279 
1280  if (is_tv)
1281  radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1282 
1283  if (rdev->is_atom_bios)
1284  radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1285  else
1286  radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1287 
1288 }
1289 
1290 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1291  struct drm_connector *connector)
1292 {
1293  struct drm_device *dev = encoder->dev;
1294  struct radeon_device *rdev = dev->dev_private;
1295  uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1296  uint32_t disp_output_cntl, gpiopad_a, tmp;
1297  bool found = false;
1298 
1299  /* save regs needed */
1300  gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1301  dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1302  crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1303  dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1304  tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1305  disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1306 
1307  WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1308 
1309  WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1310 
1311  WREG32(RADEON_CRTC2_GEN_CNTL,
1312  RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1313 
1314  tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1315  tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1316  WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1317 
1318  WREG32(RADEON_DAC_EXT_CNTL,
1319  RADEON_DAC2_FORCE_BLANK_OFF_EN |
1320  RADEON_DAC2_FORCE_DATA_EN |
1321  RADEON_DAC_FORCE_DATA_SEL_RGB |
1322  (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1323 
1324  WREG32(RADEON_TV_DAC_CNTL,
1325  RADEON_TV_DAC_STD_NTSC |
1326  (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1327  (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1328 
1329  RREG32(RADEON_TV_DAC_CNTL);
1330  mdelay(4);
1331 
1332  WREG32(RADEON_TV_DAC_CNTL,
1333  RADEON_TV_DAC_NBLANK |
1334  RADEON_TV_DAC_NHOLD |
1335  RADEON_TV_MONITOR_DETECT_EN |
1336  RADEON_TV_DAC_STD_NTSC |
1337  (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1338  (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1339 
1340  RREG32(RADEON_TV_DAC_CNTL);
1341  mdelay(6);
1342 
1343  tmp = RREG32(RADEON_TV_DAC_CNTL);
1344  if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1345  found = true;
1346  DRM_DEBUG_KMS("S-video TV connection detected\n");
1347  } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1348  found = true;
1349  DRM_DEBUG_KMS("Composite TV connection detected\n");
1350  }
1351 
1352  WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1353  WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1354  WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1355  WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1356  WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1357  WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1358  return found;
1359 }
1360 
1361 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1362  struct drm_connector *connector)
1363 {
1364  struct drm_device *dev = encoder->dev;
1365  struct radeon_device *rdev = dev->dev_private;
1366  uint32_t tv_dac_cntl, dac_cntl2;
1367  uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1368  bool found = false;
1369 
1370  if (ASIC_IS_R300(rdev))
1371  return r300_legacy_tv_detect(encoder, connector);
1372 
1373  dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1374  tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1375  tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1376  config_cntl = RREG32(RADEON_CONFIG_CNTL);
1377  tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1378 
1379  tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1380  WREG32(RADEON_DAC_CNTL2, tmp);
1381 
1382  tmp = tv_master_cntl | RADEON_TV_ON;
1383  tmp &= ~(RADEON_TV_ASYNC_RST |
1384  RADEON_RESTART_PHASE_FIX |
1385  RADEON_CRT_FIFO_CE_EN |
1386  RADEON_TV_FIFO_CE_EN |
1387  RADEON_RE_SYNC_NOW_SEL_MASK);
1388  tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1389  WREG32(RADEON_TV_MASTER_CNTL, tmp);
1390 
1391  tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1392  RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1393  (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1394 
1395  if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1396  tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1397  else
1398  tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1399  WREG32(RADEON_TV_DAC_CNTL, tmp);
1400 
1401  tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1402  RADEON_RED_MX_FORCE_DAC_DATA |
1403  RADEON_GRN_MX_FORCE_DAC_DATA |
1404  RADEON_BLU_MX_FORCE_DAC_DATA |
1405  (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1406  WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1407 
1408  mdelay(3);
1409  tmp = RREG32(RADEON_TV_DAC_CNTL);
1410  if (tmp & RADEON_TV_DAC_GDACDET) {
1411  found = true;
1412  DRM_DEBUG_KMS("S-video TV connection detected\n");
1413  } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1414  found = true;
1415  DRM_DEBUG_KMS("Composite TV connection detected\n");
1416  }
1417 
1418  WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1419  WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1420  WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1421  WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1422  return found;
1423 }
1424 
1425 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1426  struct drm_connector *connector)
1427 {
1428  struct drm_device *dev = encoder->dev;
1429  struct radeon_device *rdev = dev->dev_private;
1430  uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1431  uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1432  uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1433  uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1434  uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1435  bool found = false;
1436  int i;
1437 
1438  /* save the regs we need */
1439  gpio_monid = RREG32(RADEON_GPIO_MONID);
1440  fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1441  disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1442  crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1443  disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1444  disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1445  disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1446  disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1447  disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1448  disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1449  crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1450  crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1451  crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1452  crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1453 
1454  tmp = RREG32(RADEON_GPIO_MONID);
1455  tmp &= ~RADEON_GPIO_A_0;
1456  WREG32(RADEON_GPIO_MONID, tmp);
1457 
1458  WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1459  RADEON_FP2_PANEL_FORMAT |
1460  R200_FP2_SOURCE_SEL_TRANS_UNIT |
1461  RADEON_FP2_DVO_EN |
1462  R200_FP2_DVO_RATE_SEL_SDR));
1463 
1464  WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1465  RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1466 
1467  WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1468  RADEON_CRTC2_DISP_REQ_EN_B));
1469 
1470  WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1471  WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1472  WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1473  WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1474  WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1475  WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1476 
1477  WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1478  WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1479  WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1480  WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1481 
1482  for (i = 0; i < 200; i++) {
1483  tmp = RREG32(RADEON_GPIO_MONID);
1484  if (tmp & RADEON_GPIO_Y_0)
1485  found = true;
1486 
1487  if (found)
1488  break;
1489 
1490  if (!drm_can_sleep())
1491  mdelay(1);
1492  else
1493  msleep(1);
1494  }
1495 
1496  /* restore the regs we used */
1497  WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1498  WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1499  WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1500  WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1501  WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1502  WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1503  WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1504  WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1505  WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1506  WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1507  WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1508  WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1509  WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1510  WREG32(RADEON_GPIO_MONID, gpio_monid);
1511 
1512  return found;
1513 }
1514 
1515 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1516  struct drm_connector *connector)
1517 {
1518  struct drm_device *dev = encoder->dev;
1519  struct radeon_device *rdev = dev->dev_private;
1520  uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1521  uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1522  uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1523  enum drm_connector_status found = connector_status_disconnected;
1524  struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1525  struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1526  bool color = true;
1527  struct drm_crtc *crtc;
1528 
1529  /* find out if crtc2 is in use or if this encoder is using it */
1530  list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1531  struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1532  if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1533  if (encoder->crtc != crtc) {
1534  return connector_status_disconnected;
1535  }
1536  }
1537  }
1538 
1539  if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1540  connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1541  connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1542  bool tv_detect;
1543 
1544  if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1545  return connector_status_disconnected;
1546 
1547  tv_detect = radeon_legacy_tv_detect(encoder, connector);
1548  if (tv_detect && tv_dac)
1549  found = connector_status_connected;
1550  return found;
1551  }
1552 
1553  /* don't probe if the encoder is being used for something else not CRT related */
1554  if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1555  DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1556  return connector_status_disconnected;
1557  }
1558 
1559  /* R200 uses an external DAC for secondary DAC */
1560  if (rdev->family == CHIP_R200) {
1561  if (radeon_legacy_ext_dac_detect(encoder, connector))
1562  found = connector_status_connected;
1563  return found;
1564  }
1565 
1566  /* save the regs we need */
1567  pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1568 
1569  if (rdev->flags & RADEON_SINGLE_CRTC) {
1570  crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1571  } else {
1572  if (ASIC_IS_R300(rdev)) {
1573  gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1574  disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1575  } else {
1576  disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1577  }
1578  crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1579  }
1580  tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1581  dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1582  dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1583 
1584  tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1585  | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1586  WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1587 
1588  if (rdev->flags & RADEON_SINGLE_CRTC) {
1589  tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1590  WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1591  } else {
1592  tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1593  tmp |= RADEON_CRTC2_CRT2_ON |
1594  (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1595  WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1596 
1597  if (ASIC_IS_R300(rdev)) {
1598  WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1599  tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1600  tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1601  WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1602  } else {
1603  tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1604  WREG32(RADEON_DISP_HW_DEBUG, tmp);
1605  }
1606  }
1607 
1608  tmp = RADEON_TV_DAC_NBLANK |
1609  RADEON_TV_DAC_NHOLD |
1610  RADEON_TV_MONITOR_DETECT_EN |
1611  RADEON_TV_DAC_STD_PS2;
1612 
1613  WREG32(RADEON_TV_DAC_CNTL, tmp);
1614 
1615  tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1616  RADEON_DAC2_FORCE_DATA_EN;
1617 
1618  if (color)
1619  tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1620  else
1621  tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1622 
1623  if (ASIC_IS_R300(rdev))
1624  tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1625  else
1626  tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1627 
1628  WREG32(RADEON_DAC_EXT_CNTL, tmp);
1629 
1630  tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1631  WREG32(RADEON_DAC_CNTL2, tmp);
1632 
1633  mdelay(10);
1634 
1635  if (ASIC_IS_R300(rdev)) {
1636  if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1637  found = connector_status_connected;
1638  } else {
1639  if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1640  found = connector_status_connected;
1641  }
1642 
1643  /* restore regs we used */
1644  WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1645  WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1646  WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1647 
1648  if (rdev->flags & RADEON_SINGLE_CRTC) {
1649  WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1650  } else {
1651  WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1652  if (ASIC_IS_R300(rdev)) {
1653  WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1654  WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1655  } else {
1656  WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1657  }
1658  }
1659 
1660  WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1661 
1662  return found;
1663 
1664 }
1665 
1666 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1667  .dpms = radeon_legacy_tv_dac_dpms,
1668  .mode_fixup = radeon_legacy_mode_fixup,
1669  .prepare = radeon_legacy_tv_dac_prepare,
1670  .mode_set = radeon_legacy_tv_dac_mode_set,
1671  .commit = radeon_legacy_tv_dac_commit,
1672  .detect = radeon_legacy_tv_dac_detect,
1673  .disable = radeon_legacy_encoder_disable,
1674 };
1675 
1676 
1677 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1678  .destroy = radeon_enc_destroy,
1679 };
1680 
1681 
1682 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1683 {
1684  struct drm_device *dev = encoder->base.dev;
1685  struct radeon_device *rdev = dev->dev_private;
1686  struct radeon_encoder_int_tmds *tmds = NULL;
1687  bool ret;
1688 
1689  tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1690 
1691  if (!tmds)
1692  return NULL;
1693 
1694  if (rdev->is_atom_bios)
1695  ret = radeon_atombios_get_tmds_info(encoder, tmds);
1696  else
1697  ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1698 
1699  if (ret == false)
1700  radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1701 
1702  return tmds;
1703 }
1704 
1705 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1706 {
1707  struct drm_device *dev = encoder->base.dev;
1708  struct radeon_device *rdev = dev->dev_private;
1709  struct radeon_encoder_ext_tmds *tmds = NULL;
1710  bool ret;
1711 
1712  if (rdev->is_atom_bios)
1713  return NULL;
1714 
1715  tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1716 
1717  if (!tmds)
1718  return NULL;
1719 
1720  ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1721 
1722  if (ret == false)
1723  radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1724 
1725  return tmds;
1726 }
1727 
1728 void
1729 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1730 {
1731  struct radeon_device *rdev = dev->dev_private;
1732  struct drm_encoder *encoder;
1733  struct radeon_encoder *radeon_encoder;
1734 
1735  /* see if we already added it */
1736  list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1737  radeon_encoder = to_radeon_encoder(encoder);
1738  if (radeon_encoder->encoder_enum == encoder_enum) {
1739  radeon_encoder->devices |= supported_device;
1740  return;
1741  }
1742 
1743  }
1744 
1745  /* add a new one */
1746  radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1747  if (!radeon_encoder)
1748  return;
1749 
1750  encoder = &radeon_encoder->base;
1751  if (rdev->flags & RADEON_SINGLE_CRTC)
1752  encoder->possible_crtcs = 0x1;
1753  else
1754  encoder->possible_crtcs = 0x3;
1755 
1756  radeon_encoder->enc_priv = NULL;
1757 
1758  radeon_encoder->encoder_enum = encoder_enum;
1759  radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1760  radeon_encoder->devices = supported_device;
1761  radeon_encoder->rmx_type = RMX_OFF;
1762 
1763  switch (radeon_encoder->encoder_id) {
1764  case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1765  encoder->possible_crtcs = 0x1;
1766  drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1767  drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1768  if (rdev->is_atom_bios)
1769  radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1770  else
1771  radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1772  radeon_encoder->rmx_type = RMX_FULL;
1773  break;
1774  case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1775  drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1776  drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1777  radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1778  break;
1779  case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1780  drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1781  drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1782  if (rdev->is_atom_bios)
1783  radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1784  else
1785  radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1786  break;
1787  case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1788  drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1789  drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1790  if (rdev->is_atom_bios)
1791  radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1792  else
1793  radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1794  break;
1795  case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1796  drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1797  drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1798  if (!rdev->is_atom_bios)
1799  radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1800  break;
1801  }
1802 }
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