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s3c-fb.c
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1 /* linux/drivers/video/s3c-fb.c
2  *
3  * Copyright 2008 Openmoko Inc.
4  * Copyright 2008-2010 Simtec Electronics
5  * Ben Dooks <[email protected]>
6  * http://armlinux.simtec.co.uk/
7  *
8  * Samsung SoC Framebuffer driver
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software FoundatIon.
13 */
14 
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/fb.h>
23 #include <linux/io.h>
24 #include <linux/uaccess.h>
25 #include <linux/interrupt.h>
26 #include <linux/pm_runtime.h>
27 
28 #include <video/samsung_fimd.h>
29 #include <mach/map.h>
30 #include <plat/fb.h>
31 
32 /* This driver will export a number of framebuffer interfaces depending
33  * on the configuration passed in via the platform data. Each fb instance
34  * maps to a hardware window. Currently there is no support for runtime
35  * setting of the alpha-blending functions that each window has, so only
36  * window 0 is actually useful.
37  *
38  * Window 0 is treated specially, it is used for the basis of the LCD
39  * output timings and as the control for the output power-down state.
40 */
41 
42 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
43  * has been replaced by using the platform device name to pick the correct
44  * configuration data for the system.
45 */
46 
47 #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
48 #undef writel
49 #define writel(v, r) do { \
50  pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \
51  __raw_writel(v, r); \
52 } while (0)
53 #endif /* FB_S3C_DEBUG_REGWRITE */
54 
55 /* irq_flags bits */
56 #define S3C_FB_VSYNC_IRQ_EN 0
57 
58 #define VSYNC_TIMEOUT_MSEC 50
59 
60 struct s3c_fb;
61 
62 #define VALID_BPP(x) (1 << ((x) - 1))
63 
64 #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
65 #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
66 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
67 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
68 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
69 
90  unsigned int is_2443:1;
91  unsigned short nr_windows;
92  unsigned int vidtcon;
93  unsigned short wincon;
94  unsigned short winmap;
95  unsigned short keycon;
96  unsigned short buf_start;
97  unsigned short buf_end;
98  unsigned short buf_size;
99  unsigned short osd;
100  unsigned short osd_stride;
101  unsigned short palette[S3C_FB_MAX_WIN];
102 
103  unsigned int has_prtcon:1;
104  unsigned int has_shadowcon:1;
105  unsigned int has_blendcon:1;
106  unsigned int has_clksel:1;
107  unsigned int has_fixvclk:1;
108 };
109 
124  unsigned int has_osd_c:1;
125  unsigned int has_osd_d:1;
126  unsigned int has_osd_alpha:1;
127  unsigned int palette_16bpp:1;
128  unsigned short osd_size_off;
129  unsigned short palette_sz;
131 };
132 
141 };
142 
151  struct fb_bitfield r;
152  struct fb_bitfield g;
153  struct fb_bitfield b;
154  struct fb_bitfield a;
155 };
156 
168 struct s3c_fb_win {
170  struct s3c_fb *parent;
171  struct fb_info *fbinfo;
174 
177  unsigned int index;
178 };
179 
185 struct s3c_fb_vsync {
187  unsigned int count;
188 };
189 
206 struct s3c_fb {
208  struct device *dev;
209  struct clk *bus_clk;
210  struct clk *lcd_clk;
211  void __iomem *regs;
213 
214  unsigned char enabled;
215  bool output_on;
216 
219 
220  int irq_no;
221  unsigned long irq_flags;
223 };
224 
230 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
231 {
232  return win->variant.valid_bpp & VALID_BPP(bpp);
233 }
234 
243 static int s3c_fb_check_var(struct fb_var_screeninfo *var,
244  struct fb_info *info)
245 {
246  struct s3c_fb_win *win = info->par;
247  struct s3c_fb *sfb = win->parent;
248 
249  dev_dbg(sfb->dev, "checking parameters\n");
250 
251  var->xres_virtual = max(var->xres_virtual, var->xres);
252  var->yres_virtual = max(var->yres_virtual, var->yres);
253 
254  if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
255  dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
256  win->index, var->bits_per_pixel);
257  return -EINVAL;
258  }
259 
260  /* always ensure these are zero, for drop through cases below */
261  var->transp.offset = 0;
262  var->transp.length = 0;
263 
264  switch (var->bits_per_pixel) {
265  case 1:
266  case 2:
267  case 4:
268  case 8:
269  if (sfb->variant.palette[win->index] != 0) {
270  /* non palletised, A:1,R:2,G:3,B:2 mode */
271  var->red.offset = 4;
272  var->green.offset = 2;
273  var->blue.offset = 0;
274  var->red.length = 5;
275  var->green.length = 3;
276  var->blue.length = 2;
277  var->transp.offset = 7;
278  var->transp.length = 1;
279  } else {
280  var->red.offset = 0;
281  var->red.length = var->bits_per_pixel;
282  var->green = var->red;
283  var->blue = var->red;
284  }
285  break;
286 
287  case 19:
288  /* 666 with one bit alpha/transparency */
289  var->transp.offset = 18;
290  var->transp.length = 1;
291  case 18:
292  var->bits_per_pixel = 32;
293 
294  /* 666 format */
295  var->red.offset = 12;
296  var->green.offset = 6;
297  var->blue.offset = 0;
298  var->red.length = 6;
299  var->green.length = 6;
300  var->blue.length = 6;
301  break;
302 
303  case 16:
304  /* 16 bpp, 565 format */
305  var->red.offset = 11;
306  var->green.offset = 5;
307  var->blue.offset = 0;
308  var->red.length = 5;
309  var->green.length = 6;
310  var->blue.length = 5;
311  break;
312 
313  case 32:
314  case 28:
315  case 25:
316  var->transp.length = var->bits_per_pixel - 24;
317  var->transp.offset = 24;
318  /* drop through */
319  case 24:
320  /* our 24bpp is unpacked, so 32bpp */
321  var->bits_per_pixel = 32;
322  var->red.offset = 16;
323  var->red.length = 8;
324  var->green.offset = 8;
325  var->green.length = 8;
326  var->blue.offset = 0;
327  var->blue.length = 8;
328  break;
329 
330  default:
331  dev_err(sfb->dev, "invalid bpp\n");
332  }
333 
334  dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
335  return 0;
336 }
337 
346 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
347 {
348  unsigned long clk;
349  unsigned long long tmp;
350  unsigned int result;
351 
352  if (sfb->variant.has_clksel)
353  clk = clk_get_rate(sfb->bus_clk);
354  else
355  clk = clk_get_rate(sfb->lcd_clk);
356 
357  tmp = (unsigned long long)clk;
358  tmp *= pixclk;
359 
360  do_div(tmp, 1000000000UL);
361  result = (unsigned int)tmp / 1000;
362 
363  dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
364  pixclk, clk, result, result ? clk / result : clk);
365 
366  return result;
367 }
368 
377 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
378 {
379  int pix_per_word;
380 
381  if (bpp > 16)
382  return pix;
383 
384  pix_per_word = (8 * 32) / bpp;
385  return ALIGN(pix, pix_per_word);
386 }
387 
394 static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
395 {
396  struct s3c_fb *sfb = win->parent;
397 
398  /* OSD can be set up if osd_size_off != 0 for this window */
399  if (win->variant.osd_size_off)
400  writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
401  + win->variant.osd_size_off);
402 }
403 
410 static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
411 {
412  struct s3c_fb *sfb = win->parent;
413 
414  if (win->variant.has_osd_alpha)
415  writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
416 }
417 
424 static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
425 {
426  struct s3c_fb *sfb = win->parent;
427  u32 reg;
428 
429  if (protect) {
430  if (sfb->variant.has_prtcon) {
431  writel(PRTCON_PROTECT, sfb->regs + PRTCON);
432  } else if (sfb->variant.has_shadowcon) {
433  reg = readl(sfb->regs + SHADOWCON);
434  writel(reg | SHADOWCON_WINx_PROTECT(win->index),
435  sfb->regs + SHADOWCON);
436  }
437  } else {
438  if (sfb->variant.has_prtcon) {
439  writel(0, sfb->regs + PRTCON);
440  } else if (sfb->variant.has_shadowcon) {
441  reg = readl(sfb->regs + SHADOWCON);
442  writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
443  sfb->regs + SHADOWCON);
444  }
445  }
446 }
447 
453 static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
454 {
455  u32 vidcon0 = readl(sfb->regs + VIDCON0);
456 
457  if (enable && !sfb->output_on)
458  pm_runtime_get_sync(sfb->dev);
459 
460  if (enable) {
461  vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
462  } else {
463  /* see the note in the framebuffer datasheet about
464  * why you cannot take both of these bits down at the
465  * same time. */
466 
467  if (vidcon0 & VIDCON0_ENVID) {
468  vidcon0 |= VIDCON0_ENVID;
469  vidcon0 &= ~VIDCON0_ENVID_F;
470  }
471  }
472 
473  writel(vidcon0, sfb->regs + VIDCON0);
474 
475  if (!enable && sfb->output_on)
476  pm_runtime_put_sync(sfb->dev);
477 
478  sfb->output_on = enable;
479 }
480 
487 static int s3c_fb_set_par(struct fb_info *info)
488 {
489  struct fb_var_screeninfo *var = &info->var;
490  struct s3c_fb_win *win = info->par;
491  struct s3c_fb *sfb = win->parent;
492  void __iomem *regs = sfb->regs;
493  void __iomem *buf = regs;
494  int win_no = win->index;
495  u32 alpha = 0;
496  u32 data;
497  u32 pagewidth;
498 
499  dev_dbg(sfb->dev, "setting framebuffer parameters\n");
500 
501  pm_runtime_get_sync(sfb->dev);
502 
503  shadow_protect_win(win, 1);
504 
505  switch (var->bits_per_pixel) {
506  case 32:
507  case 24:
508  case 16:
509  case 12:
510  info->fix.visual = FB_VISUAL_TRUECOLOR;
511  break;
512  case 8:
513  if (win->variant.palette_sz >= 256)
514  info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
515  else
516  info->fix.visual = FB_VISUAL_TRUECOLOR;
517  break;
518  case 1:
519  info->fix.visual = FB_VISUAL_MONO01;
520  break;
521  default:
522  info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
523  break;
524  }
525 
526  info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
527 
528  info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
529  info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
530 
531  /* disable the window whilst we update it */
532  writel(0, regs + WINCON(win_no));
533 
534  if (!sfb->output_on)
535  s3c_fb_enable(sfb, 1);
536 
537  /* write the buffer address */
538 
539  /* start and end registers stride is 8 */
540  buf = regs + win_no * 8;
541 
542  writel(info->fix.smem_start, buf + sfb->variant.buf_start);
543 
544  data = info->fix.smem_start + info->fix.line_length * var->yres;
545  writel(data, buf + sfb->variant.buf_end);
546 
547  pagewidth = (var->xres * var->bits_per_pixel) >> 3;
548  data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
549  VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) |
550  VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) |
551  VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth);
552  writel(data, regs + sfb->variant.buf_size + (win_no * 4));
553 
554  /* write 'OSD' registers to control position of framebuffer */
555 
556  data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) |
558  writel(data, regs + VIDOSD_A(win_no, sfb->variant));
559 
560  data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
561  var->xres - 1)) |
562  VIDOSDxB_BOTRIGHT_Y(var->yres - 1) |
563  VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel,
564  var->xres - 1)) |
565  VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1);
566 
567  writel(data, regs + VIDOSD_B(win_no, sfb->variant));
568 
569  data = var->xres * var->yres;
570 
571  alpha = VIDISD14C_ALPHA1_R(0xf) |
572  VIDISD14C_ALPHA1_G(0xf) |
573  VIDISD14C_ALPHA1_B(0xf);
574 
575  vidosd_set_alpha(win, alpha);
576  vidosd_set_size(win, data);
577 
578  /* Enable DMA channel for this window */
579  if (sfb->variant.has_shadowcon) {
580  data = readl(sfb->regs + SHADOWCON);
581  data |= SHADOWCON_CHx_ENABLE(win_no);
582  writel(data, sfb->regs + SHADOWCON);
583  }
584 
585  data = WINCONx_ENWIN;
586  sfb->enabled |= (1 << win->index);
587 
588  /* note, since we have to round up the bits-per-pixel, we end up
589  * relying on the bitfield information for r/g/b/a to work out
590  * exactly which mode of operation is intended. */
591 
592  switch (var->bits_per_pixel) {
593  case 1:
594  data |= WINCON0_BPPMODE_1BPP;
595  data |= WINCONx_BITSWP;
596  data |= WINCONx_BURSTLEN_4WORD;
597  break;
598  case 2:
599  data |= WINCON0_BPPMODE_2BPP;
600  data |= WINCONx_BITSWP;
601  data |= WINCONx_BURSTLEN_8WORD;
602  break;
603  case 4:
604  data |= WINCON0_BPPMODE_4BPP;
605  data |= WINCONx_BITSWP;
606  data |= WINCONx_BURSTLEN_8WORD;
607  break;
608  case 8:
609  if (var->transp.length != 0)
611  else
613  data |= WINCONx_BURSTLEN_8WORD;
614  data |= WINCONx_BYTSWP;
615  break;
616  case 16:
617  if (var->transp.length != 0)
619  else
621  data |= WINCONx_HAWSWP;
622  data |= WINCONx_BURSTLEN_16WORD;
623  break;
624  case 24:
625  case 32:
626  if (var->red.length == 6) {
627  if (var->transp.length != 0)
629  else
631  } else if (var->transp.length == 1)
633  | WINCON1_BLD_PIX;
634  else if ((var->transp.length == 4) ||
635  (var->transp.length == 8))
638  else
640 
641  data |= WINCONx_WSWP;
642  data |= WINCONx_BURSTLEN_16WORD;
643  break;
644  }
645 
646  /* Enable the colour keying for the window below this one */
647  if (win_no > 0) {
648  u32 keycon0_data = 0, keycon1_data = 0;
649  void __iomem *keycon = regs + sfb->variant.keycon;
650 
651  keycon0_data = ~(WxKEYCON0_KEYBL_EN |
654 
655  keycon1_data = WxKEYCON1_COLVAL(0xffffff);
656 
657  keycon += (win_no - 1) * 8;
658 
659  writel(keycon0_data, keycon + WKEYCON0);
660  writel(keycon1_data, keycon + WKEYCON1);
661  }
662 
663  writel(data, regs + sfb->variant.wincon + (win_no * 4));
664  writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
665 
666  /* Set alpha value width */
667  if (sfb->variant.has_blendcon) {
668  data = readl(sfb->regs + BLENDCON);
669  data &= ~BLENDCON_NEW_MASK;
670  if (var->transp.length > 4)
672  else
674  writel(data, sfb->regs + BLENDCON);
675  }
676 
677  shadow_protect_win(win, 0);
678 
679  pm_runtime_put_sync(sfb->dev);
680 
681  return 0;
682 }
683 
698 static void s3c_fb_update_palette(struct s3c_fb *sfb,
699  struct s3c_fb_win *win,
700  unsigned int reg,
701  u32 value)
702 {
703  void __iomem *palreg;
704  u32 palcon;
705 
706  palreg = sfb->regs + sfb->variant.palette[win->index];
707 
708  dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
709  __func__, win->index, reg, palreg, value);
710 
711  win->palette_buffer[reg] = value;
712 
713  palcon = readl(sfb->regs + WPALCON);
714  writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
715 
716  if (win->variant.palette_16bpp)
717  writew(value, palreg + (reg * 2));
718  else
719  writel(value, palreg + (reg * 4));
720 
721  writel(palcon, sfb->regs + WPALCON);
722 }
723 
724 static inline unsigned int chan_to_field(unsigned int chan,
725  struct fb_bitfield *bf)
726 {
727  chan &= 0xffff;
728  chan >>= 16 - bf->length;
729  return chan << bf->offset;
730 }
731 
741 static int s3c_fb_setcolreg(unsigned regno,
742  unsigned red, unsigned green, unsigned blue,
743  unsigned transp, struct fb_info *info)
744 {
745  struct s3c_fb_win *win = info->par;
746  struct s3c_fb *sfb = win->parent;
747  unsigned int val;
748 
749  dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
750  __func__, win->index, regno, red, green, blue);
751 
752  pm_runtime_get_sync(sfb->dev);
753 
754  switch (info->fix.visual) {
755  case FB_VISUAL_TRUECOLOR:
756  /* true-colour, use pseudo-palette */
757 
758  if (regno < 16) {
759  u32 *pal = info->pseudo_palette;
760 
761  val = chan_to_field(red, &info->var.red);
762  val |= chan_to_field(green, &info->var.green);
763  val |= chan_to_field(blue, &info->var.blue);
764 
765  pal[regno] = val;
766  }
767  break;
768 
770  if (regno < win->variant.palette_sz) {
771  val = chan_to_field(red, &win->palette.r);
772  val |= chan_to_field(green, &win->palette.g);
773  val |= chan_to_field(blue, &win->palette.b);
774 
775  s3c_fb_update_palette(sfb, win, regno, val);
776  }
777 
778  break;
779 
780  default:
781  pm_runtime_put_sync(sfb->dev);
782  return 1; /* unknown type */
783  }
784 
785  pm_runtime_put_sync(sfb->dev);
786  return 0;
787 }
788 
796 static int s3c_fb_blank(int blank_mode, struct fb_info *info)
797 {
798  struct s3c_fb_win *win = info->par;
799  struct s3c_fb *sfb = win->parent;
800  unsigned int index = win->index;
801  u32 wincon;
802  u32 output_on = sfb->output_on;
803 
804  dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
805 
806  pm_runtime_get_sync(sfb->dev);
807 
808  wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
809 
810  switch (blank_mode) {
811  case FB_BLANK_POWERDOWN:
812  wincon &= ~WINCONx_ENWIN;
813  sfb->enabled &= ~(1 << index);
814  /* fall through to FB_BLANK_NORMAL */
815 
816  case FB_BLANK_NORMAL:
817  /* disable the DMA and display 0x0 (black) */
818  shadow_protect_win(win, 1);
820  sfb->regs + sfb->variant.winmap + (index * 4));
821  shadow_protect_win(win, 0);
822  break;
823 
824  case FB_BLANK_UNBLANK:
825  shadow_protect_win(win, 1);
826  writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
827  shadow_protect_win(win, 0);
828  wincon |= WINCONx_ENWIN;
829  sfb->enabled |= (1 << index);
830  break;
831 
834  default:
835  pm_runtime_put_sync(sfb->dev);
836  return 1;
837  }
838 
839  shadow_protect_win(win, 1);
840  writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
841 
842  /* Check the enabled state to see if we need to be running the
843  * main LCD interface, as if there are no active windows then
844  * it is highly likely that we also do not need to output
845  * anything.
846  */
847  s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
848  shadow_protect_win(win, 0);
849 
850  pm_runtime_put_sync(sfb->dev);
851 
852  return output_on == sfb->output_on;
853 }
854 
866 static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
867  struct fb_info *info)
868 {
869  struct s3c_fb_win *win = info->par;
870  struct s3c_fb *sfb = win->parent;
871  void __iomem *buf = sfb->regs + win->index * 8;
872  unsigned int start_boff, end_boff;
873 
874  pm_runtime_get_sync(sfb->dev);
875 
876  /* Offset in bytes to the start of the displayed area */
877  start_boff = var->yoffset * info->fix.line_length;
878  /* X offset depends on the current bpp */
879  if (info->var.bits_per_pixel >= 8) {
880  start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
881  } else {
882  switch (info->var.bits_per_pixel) {
883  case 4:
884  start_boff += var->xoffset >> 1;
885  break;
886  case 2:
887  start_boff += var->xoffset >> 2;
888  break;
889  case 1:
890  start_boff += var->xoffset >> 3;
891  break;
892  default:
893  dev_err(sfb->dev, "invalid bpp\n");
894  pm_runtime_put_sync(sfb->dev);
895  return -EINVAL;
896  }
897  }
898  /* Offset in bytes to the end of the displayed area */
899  end_boff = start_boff + info->var.yres * info->fix.line_length;
900 
901  /* Temporarily turn off per-vsync update from shadow registers until
902  * both start and end addresses are updated to prevent corruption */
903  shadow_protect_win(win, 1);
904 
905  writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
906  writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
907 
908  shadow_protect_win(win, 0);
909 
910  pm_runtime_put_sync(sfb->dev);
911  return 0;
912 }
913 
918 static void s3c_fb_enable_irq(struct s3c_fb *sfb)
919 {
920  void __iomem *regs = sfb->regs;
921  u32 irq_ctrl_reg;
922 
924  /* IRQ disabled, enable it */
925  irq_ctrl_reg = readl(regs + VIDINTCON0);
926 
927  irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
928  irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
929 
930  irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
931  irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
932  irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
933  irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
934 
935  writel(irq_ctrl_reg, regs + VIDINTCON0);
936  }
937 }
938 
943 static void s3c_fb_disable_irq(struct s3c_fb *sfb)
944 {
945  void __iomem *regs = sfb->regs;
946  u32 irq_ctrl_reg;
947 
949  /* IRQ enabled, disable it */
950  irq_ctrl_reg = readl(regs + VIDINTCON0);
951 
952  irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
953  irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
954 
955  writel(irq_ctrl_reg, regs + VIDINTCON0);
956  }
957 }
958 
959 static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
960 {
961  struct s3c_fb *sfb = dev_id;
962  void __iomem *regs = sfb->regs;
963  u32 irq_sts_reg;
964 
965  spin_lock(&sfb->slock);
966 
967  irq_sts_reg = readl(regs + VIDINTCON1);
968 
969  if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
970 
971  /* VSYNC interrupt, accept it */
972  writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
973 
974  sfb->vsync_info.count++;
975  wake_up_interruptible(&sfb->vsync_info.wait);
976  }
977 
978  /* We only support waiting for VSYNC for now, so it's safe
979  * to always disable irqs here.
980  */
981  s3c_fb_disable_irq(sfb);
982 
983  spin_unlock(&sfb->slock);
984  return IRQ_HANDLED;
985 }
986 
992 static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
993 {
994  unsigned long count;
995  int ret;
996 
997  if (crtc != 0)
998  return -ENODEV;
999 
1000  pm_runtime_get_sync(sfb->dev);
1001 
1002  count = sfb->vsync_info.count;
1003  s3c_fb_enable_irq(sfb);
1005  count != sfb->vsync_info.count,
1007 
1008  pm_runtime_put_sync(sfb->dev);
1009 
1010  if (ret == 0)
1011  return -ETIMEDOUT;
1012 
1013  return 0;
1014 }
1015 
1016 static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
1017  unsigned long arg)
1018 {
1019  struct s3c_fb_win *win = info->par;
1020  struct s3c_fb *sfb = win->parent;
1021  int ret;
1022  u32 crtc;
1023 
1024  switch (cmd) {
1025  case FBIO_WAITFORVSYNC:
1026  if (get_user(crtc, (u32 __user *)arg)) {
1027  ret = -EFAULT;
1028  break;
1029  }
1030 
1031  ret = s3c_fb_wait_for_vsync(sfb, crtc);
1032  break;
1033  default:
1034  ret = -ENOTTY;
1035  }
1036 
1037  return ret;
1038 }
1039 
1040 static struct fb_ops s3c_fb_ops = {
1041  .owner = THIS_MODULE,
1042  .fb_check_var = s3c_fb_check_var,
1043  .fb_set_par = s3c_fb_set_par,
1044  .fb_blank = s3c_fb_blank,
1045  .fb_setcolreg = s3c_fb_setcolreg,
1046  .fb_fillrect = cfb_fillrect,
1047  .fb_copyarea = cfb_copyarea,
1048  .fb_imageblit = cfb_imageblit,
1049  .fb_pan_display = s3c_fb_pan_display,
1050  .fb_ioctl = s3c_fb_ioctl,
1051 };
1052 
1059 static void s3c_fb_missing_pixclock(struct fb_videomode *mode)
1060 {
1061  u64 pixclk = 1000000000000ULL;
1062  u32 div;
1063 
1064  div = mode->left_margin + mode->hsync_len + mode->right_margin +
1065  mode->xres;
1066  div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1067  mode->yres;
1068  div *= mode->refresh ? : 60;
1069 
1070  do_div(pixclk, div);
1071 
1072  mode->pixclock = pixclk;
1073 }
1074 
1082 static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
1083  struct s3c_fb_win *win)
1084 {
1085  struct s3c_fb_pd_win *windata = win->windata;
1086  unsigned int real_size, virt_size, size;
1087  struct fb_info *fbi = win->fbinfo;
1088  dma_addr_t map_dma;
1089 
1090  dev_dbg(sfb->dev, "allocating memory for display\n");
1091 
1092  real_size = windata->xres * windata->yres;
1093  virt_size = windata->virtual_x * windata->virtual_y;
1094 
1095  dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1096  real_size, windata->xres, windata->yres,
1097  virt_size, windata->virtual_x, windata->virtual_y);
1098 
1099  size = (real_size > virt_size) ? real_size : virt_size;
1100  size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1101  size /= 8;
1102 
1103  fbi->fix.smem_len = size;
1104  size = PAGE_ALIGN(size);
1105 
1106  dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1107 
1108  fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
1109  &map_dma, GFP_KERNEL);
1110  if (!fbi->screen_base)
1111  return -ENOMEM;
1112 
1113  dev_dbg(sfb->dev, "mapped %x to %p\n",
1114  (unsigned int)map_dma, fbi->screen_base);
1115 
1116  memset(fbi->screen_base, 0x0, size);
1117  fbi->fix.smem_start = map_dma;
1118 
1119  return 0;
1120 }
1121 
1129 static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1130 {
1131  struct fb_info *fbi = win->fbinfo;
1132 
1133  if (fbi->screen_base)
1134  dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1135  fbi->screen_base, fbi->fix.smem_start);
1136 }
1137 
1145 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1146 {
1147  u32 data;
1148 
1149  if (win->fbinfo) {
1150  if (sfb->variant.has_shadowcon) {
1151  data = readl(sfb->regs + SHADOWCON);
1152  data &= ~SHADOWCON_CHx_ENABLE(win->index);
1153  data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1154  writel(data, sfb->regs + SHADOWCON);
1155  }
1157  if (win->fbinfo->cmap.len)
1158  fb_dealloc_cmap(&win->fbinfo->cmap);
1159  s3c_fb_free_memory(sfb, win);
1161  }
1162 }
1163 
1173 static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1174  struct s3c_fb_win_variant *variant,
1175  struct s3c_fb_win **res)
1176 {
1177  struct fb_var_screeninfo *var;
1178  struct fb_videomode initmode;
1179  struct s3c_fb_pd_win *windata;
1180  struct s3c_fb_win *win;
1181  struct fb_info *fbinfo;
1182  int palette_size;
1183  int ret;
1184 
1185  dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1186 
1187  init_waitqueue_head(&sfb->vsync_info.wait);
1188 
1189  palette_size = variant->palette_sz * 4;
1190 
1191  fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1192  palette_size * sizeof(u32), sfb->dev);
1193  if (!fbinfo) {
1194  dev_err(sfb->dev, "failed to allocate framebuffer\n");
1195  return -ENOENT;
1196  }
1197 
1198  windata = sfb->pdata->win[win_no];
1199  initmode = *sfb->pdata->vtiming;
1200 
1201  WARN_ON(windata->max_bpp == 0);
1202  WARN_ON(windata->xres == 0);
1203  WARN_ON(windata->yres == 0);
1204 
1205  win = fbinfo->par;
1206  *res = win;
1207  var = &fbinfo->var;
1208  win->variant = *variant;
1209  win->fbinfo = fbinfo;
1210  win->parent = sfb;
1211  win->windata = windata;
1212  win->index = win_no;
1213  win->palette_buffer = (u32 *)(win + 1);
1214 
1215  ret = s3c_fb_alloc_memory(sfb, win);
1216  if (ret) {
1217  dev_err(sfb->dev, "failed to allocate display memory\n");
1218  return ret;
1219  }
1220 
1221  /* setup the r/b/g positions for the window's palette */
1222  if (win->variant.palette_16bpp) {
1223  /* Set RGB 5:6:5 as default */
1224  win->palette.r.offset = 11;
1225  win->palette.r.length = 5;
1226  win->palette.g.offset = 5;
1227  win->palette.g.length = 6;
1228  win->palette.b.offset = 0;
1229  win->palette.b.length = 5;
1230 
1231  } else {
1232  /* Set 8bpp or 8bpp and 1bit alpha */
1233  win->palette.r.offset = 16;
1234  win->palette.r.length = 8;
1235  win->palette.g.offset = 8;
1236  win->palette.g.length = 8;
1237  win->palette.b.offset = 0;
1238  win->palette.b.length = 8;
1239  }
1240 
1241  /* setup the initial video mode from the window */
1242  initmode.xres = windata->xres;
1243  initmode.yres = windata->yres;
1244  fb_videomode_to_var(&fbinfo->var, &initmode);
1245 
1246  fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
1247  fbinfo->fix.accel = FB_ACCEL_NONE;
1248  fbinfo->var.activate = FB_ACTIVATE_NOW;
1249  fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
1250  fbinfo->var.bits_per_pixel = windata->default_bpp;
1251  fbinfo->fbops = &s3c_fb_ops;
1252  fbinfo->flags = FBINFO_FLAG_DEFAULT;
1253  fbinfo->pseudo_palette = &win->pseudo_palette;
1254 
1255  /* prepare to actually start the framebuffer */
1256 
1257  ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1258  if (ret < 0) {
1259  dev_err(sfb->dev, "check_var failed on initial video params\n");
1260  return ret;
1261  }
1262 
1263  /* create initial colour map */
1264 
1265  ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1266  if (ret == 0)
1267  fb_set_cmap(&fbinfo->cmap, fbinfo);
1268  else
1269  dev_err(sfb->dev, "failed to allocate fb cmap\n");
1270 
1271  s3c_fb_set_par(fbinfo);
1272 
1273  dev_dbg(sfb->dev, "about to register framebuffer\n");
1274 
1275  /* run the check_var and set_par on our configuration. */
1276 
1277  ret = register_framebuffer(fbinfo);
1278  if (ret < 0) {
1279  dev_err(sfb->dev, "failed to register framebuffer\n");
1280  return ret;
1281  }
1282 
1283  dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1284 
1285  return 0;
1286 }
1287 
1294 static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
1295 {
1296  struct fb_videomode *vmode = sfb->pdata->vtiming;
1297  void __iomem *regs = sfb->regs;
1298  int clkdiv;
1299  u32 data;
1300 
1301  if (!vmode->pixclock)
1302  s3c_fb_missing_pixclock(vmode);
1303 
1304  clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
1305 
1306  data = sfb->pdata->vidcon0;
1308 
1309  if (clkdiv > 1)
1310  data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
1311  else
1312  data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
1313 
1314  if (sfb->variant.is_2443)
1315  data |= (1 << 5);
1316  writel(data, regs + VIDCON0);
1317 
1318  data = VIDTCON0_VBPD(vmode->upper_margin - 1) |
1319  VIDTCON0_VFPD(vmode->lower_margin - 1) |
1320  VIDTCON0_VSPW(vmode->vsync_len - 1);
1321  writel(data, regs + sfb->variant.vidtcon);
1322 
1323  data = VIDTCON1_HBPD(vmode->left_margin - 1) |
1324  VIDTCON1_HFPD(vmode->right_margin - 1) |
1325  VIDTCON1_HSPW(vmode->hsync_len - 1);
1326  writel(data, regs + sfb->variant.vidtcon + 4);
1327 
1328  data = VIDTCON2_LINEVAL(vmode->yres - 1) |
1329  VIDTCON2_HOZVAL(vmode->xres - 1) |
1330  VIDTCON2_LINEVAL_E(vmode->yres - 1) |
1331  VIDTCON2_HOZVAL_E(vmode->xres - 1);
1332  writel(data, regs + sfb->variant.vidtcon + 8);
1333 }
1334 
1342 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1343 {
1344  void __iomem *regs = sfb->regs;
1345  u32 reg;
1346 
1347  writel(0, regs + sfb->variant.wincon + (win * 4));
1348  writel(0, regs + VIDOSD_A(win, sfb->variant));
1349  writel(0, regs + VIDOSD_B(win, sfb->variant));
1350  writel(0, regs + VIDOSD_C(win, sfb->variant));
1351 
1352  if (sfb->variant.has_shadowcon) {
1353  reg = readl(sfb->regs + SHADOWCON);
1354  reg &= ~(SHADOWCON_WINx_PROTECT(win) |
1355  SHADOWCON_CHx_ENABLE(win) |
1357  writel(reg, sfb->regs + SHADOWCON);
1358  }
1359 }
1360 
1361 static int __devinit s3c_fb_probe(struct platform_device *pdev)
1362 {
1363  const struct platform_device_id *platid;
1364  struct s3c_fb_driverdata *fbdrv;
1365  struct device *dev = &pdev->dev;
1366  struct s3c_fb_platdata *pd;
1367  struct s3c_fb *sfb;
1368  struct resource *res;
1369  int win;
1370  int ret = 0;
1371  u32 reg;
1372 
1373  platid = platform_get_device_id(pdev);
1374  fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
1375 
1376  if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1377  dev_err(dev, "too many windows, cannot attach\n");
1378  return -EINVAL;
1379  }
1380 
1381  pd = pdev->dev.platform_data;
1382  if (!pd) {
1383  dev_err(dev, "no platform data specified\n");
1384  return -EINVAL;
1385  }
1386 
1387  sfb = devm_kzalloc(dev, sizeof(struct s3c_fb), GFP_KERNEL);
1388  if (!sfb) {
1389  dev_err(dev, "no memory for framebuffers\n");
1390  return -ENOMEM;
1391  }
1392 
1393  dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1394 
1395  sfb->dev = dev;
1396  sfb->pdata = pd;
1397  sfb->variant = fbdrv->variant;
1398 
1399  spin_lock_init(&sfb->slock);
1400 
1401  sfb->bus_clk = devm_clk_get(dev, "lcd");
1402  if (IS_ERR(sfb->bus_clk)) {
1403  dev_err(dev, "failed to get bus clock\n");
1404  return PTR_ERR(sfb->bus_clk);
1405  }
1406 
1407  clk_prepare_enable(sfb->bus_clk);
1408 
1409  if (!sfb->variant.has_clksel) {
1410  sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1411  if (IS_ERR(sfb->lcd_clk)) {
1412  dev_err(dev, "failed to get lcd clock\n");
1413  ret = PTR_ERR(sfb->lcd_clk);
1414  goto err_bus_clk;
1415  }
1416 
1417  clk_prepare_enable(sfb->lcd_clk);
1418  }
1419 
1420  pm_runtime_enable(sfb->dev);
1421 
1422  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1423  sfb->regs = devm_request_and_ioremap(dev, res);
1424  if (!sfb->regs) {
1425  dev_err(dev, "failed to map registers\n");
1426  ret = -ENXIO;
1427  goto err_lcd_clk;
1428  }
1429 
1430  res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1431  if (!res) {
1432  dev_err(dev, "failed to acquire irq resource\n");
1433  ret = -ENOENT;
1434  goto err_lcd_clk;
1435  }
1436  sfb->irq_no = res->start;
1437  ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,
1438  0, "s3c_fb", sfb);
1439  if (ret) {
1440  dev_err(dev, "irq request failed\n");
1441  goto err_lcd_clk;
1442  }
1443 
1444  dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1445 
1446  platform_set_drvdata(pdev, sfb);
1447  pm_runtime_get_sync(sfb->dev);
1448 
1449  /* setup gpio and output polarity controls */
1450 
1451  pd->setup_gpio();
1452 
1453  writel(pd->vidcon1, sfb->regs + VIDCON1);
1454 
1455  /* set video clock running at under-run */
1456  if (sfb->variant.has_fixvclk) {
1457  reg = readl(sfb->regs + VIDCON1);
1458  reg &= ~VIDCON1_VCLK_MASK;
1459  reg |= VIDCON1_VCLK_RUN;
1460  writel(reg, sfb->regs + VIDCON1);
1461  }
1462 
1463  /* zero all windows before we do anything */
1464 
1465  for (win = 0; win < fbdrv->variant.nr_windows; win++)
1466  s3c_fb_clear_win(sfb, win);
1467 
1468  /* initialise colour key controls */
1469  for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1470  void __iomem *regs = sfb->regs + sfb->variant.keycon;
1471 
1472  regs += (win * 8);
1473  writel(0xffffff, regs + WKEYCON0);
1474  writel(0xffffff, regs + WKEYCON1);
1475  }
1476 
1477  s3c_fb_set_rgb_timing(sfb);
1478 
1479  /* we have the register setup, start allocating framebuffers */
1480 
1481  for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1482  if (!pd->win[win])
1483  continue;
1484 
1485  ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1486  &sfb->windows[win]);
1487  if (ret < 0) {
1488  dev_err(dev, "failed to create window %d\n", win);
1489  for (; win >= 0; win--)
1490  s3c_fb_release_win(sfb, sfb->windows[win]);
1491  goto err_pm_runtime;
1492  }
1493  }
1494 
1495  platform_set_drvdata(pdev, sfb);
1496  pm_runtime_put_sync(sfb->dev);
1497 
1498  return 0;
1499 
1500 err_pm_runtime:
1501  pm_runtime_put_sync(sfb->dev);
1502 
1503 err_lcd_clk:
1504  pm_runtime_disable(sfb->dev);
1505 
1506  if (!sfb->variant.has_clksel)
1507  clk_disable_unprepare(sfb->lcd_clk);
1508 
1509 err_bus_clk:
1510  clk_disable_unprepare(sfb->bus_clk);
1511 
1512  return ret;
1513 }
1514 
1522 static int __devexit s3c_fb_remove(struct platform_device *pdev)
1523 {
1524  struct s3c_fb *sfb = platform_get_drvdata(pdev);
1525  int win;
1526 
1527  pm_runtime_get_sync(sfb->dev);
1528 
1529  for (win = 0; win < S3C_FB_MAX_WIN; win++)
1530  if (sfb->windows[win])
1531  s3c_fb_release_win(sfb, sfb->windows[win]);
1532 
1533  if (!sfb->variant.has_clksel)
1534  clk_disable_unprepare(sfb->lcd_clk);
1535 
1536  clk_disable_unprepare(sfb->bus_clk);
1537 
1538  pm_runtime_put_sync(sfb->dev);
1539  pm_runtime_disable(sfb->dev);
1540 
1541  return 0;
1542 }
1543 
1544 #ifdef CONFIG_PM_SLEEP
1545 static int s3c_fb_suspend(struct device *dev)
1546 {
1547  struct platform_device *pdev = to_platform_device(dev);
1548  struct s3c_fb *sfb = platform_get_drvdata(pdev);
1549  struct s3c_fb_win *win;
1550  int win_no;
1551 
1552  pm_runtime_get_sync(sfb->dev);
1553 
1554  for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1555  win = sfb->windows[win_no];
1556  if (!win)
1557  continue;
1558 
1559  /* use the blank function to push into power-down */
1560  s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1561  }
1562 
1563  if (!sfb->variant.has_clksel)
1564  clk_disable_unprepare(sfb->lcd_clk);
1565 
1566  clk_disable_unprepare(sfb->bus_clk);
1567 
1568  pm_runtime_put_sync(sfb->dev);
1569 
1570  return 0;
1571 }
1572 
1573 static int s3c_fb_resume(struct device *dev)
1574 {
1575  struct platform_device *pdev = to_platform_device(dev);
1576  struct s3c_fb *sfb = platform_get_drvdata(pdev);
1577  struct s3c_fb_platdata *pd = sfb->pdata;
1578  struct s3c_fb_win *win;
1579  int win_no;
1580  u32 reg;
1581 
1582  pm_runtime_get_sync(sfb->dev);
1583 
1584  clk_prepare_enable(sfb->bus_clk);
1585 
1586  if (!sfb->variant.has_clksel)
1587  clk_prepare_enable(sfb->lcd_clk);
1588 
1589  /* setup gpio and output polarity controls */
1590  pd->setup_gpio();
1591  writel(pd->vidcon1, sfb->regs + VIDCON1);
1592 
1593  /* set video clock running at under-run */
1594  if (sfb->variant.has_fixvclk) {
1595  reg = readl(sfb->regs + VIDCON1);
1596  reg &= ~VIDCON1_VCLK_MASK;
1597  reg |= VIDCON1_VCLK_RUN;
1598  writel(reg, sfb->regs + VIDCON1);
1599  }
1600 
1601  /* zero all windows before we do anything */
1602  for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1603  s3c_fb_clear_win(sfb, win_no);
1604 
1605  for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1606  void __iomem *regs = sfb->regs + sfb->variant.keycon;
1607  win = sfb->windows[win_no];
1608  if (!win)
1609  continue;
1610 
1611  shadow_protect_win(win, 1);
1612  regs += (win_no * 8);
1613  writel(0xffffff, regs + WKEYCON0);
1614  writel(0xffffff, regs + WKEYCON1);
1615  shadow_protect_win(win, 0);
1616  }
1617 
1618  s3c_fb_set_rgb_timing(sfb);
1619 
1620  /* restore framebuffers */
1621  for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1622  win = sfb->windows[win_no];
1623  if (!win)
1624  continue;
1625 
1626  dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
1627  s3c_fb_set_par(win->fbinfo);
1628  }
1629 
1630  pm_runtime_put_sync(sfb->dev);
1631 
1632  return 0;
1633 }
1634 #endif
1635 
1636 #ifdef CONFIG_PM_RUNTIME
1637 static int s3c_fb_runtime_suspend(struct device *dev)
1638 {
1639  struct platform_device *pdev = to_platform_device(dev);
1640  struct s3c_fb *sfb = platform_get_drvdata(pdev);
1641 
1642  if (!sfb->variant.has_clksel)
1643  clk_disable_unprepare(sfb->lcd_clk);
1644 
1645  clk_disable_unprepare(sfb->bus_clk);
1646 
1647  return 0;
1648 }
1649 
1650 static int s3c_fb_runtime_resume(struct device *dev)
1651 {
1652  struct platform_device *pdev = to_platform_device(dev);
1653  struct s3c_fb *sfb = platform_get_drvdata(pdev);
1654  struct s3c_fb_platdata *pd = sfb->pdata;
1655 
1656  clk_prepare_enable(sfb->bus_clk);
1657 
1658  if (!sfb->variant.has_clksel)
1659  clk_prepare_enable(sfb->lcd_clk);
1660 
1661  /* setup gpio and output polarity controls */
1662  pd->setup_gpio();
1663  writel(pd->vidcon1, sfb->regs + VIDCON1);
1664 
1665  return 0;
1666 }
1667 #endif
1668 
1669 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1670 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1671 
1672 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1673  [0] = {
1674  .has_osd_c = 1,
1675  .osd_size_off = 0x8,
1676  .palette_sz = 256,
1677  .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1678  VALID_BPP(18) | VALID_BPP(24)),
1679  },
1680  [1] = {
1681  .has_osd_c = 1,
1682  .has_osd_d = 1,
1683  .osd_size_off = 0xc,
1684  .has_osd_alpha = 1,
1685  .palette_sz = 256,
1686  .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1687  VALID_BPP(18) | VALID_BPP(19) |
1688  VALID_BPP(24) | VALID_BPP(25) |
1689  VALID_BPP(28)),
1690  },
1691  [2] = {
1692  .has_osd_c = 1,
1693  .has_osd_d = 1,
1694  .osd_size_off = 0xc,
1695  .has_osd_alpha = 1,
1696  .palette_sz = 16,
1697  .palette_16bpp = 1,
1698  .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1699  VALID_BPP(18) | VALID_BPP(19) |
1700  VALID_BPP(24) | VALID_BPP(25) |
1701  VALID_BPP(28)),
1702  },
1703  [3] = {
1704  .has_osd_c = 1,
1705  .has_osd_alpha = 1,
1706  .palette_sz = 16,
1707  .palette_16bpp = 1,
1708  .valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
1709  VALID_BPP(18) | VALID_BPP(19) |
1710  VALID_BPP(24) | VALID_BPP(25) |
1711  VALID_BPP(28)),
1712  },
1713  [4] = {
1714  .has_osd_c = 1,
1715  .has_osd_alpha = 1,
1716  .palette_sz = 4,
1717  .palette_16bpp = 1,
1718  .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
1719  VALID_BPP(16) | VALID_BPP(18) |
1720  VALID_BPP(19) | VALID_BPP(24) |
1721  VALID_BPP(25) | VALID_BPP(28)),
1722  },
1723 };
1724 
1725 static struct s3c_fb_win_variant s3c_fb_data_s5p_wins[] = {
1726  [0] = {
1727  .has_osd_c = 1,
1728  .osd_size_off = 0x8,
1729  .palette_sz = 256,
1730  .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1731  VALID_BPP(15) | VALID_BPP(16) |
1732  VALID_BPP(18) | VALID_BPP(19) |
1733  VALID_BPP(24) | VALID_BPP(25) |
1734  VALID_BPP(32)),
1735  },
1736  [1] = {
1737  .has_osd_c = 1,
1738  .has_osd_d = 1,
1739  .osd_size_off = 0xc,
1740  .has_osd_alpha = 1,
1741  .palette_sz = 256,
1742  .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1743  VALID_BPP(15) | VALID_BPP(16) |
1744  VALID_BPP(18) | VALID_BPP(19) |
1745  VALID_BPP(24) | VALID_BPP(25) |
1746  VALID_BPP(32)),
1747  },
1748  [2] = {
1749  .has_osd_c = 1,
1750  .has_osd_d = 1,
1751  .osd_size_off = 0xc,
1752  .has_osd_alpha = 1,
1753  .palette_sz = 256,
1754  .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1755  VALID_BPP(15) | VALID_BPP(16) |
1756  VALID_BPP(18) | VALID_BPP(19) |
1757  VALID_BPP(24) | VALID_BPP(25) |
1758  VALID_BPP(32)),
1759  },
1760  [3] = {
1761  .has_osd_c = 1,
1762  .has_osd_alpha = 1,
1763  .palette_sz = 256,
1764  .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1765  VALID_BPP(15) | VALID_BPP(16) |
1766  VALID_BPP(18) | VALID_BPP(19) |
1767  VALID_BPP(24) | VALID_BPP(25) |
1768  VALID_BPP(32)),
1769  },
1770  [4] = {
1771  .has_osd_c = 1,
1772  .has_osd_alpha = 1,
1773  .palette_sz = 256,
1774  .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1775  VALID_BPP(15) | VALID_BPP(16) |
1776  VALID_BPP(18) | VALID_BPP(19) |
1777  VALID_BPP(24) | VALID_BPP(25) |
1778  VALID_BPP(32)),
1779  },
1780 };
1781 
1782 static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1783  .variant = {
1784  .nr_windows = 5,
1785  .vidtcon = VIDTCON0,
1786  .wincon = WINCON(0),
1787  .winmap = WINxMAP(0),
1788  .keycon = WKEYCON,
1789  .osd = VIDOSD_BASE,
1790  .osd_stride = 16,
1791  .buf_start = VIDW_BUF_START(0),
1792  .buf_size = VIDW_BUF_SIZE(0),
1793  .buf_end = VIDW_BUF_END(0),
1794 
1795  .palette = {
1796  [0] = 0x400,
1797  [1] = 0x800,
1798  [2] = 0x300,
1799  [3] = 0x320,
1800  [4] = 0x340,
1801  },
1802 
1803  .has_prtcon = 1,
1804  .has_clksel = 1,
1805  },
1806  .win[0] = &s3c_fb_data_64xx_wins[0],
1807  .win[1] = &s3c_fb_data_64xx_wins[1],
1808  .win[2] = &s3c_fb_data_64xx_wins[2],
1809  .win[3] = &s3c_fb_data_64xx_wins[3],
1810  .win[4] = &s3c_fb_data_64xx_wins[4],
1811 };
1812 
1813 static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
1814  .variant = {
1815  .nr_windows = 5,
1816  .vidtcon = VIDTCON0,
1817  .wincon = WINCON(0),
1818  .winmap = WINxMAP(0),
1819  .keycon = WKEYCON,
1820  .osd = VIDOSD_BASE,
1821  .osd_stride = 16,
1822  .buf_start = VIDW_BUF_START(0),
1823  .buf_size = VIDW_BUF_SIZE(0),
1824  .buf_end = VIDW_BUF_END(0),
1825 
1826  .palette = {
1827  [0] = 0x2400,
1828  [1] = 0x2800,
1829  [2] = 0x2c00,
1830  [3] = 0x3000,
1831  [4] = 0x3400,
1832  },
1833 
1834  .has_prtcon = 1,
1835  .has_blendcon = 1,
1836  .has_clksel = 1,
1837  },
1838  .win[0] = &s3c_fb_data_s5p_wins[0],
1839  .win[1] = &s3c_fb_data_s5p_wins[1],
1840  .win[2] = &s3c_fb_data_s5p_wins[2],
1841  .win[3] = &s3c_fb_data_s5p_wins[3],
1842  .win[4] = &s3c_fb_data_s5p_wins[4],
1843 };
1844 
1845 static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
1846  .variant = {
1847  .nr_windows = 5,
1848  .vidtcon = VIDTCON0,
1849  .wincon = WINCON(0),
1850  .winmap = WINxMAP(0),
1851  .keycon = WKEYCON,
1852  .osd = VIDOSD_BASE,
1853  .osd_stride = 16,
1854  .buf_start = VIDW_BUF_START(0),
1855  .buf_size = VIDW_BUF_SIZE(0),
1856  .buf_end = VIDW_BUF_END(0),
1857 
1858  .palette = {
1859  [0] = 0x2400,
1860  [1] = 0x2800,
1861  [2] = 0x2c00,
1862  [3] = 0x3000,
1863  [4] = 0x3400,
1864  },
1865 
1866  .has_shadowcon = 1,
1867  .has_blendcon = 1,
1868  .has_clksel = 1,
1869  .has_fixvclk = 1,
1870  },
1871  .win[0] = &s3c_fb_data_s5p_wins[0],
1872  .win[1] = &s3c_fb_data_s5p_wins[1],
1873  .win[2] = &s3c_fb_data_s5p_wins[2],
1874  .win[3] = &s3c_fb_data_s5p_wins[3],
1875  .win[4] = &s3c_fb_data_s5p_wins[4],
1876 };
1877 
1878 static struct s3c_fb_driverdata s3c_fb_data_exynos4 = {
1879  .variant = {
1880  .nr_windows = 5,
1881  .vidtcon = VIDTCON0,
1882  .wincon = WINCON(0),
1883  .winmap = WINxMAP(0),
1884  .keycon = WKEYCON,
1885  .osd = VIDOSD_BASE,
1886  .osd_stride = 16,
1887  .buf_start = VIDW_BUF_START(0),
1888  .buf_size = VIDW_BUF_SIZE(0),
1889  .buf_end = VIDW_BUF_END(0),
1890 
1891  .palette = {
1892  [0] = 0x2400,
1893  [1] = 0x2800,
1894  [2] = 0x2c00,
1895  [3] = 0x3000,
1896  [4] = 0x3400,
1897  },
1898 
1899  .has_shadowcon = 1,
1900  .has_blendcon = 1,
1901  .has_fixvclk = 1,
1902  },
1903  .win[0] = &s3c_fb_data_s5p_wins[0],
1904  .win[1] = &s3c_fb_data_s5p_wins[1],
1905  .win[2] = &s3c_fb_data_s5p_wins[2],
1906  .win[3] = &s3c_fb_data_s5p_wins[3],
1907  .win[4] = &s3c_fb_data_s5p_wins[4],
1908 };
1909 
1910 static struct s3c_fb_driverdata s3c_fb_data_exynos5 = {
1911  .variant = {
1912  .nr_windows = 5,
1913  .vidtcon = VIDTCON0,
1914  .wincon = WINCON(0),
1915  .winmap = WINxMAP(0),
1916  .keycon = WKEYCON,
1917  .osd = VIDOSD_BASE,
1918  .osd_stride = 16,
1919  .buf_start = VIDW_BUF_START(0),
1920  .buf_size = VIDW_BUF_SIZE(0),
1921  .buf_end = VIDW_BUF_END(0),
1922 
1923  .palette = {
1924  [0] = 0x2400,
1925  [1] = 0x2800,
1926  [2] = 0x2c00,
1927  [3] = 0x3000,
1928  [4] = 0x3400,
1929  },
1930  .has_shadowcon = 1,
1931  .has_blendcon = 1,
1932  .has_fixvclk = 1,
1933  },
1934  .win[0] = &s3c_fb_data_s5p_wins[0],
1935  .win[1] = &s3c_fb_data_s5p_wins[1],
1936  .win[2] = &s3c_fb_data_s5p_wins[2],
1937  .win[3] = &s3c_fb_data_s5p_wins[3],
1938  .win[4] = &s3c_fb_data_s5p_wins[4],
1939 };
1940 
1941 /* S3C2443/S3C2416 style hardware */
1942 static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1943  .variant = {
1944  .nr_windows = 2,
1945  .is_2443 = 1,
1946 
1947  .vidtcon = 0x08,
1948  .wincon = 0x14,
1949  .winmap = 0xd0,
1950  .keycon = 0xb0,
1951  .osd = 0x28,
1952  .osd_stride = 12,
1953  .buf_start = 0x64,
1954  .buf_size = 0x94,
1955  .buf_end = 0x7c,
1956 
1957  .palette = {
1958  [0] = 0x400,
1959  [1] = 0x800,
1960  },
1961  .has_clksel = 1,
1962  },
1963  .win[0] = &(struct s3c_fb_win_variant) {
1964  .palette_sz = 256,
1965  .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1966  },
1967  .win[1] = &(struct s3c_fb_win_variant) {
1968  .has_osd_c = 1,
1969  .has_osd_alpha = 1,
1970  .palette_sz = 256,
1971  .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1972  VALID_BPP(18) | VALID_BPP(19) |
1973  VALID_BPP(24) | VALID_BPP(25) |
1974  VALID_BPP(28)),
1975  },
1976 };
1977 
1978 static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = {
1979  .variant = {
1980  .nr_windows = 3,
1981  .vidtcon = VIDTCON0,
1982  .wincon = WINCON(0),
1983  .winmap = WINxMAP(0),
1984  .keycon = WKEYCON,
1985  .osd = VIDOSD_BASE,
1986  .osd_stride = 16,
1987  .buf_start = VIDW_BUF_START(0),
1988  .buf_size = VIDW_BUF_SIZE(0),
1989  .buf_end = VIDW_BUF_END(0),
1990 
1991  .palette = {
1992  [0] = 0x2400,
1993  [1] = 0x2800,
1994  [2] = 0x2c00,
1995  },
1996 
1997  .has_blendcon = 1,
1998  .has_fixvclk = 1,
1999  },
2000  .win[0] = &s3c_fb_data_s5p_wins[0],
2001  .win[1] = &s3c_fb_data_s5p_wins[1],
2002  .win[2] = &s3c_fb_data_s5p_wins[2],
2003 };
2004 
2005 static struct platform_device_id s3c_fb_driver_ids[] = {
2006  {
2007  .name = "s3c-fb",
2008  .driver_data = (unsigned long)&s3c_fb_data_64xx,
2009  }, {
2010  .name = "s5pc100-fb",
2011  .driver_data = (unsigned long)&s3c_fb_data_s5pc100,
2012  }, {
2013  .name = "s5pv210-fb",
2014  .driver_data = (unsigned long)&s3c_fb_data_s5pv210,
2015  }, {
2016  .name = "exynos4-fb",
2017  .driver_data = (unsigned long)&s3c_fb_data_exynos4,
2018  }, {
2019  .name = "exynos5-fb",
2020  .driver_data = (unsigned long)&s3c_fb_data_exynos5,
2021  }, {
2022  .name = "s3c2443-fb",
2023  .driver_data = (unsigned long)&s3c_fb_data_s3c2443,
2024  }, {
2025  .name = "s5p64x0-fb",
2026  .driver_data = (unsigned long)&s3c_fb_data_s5p64x0,
2027  },
2028  {},
2029 };
2030 MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
2031 
2032 static const struct dev_pm_ops s3cfb_pm_ops = {
2033  SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
2034  SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
2035  NULL)
2036 };
2037 
2038 static struct platform_driver s3c_fb_driver = {
2039  .probe = s3c_fb_probe,
2040  .remove = __devexit_p(s3c_fb_remove),
2041  .id_table = s3c_fb_driver_ids,
2042  .driver = {
2043  .name = "s3c-fb",
2044  .owner = THIS_MODULE,
2045  .pm = &s3cfb_pm_ops,
2046  },
2047 };
2048 
2049 module_platform_driver(s3c_fb_driver);
2050 
2051 MODULE_AUTHOR("Ben Dooks <[email protected]>");
2052 MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
2053 MODULE_LICENSE("GPL");
2054 MODULE_ALIAS("platform:s3c-fb");