#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/edac.h>
#include <linux/mmzone.h>
#include <linux/smp.h>
#include <linux/bitmap.h>
#include <linux/math64.h>
#include <asm/processor.h>
#include <asm/mce.h>
#include "edac_core.h"

Data Structures
struct	sbridge_info

struct	sbridge_channel

struct	pci_id_descr

struct	pci_id_table

struct	sbridge_dev

struct	sbridge_pvt

Macros
#define	SBRIDGE_REVISION " Ver: 1.0.0 "

#define	EDAC_MOD_STR "sbridge_edac"

#define	sbridge_printk(level, fmt, arg...) edac_printk(level, "sbridge", fmt, ##arg)

#define	sbridge_mc_printk(mci, level, fmt, arg...) edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)

#define	GET_BITFIELD(v, lo, hi) (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */

#define	PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */

#define	MAX_SAD ARRAY_SIZE(dram_rule)

#define	SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) \| 0x3ffffff)

#define	DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)

#define	INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)

#define	DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)

#define	MAX_INTERLEAVE ARRAY_SIZE(interleave_list)

#define	SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)

#define	SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)

#define	SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)

#define	SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)

#define	SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)

#define	SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)

#define	SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)

#define	SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)

#define	TOLM 0x80

#define	TOHM 0x84

#define	GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) \| 0x3ffffff)

#define	GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) \| 0x3ffffff)

#define	SAD_TARGET 0xf0

#define	SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)

#define	SAD_CONTROL 0xf4

#define	NODE_ID(reg) GET_BITFIELD(reg, 0, 2)

#define	MAX_TAD ARRAY_SIZE(tad_dram_rule)

#define	TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) \| 0x3ffffff)

#define	TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)

#define	TAD_CH(reg) GET_BITFIELD(reg, 8, 9)

#define	TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)

#define	TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)

#define	TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)

#define	TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)

#define	MCMTR 0x7c

#define	IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)

#define	IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)

#define	IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)

#define	RASENABLES 0xac

#define	IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)

#define	RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)

#define	IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)

#define	RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)

#define	RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)

#define	COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)

#define	CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)

#define	TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)

#define	MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)

#define	IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)

#define	RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)

#define	RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)\| 0x1fffffff)

#define	MAX_RIR_WAY 8

#define	RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)

#define	RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)

#define	RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)

#define	RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)

#define	RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)

#define	RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)

#define	RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)

#define	RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)

#define	RANK_CFG_A 0x0328

#define	IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)

#define	NUM_CHANNELS 4

#define	MAX_DIMMS 3 /* Max DIMMS per channel */

#define	PCI_DESCR(device, function, device_id)

#define	PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }

Functions
struct mem_ctl_info *	get_mci_for_node_id (u8 node_id)

	MODULE_DEVICE_TABLE (pci, sbridge_pci_tbl)

	module_init (sbridge_init)

	module_exit (sbridge_exit)

	module_param (edac_op_state, int, 0444)

	MODULE_PARM_DESC (edac_op_state,"EDAC Error Reporting state: 0=Poll,1=NMI")

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Mauro Carvalho Chehab <[email protected]>")

	MODULE_AUTHOR ("Red Hat Inc. (http://www.redhat.com)")

	MODULE_DESCRIPTION ("MC Driver for Intel Sandy Bridge memory controllers - "SBRIDGE_REVISION)

Macro Definition Documentation

#define CHN_IDX_OFFSET ( reg ) GET_BITFIELD(reg, 28, 29)

Definition at line 215 of file sb_edac.c.

#define COL_WIDTH_BITS ( mtr ) GET_BITFIELD(mtr, 0, 1)

Definition at line 208 of file sb_edac.c.

#define DRAM_ATTR ( reg ) GET_BITFIELD(reg, 2, 3)

Definition at line 93 of file sb_edac.c.

#define DRAM_RULE_ENABLE ( reg ) GET_BITFIELD(reg, 0, 0)

Definition at line 95 of file sb_edac.c.

#define EDAC_MOD_STR "sbridge_edac"

Definition at line 38 of file sb_edac.c.

#define GET_BITFIELD	(	v,
		lo,
		hi
	)	(((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))

Definition at line 52 of file sb_edac.c.

#define GET_TOHM ( reg ) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)

Definition at line 156 of file sb_edac.c.

#define GET_TOLM ( reg ) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)

Definition at line 155 of file sb_edac.c.

#define INTERLEAVE_MODE ( reg ) GET_BITFIELD(reg, 1, 1)

Definition at line 94 of file sb_edac.c.

#define IS_CLOSE_PG ( mcmtr ) GET_BITFIELD(mcmtr, 0, 0)

Definition at line 191 of file sb_edac.c.

#define IS_DIMM_PRESENT ( mtr ) GET_BITFIELD(mtr, 14, 14)

Definition at line 205 of file sb_edac.c.

#define IS_ECC_ENABLED ( mcmtr ) GET_BITFIELD(mcmtr, 2, 2)

Definition at line 189 of file sb_edac.c.

#define IS_LOCKSTEP_ENABLED ( mcmtr ) GET_BITFIELD(mcmtr, 1, 1)

Definition at line 190 of file sb_edac.c.

#define IS_MIRROR_ENABLED ( reg ) GET_BITFIELD(reg, 0, 0)

Definition at line 196 of file sb_edac.c.

#define IS_RDIMM_ENABLED ( reg ) GET_BITFIELD(reg, 11, 11)

Definition at line 267 of file sb_edac.c.

#define IS_RIR_VALID ( reg ) GET_BITFIELD(reg, 31, 31)

Definition at line 223 of file sb_edac.c.

#define MAX_DIMMS 3 /* Max DIMMS per channel */

Definition at line 274 of file sb_edac.c.

#define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)

Definition at line 115 of file sb_edac.c.

#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)

Definition at line 221 of file sb_edac.c.

#define MAX_RIR_WAY 8

Definition at line 227 of file sb_edac.c.

#define MAX_SAD ARRAY_SIZE(dram_rule)

Definition at line 90 of file sb_edac.c.

#define MAX_TAD ARRAY_SIZE(tad_dram_rule)

Definition at line 175 of file sb_edac.c.

#define MCMTR 0x7c

Definition at line 187 of file sb_edac.c.

#define NODE_ID ( reg ) GET_BITFIELD(reg, 0, 2)

Definition at line 166 of file sb_edac.c.

#define NUM_CHANNELS 4

Definition at line 273 of file sb_edac.c.

#define PCI_DESCR	(	device,
		function,
		device_id
	)

Value:

.dev = (device),            \
    .func = (function),         \
    .dev_id = (device_id)

Definition at line 334 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */

Definition at line 66 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */

Definition at line 74 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */

Definition at line 80 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */

Definition at line 81 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */

Definition at line 82 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */

Definition at line 83 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */

Definition at line 67 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */

Definition at line 69 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */

Definition at line 68 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */

Definition at line 70 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */

Definition at line 71 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */

Definition at line 72 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */

Definition at line 73 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */

Definition at line 64 of file sb_edac.c.

#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */

Definition at line 65 of file sb_edac.c.

#define PCI_ID_TABLE_ENTRY ( A ) { .descr=A, .n_devs = ARRAY_SIZE(A) }

Definition at line 360 of file sb_edac.c.

#define RANK_CFG_A 0x0328

Definition at line 265 of file sb_edac.c.

#define RANK_CNT_BITS ( mtr ) GET_BITFIELD(mtr, 12, 13)

Definition at line 206 of file sb_edac.c.

#define RANK_DISABLE ( mtr ) GET_BITFIELD(mtr, 16, 19)

Definition at line 204 of file sb_edac.c.

#define RANK_EVEN_ERR_CNT ( reg ) GET_BITFIELD(reg, 0, 14)

Definition at line 253 of file sb_edac.c.

#define RANK_EVEN_ERR_THRSLD ( reg ) GET_BITFIELD(reg, 0, 14)

Definition at line 260 of file sb_edac.c.

#define RANK_EVEN_OV ( reg ) GET_BITFIELD(reg, 15, 15)

Definition at line 252 of file sb_edac.c.

#define RANK_ODD_ERR_CNT ( reg ) GET_BITFIELD(reg, 16, 30)

Definition at line 251 of file sb_edac.c.

#define RANK_ODD_ERR_THRSLD ( reg ) GET_BITFIELD(reg, 16, 30)

Definition at line 259 of file sb_edac.c.

#define RANK_ODD_OV ( reg ) GET_BITFIELD(reg, 31, 31)

Definition at line 250 of file sb_edac.c.

#define RANK_WIDTH_BITS ( mtr ) GET_BITFIELD(mtr, 2, 4)

Definition at line 207 of file sb_edac.c.

#define RASENABLES 0xac

Definition at line 195 of file sb_edac.c.

#define RIR_LIMIT ( reg ) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)

Definition at line 225 of file sb_edac.c.

#define RIR_OFFSET ( reg ) GET_BITFIELD(reg, 2, 14)

Definition at line 238 of file sb_edac.c.

#define RIR_RNK_TGT ( reg ) GET_BITFIELD(reg, 16, 19)

Definition at line 237 of file sb_edac.c.

#define RIR_WAY ( reg ) GET_BITFIELD(reg, 28, 29)

Definition at line 224 of file sb_edac.c.

#define SAD_CONTROL 0xf4

Definition at line 164 of file sb_edac.c.

#define SAD_LIMIT ( reg ) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)

Definition at line 92 of file sb_edac.c.

#define SAD_PKG0 ( reg ) GET_BITFIELD(reg, 0, 2)

Definition at line 117 of file sb_edac.c.

#define SAD_PKG1 ( reg ) GET_BITFIELD(reg, 3, 5)

Definition at line 118 of file sb_edac.c.

#define SAD_PKG2 ( reg ) GET_BITFIELD(reg, 8, 10)

Definition at line 119 of file sb_edac.c.

#define SAD_PKG3 ( reg ) GET_BITFIELD(reg, 11, 13)

Definition at line 120 of file sb_edac.c.

#define SAD_PKG4 ( reg ) GET_BITFIELD(reg, 16, 18)

Definition at line 121 of file sb_edac.c.

#define SAD_PKG5 ( reg ) GET_BITFIELD(reg, 19, 21)

Definition at line 122 of file sb_edac.c.

#define SAD_PKG6 ( reg ) GET_BITFIELD(reg, 24, 26)

Definition at line 123 of file sb_edac.c.

#define SAD_PKG7 ( reg ) GET_BITFIELD(reg, 27, 29)

Definition at line 124 of file sb_edac.c.

#define SAD_TARGET 0xf0

Definition at line 160 of file sb_edac.c.

#define sbridge_mc_printk	(	mci,
		level,
		fmt,
		arg...
	)	edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)

Definition at line 46 of file sb_edac.c.

#define sbridge_printk	(	level,
		fmt,
		arg...
	)	edac_printk(level, "sbridge", fmt, ##arg)

Definition at line 43 of file sb_edac.c.

#define SBRIDGE_REVISION " Ver: 1.0.0 "

Definition at line 37 of file sb_edac.c.

#define SOURCE_ID ( reg ) GET_BITFIELD(reg, 9, 11)

Definition at line 162 of file sb_edac.c.

#define TAD_CH ( reg ) GET_BITFIELD(reg, 8, 9)

Definition at line 179 of file sb_edac.c.

#define TAD_LIMIT ( reg ) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)

Definition at line 177 of file sb_edac.c.

#define TAD_OFFSET ( reg ) (GET_BITFIELD(reg, 6, 25) << 26)

Definition at line 216 of file sb_edac.c.

#define TAD_SOCK ( reg ) GET_BITFIELD(reg, 10, 11)

Definition at line 178 of file sb_edac.c.

#define TAD_TGT0 ( reg ) GET_BITFIELD(reg, 0, 1)

Definition at line 183 of file sb_edac.c.

#define TAD_TGT1 ( reg ) GET_BITFIELD(reg, 2, 3)

Definition at line 182 of file sb_edac.c.

#define TAD_TGT2 ( reg ) GET_BITFIELD(reg, 4, 5)

Definition at line 181 of file sb_edac.c.

#define TAD_TGT3 ( reg ) GET_BITFIELD(reg, 6, 7)

Definition at line 180 of file sb_edac.c.

#define TOHM 0x84

Definition at line 153 of file sb_edac.c.

#define TOLM 0x80

Definition at line 152 of file sb_edac.c.

Function Documentation

struct mem_ctl_info* get_mci_for_node_id ( u8 node_id )

read

Definition at line 774 of file sb_edac.c.

MODULE_AUTHOR ( "Mauro Carvalho Chehab <[email protected]>" )

MODULE_AUTHOR ( "Red Hat Inc. (http://www.redhat.com)" )

MODULE_DESCRIPTION ( "MC Driver for Intel Sandy Bridge memory controllers - " SBRIDGE_REVISION )

MODULE_DEVICE_TABLE	(	pci	,
		sbridge_pci_tbl
	)

module_exit ( sbridge_exit )

module_init ( sbridge_init )

MODULE_LICENSE ( "GPL" )

module_param	(	edac_op_state	,
		int	,
		0444
	)

MODULE_PARM_DESC	(	edac_op_state	,
		"EDAC Error Reporting state:	0 = `Poll`
	)

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation