Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
sdhci-pci.c
Go to the documentation of this file.
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2  *
3  * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or (at
8  * your option) any later version.
9  *
10  * Thanks to the following companies for their support:
11  *
12  * - JMicron (hardware and technical support)
13  */
14 
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mmc/sdhci-pci-data.h>
28 
29 #include "sdhci.h"
30 
31 /*
32  * PCI device IDs
33  */
34 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
35 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
36 
37 /*
38  * PCI registers
39  */
40 
41 #define PCI_SDHCI_IFPIO 0x00
42 #define PCI_SDHCI_IFDMA 0x01
43 #define PCI_SDHCI_IFVENDOR 0x02
44 
45 #define PCI_SLOT_INFO 0x40 /* 8 bits */
46 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
47 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
48 
49 #define MAX_SLOTS 8
50 
51 struct sdhci_pci_chip;
52 struct sdhci_pci_slot;
53 
54 struct sdhci_pci_fixes {
55  unsigned int quirks;
56  unsigned int quirks2;
57  bool allow_runtime_pm;
58 
59  int (*probe) (struct sdhci_pci_chip *);
60 
61  int (*probe_slot) (struct sdhci_pci_slot *);
62  void (*remove_slot) (struct sdhci_pci_slot *, int);
63 
64  int (*suspend) (struct sdhci_pci_chip *);
65  int (*resume) (struct sdhci_pci_chip *);
66 };
67 
68 struct sdhci_pci_slot {
69  struct sdhci_pci_chip *chip;
70  struct sdhci_host *host;
71  struct sdhci_pci_data *data;
72 
73  int pci_bar;
74  int rst_n_gpio;
75  int cd_gpio;
76  int cd_irq;
77 };
78 
79 struct sdhci_pci_chip {
80  struct pci_dev *pdev;
81 
82  unsigned int quirks;
83  unsigned int quirks2;
84  bool allow_runtime_pm;
85  const struct sdhci_pci_fixes *fixes;
86 
87  int num_slots; /* Slots on controller */
88  struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
89 };
90 
91 
92 /*****************************************************************************\
93  * *
94  * Hardware specific quirk handling *
95  * *
96 \*****************************************************************************/
97 
98 static int ricoh_probe(struct sdhci_pci_chip *chip)
99 {
100  if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
101  chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
102  chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
103  return 0;
104 }
105 
106 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
107 {
108  slot->host->caps =
109  ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
110  & SDHCI_TIMEOUT_CLK_MASK) |
111 
112  ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
113  & SDHCI_CLOCK_BASE_MASK) |
114 
115  SDHCI_TIMEOUT_CLK_UNIT |
116  SDHCI_CAN_VDD_330 |
117  SDHCI_CAN_DO_SDMA;
118  return 0;
119 }
120 
121 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
122 {
123  /* Apply a delay to allow controller to settle */
124  /* Otherwise it becomes confused if card state changed
125  during suspend */
126  msleep(500);
127  return 0;
128 }
129 
130 static const struct sdhci_pci_fixes sdhci_ricoh = {
131  .probe = ricoh_probe,
132  .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
133  SDHCI_QUIRK_FORCE_DMA |
134  SDHCI_QUIRK_CLOCK_BEFORE_RESET,
135 };
136 
137 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
138  .probe_slot = ricoh_mmc_probe_slot,
139  .resume = ricoh_mmc_resume,
140  .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
141  SDHCI_QUIRK_CLOCK_BEFORE_RESET |
142  SDHCI_QUIRK_NO_CARD_NO_RESET |
143  SDHCI_QUIRK_MISSING_CAPS
144 };
145 
146 static const struct sdhci_pci_fixes sdhci_ene_712 = {
147  .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
148  SDHCI_QUIRK_BROKEN_DMA,
149 };
150 
151 static const struct sdhci_pci_fixes sdhci_ene_714 = {
152  .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
153  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
154  SDHCI_QUIRK_BROKEN_DMA,
155 };
156 
157 static const struct sdhci_pci_fixes sdhci_cafe = {
158  .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
159  SDHCI_QUIRK_NO_BUSY_IRQ |
160  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
161  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
162 };
163 
164 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
165 {
166  slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
167  return 0;
168 }
169 
170 /*
171  * ADMA operation is disabled for Moorestown platform due to
172  * hardware bugs.
173  */
174 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
175 {
176  /*
177  * slots number is fixed here for MRST as SDIO3/5 are never used and
178  * have hardware bugs.
179  */
180  chip->num_slots = 1;
181  return 0;
182 }
183 
184 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
185 {
186  slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
187  return 0;
188 }
189 
190 #ifdef CONFIG_PM_RUNTIME
191 
192 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
193 {
194  struct sdhci_pci_slot *slot = dev_id;
195  struct sdhci_host *host = slot->host;
196 
197  mmc_detect_change(host->mmc, msecs_to_jiffies(200));
198  return IRQ_HANDLED;
199 }
200 
201 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
202 {
203  int err, irq, gpio = slot->cd_gpio;
204 
205  slot->cd_gpio = -EINVAL;
206  slot->cd_irq = -EINVAL;
207 
208  if (!gpio_is_valid(gpio))
209  return;
210 
211  err = gpio_request(gpio, "sd_cd");
212  if (err < 0)
213  goto out;
214 
215  err = gpio_direction_input(gpio);
216  if (err < 0)
217  goto out_free;
218 
219  irq = gpio_to_irq(gpio);
220  if (irq < 0)
221  goto out_free;
222 
223  err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
224  IRQF_TRIGGER_FALLING, "sd_cd", slot);
225  if (err)
226  goto out_free;
227 
228  slot->cd_gpio = gpio;
229  slot->cd_irq = irq;
230 
231  return;
232 
233 out_free:
234  gpio_free(gpio);
235 out:
236  dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
237 }
238 
239 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
240 {
241  if (slot->cd_irq >= 0)
242  free_irq(slot->cd_irq, slot);
243  if (gpio_is_valid(slot->cd_gpio))
244  gpio_free(slot->cd_gpio);
245 }
246 
247 #else
248 
249 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
250 {
251 }
252 
253 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
254 {
255 }
256 
257 #endif
258 
259 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
260 {
261  slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
262  slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
263  MMC_CAP2_HC_ERASE_SZ;
264  return 0;
265 }
266 
267 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
268 {
269  slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
270  return 0;
271 }
272 
273 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
274  .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
275  .probe_slot = mrst_hc_probe_slot,
276 };
277 
278 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
279  .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
280  .probe = mrst_hc_probe,
281 };
282 
283 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
284  .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
285  .allow_runtime_pm = true,
286 };
287 
288 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
289  .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
290  .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
291  .allow_runtime_pm = true,
292  .probe_slot = mfd_sdio_probe_slot,
293 };
294 
295 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
296  .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
297  .allow_runtime_pm = true,
298  .probe_slot = mfd_emmc_probe_slot,
299 };
300 
301 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
302  .quirks = SDHCI_QUIRK_BROKEN_ADMA,
303  .probe_slot = pch_hc_probe_slot,
304 };
305 
306 /* O2Micro extra registers */
307 #define O2_SD_LOCK_WP 0xD3
308 #define O2_SD_MULTI_VCC3V 0xEE
309 #define O2_SD_CLKREQ 0xEC
310 #define O2_SD_CAPS 0xE0
311 #define O2_SD_ADMA1 0xE2
312 #define O2_SD_ADMA2 0xE7
313 #define O2_SD_INF_MOD 0xF1
314 
315 static int o2_probe(struct sdhci_pci_chip *chip)
316 {
317  int ret;
318  u8 scratch;
319 
320  switch (chip->pdev->device) {
321  case PCI_DEVICE_ID_O2_8220:
322  case PCI_DEVICE_ID_O2_8221:
323  case PCI_DEVICE_ID_O2_8320:
324  case PCI_DEVICE_ID_O2_8321:
325  /* This extra setup is required due to broken ADMA. */
326  ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
327  if (ret)
328  return ret;
329  scratch &= 0x7f;
330  pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
331 
332  /* Set Multi 3 to VCC3V# */
333  pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
334 
335  /* Disable CLK_REQ# support after media DET */
336  ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
337  if (ret)
338  return ret;
339  scratch |= 0x20;
340  pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
341 
342  /* Choose capabilities, enable SDMA. We have to write 0x01
343  * to the capabilities register first to unlock it.
344  */
345  ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
346  if (ret)
347  return ret;
348  scratch |= 0x01;
349  pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
350  pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
351 
352  /* Disable ADMA1/2 */
353  pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
354  pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
355 
356  /* Disable the infinite transfer mode */
357  ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
358  if (ret)
359  return ret;
360  scratch |= 0x08;
361  pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
362 
363  /* Lock WP */
364  ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
365  if (ret)
366  return ret;
367  scratch |= 0x80;
368  pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
369  }
370 
371  return 0;
372 }
373 
374 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
375 {
376  u8 scratch;
377  int ret;
378 
379  ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
380  if (ret)
381  return ret;
382 
383  /*
384  * Turn PMOS on [bit 0], set over current detection to 2.4 V
385  * [bit 1:2] and enable over current debouncing [bit 6].
386  */
387  if (on)
388  scratch |= 0x47;
389  else
390  scratch &= ~0x47;
391 
392  ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
393  if (ret)
394  return ret;
395 
396  return 0;
397 }
398 
399 static int jmicron_probe(struct sdhci_pci_chip *chip)
400 {
401  int ret;
402  u16 mmcdev = 0;
403 
404  if (chip->pdev->revision == 0) {
405  chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
406  SDHCI_QUIRK_32BIT_DMA_SIZE |
407  SDHCI_QUIRK_32BIT_ADMA_SIZE |
408  SDHCI_QUIRK_RESET_AFTER_REQUEST |
409  SDHCI_QUIRK_BROKEN_SMALL_PIO;
410  }
411 
412  /*
413  * JMicron chips can have two interfaces to the same hardware
414  * in order to work around limitations in Microsoft's driver.
415  * We need to make sure we only bind to one of them.
416  *
417  * This code assumes two things:
418  *
419  * 1. The PCI code adds subfunctions in order.
420  *
421  * 2. The MMC interface has a lower subfunction number
422  * than the SD interface.
423  */
424  if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
425  mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
426  else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
427  mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
428 
429  if (mmcdev) {
430  struct pci_dev *sd_dev;
431 
432  sd_dev = NULL;
433  while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
434  mmcdev, sd_dev)) != NULL) {
435  if ((PCI_SLOT(chip->pdev->devfn) ==
436  PCI_SLOT(sd_dev->devfn)) &&
437  (chip->pdev->bus == sd_dev->bus))
438  break;
439  }
440 
441  if (sd_dev) {
442  pci_dev_put(sd_dev);
443  dev_info(&chip->pdev->dev, "Refusing to bind to "
444  "secondary interface.\n");
445  return -ENODEV;
446  }
447  }
448 
449  /*
450  * JMicron chips need a bit of a nudge to enable the power
451  * output pins.
452  */
453  ret = jmicron_pmos(chip, 1);
454  if (ret) {
455  dev_err(&chip->pdev->dev, "Failure enabling card power\n");
456  return ret;
457  }
458 
459  /* quirk for unsable RO-detection on JM388 chips */
460  if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
461  chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
462  chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
463 
464  return 0;
465 }
466 
467 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
468 {
469  u8 scratch;
470 
471  scratch = readb(host->ioaddr + 0xC0);
472 
473  if (on)
474  scratch |= 0x01;
475  else
476  scratch &= ~0x01;
477 
478  writeb(scratch, host->ioaddr + 0xC0);
479 }
480 
481 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
482 {
483  if (slot->chip->pdev->revision == 0) {
484  u16 version;
485 
486  version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
487  version = (version & SDHCI_VENDOR_VER_MASK) >>
488  SDHCI_VENDOR_VER_SHIFT;
489 
490  /*
491  * Older versions of the chip have lots of nasty glitches
492  * in the ADMA engine. It's best just to avoid it
493  * completely.
494  */
495  if (version < 0xAC)
496  slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
497  }
498 
499  /* JM388 MMC doesn't support 1.8V while SD supports it */
500  if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
501  slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
502  MMC_VDD_29_30 | MMC_VDD_30_31 |
503  MMC_VDD_165_195; /* allow 1.8V */
504  slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
505  MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
506  }
507 
508  /*
509  * The secondary interface requires a bit set to get the
510  * interrupts.
511  */
512  if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
513  slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
514  jmicron_enable_mmc(slot->host, 1);
515 
516  slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
517 
518  return 0;
519 }
520 
521 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
522 {
523  if (dead)
524  return;
525 
526  if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
527  slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
528  jmicron_enable_mmc(slot->host, 0);
529 }
530 
531 static int jmicron_suspend(struct sdhci_pci_chip *chip)
532 {
533  int i;
534 
535  if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
536  chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
537  for (i = 0; i < chip->num_slots; i++)
538  jmicron_enable_mmc(chip->slots[i]->host, 0);
539  }
540 
541  return 0;
542 }
543 
544 static int jmicron_resume(struct sdhci_pci_chip *chip)
545 {
546  int ret, i;
547 
548  if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
549  chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
550  for (i = 0; i < chip->num_slots; i++)
551  jmicron_enable_mmc(chip->slots[i]->host, 1);
552  }
553 
554  ret = jmicron_pmos(chip, 1);
555  if (ret) {
556  dev_err(&chip->pdev->dev, "Failure enabling card power\n");
557  return ret;
558  }
559 
560  return 0;
561 }
562 
563 static const struct sdhci_pci_fixes sdhci_o2 = {
564  .probe = o2_probe,
565 };
566 
567 static const struct sdhci_pci_fixes sdhci_jmicron = {
568  .probe = jmicron_probe,
569 
570  .probe_slot = jmicron_probe_slot,
571  .remove_slot = jmicron_remove_slot,
572 
573  .suspend = jmicron_suspend,
574  .resume = jmicron_resume,
575 };
576 
577 /* SysKonnect CardBus2SDIO extra registers */
578 #define SYSKT_CTRL 0x200
579 #define SYSKT_RDFIFO_STAT 0x204
580 #define SYSKT_WRFIFO_STAT 0x208
581 #define SYSKT_POWER_DATA 0x20c
582 #define SYSKT_POWER_330 0xef
583 #define SYSKT_POWER_300 0xf8
584 #define SYSKT_POWER_184 0xcc
585 #define SYSKT_POWER_CMD 0x20d
586 #define SYSKT_POWER_START (1 << 7)
587 #define SYSKT_POWER_STATUS 0x20e
588 #define SYSKT_POWER_STATUS_OK (1 << 0)
589 #define SYSKT_BOARD_REV 0x210
590 #define SYSKT_CHIP_REV 0x211
591 #define SYSKT_CONF_DATA 0x212
592 #define SYSKT_CONF_DATA_1V8 (1 << 2)
593 #define SYSKT_CONF_DATA_2V5 (1 << 1)
594 #define SYSKT_CONF_DATA_3V3 (1 << 0)
595 
596 static int syskt_probe(struct sdhci_pci_chip *chip)
597 {
598  if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
599  chip->pdev->class &= ~0x0000FF;
600  chip->pdev->class |= PCI_SDHCI_IFDMA;
601  }
602  return 0;
603 }
604 
605 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
606 {
607  int tm, ps;
608 
609  u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
610  u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
611  dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
612  "board rev %d.%d, chip rev %d.%d\n",
613  board_rev >> 4, board_rev & 0xf,
614  chip_rev >> 4, chip_rev & 0xf);
615  if (chip_rev >= 0x20)
616  slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
617 
618  writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
619  writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
620  udelay(50);
621  tm = 10; /* Wait max 1 ms */
622  do {
623  ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
624  if (ps & SYSKT_POWER_STATUS_OK)
625  break;
626  udelay(100);
627  } while (--tm);
628  if (!tm) {
629  dev_err(&slot->chip->pdev->dev,
630  "power regulator never stabilized");
631  writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
632  return -ENODEV;
633  }
634 
635  return 0;
636 }
637 
638 static const struct sdhci_pci_fixes sdhci_syskt = {
639  .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
640  .probe = syskt_probe,
641  .probe_slot = syskt_probe_slot,
642 };
643 
644 static int via_probe(struct sdhci_pci_chip *chip)
645 {
646  if (chip->pdev->revision == 0x10)
647  chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
648 
649  return 0;
650 }
651 
652 static const struct sdhci_pci_fixes sdhci_via = {
653  .probe = via_probe,
654 };
655 
656 static const struct pci_device_id pci_ids[] __devinitconst = {
657  {
658  .vendor = PCI_VENDOR_ID_RICOH,
659  .device = PCI_DEVICE_ID_RICOH_R5C822,
660  .subvendor = PCI_ANY_ID,
661  .subdevice = PCI_ANY_ID,
662  .driver_data = (kernel_ulong_t)&sdhci_ricoh,
663  },
664 
665  {
666  .vendor = PCI_VENDOR_ID_RICOH,
667  .device = 0x843,
668  .subvendor = PCI_ANY_ID,
669  .subdevice = PCI_ANY_ID,
670  .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
671  },
672 
673  {
674  .vendor = PCI_VENDOR_ID_RICOH,
675  .device = 0xe822,
676  .subvendor = PCI_ANY_ID,
677  .subdevice = PCI_ANY_ID,
678  .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
679  },
680 
681  {
682  .vendor = PCI_VENDOR_ID_RICOH,
683  .device = 0xe823,
684  .subvendor = PCI_ANY_ID,
685  .subdevice = PCI_ANY_ID,
686  .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
687  },
688 
689  {
690  .vendor = PCI_VENDOR_ID_ENE,
691  .device = PCI_DEVICE_ID_ENE_CB712_SD,
692  .subvendor = PCI_ANY_ID,
693  .subdevice = PCI_ANY_ID,
694  .driver_data = (kernel_ulong_t)&sdhci_ene_712,
695  },
696 
697  {
698  .vendor = PCI_VENDOR_ID_ENE,
699  .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
700  .subvendor = PCI_ANY_ID,
701  .subdevice = PCI_ANY_ID,
702  .driver_data = (kernel_ulong_t)&sdhci_ene_712,
703  },
704 
705  {
706  .vendor = PCI_VENDOR_ID_ENE,
707  .device = PCI_DEVICE_ID_ENE_CB714_SD,
708  .subvendor = PCI_ANY_ID,
709  .subdevice = PCI_ANY_ID,
710  .driver_data = (kernel_ulong_t)&sdhci_ene_714,
711  },
712 
713  {
714  .vendor = PCI_VENDOR_ID_ENE,
715  .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
716  .subvendor = PCI_ANY_ID,
717  .subdevice = PCI_ANY_ID,
718  .driver_data = (kernel_ulong_t)&sdhci_ene_714,
719  },
720 
721  {
722  .vendor = PCI_VENDOR_ID_MARVELL,
723  .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
724  .subvendor = PCI_ANY_ID,
725  .subdevice = PCI_ANY_ID,
726  .driver_data = (kernel_ulong_t)&sdhci_cafe,
727  },
728 
729  {
730  .vendor = PCI_VENDOR_ID_JMICRON,
731  .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
732  .subvendor = PCI_ANY_ID,
733  .subdevice = PCI_ANY_ID,
734  .driver_data = (kernel_ulong_t)&sdhci_jmicron,
735  },
736 
737  {
738  .vendor = PCI_VENDOR_ID_JMICRON,
739  .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
740  .subvendor = PCI_ANY_ID,
741  .subdevice = PCI_ANY_ID,
742  .driver_data = (kernel_ulong_t)&sdhci_jmicron,
743  },
744 
745  {
746  .vendor = PCI_VENDOR_ID_JMICRON,
747  .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
748  .subvendor = PCI_ANY_ID,
749  .subdevice = PCI_ANY_ID,
750  .driver_data = (kernel_ulong_t)&sdhci_jmicron,
751  },
752 
753  {
754  .vendor = PCI_VENDOR_ID_JMICRON,
755  .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
756  .subvendor = PCI_ANY_ID,
757  .subdevice = PCI_ANY_ID,
758  .driver_data = (kernel_ulong_t)&sdhci_jmicron,
759  },
760 
761  {
762  .vendor = PCI_VENDOR_ID_SYSKONNECT,
763  .device = 0x8000,
764  .subvendor = PCI_ANY_ID,
765  .subdevice = PCI_ANY_ID,
766  .driver_data = (kernel_ulong_t)&sdhci_syskt,
767  },
768 
769  {
770  .vendor = PCI_VENDOR_ID_VIA,
771  .device = 0x95d0,
772  .subvendor = PCI_ANY_ID,
773  .subdevice = PCI_ANY_ID,
774  .driver_data = (kernel_ulong_t)&sdhci_via,
775  },
776 
777  {
778  .vendor = PCI_VENDOR_ID_INTEL,
779  .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
780  .subvendor = PCI_ANY_ID,
781  .subdevice = PCI_ANY_ID,
782  .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
783  },
784 
785  {
786  .vendor = PCI_VENDOR_ID_INTEL,
787  .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
788  .subvendor = PCI_ANY_ID,
789  .subdevice = PCI_ANY_ID,
790  .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
791  },
792 
793  {
794  .vendor = PCI_VENDOR_ID_INTEL,
795  .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
796  .subvendor = PCI_ANY_ID,
797  .subdevice = PCI_ANY_ID,
798  .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
799  },
800 
801  {
802  .vendor = PCI_VENDOR_ID_INTEL,
803  .device = PCI_DEVICE_ID_INTEL_MFD_SD,
804  .subvendor = PCI_ANY_ID,
805  .subdevice = PCI_ANY_ID,
806  .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
807  },
808 
809  {
810  .vendor = PCI_VENDOR_ID_INTEL,
811  .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
812  .subvendor = PCI_ANY_ID,
813  .subdevice = PCI_ANY_ID,
814  .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
815  },
816 
817  {
818  .vendor = PCI_VENDOR_ID_INTEL,
819  .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
820  .subvendor = PCI_ANY_ID,
821  .subdevice = PCI_ANY_ID,
822  .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
823  },
824 
825  {
826  .vendor = PCI_VENDOR_ID_INTEL,
827  .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
828  .subvendor = PCI_ANY_ID,
829  .subdevice = PCI_ANY_ID,
830  .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
831  },
832 
833  {
834  .vendor = PCI_VENDOR_ID_INTEL,
835  .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
836  .subvendor = PCI_ANY_ID,
837  .subdevice = PCI_ANY_ID,
838  .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
839  },
840 
841  {
842  .vendor = PCI_VENDOR_ID_INTEL,
843  .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
844  .subvendor = PCI_ANY_ID,
845  .subdevice = PCI_ANY_ID,
846  .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
847  },
848 
849  {
850  .vendor = PCI_VENDOR_ID_INTEL,
851  .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
852  .subvendor = PCI_ANY_ID,
853  .subdevice = PCI_ANY_ID,
854  .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
855  },
856 
857  {
858  .vendor = PCI_VENDOR_ID_O2,
859  .device = PCI_DEVICE_ID_O2_8120,
860  .subvendor = PCI_ANY_ID,
861  .subdevice = PCI_ANY_ID,
862  .driver_data = (kernel_ulong_t)&sdhci_o2,
863  },
864 
865  {
866  .vendor = PCI_VENDOR_ID_O2,
867  .device = PCI_DEVICE_ID_O2_8220,
868  .subvendor = PCI_ANY_ID,
869  .subdevice = PCI_ANY_ID,
870  .driver_data = (kernel_ulong_t)&sdhci_o2,
871  },
872 
873  {
874  .vendor = PCI_VENDOR_ID_O2,
875  .device = PCI_DEVICE_ID_O2_8221,
876  .subvendor = PCI_ANY_ID,
877  .subdevice = PCI_ANY_ID,
878  .driver_data = (kernel_ulong_t)&sdhci_o2,
879  },
880 
881  {
882  .vendor = PCI_VENDOR_ID_O2,
883  .device = PCI_DEVICE_ID_O2_8320,
884  .subvendor = PCI_ANY_ID,
885  .subdevice = PCI_ANY_ID,
886  .driver_data = (kernel_ulong_t)&sdhci_o2,
887  },
888 
889  {
890  .vendor = PCI_VENDOR_ID_O2,
891  .device = PCI_DEVICE_ID_O2_8321,
892  .subvendor = PCI_ANY_ID,
893  .subdevice = PCI_ANY_ID,
894  .driver_data = (kernel_ulong_t)&sdhci_o2,
895  },
896 
897  { /* Generic SD host controller */
898  PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
899  },
900 
901  { /* end: all zeroes */ },
902 };
903 
904 MODULE_DEVICE_TABLE(pci, pci_ids);
905 
906 /*****************************************************************************\
907  * *
908  * SDHCI core callbacks *
909  * *
910 \*****************************************************************************/
911 
912 static int sdhci_pci_enable_dma(struct sdhci_host *host)
913 {
914  struct sdhci_pci_slot *slot;
915  struct pci_dev *pdev;
916  int ret;
917 
918  slot = sdhci_priv(host);
919  pdev = slot->chip->pdev;
920 
921  if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
922  ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
923  (host->flags & SDHCI_USE_SDMA)) {
924  dev_warn(&pdev->dev, "Will use DMA mode even though HW "
925  "doesn't fully claim to support it.\n");
926  }
927 
928  ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
929  if (ret)
930  return ret;
931 
932  pci_set_master(pdev);
933 
934  return 0;
935 }
936 
937 static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
938 {
939  u8 ctrl;
940 
941  ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
942 
943  switch (width) {
944  case MMC_BUS_WIDTH_8:
945  ctrl |= SDHCI_CTRL_8BITBUS;
946  ctrl &= ~SDHCI_CTRL_4BITBUS;
947  break;
948  case MMC_BUS_WIDTH_4:
949  ctrl |= SDHCI_CTRL_4BITBUS;
950  ctrl &= ~SDHCI_CTRL_8BITBUS;
951  break;
952  default:
953  ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
954  break;
955  }
956 
957  sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
958 
959  return 0;
960 }
961 
962 static void sdhci_pci_hw_reset(struct sdhci_host *host)
963 {
964  struct sdhci_pci_slot *slot = sdhci_priv(host);
965  int rst_n_gpio = slot->rst_n_gpio;
966 
967  if (!gpio_is_valid(rst_n_gpio))
968  return;
969  gpio_set_value_cansleep(rst_n_gpio, 0);
970  /* For eMMC, minimum is 1us but give it 10us for good measure */
971  udelay(10);
972  gpio_set_value_cansleep(rst_n_gpio, 1);
973  /* For eMMC, minimum is 200us but give it 300us for good measure */
974  usleep_range(300, 1000);
975 }
976 
977 static struct sdhci_ops sdhci_pci_ops = {
978  .enable_dma = sdhci_pci_enable_dma,
979  .platform_8bit_width = sdhci_pci_8bit_width,
980  .hw_reset = sdhci_pci_hw_reset,
981 };
982 
983 /*****************************************************************************\
984  * *
985  * Suspend/resume *
986  * *
987 \*****************************************************************************/
988 
989 #ifdef CONFIG_PM
990 
991 static int sdhci_pci_suspend(struct device *dev)
992 {
993  struct pci_dev *pdev = to_pci_dev(dev);
994  struct sdhci_pci_chip *chip;
995  struct sdhci_pci_slot *slot;
996  mmc_pm_flag_t slot_pm_flags;
997  mmc_pm_flag_t pm_flags = 0;
998  int i, ret;
999 
1000  chip = pci_get_drvdata(pdev);
1001  if (!chip)
1002  return 0;
1003 
1004  for (i = 0; i < chip->num_slots; i++) {
1005  slot = chip->slots[i];
1006  if (!slot)
1007  continue;
1008 
1009  ret = sdhci_suspend_host(slot->host);
1010 
1011  if (ret)
1012  goto err_pci_suspend;
1013 
1014  slot_pm_flags = slot->host->mmc->pm_flags;
1015  if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1016  sdhci_enable_irq_wakeups(slot->host);
1017 
1018  pm_flags |= slot_pm_flags;
1019  }
1020 
1021  if (chip->fixes && chip->fixes->suspend) {
1022  ret = chip->fixes->suspend(chip);
1023  if (ret)
1024  goto err_pci_suspend;
1025  }
1026 
1027  pci_save_state(pdev);
1028  if (pm_flags & MMC_PM_KEEP_POWER) {
1029  if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1030  pci_pme_active(pdev, true);
1031  pci_enable_wake(pdev, PCI_D3hot, 1);
1032  }
1033  pci_set_power_state(pdev, PCI_D3hot);
1034  } else {
1035  pci_enable_wake(pdev, PCI_D3hot, 0);
1036  pci_disable_device(pdev);
1037  pci_set_power_state(pdev, PCI_D3hot);
1038  }
1039 
1040  return 0;
1041 
1042 err_pci_suspend:
1043  while (--i >= 0)
1044  sdhci_resume_host(chip->slots[i]->host);
1045  return ret;
1046 }
1047 
1048 static int sdhci_pci_resume(struct device *dev)
1049 {
1050  struct pci_dev *pdev = to_pci_dev(dev);
1051  struct sdhci_pci_chip *chip;
1052  struct sdhci_pci_slot *slot;
1053  int i, ret;
1054 
1055  chip = pci_get_drvdata(pdev);
1056  if (!chip)
1057  return 0;
1058 
1059  pci_set_power_state(pdev, PCI_D0);
1060  pci_restore_state(pdev);
1061  ret = pci_enable_device(pdev);
1062  if (ret)
1063  return ret;
1064 
1065  if (chip->fixes && chip->fixes->resume) {
1066  ret = chip->fixes->resume(chip);
1067  if (ret)
1068  return ret;
1069  }
1070 
1071  for (i = 0; i < chip->num_slots; i++) {
1072  slot = chip->slots[i];
1073  if (!slot)
1074  continue;
1075 
1076  ret = sdhci_resume_host(slot->host);
1077  if (ret)
1078  return ret;
1079  }
1080 
1081  return 0;
1082 }
1083 
1084 #else /* CONFIG_PM */
1085 
1086 #define sdhci_pci_suspend NULL
1087 #define sdhci_pci_resume NULL
1088 
1089 #endif /* CONFIG_PM */
1090 
1091 #ifdef CONFIG_PM_RUNTIME
1092 
1093 static int sdhci_pci_runtime_suspend(struct device *dev)
1094 {
1095  struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1096  struct sdhci_pci_chip *chip;
1097  struct sdhci_pci_slot *slot;
1098  int i, ret;
1099 
1100  chip = pci_get_drvdata(pdev);
1101  if (!chip)
1102  return 0;
1103 
1104  for (i = 0; i < chip->num_slots; i++) {
1105  slot = chip->slots[i];
1106  if (!slot)
1107  continue;
1108 
1109  ret = sdhci_runtime_suspend_host(slot->host);
1110 
1111  if (ret)
1112  goto err_pci_runtime_suspend;
1113  }
1114 
1115  if (chip->fixes && chip->fixes->suspend) {
1116  ret = chip->fixes->suspend(chip);
1117  if (ret)
1118  goto err_pci_runtime_suspend;
1119  }
1120 
1121  return 0;
1122 
1123 err_pci_runtime_suspend:
1124  while (--i >= 0)
1125  sdhci_runtime_resume_host(chip->slots[i]->host);
1126  return ret;
1127 }
1128 
1129 static int sdhci_pci_runtime_resume(struct device *dev)
1130 {
1131  struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1132  struct sdhci_pci_chip *chip;
1133  struct sdhci_pci_slot *slot;
1134  int i, ret;
1135 
1136  chip = pci_get_drvdata(pdev);
1137  if (!chip)
1138  return 0;
1139 
1140  if (chip->fixes && chip->fixes->resume) {
1141  ret = chip->fixes->resume(chip);
1142  if (ret)
1143  return ret;
1144  }
1145 
1146  for (i = 0; i < chip->num_slots; i++) {
1147  slot = chip->slots[i];
1148  if (!slot)
1149  continue;
1150 
1151  ret = sdhci_runtime_resume_host(slot->host);
1152  if (ret)
1153  return ret;
1154  }
1155 
1156  return 0;
1157 }
1158 
1159 static int sdhci_pci_runtime_idle(struct device *dev)
1160 {
1161  return 0;
1162 }
1163 
1164 #else
1165 
1166 #define sdhci_pci_runtime_suspend NULL
1167 #define sdhci_pci_runtime_resume NULL
1168 #define sdhci_pci_runtime_idle NULL
1169 
1170 #endif
1171 
1172 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1173  .suspend = sdhci_pci_suspend,
1174  .resume = sdhci_pci_resume,
1175  .runtime_suspend = sdhci_pci_runtime_suspend,
1176  .runtime_resume = sdhci_pci_runtime_resume,
1177  .runtime_idle = sdhci_pci_runtime_idle,
1178 };
1179 
1180 /*****************************************************************************\
1181  * *
1182  * Device probing/removal *
1183  * *
1184 \*****************************************************************************/
1185 
1186 static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
1187  struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1188  int slotno)
1189 {
1190  struct sdhci_pci_slot *slot;
1191  struct sdhci_host *host;
1192  int ret, bar = first_bar + slotno;
1193 
1194  if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1195  dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1196  return ERR_PTR(-ENODEV);
1197  }
1198 
1199  if (pci_resource_len(pdev, bar) < 0x100) {
1200  dev_err(&pdev->dev, "Invalid iomem size. You may "
1201  "experience problems.\n");
1202  }
1203 
1204  if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1205  dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1206  return ERR_PTR(-ENODEV);
1207  }
1208 
1209  if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1210  dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1211  return ERR_PTR(-ENODEV);
1212  }
1213 
1214  host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1215  if (IS_ERR(host)) {
1216  dev_err(&pdev->dev, "cannot allocate host\n");
1217  return ERR_CAST(host);
1218  }
1219 
1220  slot = sdhci_priv(host);
1221 
1222  slot->chip = chip;
1223  slot->host = host;
1224  slot->pci_bar = bar;
1225  slot->rst_n_gpio = -EINVAL;
1226  slot->cd_gpio = -EINVAL;
1227 
1228  /* Retrieve platform data if there is any */
1229  if (*sdhci_pci_get_data)
1230  slot->data = sdhci_pci_get_data(pdev, slotno);
1231 
1232  if (slot->data) {
1233  if (slot->data->setup) {
1234  ret = slot->data->setup(slot->data);
1235  if (ret) {
1236  dev_err(&pdev->dev, "platform setup failed\n");
1237  goto free;
1238  }
1239  }
1240  slot->rst_n_gpio = slot->data->rst_n_gpio;
1241  slot->cd_gpio = slot->data->cd_gpio;
1242  }
1243 
1244  host->hw_name = "PCI";
1245  host->ops = &sdhci_pci_ops;
1246  host->quirks = chip->quirks;
1247  host->quirks2 = chip->quirks2;
1248 
1249  host->irq = pdev->irq;
1250 
1251  ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1252  if (ret) {
1253  dev_err(&pdev->dev, "cannot request region\n");
1254  goto cleanup;
1255  }
1256 
1257  host->ioaddr = pci_ioremap_bar(pdev, bar);
1258  if (!host->ioaddr) {
1259  dev_err(&pdev->dev, "failed to remap registers\n");
1260  ret = -ENOMEM;
1261  goto release;
1262  }
1263 
1264  if (chip->fixes && chip->fixes->probe_slot) {
1265  ret = chip->fixes->probe_slot(slot);
1266  if (ret)
1267  goto unmap;
1268  }
1269 
1270  if (gpio_is_valid(slot->rst_n_gpio)) {
1271  if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1272  gpio_direction_output(slot->rst_n_gpio, 1);
1273  slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1274  } else {
1275  dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1276  slot->rst_n_gpio = -EINVAL;
1277  }
1278  }
1279 
1280  host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1281 
1282  ret = sdhci_add_host(host);
1283  if (ret)
1284  goto remove;
1285 
1286  sdhci_pci_add_own_cd(slot);
1287 
1288  return slot;
1289 
1290 remove:
1291  if (gpio_is_valid(slot->rst_n_gpio))
1292  gpio_free(slot->rst_n_gpio);
1293 
1294  if (chip->fixes && chip->fixes->remove_slot)
1295  chip->fixes->remove_slot(slot, 0);
1296 
1297 unmap:
1298  iounmap(host->ioaddr);
1299 
1300 release:
1301  pci_release_region(pdev, bar);
1302 
1303 cleanup:
1304  if (slot->data && slot->data->cleanup)
1305  slot->data->cleanup(slot->data);
1306 
1307 free:
1308  sdhci_free_host(host);
1309 
1310  return ERR_PTR(ret);
1311 }
1312 
1313 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1314 {
1315  int dead;
1316  u32 scratch;
1317 
1318  sdhci_pci_remove_own_cd(slot);
1319 
1320  dead = 0;
1321  scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1322  if (scratch == (u32)-1)
1323  dead = 1;
1324 
1325  sdhci_remove_host(slot->host, dead);
1326 
1327  if (gpio_is_valid(slot->rst_n_gpio))
1328  gpio_free(slot->rst_n_gpio);
1329 
1330  if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1331  slot->chip->fixes->remove_slot(slot, dead);
1332 
1333  if (slot->data && slot->data->cleanup)
1334  slot->data->cleanup(slot->data);
1335 
1336  pci_release_region(slot->chip->pdev, slot->pci_bar);
1337 
1338  sdhci_free_host(slot->host);
1339 }
1340 
1341 static void __devinit sdhci_pci_runtime_pm_allow(struct device *dev)
1342 {
1343  pm_runtime_put_noidle(dev);
1344  pm_runtime_allow(dev);
1345  pm_runtime_set_autosuspend_delay(dev, 50);
1346  pm_runtime_use_autosuspend(dev);
1347  pm_suspend_ignore_children(dev, 1);
1348 }
1349 
1350 static void __devexit sdhci_pci_runtime_pm_forbid(struct device *dev)
1351 {
1352  pm_runtime_forbid(dev);
1353  pm_runtime_get_noresume(dev);
1354 }
1355 
1356 static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1357  const struct pci_device_id *ent)
1358 {
1359  struct sdhci_pci_chip *chip;
1360  struct sdhci_pci_slot *slot;
1361 
1362  u8 slots, first_bar;
1363  int ret, i;
1364 
1365  BUG_ON(pdev == NULL);
1366  BUG_ON(ent == NULL);
1367 
1368  dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1369  (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1370 
1371  ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1372  if (ret)
1373  return ret;
1374 
1375  slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1376  dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1377  if (slots == 0)
1378  return -ENODEV;
1379 
1380  BUG_ON(slots > MAX_SLOTS);
1381 
1382  ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1383  if (ret)
1384  return ret;
1385 
1386  first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1387 
1388  if (first_bar > 5) {
1389  dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1390  return -ENODEV;
1391  }
1392 
1393  ret = pci_enable_device(pdev);
1394  if (ret)
1395  return ret;
1396 
1397  chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1398  if (!chip) {
1399  ret = -ENOMEM;
1400  goto err;
1401  }
1402 
1403  chip->pdev = pdev;
1404  chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1405  if (chip->fixes) {
1406  chip->quirks = chip->fixes->quirks;
1407  chip->quirks2 = chip->fixes->quirks2;
1408  chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1409  }
1410  chip->num_slots = slots;
1411 
1412  pci_set_drvdata(pdev, chip);
1413 
1414  if (chip->fixes && chip->fixes->probe) {
1415  ret = chip->fixes->probe(chip);
1416  if (ret)
1417  goto free;
1418  }
1419 
1420  slots = chip->num_slots; /* Quirk may have changed this */
1421 
1422  for (i = 0; i < slots; i++) {
1423  slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1424  if (IS_ERR(slot)) {
1425  for (i--; i >= 0; i--)
1426  sdhci_pci_remove_slot(chip->slots[i]);
1427  ret = PTR_ERR(slot);
1428  goto free;
1429  }
1430 
1431  chip->slots[i] = slot;
1432  }
1433 
1434  if (chip->allow_runtime_pm)
1435  sdhci_pci_runtime_pm_allow(&pdev->dev);
1436 
1437  return 0;
1438 
1439 free:
1440  pci_set_drvdata(pdev, NULL);
1441  kfree(chip);
1442 
1443 err:
1444  pci_disable_device(pdev);
1445  return ret;
1446 }
1447 
1448 static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1449 {
1450  int i;
1451  struct sdhci_pci_chip *chip;
1452 
1453  chip = pci_get_drvdata(pdev);
1454 
1455  if (chip) {
1456  if (chip->allow_runtime_pm)
1457  sdhci_pci_runtime_pm_forbid(&pdev->dev);
1458 
1459  for (i = 0; i < chip->num_slots; i++)
1460  sdhci_pci_remove_slot(chip->slots[i]);
1461 
1462  pci_set_drvdata(pdev, NULL);
1463  kfree(chip);
1464  }
1465 
1466  pci_disable_device(pdev);
1467 }
1468 
1469 static struct pci_driver sdhci_driver = {
1470  .name = "sdhci-pci",
1471  .id_table = pci_ids,
1472  .probe = sdhci_pci_probe,
1473  .remove = __devexit_p(sdhci_pci_remove),
1474  .driver = {
1475  .pm = &sdhci_pci_pm_ops
1476  },
1477 };
1478 
1479 module_pci_driver(sdhci_driver);
1480 
1481 MODULE_AUTHOR("Pierre Ossman <[email protected]>");
1482 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1483 MODULE_LICENSE("GPL");
Generated on Thu Jan 10 2013 13:55:57 for Linux Kernel by   doxygen 1.8.2