Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
setup-sh7372.c
Go to the documentation of this file.
1 /*
2  * sh7372 processor support
3  *
4  * Copyright (C) 2010 Magnus Damm
5  * Copyright (C) 2008 Yoshihiro Shimoda
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19  */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
29 #include <linux/io.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <mach/dma-register.h>
37 #include <mach/hardware.h>
38 #include <mach/irqs.h>
39 #include <mach/sh7372.h>
40 #include <mach/common.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/time.h>
45 
46 static struct map_desc sh7372_io_desc[] __initdata = {
47  /* create a 1:1 entity map for 0xe6xxxxxx
48  * used by CPGA, INTC and PFC.
49  */
50  {
51  .virtual = 0xe6000000,
52  .pfn = __phys_to_pfn(0xe6000000),
53  .length = 256 << 20,
54  .type = MT_DEVICE_NONSHARED
55  },
56 };
57 
58 void __init sh7372_map_io(void)
59 {
60  iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
61 
62  /*
63  * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
64  * enough to allocate the frame buffer memory.
65  */
66  init_consistent_dma_size(12 << 20);
67 }
68 
69 /* SCIFA0 */
70 static struct plat_sci_port scif0_platform_data = {
71  .mapbase = 0xe6c40000,
72  .flags = UPF_BOOT_AUTOCONF,
73  .scscr = SCSCR_RE | SCSCR_TE,
74  .scbrr_algo_id = SCBRR_ALGO_4,
75  .type = PORT_SCIFA,
76  .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
77  evt2irq(0x0c00), evt2irq(0x0c00) },
78 };
79 
80 static struct platform_device scif0_device = {
81  .name = "sh-sci",
82  .id = 0,
83  .dev = {
84  .platform_data = &scif0_platform_data,
85  },
86 };
87 
88 /* SCIFA1 */
89 static struct plat_sci_port scif1_platform_data = {
90  .mapbase = 0xe6c50000,
91  .flags = UPF_BOOT_AUTOCONF,
92  .scscr = SCSCR_RE | SCSCR_TE,
93  .scbrr_algo_id = SCBRR_ALGO_4,
94  .type = PORT_SCIFA,
95  .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
96  evt2irq(0x0c20), evt2irq(0x0c20) },
97 };
98 
99 static struct platform_device scif1_device = {
100  .name = "sh-sci",
101  .id = 1,
102  .dev = {
103  .platform_data = &scif1_platform_data,
104  },
105 };
106 
107 /* SCIFA2 */
108 static struct plat_sci_port scif2_platform_data = {
109  .mapbase = 0xe6c60000,
110  .flags = UPF_BOOT_AUTOCONF,
111  .scscr = SCSCR_RE | SCSCR_TE,
112  .scbrr_algo_id = SCBRR_ALGO_4,
113  .type = PORT_SCIFA,
114  .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
115  evt2irq(0x0c40), evt2irq(0x0c40) },
116 };
117 
118 static struct platform_device scif2_device = {
119  .name = "sh-sci",
120  .id = 2,
121  .dev = {
122  .platform_data = &scif2_platform_data,
123  },
124 };
125 
126 /* SCIFA3 */
127 static struct plat_sci_port scif3_platform_data = {
128  .mapbase = 0xe6c70000,
129  .flags = UPF_BOOT_AUTOCONF,
130  .scscr = SCSCR_RE | SCSCR_TE,
131  .scbrr_algo_id = SCBRR_ALGO_4,
132  .type = PORT_SCIFA,
133  .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
134  evt2irq(0x0c60), evt2irq(0x0c60) },
135 };
136 
137 static struct platform_device scif3_device = {
138  .name = "sh-sci",
139  .id = 3,
140  .dev = {
141  .platform_data = &scif3_platform_data,
142  },
143 };
144 
145 /* SCIFA4 */
146 static struct plat_sci_port scif4_platform_data = {
147  .mapbase = 0xe6c80000,
148  .flags = UPF_BOOT_AUTOCONF,
149  .scscr = SCSCR_RE | SCSCR_TE,
150  .scbrr_algo_id = SCBRR_ALGO_4,
151  .type = PORT_SCIFA,
152  .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
153  evt2irq(0x0d20), evt2irq(0x0d20) },
154 };
155 
156 static struct platform_device scif4_device = {
157  .name = "sh-sci",
158  .id = 4,
159  .dev = {
160  .platform_data = &scif4_platform_data,
161  },
162 };
163 
164 /* SCIFA5 */
165 static struct plat_sci_port scif5_platform_data = {
166  .mapbase = 0xe6cb0000,
167  .flags = UPF_BOOT_AUTOCONF,
168  .scscr = SCSCR_RE | SCSCR_TE,
169  .scbrr_algo_id = SCBRR_ALGO_4,
170  .type = PORT_SCIFA,
171  .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
172  evt2irq(0x0d40), evt2irq(0x0d40) },
173 };
174 
175 static struct platform_device scif5_device = {
176  .name = "sh-sci",
177  .id = 5,
178  .dev = {
179  .platform_data = &scif5_platform_data,
180  },
181 };
182 
183 /* SCIFB */
184 static struct plat_sci_port scif6_platform_data = {
185  .mapbase = 0xe6c30000,
186  .flags = UPF_BOOT_AUTOCONF,
187  .scscr = SCSCR_RE | SCSCR_TE,
188  .scbrr_algo_id = SCBRR_ALGO_4,
189  .type = PORT_SCIFB,
190  .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
191  evt2irq(0x0d60), evt2irq(0x0d60) },
192 };
193 
194 static struct platform_device scif6_device = {
195  .name = "sh-sci",
196  .id = 6,
197  .dev = {
198  .platform_data = &scif6_platform_data,
199  },
200 };
201 
202 /* CMT */
203 static struct sh_timer_config cmt2_platform_data = {
204  .name = "CMT2",
205  .channel_offset = 0x40,
206  .timer_bit = 5,
207  .clockevent_rating = 125,
208  .clocksource_rating = 125,
209 };
210 
211 static struct resource cmt2_resources[] = {
212  [0] = {
213  .name = "CMT2",
214  .start = 0xe6130040,
215  .end = 0xe613004b,
216  .flags = IORESOURCE_MEM,
217  },
218  [1] = {
219  .start = evt2irq(0x0b80), /* CMT2 */
220  .flags = IORESOURCE_IRQ,
221  },
222 };
223 
224 static struct platform_device cmt2_device = {
225  .name = "sh_cmt",
226  .id = 2,
227  .dev = {
228  .platform_data = &cmt2_platform_data,
229  },
230  .resource = cmt2_resources,
231  .num_resources = ARRAY_SIZE(cmt2_resources),
232 };
233 
234 /* TMU */
235 static struct sh_timer_config tmu00_platform_data = {
236  .name = "TMU00",
237  .channel_offset = 0x4,
238  .timer_bit = 0,
239  .clockevent_rating = 200,
240 };
241 
242 static struct resource tmu00_resources[] = {
243  [0] = {
244  .name = "TMU00",
245  .start = 0xfff60008,
246  .end = 0xfff60013,
247  .flags = IORESOURCE_MEM,
248  },
249  [1] = {
250  .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
251  .flags = IORESOURCE_IRQ,
252  },
253 };
254 
255 static struct platform_device tmu00_device = {
256  .name = "sh_tmu",
257  .id = 0,
258  .dev = {
259  .platform_data = &tmu00_platform_data,
260  },
261  .resource = tmu00_resources,
262  .num_resources = ARRAY_SIZE(tmu00_resources),
263 };
264 
265 static struct sh_timer_config tmu01_platform_data = {
266  .name = "TMU01",
267  .channel_offset = 0x10,
268  .timer_bit = 1,
269  .clocksource_rating = 200,
270 };
271 
272 static struct resource tmu01_resources[] = {
273  [0] = {
274  .name = "TMU01",
275  .start = 0xfff60014,
276  .end = 0xfff6001f,
277  .flags = IORESOURCE_MEM,
278  },
279  [1] = {
280  .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
281  .flags = IORESOURCE_IRQ,
282  },
283 };
284 
285 static struct platform_device tmu01_device = {
286  .name = "sh_tmu",
287  .id = 1,
288  .dev = {
289  .platform_data = &tmu01_platform_data,
290  },
291  .resource = tmu01_resources,
292  .num_resources = ARRAY_SIZE(tmu01_resources),
293 };
294 
295 /* I2C */
296 static struct resource iic0_resources[] = {
297  [0] = {
298  .name = "IIC0",
299  .start = 0xFFF20000,
300  .end = 0xFFF20425 - 1,
301  .flags = IORESOURCE_MEM,
302  },
303  [1] = {
304  .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
305  .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
306  .flags = IORESOURCE_IRQ,
307  },
308 };
309 
310 static struct platform_device iic0_device = {
311  .name = "i2c-sh_mobile",
312  .id = 0, /* "i2c0" clock */
313  .num_resources = ARRAY_SIZE(iic0_resources),
314  .resource = iic0_resources,
315 };
316 
317 static struct resource iic1_resources[] = {
318  [0] = {
319  .name = "IIC1",
320  .start = 0xE6C20000,
321  .end = 0xE6C20425 - 1,
322  .flags = IORESOURCE_MEM,
323  },
324  [1] = {
325  .start = evt2irq(0x780), /* IIC1_ALI1 */
326  .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
327  .flags = IORESOURCE_IRQ,
328  },
329 };
330 
331 static struct platform_device iic1_device = {
332  .name = "i2c-sh_mobile",
333  .id = 1, /* "i2c1" clock */
334  .num_resources = ARRAY_SIZE(iic1_resources),
335  .resource = iic1_resources,
336 };
337 
338 /* DMA */
339 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
340  {
341  .slave_id = SHDMA_SLAVE_SCIF0_TX,
342  .addr = 0xe6c40020,
343  .chcr = CHCR_TX(XMIT_SZ_8BIT),
344  .mid_rid = 0x21,
345  }, {
346  .slave_id = SHDMA_SLAVE_SCIF0_RX,
347  .addr = 0xe6c40024,
348  .chcr = CHCR_RX(XMIT_SZ_8BIT),
349  .mid_rid = 0x22,
350  }, {
351  .slave_id = SHDMA_SLAVE_SCIF1_TX,
352  .addr = 0xe6c50020,
353  .chcr = CHCR_TX(XMIT_SZ_8BIT),
354  .mid_rid = 0x25,
355  }, {
356  .slave_id = SHDMA_SLAVE_SCIF1_RX,
357  .addr = 0xe6c50024,
358  .chcr = CHCR_RX(XMIT_SZ_8BIT),
359  .mid_rid = 0x26,
360  }, {
361  .slave_id = SHDMA_SLAVE_SCIF2_TX,
362  .addr = 0xe6c60020,
363  .chcr = CHCR_TX(XMIT_SZ_8BIT),
364  .mid_rid = 0x29,
365  }, {
366  .slave_id = SHDMA_SLAVE_SCIF2_RX,
367  .addr = 0xe6c60024,
368  .chcr = CHCR_RX(XMIT_SZ_8BIT),
369  .mid_rid = 0x2a,
370  }, {
371  .slave_id = SHDMA_SLAVE_SCIF3_TX,
372  .addr = 0xe6c70020,
373  .chcr = CHCR_TX(XMIT_SZ_8BIT),
374  .mid_rid = 0x2d,
375  }, {
376  .slave_id = SHDMA_SLAVE_SCIF3_RX,
377  .addr = 0xe6c70024,
378  .chcr = CHCR_RX(XMIT_SZ_8BIT),
379  .mid_rid = 0x2e,
380  }, {
381  .slave_id = SHDMA_SLAVE_SCIF4_TX,
382  .addr = 0xe6c80020,
383  .chcr = CHCR_TX(XMIT_SZ_8BIT),
384  .mid_rid = 0x39,
385  }, {
386  .slave_id = SHDMA_SLAVE_SCIF4_RX,
387  .addr = 0xe6c80024,
388  .chcr = CHCR_RX(XMIT_SZ_8BIT),
389  .mid_rid = 0x3a,
390  }, {
391  .slave_id = SHDMA_SLAVE_SCIF5_TX,
392  .addr = 0xe6cb0020,
393  .chcr = CHCR_TX(XMIT_SZ_8BIT),
394  .mid_rid = 0x35,
395  }, {
396  .slave_id = SHDMA_SLAVE_SCIF5_RX,
397  .addr = 0xe6cb0024,
398  .chcr = CHCR_RX(XMIT_SZ_8BIT),
399  .mid_rid = 0x36,
400  }, {
401  .slave_id = SHDMA_SLAVE_SCIF6_TX,
402  .addr = 0xe6c30040,
403  .chcr = CHCR_TX(XMIT_SZ_8BIT),
404  .mid_rid = 0x3d,
405  }, {
406  .slave_id = SHDMA_SLAVE_SCIF6_RX,
407  .addr = 0xe6c30060,
408  .chcr = CHCR_RX(XMIT_SZ_8BIT),
409  .mid_rid = 0x3e,
410  }, {
411  .slave_id = SHDMA_SLAVE_SDHI0_TX,
412  .addr = 0xe6850030,
413  .chcr = CHCR_TX(XMIT_SZ_16BIT),
414  .mid_rid = 0xc1,
415  }, {
416  .slave_id = SHDMA_SLAVE_SDHI0_RX,
417  .addr = 0xe6850030,
418  .chcr = CHCR_RX(XMIT_SZ_16BIT),
419  .mid_rid = 0xc2,
420  }, {
421  .slave_id = SHDMA_SLAVE_SDHI1_TX,
422  .addr = 0xe6860030,
423  .chcr = CHCR_TX(XMIT_SZ_16BIT),
424  .mid_rid = 0xc9,
425  }, {
426  .slave_id = SHDMA_SLAVE_SDHI1_RX,
427  .addr = 0xe6860030,
428  .chcr = CHCR_RX(XMIT_SZ_16BIT),
429  .mid_rid = 0xca,
430  }, {
431  .slave_id = SHDMA_SLAVE_SDHI2_TX,
432  .addr = 0xe6870030,
433  .chcr = CHCR_TX(XMIT_SZ_16BIT),
434  .mid_rid = 0xcd,
435  }, {
436  .slave_id = SHDMA_SLAVE_SDHI2_RX,
437  .addr = 0xe6870030,
438  .chcr = CHCR_RX(XMIT_SZ_16BIT),
439  .mid_rid = 0xce,
440  }, {
441  .slave_id = SHDMA_SLAVE_FSIA_TX,
442  .addr = 0xfe1f0024,
443  .chcr = CHCR_TX(XMIT_SZ_32BIT),
444  .mid_rid = 0xb1,
445  }, {
446  .slave_id = SHDMA_SLAVE_FSIA_RX,
447  .addr = 0xfe1f0020,
448  .chcr = CHCR_RX(XMIT_SZ_32BIT),
449  .mid_rid = 0xb2,
450  }, {
451  .slave_id = SHDMA_SLAVE_MMCIF_TX,
452  .addr = 0xe6bd0034,
453  .chcr = CHCR_TX(XMIT_SZ_32BIT),
454  .mid_rid = 0xd1,
455  }, {
456  .slave_id = SHDMA_SLAVE_MMCIF_RX,
457  .addr = 0xe6bd0034,
458  .chcr = CHCR_RX(XMIT_SZ_32BIT),
459  .mid_rid = 0xd2,
460  },
461 };
462 
463 #define SH7372_CHCLR (0x220 - 0x20)
464 
465 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
466  {
467  .offset = 0,
468  .dmars = 0,
469  .dmars_bit = 0,
470  .chclr_offset = SH7372_CHCLR + 0,
471  }, {
472  .offset = 0x10,
473  .dmars = 0,
474  .dmars_bit = 8,
475  .chclr_offset = SH7372_CHCLR + 0x10,
476  }, {
477  .offset = 0x20,
478  .dmars = 4,
479  .dmars_bit = 0,
480  .chclr_offset = SH7372_CHCLR + 0x20,
481  }, {
482  .offset = 0x30,
483  .dmars = 4,
484  .dmars_bit = 8,
485  .chclr_offset = SH7372_CHCLR + 0x30,
486  }, {
487  .offset = 0x50,
488  .dmars = 8,
489  .dmars_bit = 0,
490  .chclr_offset = SH7372_CHCLR + 0x50,
491  }, {
492  .offset = 0x60,
493  .dmars = 8,
494  .dmars_bit = 8,
495  .chclr_offset = SH7372_CHCLR + 0x60,
496  }
497 };
498 
499 static struct sh_dmae_pdata dma_platform_data = {
500  .slave = sh7372_dmae_slaves,
501  .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
502  .channel = sh7372_dmae_channels,
503  .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
504  .ts_low_shift = TS_LOW_SHIFT,
505  .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
506  .ts_high_shift = TS_HI_SHIFT,
507  .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
508  .ts_shift = dma_ts_shift,
509  .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
510  .dmaor_init = DMAOR_DME,
511  .chclr_present = 1,
512 };
513 
514 /* Resource order important! */
515 static struct resource sh7372_dmae0_resources[] = {
516  {
517  /* Channel registers and DMAOR */
518  .start = 0xfe008020,
519  .end = 0xfe00828f,
520  .flags = IORESOURCE_MEM,
521  },
522  {
523  /* DMARSx */
524  .start = 0xfe009000,
525  .end = 0xfe00900b,
526  .flags = IORESOURCE_MEM,
527  },
528  {
529  .name = "error_irq",
530  .start = evt2irq(0x20c0),
531  .end = evt2irq(0x20c0),
532  .flags = IORESOURCE_IRQ,
533  },
534  {
535  /* IRQ for channels 0-5 */
536  .start = evt2irq(0x2000),
537  .end = evt2irq(0x20a0),
538  .flags = IORESOURCE_IRQ,
539  },
540 };
541 
542 /* Resource order important! */
543 static struct resource sh7372_dmae1_resources[] = {
544  {
545  /* Channel registers and DMAOR */
546  .start = 0xfe018020,
547  .end = 0xfe01828f,
548  .flags = IORESOURCE_MEM,
549  },
550  {
551  /* DMARSx */
552  .start = 0xfe019000,
553  .end = 0xfe01900b,
554  .flags = IORESOURCE_MEM,
555  },
556  {
557  .name = "error_irq",
558  .start = evt2irq(0x21c0),
559  .end = evt2irq(0x21c0),
560  .flags = IORESOURCE_IRQ,
561  },
562  {
563  /* IRQ for channels 0-5 */
564  .start = evt2irq(0x2100),
565  .end = evt2irq(0x21a0),
566  .flags = IORESOURCE_IRQ,
567  },
568 };
569 
570 /* Resource order important! */
571 static struct resource sh7372_dmae2_resources[] = {
572  {
573  /* Channel registers and DMAOR */
574  .start = 0xfe028020,
575  .end = 0xfe02828f,
576  .flags = IORESOURCE_MEM,
577  },
578  {
579  /* DMARSx */
580  .start = 0xfe029000,
581  .end = 0xfe02900b,
582  .flags = IORESOURCE_MEM,
583  },
584  {
585  .name = "error_irq",
586  .start = evt2irq(0x22c0),
587  .end = evt2irq(0x22c0),
588  .flags = IORESOURCE_IRQ,
589  },
590  {
591  /* IRQ for channels 0-5 */
592  .start = evt2irq(0x2200),
593  .end = evt2irq(0x22a0),
594  .flags = IORESOURCE_IRQ,
595  },
596 };
597 
598 static struct platform_device dma0_device = {
599  .name = "sh-dma-engine",
600  .id = 0,
601  .resource = sh7372_dmae0_resources,
602  .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
603  .dev = {
604  .platform_data = &dma_platform_data,
605  },
606 };
607 
608 static struct platform_device dma1_device = {
609  .name = "sh-dma-engine",
610  .id = 1,
611  .resource = sh7372_dmae1_resources,
612  .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
613  .dev = {
614  .platform_data = &dma_platform_data,
615  },
616 };
617 
618 static struct platform_device dma2_device = {
619  .name = "sh-dma-engine",
620  .id = 2,
621  .resource = sh7372_dmae2_resources,
622  .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
623  .dev = {
624  .platform_data = &dma_platform_data,
625  },
626 };
627 
628 /*
629  * USB-DMAC
630  */
631 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
632  {
633  .offset = 0,
634  }, {
635  .offset = 0x20,
636  },
637 };
638 
639 /* USB DMAC0 */
640 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
641  {
642  .slave_id = SHDMA_SLAVE_USB0_TX,
643  .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
644  }, {
645  .slave_id = SHDMA_SLAVE_USB0_RX,
646  .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
647  },
648 };
649 
650 static struct sh_dmae_pdata usb_dma0_platform_data = {
651  .slave = sh7372_usb_dmae0_slaves,
652  .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
653  .channel = sh7372_usb_dmae_channels,
654  .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
655  .ts_low_shift = USBTS_LOW_SHIFT,
656  .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
657  .ts_high_shift = USBTS_HI_SHIFT,
658  .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
659  .ts_shift = dma_usbts_shift,
660  .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
661  .dmaor_init = DMAOR_DME,
662  .chcr_offset = 0x14,
663  .chcr_ie_bit = 1 << 5,
664  .dmaor_is_32bit = 1,
665  .needs_tend_set = 1,
666  .no_dmars = 1,
667  .slave_only = 1,
668 };
669 
670 static struct resource sh7372_usb_dmae0_resources[] = {
671  {
672  /* Channel registers and DMAOR */
673  .start = 0xe68a0020,
674  .end = 0xe68a0064 - 1,
675  .flags = IORESOURCE_MEM,
676  },
677  {
678  /* VCR/SWR/DMICR */
679  .start = 0xe68a0000,
680  .end = 0xe68a0014 - 1,
681  .flags = IORESOURCE_MEM,
682  },
683  {
684  /* IRQ for channels */
685  .start = evt2irq(0x0a00),
686  .end = evt2irq(0x0a00),
687  .flags = IORESOURCE_IRQ,
688  },
689 };
690 
691 static struct platform_device usb_dma0_device = {
692  .name = "sh-dma-engine",
693  .id = 3,
694  .resource = sh7372_usb_dmae0_resources,
695  .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
696  .dev = {
697  .platform_data = &usb_dma0_platform_data,
698  },
699 };
700 
701 /* USB DMAC1 */
702 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
703  {
704  .slave_id = SHDMA_SLAVE_USB1_TX,
705  .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
706  }, {
707  .slave_id = SHDMA_SLAVE_USB1_RX,
708  .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
709  },
710 };
711 
712 static struct sh_dmae_pdata usb_dma1_platform_data = {
713  .slave = sh7372_usb_dmae1_slaves,
714  .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
715  .channel = sh7372_usb_dmae_channels,
716  .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
717  .ts_low_shift = USBTS_LOW_SHIFT,
718  .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
719  .ts_high_shift = USBTS_HI_SHIFT,
720  .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
721  .ts_shift = dma_usbts_shift,
722  .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
723  .dmaor_init = DMAOR_DME,
724  .chcr_offset = 0x14,
725  .chcr_ie_bit = 1 << 5,
726  .dmaor_is_32bit = 1,
727  .needs_tend_set = 1,
728  .no_dmars = 1,
729  .slave_only = 1,
730 };
731 
732 static struct resource sh7372_usb_dmae1_resources[] = {
733  {
734  /* Channel registers and DMAOR */
735  .start = 0xe68c0020,
736  .end = 0xe68c0064 - 1,
737  .flags = IORESOURCE_MEM,
738  },
739  {
740  /* VCR/SWR/DMICR */
741  .start = 0xe68c0000,
742  .end = 0xe68c0014 - 1,
743  .flags = IORESOURCE_MEM,
744  },
745  {
746  /* IRQ for channels */
747  .start = evt2irq(0x1d00),
748  .end = evt2irq(0x1d00),
749  .flags = IORESOURCE_IRQ,
750  },
751 };
752 
753 static struct platform_device usb_dma1_device = {
754  .name = "sh-dma-engine",
755  .id = 4,
756  .resource = sh7372_usb_dmae1_resources,
757  .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
758  .dev = {
759  .platform_data = &usb_dma1_platform_data,
760  },
761 };
762 
763 /* VPU */
764 static struct uio_info vpu_platform_data = {
765  .name = "VPU5HG",
766  .version = "0",
767  .irq = intcs_evt2irq(0x980),
768 };
769 
770 static struct resource vpu_resources[] = {
771  [0] = {
772  .name = "VPU",
773  .start = 0xfe900000,
774  .end = 0xfe900157,
775  .flags = IORESOURCE_MEM,
776  },
777 };
778 
779 static struct platform_device vpu_device = {
780  .name = "uio_pdrv_genirq",
781  .id = 0,
782  .dev = {
783  .platform_data = &vpu_platform_data,
784  },
785  .resource = vpu_resources,
786  .num_resources = ARRAY_SIZE(vpu_resources),
787 };
788 
789 /* VEU0 */
790 static struct uio_info veu0_platform_data = {
791  .name = "VEU0",
792  .version = "0",
793  .irq = intcs_evt2irq(0x700),
794 };
795 
796 static struct resource veu0_resources[] = {
797  [0] = {
798  .name = "VEU0",
799  .start = 0xfe920000,
800  .end = 0xfe9200cb,
801  .flags = IORESOURCE_MEM,
802  },
803 };
804 
805 static struct platform_device veu0_device = {
806  .name = "uio_pdrv_genirq",
807  .id = 1,
808  .dev = {
809  .platform_data = &veu0_platform_data,
810  },
811  .resource = veu0_resources,
812  .num_resources = ARRAY_SIZE(veu0_resources),
813 };
814 
815 /* VEU1 */
816 static struct uio_info veu1_platform_data = {
817  .name = "VEU1",
818  .version = "0",
819  .irq = intcs_evt2irq(0x720),
820 };
821 
822 static struct resource veu1_resources[] = {
823  [0] = {
824  .name = "VEU1",
825  .start = 0xfe924000,
826  .end = 0xfe9240cb,
827  .flags = IORESOURCE_MEM,
828  },
829 };
830 
831 static struct platform_device veu1_device = {
832  .name = "uio_pdrv_genirq",
833  .id = 2,
834  .dev = {
835  .platform_data = &veu1_platform_data,
836  },
837  .resource = veu1_resources,
838  .num_resources = ARRAY_SIZE(veu1_resources),
839 };
840 
841 /* VEU2 */
842 static struct uio_info veu2_platform_data = {
843  .name = "VEU2",
844  .version = "0",
845  .irq = intcs_evt2irq(0x740),
846 };
847 
848 static struct resource veu2_resources[] = {
849  [0] = {
850  .name = "VEU2",
851  .start = 0xfe928000,
852  .end = 0xfe928307,
853  .flags = IORESOURCE_MEM,
854  },
855 };
856 
857 static struct platform_device veu2_device = {
858  .name = "uio_pdrv_genirq",
859  .id = 3,
860  .dev = {
861  .platform_data = &veu2_platform_data,
862  },
863  .resource = veu2_resources,
864  .num_resources = ARRAY_SIZE(veu2_resources),
865 };
866 
867 /* VEU3 */
868 static struct uio_info veu3_platform_data = {
869  .name = "VEU3",
870  .version = "0",
871  .irq = intcs_evt2irq(0x760),
872 };
873 
874 static struct resource veu3_resources[] = {
875  [0] = {
876  .name = "VEU3",
877  .start = 0xfe92c000,
878  .end = 0xfe92c307,
879  .flags = IORESOURCE_MEM,
880  },
881 };
882 
883 static struct platform_device veu3_device = {
884  .name = "uio_pdrv_genirq",
885  .id = 4,
886  .dev = {
887  .platform_data = &veu3_platform_data,
888  },
889  .resource = veu3_resources,
890  .num_resources = ARRAY_SIZE(veu3_resources),
891 };
892 
893 /* JPU */
894 static struct uio_info jpu_platform_data = {
895  .name = "JPU",
896  .version = "0",
897  .irq = intcs_evt2irq(0x560),
898 };
899 
900 static struct resource jpu_resources[] = {
901  [0] = {
902  .name = "JPU",
903  .start = 0xfe980000,
904  .end = 0xfe9902d3,
905  .flags = IORESOURCE_MEM,
906  },
907 };
908 
909 static struct platform_device jpu_device = {
910  .name = "uio_pdrv_genirq",
911  .id = 5,
912  .dev = {
913  .platform_data = &jpu_platform_data,
914  },
915  .resource = jpu_resources,
916  .num_resources = ARRAY_SIZE(jpu_resources),
917 };
918 
919 /* SPU2DSP0 */
920 static struct uio_info spu0_platform_data = {
921  .name = "SPU2DSP0",
922  .version = "0",
923  .irq = evt2irq(0x1800),
924 };
925 
926 static struct resource spu0_resources[] = {
927  [0] = {
928  .name = "SPU2DSP0",
929  .start = 0xfe200000,
930  .end = 0xfe2fffff,
931  .flags = IORESOURCE_MEM,
932  },
933 };
934 
935 static struct platform_device spu0_device = {
936  .name = "uio_pdrv_genirq",
937  .id = 6,
938  .dev = {
939  .platform_data = &spu0_platform_data,
940  },
941  .resource = spu0_resources,
942  .num_resources = ARRAY_SIZE(spu0_resources),
943 };
944 
945 /* SPU2DSP1 */
946 static struct uio_info spu1_platform_data = {
947  .name = "SPU2DSP1",
948  .version = "0",
949  .irq = evt2irq(0x1820),
950 };
951 
952 static struct resource spu1_resources[] = {
953  [0] = {
954  .name = "SPU2DSP1",
955  .start = 0xfe300000,
956  .end = 0xfe3fffff,
957  .flags = IORESOURCE_MEM,
958  },
959 };
960 
961 static struct platform_device spu1_device = {
962  .name = "uio_pdrv_genirq",
963  .id = 7,
964  .dev = {
965  .platform_data = &spu1_platform_data,
966  },
967  .resource = spu1_resources,
968  .num_resources = ARRAY_SIZE(spu1_resources),
969 };
970 
971 static struct platform_device *sh7372_early_devices[] __initdata = {
972  &scif0_device,
973  &scif1_device,
974  &scif2_device,
975  &scif3_device,
976  &scif4_device,
977  &scif5_device,
978  &scif6_device,
979  &cmt2_device,
980  &tmu00_device,
981  &tmu01_device,
982 };
983 
984 static struct platform_device *sh7372_late_devices[] __initdata = {
985  &iic0_device,
986  &iic1_device,
987  &dma0_device,
988  &dma1_device,
989  &dma2_device,
990  &usb_dma0_device,
991  &usb_dma1_device,
992  &vpu_device,
993  &veu0_device,
994  &veu1_device,
995  &veu2_device,
996  &veu3_device,
997  &jpu_device,
998  &spu0_device,
999  &spu1_device,
1000 };
1001 
1002 void __init sh7372_add_standard_devices(void)
1003 {
1004  struct pm_domain_device domain_devices[] = {
1005  { "A3RV", &vpu_device, },
1006  { "A4MP", &spu0_device, },
1007  { "A4MP", &spu1_device, },
1008  { "A3SP", &scif0_device, },
1009  { "A3SP", &scif1_device, },
1010  { "A3SP", &scif2_device, },
1011  { "A3SP", &scif3_device, },
1012  { "A3SP", &scif4_device, },
1013  { "A3SP", &scif5_device, },
1014  { "A3SP", &scif6_device, },
1015  { "A3SP", &iic1_device, },
1016  { "A3SP", &dma0_device, },
1017  { "A3SP", &dma1_device, },
1018  { "A3SP", &dma2_device, },
1019  { "A3SP", &usb_dma0_device, },
1020  { "A3SP", &usb_dma1_device, },
1021  { "A4R", &iic0_device, },
1022  { "A4R", &veu0_device, },
1023  { "A4R", &veu1_device, },
1024  { "A4R", &veu2_device, },
1025  { "A4R", &veu3_device, },
1026  { "A4R", &jpu_device, },
1027  { "A4R", &tmu00_device, },
1028  { "A4R", &tmu01_device, },
1029  };
1030 
1031  sh7372_init_pm_domains();
1032 
1033  platform_add_devices(sh7372_early_devices,
1034  ARRAY_SIZE(sh7372_early_devices));
1035 
1036  platform_add_devices(sh7372_late_devices,
1037  ARRAY_SIZE(sh7372_late_devices));
1038 
1039  rmobile_add_devices_to_domains(domain_devices,
1040  ARRAY_SIZE(domain_devices));
1041 }
1042 
1043 static void __init sh7372_earlytimer_init(void)
1044 {
1045  sh7372_clock_init();
1046  shmobile_earlytimer_init();
1047 }
1048 
1049 void __init sh7372_add_early_devices(void)
1050 {
1051  early_platform_add_devices(sh7372_early_devices,
1052  ARRAY_SIZE(sh7372_early_devices));
1053 
1054  /* setup early console here as well */
1055  shmobile_setup_console();
1056 
1057  /* override timer setup with soc-specific code */
1058  shmobile_timer.init = sh7372_earlytimer_init;
1059 }
1060 
1061 #ifdef CONFIG_USE_OF
1062 
1063 void __init sh7372_add_early_devices_dt(void)
1064 {
1065  shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1066 
1067  early_platform_add_devices(sh7372_early_devices,
1068  ARRAY_SIZE(sh7372_early_devices));
1069 
1070  /* setup early console here as well */
1071  shmobile_setup_console();
1072 }
1073 
1074 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1075  { }
1076 };
1077 
1078 void __init sh7372_add_standard_devices_dt(void)
1079 {
1080  /* clocks are setup late during boot in the case of DT */
1081  sh7372_clock_init();
1082 
1083  platform_add_devices(sh7372_early_devices,
1084  ARRAY_SIZE(sh7372_early_devices));
1085 
1086  of_platform_populate(NULL, of_default_bus_match_table,
1087  sh7372_auxdata_lookup, NULL);
1088 }
1089 
1090 static const char *sh7372_boards_compat_dt[] __initdata = {
1091  "renesas,sh7372",
1092  NULL,
1093 };
1094 
1095 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1096  .map_io = sh7372_map_io,
1097  .init_early = sh7372_add_early_devices_dt,
1098  .nr_irqs = NR_IRQS_LEGACY,
1099  .init_irq = sh7372_init_irq,
1100  .handle_irq = shmobile_handle_irq_intc,
1101  .init_machine = sh7372_add_standard_devices_dt,
1102  .timer = &shmobile_timer,
1103  .dt_compat = sh7372_boards_compat_dt,
1104 MACHINE_END
1105 
1106 #endif /* CONFIG_USE_OF */
Generated on Thu Jan 10 2013 13:02:05 for Linux Kernel by   doxygen 1.8.2