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setup_tx4939.c
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1 /*
2  * TX4939 setup routines
3  * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
4  * and RBTX49xx patch from CELF patch archive.
5  *
6  * 2003-2005 (c) MontaVista Software, Inc.
7  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8  *
9  * This file is subject to the terms and conditions of the GNU General Public
10  * License. See the file "COPYING" in the main directory of this archive
11  * for more details.
12  */
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/netdevice.h>
17 #include <linux/notifier.h>
18 #include <linux/device.h>
19 #include <linux/ethtool.h>
20 #include <linux/param.h>
21 #include <linux/ptrace.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/platform_device.h>
24 #include <asm/bootinfo.h>
25 #include <asm/reboot.h>
26 #include <asm/traps.h>
27 #include <asm/txx9irq.h>
28 #include <asm/txx9tmr.h>
29 #include <asm/txx9/generic.h>
30 #include <asm/txx9/ndfmc.h>
31 #include <asm/txx9/dmac.h>
32 #include <asm/txx9/tx4939.h>
33 
34 static void __init tx4939_wdr_init(void)
35 {
36  /* report watchdog reset status */
37  if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
38  pr_warning("Watchdog reset detected at 0x%lx\n",
39  read_c0_errorepc());
40  /* clear WatchDogReset (W1C) */
41  tx4939_ccfg_set(TX4939_CCFG_WDRST);
42  /* do reset on watchdog */
43  tx4939_ccfg_set(TX4939_CCFG_WR);
44 }
45 
46 void __init tx4939_wdt_init(void)
47 {
48  txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
49 }
50 
51 static void tx4939_machine_restart(char *command)
52 {
53  local_irq_disable();
54  pr_emerg("Rebooting (with %s watchdog reset)...\n",
55  (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
56  "external" : "internal");
57  /* clear watchdog status */
58  tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
59  txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
60  while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
61  ;
62  mdelay(10);
63  if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
64  pr_emerg("Rebooting (with internal watchdog reset)...\n");
65  /* External WDRST failed. Do internal watchdog reset */
66  tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
67  }
68  /* fallback */
69  (*_machine_halt)();
70 }
71 
72 void show_registers(struct pt_regs *regs);
73 static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
74 {
75  int data = regs->cp0_cause & 4;
76  console_verbose();
77  pr_err("%cBE exception at %#lx\n",
78  data ? 'D' : 'I', regs->cp0_epc);
79  pr_err("ccfg:%llx, toea:%llx\n",
80  (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
81  (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
82 #ifdef CONFIG_PCI
83  tx4927_report_pcic_status();
84 #endif
85  show_registers(regs);
86  panic("BusError!");
87 }
88 static void __init tx4939_be_init(void)
89 {
90  board_be_handler = tx4939_be_handler;
91 }
92 
93 static struct resource tx4939_sdram_resource[4];
94 static struct resource tx4939_sram_resource;
95 #define TX4939_SRAM_SIZE 0x800
96 
97 void __init tx4939_add_memory_regions(void)
98 {
99  int i;
100  unsigned long start, size;
101  u64 win;
102 
103  for (i = 0; i < 4; i++) {
104  if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
105  continue;
106  win = ____raw_readq(&tx4939_ddrcptr->win[i]);
107  start = (unsigned long)(win >> 48);
108  size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
109  add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
110  }
111 }
112 
113 void __init tx4939_setup(void)
114 {
115  int i;
116  __u32 divmode;
117  __u64 pcfg;
118  unsigned int cpuclk = 0;
119 
120  txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
121  TX4939_REG_SIZE);
122  set_c0_config(TX49_CONF_CWFON);
123 
124  /* SDRAMC,EBUSC are configured by PROM */
125  for (i = 0; i < 4; i++) {
126  if (!(TX4939_EBUSC_CR(i) & 0x8))
127  continue; /* disabled */
128  txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
129  txx9_ce_res[i].end =
130  txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
131  request_resource(&iomem_resource, &txx9_ce_res[i]);
132  }
133 
134  /* clocks */
135  if (txx9_master_clock) {
136  /* calculate cpu_clock from master_clock */
137  divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
138  TX4939_CCFG_MULCLK_MASK;
139  cpuclk = txx9_master_clock * 20 / 2;
140  switch (divmode) {
141  case TX4939_CCFG_MULCLK_8:
142  cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
143  case TX4939_CCFG_MULCLK_9:
144  cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
145  case TX4939_CCFG_MULCLK_10:
146  cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
147  case TX4939_CCFG_MULCLK_11:
148  cpuclk = cpuclk / 6 * 11; break;
149  case TX4939_CCFG_MULCLK_12:
150  cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
151  case TX4939_CCFG_MULCLK_13:
152  cpuclk = cpuclk / 6 * 13; break;
153  case TX4939_CCFG_MULCLK_14:
154  cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
155  case TX4939_CCFG_MULCLK_15:
156  cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
157  }
158  txx9_cpu_clock = cpuclk;
159  } else {
160  if (txx9_cpu_clock == 0)
161  txx9_cpu_clock = 400000000; /* 400MHz */
162  /* calculate master_clock from cpu_clock */
163  cpuclk = txx9_cpu_clock;
164  divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
165  TX4939_CCFG_MULCLK_MASK;
166  switch (divmode) {
167  case TX4939_CCFG_MULCLK_8:
168  txx9_master_clock = cpuclk * 6 / 8; break;
169  case TX4939_CCFG_MULCLK_9:
170  txx9_master_clock = cpuclk * 6 / 9; break;
171  case TX4939_CCFG_MULCLK_10:
172  txx9_master_clock = cpuclk * 6 / 10; break;
173  case TX4939_CCFG_MULCLK_11:
174  txx9_master_clock = cpuclk * 6 / 11; break;
175  case TX4939_CCFG_MULCLK_12:
176  txx9_master_clock = cpuclk * 6 / 12; break;
177  case TX4939_CCFG_MULCLK_13:
178  txx9_master_clock = cpuclk * 6 / 13; break;
179  case TX4939_CCFG_MULCLK_14:
180  txx9_master_clock = cpuclk * 6 / 14; break;
181  case TX4939_CCFG_MULCLK_15:
182  txx9_master_clock = cpuclk * 6 / 15; break;
183  }
184  txx9_master_clock /= 10; /* * 2 / 20 */
185  }
186  /* calculate gbus_clock from cpu_clock */
187  divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
188  TX4939_CCFG_YDIVMODE_MASK;
189  txx9_gbus_clock = txx9_cpu_clock;
190  switch (divmode) {
191  case TX4939_CCFG_YDIVMODE_2:
192  txx9_gbus_clock /= 2; break;
193  case TX4939_CCFG_YDIVMODE_3:
194  txx9_gbus_clock /= 3; break;
195  case TX4939_CCFG_YDIVMODE_5:
196  txx9_gbus_clock /= 5; break;
197  case TX4939_CCFG_YDIVMODE_6:
198  txx9_gbus_clock /= 6; break;
199  }
200  /* change default value to udelay/mdelay take reasonable time */
201  loops_per_jiffy = txx9_cpu_clock / HZ / 2;
202 
203  /* CCFG */
204  tx4939_wdr_init();
205  /* clear BusErrorOnWrite flag (W1C) */
206  tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
207  /* enable Timeout BusError */
208  if (txx9_ccfg_toeon)
209  tx4939_ccfg_set(TX4939_CCFG_TOE);
210 
211  /* DMA selection */
212  txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
213 
214  /* Use external clock for external arbiter */
215  if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
216  txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
217 
218  pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
219  txx9_pcode_str,
220  (cpuclk + 500000) / 1000000,
221  (txx9_master_clock + 500000) / 1000000,
222  (txx9_gbus_clock + 500000) / 1000000,
223  (__u32)____raw_readq(&tx4939_ccfgptr->crir),
224  (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
225  (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
226 
227  pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
228  (__u32)____raw_readq(&tx4939_ddrcptr->winen));
229  for (i = 0; i < 4; i++) {
230  __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
231  if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
232  continue; /* disabled */
233  printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
234  tx4939_sdram_resource[i].name = "DDR SDRAM";
235  tx4939_sdram_resource[i].start =
236  (unsigned long)(win >> 48) << 20;
237  tx4939_sdram_resource[i].end =
238  ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
239  20) - 1;
240  tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
241  request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
242  }
243  printk(KERN_CONT "\n");
244 
245  /* SRAM */
246  if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
247  unsigned int size = TX4939_SRAM_SIZE;
248  tx4939_sram_resource.name = "SRAM";
249  tx4939_sram_resource.start =
250  (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
251  & ~(size - 1);
252  tx4939_sram_resource.end =
253  tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
254  tx4939_sram_resource.flags = IORESOURCE_MEM;
255  request_resource(&iomem_resource, &tx4939_sram_resource);
256  }
257 
258  /* TMR */
259  /* disable all timers */
260  for (i = 0; i < TX4939_NR_TMR; i++)
261  txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
262 
263  /* set PCIC1 reset (required to prevent hangup on BIST) */
264  txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
265  pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
266  if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
267  mdelay(1); /* at least 128 cpu clock */
268  /* clear PCIC1 reset */
269  txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
270  } else {
271  pr_info("%s: stop PCIC1\n", txx9_pcode_str);
272  /* stop PCIC1 */
273  txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
274  }
275  if (!(pcfg & TX4939_PCFG_ET0MODE)) {
276  pr_info("%s: stop ETH0\n", txx9_pcode_str);
277  txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
278  txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
279  }
280  if (!(pcfg & TX4939_PCFG_ET1MODE)) {
281  pr_info("%s: stop ETH1\n", txx9_pcode_str);
282  txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
283  txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
284  }
285 
286  _machine_restart = tx4939_machine_restart;
287  board_be_init = tx4939_be_init;
288 }
289 
290 void __init tx4939_time_init(unsigned int tmrnr)
291 {
292  if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
293  txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
294  TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
295  TXX9_IMCLK);
296 }
297 
298 void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
299 {
300  int i;
301  unsigned int ch_mask = 0;
302  __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
303 
304  cts_mask |= ~1; /* only SIO0 have RTS/CTS */
305  if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
306  cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
307  if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
308  ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
309  if (pcfg & TX4939_PCFG_SIO3MODE)
310  ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
311  for (i = 0; i < 4; i++) {
312  if ((1 << i) & ch_mask)
313  continue;
314  txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
315  TXX9_IRQ_BASE + TX4939_IR_SIO(i),
316  i, sclk, (1 << i) & cts_mask);
317  }
318 }
319 
320 #if IS_ENABLED(CONFIG_TC35815)
321 static u32 tx4939_get_eth_speed(struct net_device *dev)
322 {
323  struct ethtool_cmd cmd;
324  if (__ethtool_get_settings(dev, &cmd))
325  return 100; /* default 100Mbps */
326 
327  return ethtool_cmd_speed(&cmd);
328 }
329 
330 static int tx4939_netdev_event(struct notifier_block *this,
331  unsigned long event,
332  void *ptr)
333 {
334  struct net_device *dev = ptr;
335  if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
336  __u64 bit = 0;
337  if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
338  bit = TX4939_PCFG_SPEED0;
339  else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
340  bit = TX4939_PCFG_SPEED1;
341  if (bit) {
342  if (tx4939_get_eth_speed(dev) == 100)
343  txx9_set64(&tx4939_ccfgptr->pcfg, bit);
344  else
345  txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
346  }
347  }
348  return NOTIFY_DONE;
349 }
350 
351 static struct notifier_block tx4939_netdev_notifier = {
352  .notifier_call = tx4939_netdev_event,
353  .priority = 1,
354 };
355 
356 void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
357 {
358  u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
359 
360  if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
361  txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
362  if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
363  txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
364  register_netdevice_notifier(&tx4939_netdev_notifier);
365 }
366 #else
367 void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
368 {
369 }
370 #endif
371 
372 void __init tx4939_mtd_init(int ch)
373 {
374  struct physmap_flash_data pdata = {
375  .width = TX4939_EBUSC_WIDTH(ch) / 8,
376  };
377  unsigned long start = txx9_ce_res[ch].start;
378  unsigned long size = txx9_ce_res[ch].end - start + 1;
379 
380  if (!(TX4939_EBUSC_CR(ch) & 0x8))
381  return; /* disabled */
382  txx9_physmap_flash_init(ch, start, size, &pdata);
383 }
384 
385 #define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
386 void __init tx4939_ata_init(void)
387 {
388  static struct resource ata0_res[] = {
389  {
390  .start = TX4939_ATA_REG_PHYS(0),
391  .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
392  .flags = IORESOURCE_MEM,
393  }, {
394  .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
395  .flags = IORESOURCE_IRQ,
396  },
397  };
398  static struct resource ata1_res[] = {
399  {
400  .start = TX4939_ATA_REG_PHYS(1),
401  .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
402  .flags = IORESOURCE_MEM,
403  }, {
404  .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
405  .flags = IORESOURCE_IRQ,
406  },
407  };
408  static struct platform_device ata0_dev = {
409  .name = "tx4939ide",
410  .id = 0,
411  .num_resources = ARRAY_SIZE(ata0_res),
412  .resource = ata0_res,
413  };
414  static struct platform_device ata1_dev = {
415  .name = "tx4939ide",
416  .id = 1,
417  .num_resources = ARRAY_SIZE(ata1_res),
418  .resource = ata1_res,
419  };
420  __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
421 
422  if (pcfg & TX4939_PCFG_ATA0MODE)
423  platform_device_register(&ata0_dev);
424  if ((pcfg & (TX4939_PCFG_ATA1MODE |
425  TX4939_PCFG_ET1MODE |
426  TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
427  platform_device_register(&ata1_dev);
428 }
429 
430 void __init tx4939_rtc_init(void)
431 {
432  static struct resource res[] = {
433  {
434  .start = TX4939_RTC_REG & 0xfffffffffULL,
435  .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
436  .flags = IORESOURCE_MEM,
437  }, {
438  .start = TXX9_IRQ_BASE + TX4939_IR_RTC,
439  .flags = IORESOURCE_IRQ,
440  },
441  };
442  static struct platform_device rtc_dev = {
443  .name = "tx4939rtc",
444  .id = -1,
445  .num_resources = ARRAY_SIZE(res),
446  .resource = res,
447  };
448 
449  platform_device_register(&rtc_dev);
450 }
451 
452 void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
453  unsigned char ch_mask, unsigned char wide_mask)
454 {
455  struct txx9ndfmc_platform_data plat_data = {
456  .shift = 1,
457  .gbus_clock = txx9_gbus_clock,
458  .hold = hold,
459  .spw = spw,
460  .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD |
461  NDFMC_PLAT_FLAG_DUMMYWRITE,
462  .ch_mask = ch_mask,
463  .wide_mask = wide_mask,
464  };
465  txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
466 }
467 
468 void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
469 {
470  struct txx9dmac_platform_data plat_data = {
471  .have_64bit_regs = true,
472  };
473  int i;
474 
475  for (i = 0; i < 2; i++) {
476  plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
477  txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
478  TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
479  &plat_data);
480  }
481 }
482 
483 void __init tx4939_aclc_init(void)
484 {
485  u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
486 
487  if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
488  txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
489  TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
490 }
491 
492 void __init tx4939_sramc_init(void)
493 {
494  if (tx4939_sram_resource.start)
495  txx9_sramc_init(&tx4939_sram_resource);
496 }
497 
498 void __init tx4939_rng_init(void)
499 {
500  static struct resource res = {
501  .start = TX4939_RNG_REG & 0xfffffffffULL,
502  .end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
503  .flags = IORESOURCE_MEM,
504  };
505  static struct platform_device pdev = {
506  .name = "tx4939-rng",
507  .id = -1,
508  .num_resources = 1,
509  .resource = &res,
510  };
511 
512  platform_device_register(&pdev);
513 }
514 
515 static void __init tx4939_stop_unused_modules(void)
516 {
517  __u64 pcfg, rst = 0, ckd = 0;
518  char buf[128];
519 
520  buf[0] = '\0';
521  local_irq_disable();
522  pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
523  if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
524  TX4939_PCFG_I2SMODE_ACLC) {
525  rst |= TX4939_CLKCTR_ACLRST;
526  ckd |= TX4939_CLKCTR_ACLCKD;
527  strcat(buf, " ACLC");
528  }
529  if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
530  TX4939_PCFG_I2SMODE_I2S &&
531  (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
532  TX4939_PCFG_I2SMODE_I2S_ALT) {
533  rst |= TX4939_CLKCTR_I2SRST;
534  ckd |= TX4939_CLKCTR_I2SCKD;
535  strcat(buf, " I2S");
536  }
537  if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
538  rst |= TX4939_CLKCTR_ATA0RST;
539  ckd |= TX4939_CLKCTR_ATA0CKD;
540  strcat(buf, " ATA0");
541  }
542  if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
543  rst |= TX4939_CLKCTR_ATA1RST;
544  ckd |= TX4939_CLKCTR_ATA1CKD;
545  strcat(buf, " ATA1");
546  }
547  if (pcfg & TX4939_PCFG_SPIMODE) {
548  rst |= TX4939_CLKCTR_SPIRST;
549  ckd |= TX4939_CLKCTR_SPICKD;
550  strcat(buf, " SPI");
551  }
552  if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
553  rst |= TX4939_CLKCTR_VPCRST;
554  ckd |= TX4939_CLKCTR_VPCCKD;
555  strcat(buf, " VPC");
556  }
557  if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
558  rst |= TX4939_CLKCTR_SIO2RST;
559  ckd |= TX4939_CLKCTR_SIO2CKD;
560  strcat(buf, " SIO2");
561  }
562  if (pcfg & TX4939_PCFG_SIO3MODE) {
563  rst |= TX4939_CLKCTR_SIO3RST;
564  ckd |= TX4939_CLKCTR_SIO3CKD;
565  strcat(buf, " SIO3");
566  }
567  if (rst | ckd) {
568  txx9_set64(&tx4939_ccfgptr->clkctr, rst);
569  txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
570  }
571  local_irq_enable();
572  if (buf[0])
573  pr_info("%s: stop%s\n", txx9_pcode_str, buf);
574 }
575 
576 static int __init tx4939_late_init(void)
577 {
578  if (txx9_pcode != 0x4939)
579  return -ENODEV;
580  tx4939_stop_unused_modules();
581  return 0;
582 }
583 late_initcall(tx4939_late_init);
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