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| #define | DRV_NAME "eepro" |
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| #define | DRV_VERSION "0.13c" |
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| #define | compat_dev_kfree_skb(skb, mode) dev_kfree_skb( (skb) ) |
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| #define | SLOW_DOWN inb(0x80) |
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| #define | compat_init_data __initdata |
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| #define | NET_DEBUG 0 |
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| #define | EEPRO_IO_EXTENT 16 |
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| #define | LAN595 0 |
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| #define | LAN595TX 1 |
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| #define | LAN595FX 2 |
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| #define | LAN595FX_10ISA 3 |
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| #define | SA_ADDR0 0x00 /* Etherexpress Pro/10 */ |
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| #define | SA_ADDR1 0xaa |
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| #define | SA_ADDR2 0x00 |
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| #define | GetBit(x, y) ((x & (1<<y))>>y) |
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| #define | ee_PnP 0 /* Plug 'n Play enable bit */ |
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| #define | ee_Word1 1 /* Word 1? */ |
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| #define | ee_BusWidth 2 /* 8/16 bit */ |
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| #define | ee_FlashAddr 3 /* Flash Address */ |
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| #define | ee_FlashMask 0x7 /* Mask */ |
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| #define | ee_AutoIO 6 /* */ |
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| #define | ee_reserved0 7 /* =0! */ |
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| #define | ee_Flash 8 /* Flash there? */ |
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| #define | ee_AutoNeg 9 /* Auto Negotiation enabled? */ |
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| #define | ee_IO0 10 /* IO Address LSB */ |
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| #define | ee_IO0Mask 0x /*...*/ |
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| #define | ee_IO1 15 /* IO MSB */ |
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| #define | ee_IntSel 0 /* Interrupt */ |
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| #define | ee_IntMask 0x7 |
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| #define | ee_LI 3 /* Link Integrity 0= enabled */ |
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| #define | ee_PC 4 /* Polarity Correction 0= enabled */ |
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| #define | ee_TPE_AUI 5 /* PortSelection 1=TPE */ |
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| #define | ee_Jabber 6 /* Jabber prevention 0= enabled */ |
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| #define | ee_AutoPort 7 /* Auto Port Selection 1= Disabled */ |
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| #define | ee_SMOUT 8 /* SMout Pin Control 0= Input */ |
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| #define | ee_PROM 9 /* Flash EPROM / PROM 0=Flash */ |
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| #define | ee_reserved1 10 /* .. 12 =0! */ |
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| #define | ee_AltReady 13 /* Alternate Ready, 0=normal */ |
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| #define | ee_reserved2 14 /* =0! */ |
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| #define | ee_Duplex 15 |
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| #define | ee_IA5 0 /*bit start for individual Addr Byte 5 */ |
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| #define | ee_IA4 8 /*bit start for individual Addr Byte 5 */ |
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| #define | ee_IA3 0 /*bit start for individual Addr Byte 5 */ |
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| #define | ee_IA2 8 /*bit start for individual Addr Byte 5 */ |
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| #define | ee_IA1 0 /*bit start for individual Addr Byte 5 */ |
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| #define | ee_IA0 8 /*bit start for individual Addr Byte 5 */ |
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| #define | ee_BNC_TPE 0 /* 0=TPE */ |
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| #define | ee_BootType 1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */ |
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| #define | ee_BootTypeMask 0x3 |
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| #define | ee_NumConn 3 /* Number of Connections 0= One or Two */ |
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| #define | ee_FlashSock 4 /* Presence of Flash Socket 0= Present */ |
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| #define | ee_PortTPE 5 |
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| #define | ee_PortBNC 6 |
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| #define | ee_PortAUI 7 |
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| #define | ee_PowerMgt 10 /* 0= disabled */ |
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| #define | ee_CP 13 /* Concurrent Processing */ |
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| #define | ee_CPMask 0x7 |
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| #define | ee_Stepping 0 /* Stepping info */ |
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| #define | ee_StepMask 0x0F |
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| #define | ee_BoardID 4 /* Manucaturer Board ID, reserved */ |
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| #define | ee_BoardMask 0x0FFF |
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| #define | ee_INT_TO_IRQ 0 /* int to IRQ Mapping = 0x1EB8 for Pro/10+ */ |
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| #define | ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */ |
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| #define | ee_SIZE 0x40 /* total EEprom Size */ |
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| #define | ee_Checksum 0xBABA /* initial and final value for adding checksum */ |
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| #define | ee_addr_vendor 0x10 /* Word offset for EISA Vendor ID */ |
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| #define | ee_addr_id 0x11 /* Word offset for Card ID */ |
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| #define | ee_addr_SN 0x12 /* Serial Number */ |
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| #define | ee_addr_CRC_8 0x14 /* CRC over last thee Bytes */ |
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| #define | ee_vendor_intel0 0x25 /* Vendor ID Intel */ |
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| #define | ee_vendor_intel1 0xD4 |
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| #define | ee_id_eepro10p0 0x10 /* ID for eepro/10+ */ |
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| #define | ee_id_eepro10p1 0x31 |
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| #define | TX_TIMEOUT ((4*HZ)/10) |
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| #define | RAM_SIZE 0x8000 |
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| #define | RCV_HEADER 8 |
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| #define | RCV_DEFAULT_RAM 0x6000 |
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| #define | XMT_HEADER 8 |
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| #define | XMT_DEFAULT_RAM (RAM_SIZE - RCV_DEFAULT_RAM) |
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| #define | XMT_START_PRO RCV_DEFAULT_RAM |
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| #define | XMT_START_10 0x0000 |
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| #define | RCV_START_PRO 0x0000 |
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| #define | RCV_START_10 XMT_DEFAULT_RAM |
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| #define | RCV_DONE 0x0008 |
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| #define | RX_OK 0x2000 |
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| #define | RX_ERROR 0x0d81 |
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| #define | TX_DONE_BIT 0x0080 |
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| #define | TX_OK 0x2000 |
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| #define | CHAIN_BIT 0x8000 |
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| #define | XMT_STATUS 0x02 |
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| #define | XMT_CHAIN 0x04 |
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| #define | XMT_COUNT 0x06 |
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| #define | BANK0_SELECT 0x00 |
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| #define | BANK1_SELECT 0x40 |
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| #define | BANK2_SELECT 0x80 |
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| #define | COMMAND_REG 0x00 /* Register 0 */ |
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| #define | MC_SETUP 0x03 |
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| #define | XMT_CMD 0x04 |
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| #define | DIAGNOSE_CMD 0x07 |
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| #define | RCV_ENABLE_CMD 0x08 |
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| #define | RCV_DISABLE_CMD 0x0a |
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| #define | STOP_RCV_CMD 0x0b |
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| #define | RESET_CMD 0x0e |
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| #define | POWER_DOWN_CMD 0x18 |
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| #define | RESUME_XMT_CMD 0x1c |
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| #define | SEL_RESET_CMD 0x1e |
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| #define | STATUS_REG 0x01 /* Register 1 */ |
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| #define | RX_INT 0x02 |
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| #define | TX_INT 0x04 |
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| #define | EXEC_STATUS 0x30 |
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| #define | ID_REG 0x02 /* Register 2 */ |
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| #define | R_ROBIN_BITS 0xc0 /* round robin counter */ |
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| #define | ID_REG_MASK 0x2c |
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| #define | ID_REG_SIG 0x24 |
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| #define | AUTO_ENABLE 0x10 |
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| #define | INT_MASK_REG 0x03 /* Register 3 */ |
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| #define | RX_STOP_MASK 0x01 |
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| #define | RX_MASK 0x02 |
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| #define | TX_MASK 0x04 |
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| #define | EXEC_MASK 0x08 |
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| #define | ALL_MASK 0x0f |
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| #define | IO_32_BIT 0x10 |
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| #define | RCV_BAR 0x04 /* The following are word (16-bit) registers */ |
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| #define | RCV_STOP 0x06 |
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| #define | XMT_BAR_PRO 0x0a |
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| #define | XMT_BAR_10 0x0b |
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| #define | HOST_ADDRESS_REG 0x0c |
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| #define | IO_PORT 0x0e |
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| #define | IO_PORT_32_BIT 0x0c |
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| #define | REG1 0x01 |
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| #define | WORD_WIDTH 0x02 |
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| #define | INT_ENABLE 0x80 |
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| #define | INT_NO_REG 0x02 |
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| #define | RCV_LOWER_LIMIT_REG 0x08 |
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| #define | RCV_UPPER_LIMIT_REG 0x09 |
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| #define | XMT_LOWER_LIMIT_REG_PRO 0x0a |
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| #define | XMT_UPPER_LIMIT_REG_PRO 0x0b |
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| #define | XMT_LOWER_LIMIT_REG_10 0x0b |
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| #define | XMT_UPPER_LIMIT_REG_10 0x0a |
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| #define | XMT_Chain_Int 0x20 /* Interrupt at the end of the transmit chain */ |
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| #define | XMT_Chain_ErrStop 0x40 /* Interrupt at the end of the chain even if there are errors */ |
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| #define | RCV_Discard_BadFrame 0x80 /* Throw bad frames away, and continue to receive others */ |
| |
| #define | REG2 0x02 |
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| #define | PRMSC_Mode 0x01 |
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| #define | Multi_IA 0x20 |
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| #define | REG3 0x03 |
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| #define | TPE_BIT 0x04 |
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| #define | BNC_BIT 0x20 |
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| #define | REG13 0x0d |
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| #define | FDX 0x00 |
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| #define | A_N_ENABLE 0x02 |
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| #define | I_ADD_REG0 0x04 |
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| #define | I_ADD_REG1 0x05 |
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| #define | I_ADD_REG2 0x06 |
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| #define | I_ADD_REG3 0x07 |
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| #define | I_ADD_REG4 0x08 |
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| #define | I_ADD_REG5 0x09 |
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| #define | EEPROM_REG_PRO 0x0a |
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| #define | EEPROM_REG_10 0x0b |
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| #define | EESK 0x01 |
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| #define | EECS 0x02 |
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| #define | EEDI 0x04 |
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| #define | EEDO 0x08 |
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| #define | eepro_reset(ioaddr) outb(RESET_CMD, ioaddr) |
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| #define | eepro_sel_reset(ioaddr) |
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| #define | eepro_dis_int(ioaddr) outb(ALL_MASK, ioaddr + INT_MASK_REG) |
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| #define | eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG) |
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| #define | eepro_en_int(ioaddr) |
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| #define | eepro_en_intexec(ioaddr) outb(ALL_MASK & ~(EXEC_MASK), ioaddr + INT_MASK_REG) |
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| #define | eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr) |
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| #define | eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr) |
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| #define | eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr) |
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| #define | eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr) |
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| #define | eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr) |
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| #define | eepro_en_intline(ioaddr) |
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| #define | eepro_dis_intline(ioaddr) |
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| #define | eepro_diag(ioaddr) outb(DIAGNOSE_CMD, ioaddr) |
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| #define | eepro_ack_rx(ioaddr) outb (RX_INT, ioaddr + STATUS_REG) |
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| #define | eepro_ack_tx(ioaddr) outb (TX_INT, ioaddr + STATUS_REG) |
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| #define | eepro_complete_selreset(ioaddr) |
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| #define | eeprom_delay() { udelay(40); } |
| |
| #define | EE_READ_CMD (6 << 6) |
| |
1.8.2