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wm8996.c
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1 /*
2  * wm8996.c - WM8996 audio codec interface
3  *
4  * Copyright 2011-2 Wolfson Microelectronics PLC.
5  * Author: Mark Brown <[email protected]>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/gcd.h>
20 #include <linux/gpio.h>
21 #include <linux/i2c.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <linux/workqueue.h>
26 #include <sound/core.h>
27 #include <sound/jack.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <trace/events/asoc.h>
34 
35 #include <sound/wm8996.h>
36 #include "wm8996.h"
37 
38 #define WM8996_AIFS 2
39 
40 #define HPOUT1L 1
41 #define HPOUT1R 2
42 #define HPOUT2L 4
43 #define HPOUT2R 8
44 
45 #define WM8996_NUM_SUPPLIES 3
46 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
47  "DBVDD",
48  "AVDD1",
49  "AVDD2",
50 };
51 
52 struct wm8996_priv {
53  struct device *dev;
54  struct regmap *regmap;
55  struct snd_soc_codec *codec;
56 
57  int ldo1ena;
58 
59  int sysclk;
60  int sysclk_src;
61 
62  int fll_src;
63  int fll_fref;
64  int fll_fout;
65 
66  struct completion fll_lock;
67 
68  u16 dcs_pending;
69  struct completion dcs_done;
70 
71  u16 hpout_ena;
72  u16 hpout_pending;
73 
74  struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
75  struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
76  int bg_ena;
77 
78  struct wm8996_pdata pdata;
79 
80  int rx_rate[WM8996_AIFS];
81  int bclk_rate[WM8996_AIFS];
82 
83  /* Platform dependant ReTune mobile configuration */
84  int num_retune_mobile_texts;
85  const char **retune_mobile_texts;
86  int retune_mobile_cfg[2];
87  struct soc_enum retune_mobile_enum;
88 
89  struct snd_soc_jack *jack;
90  bool detecting;
91  bool jack_mic;
92  int jack_flips;
93  wm8996_polarity_fn polarity_cb;
94 
95 #ifdef CONFIG_GPIOLIB
96  struct gpio_chip gpio_chip;
97 #endif
98 };
99 
100 /* We can't use the same notifier block for more than one supply and
101  * there's no way I can see to get from a callback to the caller
102  * except container_of().
103  */
104 #define WM8996_REGULATOR_EVENT(n) \
105 static int wm8996_regulator_event_##n(struct notifier_block *nb, \
106  unsigned long event, void *data) \
107 { \
108  struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
109  disable_nb[n]); \
110  if (event & REGULATOR_EVENT_DISABLE) { \
111  regcache_mark_dirty(wm8996->regmap); \
112  } \
113  return 0; \
114 }
115 
116 WM8996_REGULATOR_EVENT(0)
117 WM8996_REGULATOR_EVENT(1)
118 WM8996_REGULATOR_EVENT(2)
119 
120 static struct reg_default wm8996_reg[] = {
121  { WM8996_POWER_MANAGEMENT_1, 0x0 },
122  { WM8996_POWER_MANAGEMENT_2, 0x0 },
123  { WM8996_POWER_MANAGEMENT_3, 0x0 },
124  { WM8996_POWER_MANAGEMENT_4, 0x0 },
125  { WM8996_POWER_MANAGEMENT_5, 0x0 },
126  { WM8996_POWER_MANAGEMENT_6, 0x0 },
127  { WM8996_POWER_MANAGEMENT_7, 0x10 },
128  { WM8996_POWER_MANAGEMENT_8, 0x0 },
129  { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
130  { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
131  { WM8996_LINE_INPUT_CONTROL, 0x0 },
132  { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
133  { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
134  { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
135  { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
136  { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
137  { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
138  { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
139  { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
140  { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
141  { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
142  { WM8996_MICBIAS_1, 0x39 },
143  { WM8996_MICBIAS_2, 0x39 },
144  { WM8996_LDO_1, 0x3 },
145  { WM8996_LDO_2, 0x13 },
146  { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
147  { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
148  { WM8996_HEADPHONE_DETECT_1, 0x20 },
149  { WM8996_HEADPHONE_DETECT_2, 0x0 },
150  { WM8996_MIC_DETECT_1, 0x7600 },
151  { WM8996_MIC_DETECT_2, 0xbf },
152  { WM8996_CHARGE_PUMP_1, 0x1f25 },
153  { WM8996_CHARGE_PUMP_2, 0xab19 },
154  { WM8996_DC_SERVO_1, 0x0 },
155  { WM8996_DC_SERVO_3, 0x0 },
156  { WM8996_DC_SERVO_5, 0x2a2a },
157  { WM8996_DC_SERVO_6, 0x0 },
158  { WM8996_DC_SERVO_7, 0x0 },
159  { WM8996_ANALOGUE_HP_1, 0x0 },
160  { WM8996_ANALOGUE_HP_2, 0x0 },
161  { WM8996_CONTROL_INTERFACE_1, 0x8004 },
162  { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
163  { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
164  { WM8996_AIF_CLOCKING_1, 0x0 },
165  { WM8996_AIF_CLOCKING_2, 0x0 },
166  { WM8996_CLOCKING_1, 0x10 },
167  { WM8996_CLOCKING_2, 0x0 },
168  { WM8996_AIF_RATE, 0x83 },
169  { WM8996_FLL_CONTROL_1, 0x0 },
170  { WM8996_FLL_CONTROL_2, 0x0 },
171  { WM8996_FLL_CONTROL_3, 0x0 },
172  { WM8996_FLL_CONTROL_4, 0x5dc0 },
173  { WM8996_FLL_CONTROL_5, 0xc84 },
174  { WM8996_FLL_EFS_1, 0x0 },
175  { WM8996_FLL_EFS_2, 0x2 },
176  { WM8996_AIF1_CONTROL, 0x0 },
177  { WM8996_AIF1_BCLK, 0x0 },
178  { WM8996_AIF1_TX_LRCLK_1, 0x80 },
179  { WM8996_AIF1_TX_LRCLK_2, 0x8 },
180  { WM8996_AIF1_RX_LRCLK_1, 0x80 },
181  { WM8996_AIF1_RX_LRCLK_2, 0x0 },
182  { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
183  { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
184  { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
185  { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
186  { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
187  { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
188  { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
189  { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
190  { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
191  { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
192  { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
193  { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
194  { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
195  { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
196  { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
197  { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
198  { WM8996_AIF1TX_TEST, 0x7 },
199  { WM8996_AIF2_CONTROL, 0x0 },
200  { WM8996_AIF2_BCLK, 0x0 },
201  { WM8996_AIF2_TX_LRCLK_1, 0x80 },
202  { WM8996_AIF2_TX_LRCLK_2, 0x8 },
203  { WM8996_AIF2_RX_LRCLK_1, 0x80 },
204  { WM8996_AIF2_RX_LRCLK_2, 0x0 },
205  { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
206  { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
207  { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
208  { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
209  { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
210  { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
211  { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
212  { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
213  { WM8996_AIF2TX_TEST, 0x1 },
214  { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
215  { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
216  { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
217  { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
218  { WM8996_DSP1_TX_FILTERS, 0x2000 },
219  { WM8996_DSP1_RX_FILTERS_1, 0x200 },
220  { WM8996_DSP1_RX_FILTERS_2, 0x10 },
221  { WM8996_DSP1_DRC_1, 0x98 },
222  { WM8996_DSP1_DRC_2, 0x845 },
223  { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
224  { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
225  { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
226  { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
227  { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
228  { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
229  { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
230  { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
231  { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
232  { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
233  { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
234  { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
235  { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
236  { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
237  { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
238  { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
239  { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
240  { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
241  { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
242  { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
243  { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
244  { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
245  { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
246  { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
247  { WM8996_DSP2_TX_FILTERS, 0x2000 },
248  { WM8996_DSP2_RX_FILTERS_1, 0x200 },
249  { WM8996_DSP2_RX_FILTERS_2, 0x10 },
250  { WM8996_DSP2_DRC_1, 0x98 },
251  { WM8996_DSP2_DRC_2, 0x845 },
252  { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
253  { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
254  { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
255  { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
256  { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
257  { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
258  { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
259  { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
260  { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
261  { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
262  { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
263  { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
264  { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
265  { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
266  { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
267  { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
268  { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
269  { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
270  { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
271  { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
272  { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
273  { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
274  { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
275  { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
276  { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
277  { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
278  { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
279  { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
280  { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
281  { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
282  { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
283  { WM8996_DAC_SOFTMUTE, 0x0 },
284  { WM8996_OVERSAMPLING, 0xd },
285  { WM8996_SIDETONE, 0x1040 },
286  { WM8996_GPIO_1, 0xa101 },
287  { WM8996_GPIO_2, 0xa101 },
288  { WM8996_GPIO_3, 0xa101 },
289  { WM8996_GPIO_4, 0xa101 },
290  { WM8996_GPIO_5, 0xa101 },
291  { WM8996_PULL_CONTROL_1, 0x0 },
292  { WM8996_PULL_CONTROL_2, 0x140 },
293  { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
294  { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
295  { WM8996_LEFT_PDM_SPEAKER, 0x0 },
296  { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
297  { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
298  { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
299 };
300 
301 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
302 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
303 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
304 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
305 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
306 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
307 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
308 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
309 
310 static const char *sidetone_hpf_text[] = {
311  "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
312 };
313 
314 static const struct soc_enum sidetone_hpf =
315  SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
316 
317 static const char *hpf_mode_text[] = {
318  "HiFi", "Custom", "Voice"
319 };
320 
321 static const struct soc_enum dsp1tx_hpf_mode =
322  SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
323 
324 static const struct soc_enum dsp2tx_hpf_mode =
325  SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
326 
327 static const char *hpf_cutoff_text[] = {
328  "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
329 };
330 
331 static const struct soc_enum dsp1tx_hpf_cutoff =
332  SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
333 
334 static const struct soc_enum dsp2tx_hpf_cutoff =
335  SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
336 
337 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
338 {
339  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
340  struct wm8996_pdata *pdata = &wm8996->pdata;
341  int base, best, best_val, save, i, cfg, iface;
342 
343  if (!wm8996->num_retune_mobile_texts)
344  return;
345 
346  switch (block) {
347  case 0:
348  base = WM8996_DSP1_RX_EQ_GAINS_1;
349  if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
350  WM8996_DSP1RX_SRC)
351  iface = 1;
352  else
353  iface = 0;
354  break;
355  case 1:
356  base = WM8996_DSP1_RX_EQ_GAINS_2;
357  if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
358  WM8996_DSP2RX_SRC)
359  iface = 1;
360  else
361  iface = 0;
362  break;
363  default:
364  return;
365  }
366 
367  /* Find the version of the currently selected configuration
368  * with the nearest sample rate. */
369  cfg = wm8996->retune_mobile_cfg[block];
370  best = 0;
371  best_val = INT_MAX;
372  for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
373  if (strcmp(pdata->retune_mobile_cfgs[i].name,
374  wm8996->retune_mobile_texts[cfg]) == 0 &&
375  abs(pdata->retune_mobile_cfgs[i].rate
376  - wm8996->rx_rate[iface]) < best_val) {
377  best = i;
378  best_val = abs(pdata->retune_mobile_cfgs[i].rate
379  - wm8996->rx_rate[iface]);
380  }
381  }
382 
383  dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
384  block,
385  pdata->retune_mobile_cfgs[best].name,
386  pdata->retune_mobile_cfgs[best].rate,
387  wm8996->rx_rate[iface]);
388 
389  /* The EQ will be disabled while reconfiguring it, remember the
390  * current configuration.
391  */
392  save = snd_soc_read(codec, base);
393  save &= WM8996_DSP1RX_EQ_ENA;
394 
395  for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
396  snd_soc_update_bits(codec, base + i, 0xffff,
397  pdata->retune_mobile_cfgs[best].regs[i]);
398 
399  snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
400 }
401 
402 /* Icky as hell but saves code duplication */
403 static int wm8996_get_retune_mobile_block(const char *name)
404 {
405  if (strcmp(name, "DSP1 EQ Mode") == 0)
406  return 0;
407  if (strcmp(name, "DSP2 EQ Mode") == 0)
408  return 1;
409  return -EINVAL;
410 }
411 
412 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
413  struct snd_ctl_elem_value *ucontrol)
414 {
415  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
416  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
417  struct wm8996_pdata *pdata = &wm8996->pdata;
418  int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
419  int value = ucontrol->value.integer.value[0];
420 
421  if (block < 0)
422  return block;
423 
424  if (value >= pdata->num_retune_mobile_cfgs)
425  return -EINVAL;
426 
427  wm8996->retune_mobile_cfg[block] = value;
428 
429  wm8996_set_retune_mobile(codec, block);
430 
431  return 0;
432 }
433 
434 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
435  struct snd_ctl_elem_value *ucontrol)
436 {
437  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
438  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
439  int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
440 
441  ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
442 
443  return 0;
444 }
445 
446 static const struct snd_kcontrol_new wm8996_snd_controls[] = {
447 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
448  WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
449 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
450  WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
451 
452 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
453  0, 5, 24, 0, sidetone_tlv),
454 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
455  0, 5, 24, 0, sidetone_tlv),
456 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
457 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
458 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
459 
460 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
461  WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
462 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
463  WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
464 
465 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
466  13, 1, 0),
467 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
468 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
469 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
470 
471 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
472  13, 1, 0),
473 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
474 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
475 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
476 
477 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
478  WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
479 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
480 
481 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
482  WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
483 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
484 
485 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
486  WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
487 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
488  WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
489 
490 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
491  WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
492 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
493  WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
494 
495 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
496 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
497 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
498 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
499 
500 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
501 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
502 
503 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
504 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
505 
506 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
507  0, threedstereo_tlv),
508 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
509  0, threedstereo_tlv),
510 
511 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
512  8, 0, out_digital_tlv),
513 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
514  8, 0, out_digital_tlv),
515 
516 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
517  WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
518 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
519  WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
520 
521 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
522  WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
523 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
524  WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
525 
526 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
527  spk_tlv),
528 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
529  WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
530 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
531  WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
532 
533 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
534 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
535 
536 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
537 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
538 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
539 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
540  WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
541  WM8996_DSP1TXR_DRC_ENA),
542 
543 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
544 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
545 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
546 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
547  WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
548  WM8996_DSP2TXR_DRC_ENA),
549 };
550 
551 static const struct snd_kcontrol_new wm8996_eq_controls[] = {
552 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
553  eq_tlv),
554 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
555  eq_tlv),
556 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
557  eq_tlv),
558 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
559  eq_tlv),
560 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
561  eq_tlv),
562 
563 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
564  eq_tlv),
565 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
566  eq_tlv),
567 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
568  eq_tlv),
569 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
570  eq_tlv),
571 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
572  eq_tlv),
573 };
574 
575 static void wm8996_bg_enable(struct snd_soc_codec *codec)
576 {
577  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
578 
579  wm8996->bg_ena++;
580  if (wm8996->bg_ena == 1) {
581  snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
582  WM8996_BG_ENA, WM8996_BG_ENA);
583  msleep(2);
584  }
585 }
586 
587 static void wm8996_bg_disable(struct snd_soc_codec *codec)
588 {
589  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
590 
591  wm8996->bg_ena--;
592  if (!wm8996->bg_ena)
593  snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
594  WM8996_BG_ENA, 0);
595 }
596 
597 static int bg_event(struct snd_soc_dapm_widget *w,
598  struct snd_kcontrol *kcontrol, int event)
599 {
600  struct snd_soc_codec *codec = w->codec;
601  int ret = 0;
602 
603  switch (event) {
604  case SND_SOC_DAPM_PRE_PMU:
605  wm8996_bg_enable(codec);
606  break;
607  case SND_SOC_DAPM_POST_PMD:
608  wm8996_bg_disable(codec);
609  break;
610  default:
611  BUG();
612  ret = -EINVAL;
613  }
614 
615  return ret;
616 }
617 
618 static int cp_event(struct snd_soc_dapm_widget *w,
619  struct snd_kcontrol *kcontrol, int event)
620 {
621  int ret = 0;
622 
623  switch (event) {
624  case SND_SOC_DAPM_POST_PMU:
625  msleep(5);
626  break;
627  default:
628  BUG();
629  ret = -EINVAL;
630  }
631 
632  return 0;
633 }
634 
635 static int rmv_short_event(struct snd_soc_dapm_widget *w,
636  struct snd_kcontrol *kcontrol, int event)
637 {
638  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
639 
640  /* Record which outputs we enabled */
641  switch (event) {
642  case SND_SOC_DAPM_PRE_PMD:
643  wm8996->hpout_pending &= ~w->shift;
644  break;
645  case SND_SOC_DAPM_PRE_PMU:
646  wm8996->hpout_pending |= w->shift;
647  break;
648  default:
649  BUG();
650  return -EINVAL;
651  }
652 
653  return 0;
654 }
655 
656 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
657 {
658  struct i2c_client *i2c = to_i2c_client(codec->dev);
659  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
660  int ret;
661  unsigned long timeout = 200;
662 
663  snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
664 
665  /* Use the interrupt if possible */
666  do {
667  if (i2c->irq) {
668  timeout = wait_for_completion_timeout(&wm8996->dcs_done,
669  msecs_to_jiffies(200));
670  if (timeout == 0)
671  dev_err(codec->dev, "DC servo timed out\n");
672 
673  } else {
674  msleep(1);
675  timeout--;
676  }
677 
678  ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
679  dev_dbg(codec->dev, "DC servo state: %x\n", ret);
680  } while (timeout && ret & mask);
681 
682  if (timeout == 0)
683  dev_err(codec->dev, "DC servo timed out for %x\n", mask);
684  else
685  dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
686 }
687 
688 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
689  enum snd_soc_dapm_type event, int subseq)
690 {
691  struct snd_soc_codec *codec = container_of(dapm,
692  struct snd_soc_codec, dapm);
693  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
694  u16 val, mask;
695 
696  /* Complete any pending DC servo starts */
697  if (wm8996->dcs_pending) {
698  dev_dbg(codec->dev, "Starting DC servo for %x\n",
699  wm8996->dcs_pending);
700 
701  /* Trigger a startup sequence */
702  wait_for_dc_servo(codec, wm8996->dcs_pending
703  << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
704 
705  wm8996->dcs_pending = 0;
706  }
707 
708  if (wm8996->hpout_pending != wm8996->hpout_ena) {
709  dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
710  wm8996->hpout_ena, wm8996->hpout_pending);
711 
712  val = 0;
713  mask = 0;
714  if (wm8996->hpout_pending & HPOUT1L) {
715  val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
716  mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
717  } else {
718  mask |= WM8996_HPOUT1L_RMV_SHORT |
719  WM8996_HPOUT1L_OUTP |
720  WM8996_HPOUT1L_DLY;
721  }
722 
723  if (wm8996->hpout_pending & HPOUT1R) {
724  val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
725  mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
726  } else {
727  mask |= WM8996_HPOUT1R_RMV_SHORT |
728  WM8996_HPOUT1R_OUTP |
729  WM8996_HPOUT1R_DLY;
730  }
731 
732  snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
733 
734  val = 0;
735  mask = 0;
736  if (wm8996->hpout_pending & HPOUT2L) {
737  val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
738  mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
739  } else {
740  mask |= WM8996_HPOUT2L_RMV_SHORT |
741  WM8996_HPOUT2L_OUTP |
742  WM8996_HPOUT2L_DLY;
743  }
744 
745  if (wm8996->hpout_pending & HPOUT2R) {
746  val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
747  mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
748  } else {
749  mask |= WM8996_HPOUT2R_RMV_SHORT |
750  WM8996_HPOUT2R_OUTP |
751  WM8996_HPOUT2R_DLY;
752  }
753 
754  snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
755 
756  wm8996->hpout_ena = wm8996->hpout_pending;
757  }
758 }
759 
760 static int dcs_start(struct snd_soc_dapm_widget *w,
761  struct snd_kcontrol *kcontrol, int event)
762 {
763  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
764 
765  switch (event) {
766  case SND_SOC_DAPM_POST_PMU:
767  wm8996->dcs_pending |= 1 << w->shift;
768  break;
769  default:
770  BUG();
771  return -EINVAL;
772  }
773 
774  return 0;
775 }
776 
777 static const char *sidetone_text[] = {
778  "IN1", "IN2",
779 };
780 
781 static const struct soc_enum left_sidetone_enum =
782  SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
783 
784 static const struct snd_kcontrol_new left_sidetone =
785  SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
786 
787 static const struct soc_enum right_sidetone_enum =
788  SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
789 
790 static const struct snd_kcontrol_new right_sidetone =
791  SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
792 
793 static const char *spk_text[] = {
794  "DAC1L", "DAC1R", "DAC2L", "DAC2R"
795 };
796 
797 static const struct soc_enum spkl_enum =
798  SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
799 
800 static const struct snd_kcontrol_new spkl_mux =
801  SOC_DAPM_ENUM("SPKL", spkl_enum);
802 
803 static const struct soc_enum spkr_enum =
804  SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
805 
806 static const struct snd_kcontrol_new spkr_mux =
807  SOC_DAPM_ENUM("SPKR", spkr_enum);
808 
809 static const char *dsp1rx_text[] = {
810  "AIF1", "AIF2"
811 };
812 
813 static const struct soc_enum dsp1rx_enum =
814  SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
815 
816 static const struct snd_kcontrol_new dsp1rx =
817  SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
818 
819 static const char *dsp2rx_text[] = {
820  "AIF2", "AIF1"
821 };
822 
823 static const struct soc_enum dsp2rx_enum =
824  SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
825 
826 static const struct snd_kcontrol_new dsp2rx =
827  SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
828 
829 static const char *aif2tx_text[] = {
830  "DSP2", "DSP1", "AIF1"
831 };
832 
833 static const struct soc_enum aif2tx_enum =
834  SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
835 
836 static const struct snd_kcontrol_new aif2tx =
837  SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
838 
839 static const char *inmux_text[] = {
840  "ADC", "DMIC1", "DMIC2"
841 };
842 
843 static const struct soc_enum in1_enum =
844  SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
845 
846 static const struct snd_kcontrol_new in1_mux =
847  SOC_DAPM_ENUM("IN1 Mux", in1_enum);
848 
849 static const struct soc_enum in2_enum =
850  SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
851 
852 static const struct snd_kcontrol_new in2_mux =
853  SOC_DAPM_ENUM("IN2 Mux", in2_enum);
854 
855 static const struct snd_kcontrol_new dac2r_mix[] = {
856 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
857  5, 1, 0),
858 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
859  4, 1, 0),
860 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
861 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
862 };
863 
864 static const struct snd_kcontrol_new dac2l_mix[] = {
865 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
866  5, 1, 0),
867 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
868  4, 1, 0),
869 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
870 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
871 };
872 
873 static const struct snd_kcontrol_new dac1r_mix[] = {
874 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
875  5, 1, 0),
876 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
877  4, 1, 0),
878 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
879 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
880 };
881 
882 static const struct snd_kcontrol_new dac1l_mix[] = {
883 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
884  5, 1, 0),
885 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
886  4, 1, 0),
887 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
888 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
889 };
890 
891 static const struct snd_kcontrol_new dsp1txl[] = {
892 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
893  1, 1, 0),
894 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
895  0, 1, 0),
896 };
897 
898 static const struct snd_kcontrol_new dsp1txr[] = {
899 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
900  1, 1, 0),
901 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
902  0, 1, 0),
903 };
904 
905 static const struct snd_kcontrol_new dsp2txl[] = {
906 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
907  1, 1, 0),
908 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
909  0, 1, 0),
910 };
911 
912 static const struct snd_kcontrol_new dsp2txr[] = {
913 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
914  1, 1, 0),
915 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
916  0, 1, 0),
917 };
918 
919 
920 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
921 SND_SOC_DAPM_INPUT("IN1LN"),
922 SND_SOC_DAPM_INPUT("IN1LP"),
923 SND_SOC_DAPM_INPUT("IN1RN"),
924 SND_SOC_DAPM_INPUT("IN1RP"),
925 
926 SND_SOC_DAPM_INPUT("IN2LN"),
927 SND_SOC_DAPM_INPUT("IN2LP"),
928 SND_SOC_DAPM_INPUT("IN2RN"),
929 SND_SOC_DAPM_INPUT("IN2RP"),
930 
931 SND_SOC_DAPM_INPUT("DMIC1DAT"),
932 SND_SOC_DAPM_INPUT("DMIC2DAT"),
933 
934 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
935 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
936 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
937 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
938 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
939  SND_SOC_DAPM_POST_PMU),
940 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
941  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
942 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
943 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
944 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
945 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
946 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
947 
948 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
949 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
950 
951 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
952 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
953 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
954 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
955 
956 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
957 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
958 
959 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
960 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
961 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
962 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
963 
964 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
965 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
966 
967 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
968 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
969 
970 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
971 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
972 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
973 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
974 
975 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
976  dsp2txl, ARRAY_SIZE(dsp2txl)),
977 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
978  dsp2txr, ARRAY_SIZE(dsp2txr)),
979 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
980  dsp1txl, ARRAY_SIZE(dsp1txl)),
981 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
982  dsp1txr, ARRAY_SIZE(dsp1txr)),
983 
984 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
985  dac2l_mix, ARRAY_SIZE(dac2l_mix)),
986 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
987  dac2r_mix, ARRAY_SIZE(dac2r_mix)),
988 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
989  dac1l_mix, ARRAY_SIZE(dac1l_mix)),
990 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
991  dac1r_mix, ARRAY_SIZE(dac1r_mix)),
992 
993 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
994 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
995 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
996 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
997 
998 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0),
999 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0),
1000 
1001 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0),
1002 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0),
1003 
1004 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0),
1005 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0),
1006 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0),
1007 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0),
1008 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0),
1009 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0),
1010 
1011 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0),
1012 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0),
1013 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0),
1014 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0),
1015 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0),
1016 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0),
1017 
1018 /* We route as stereo pairs so define some dummy widgets to squash
1019  * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1020 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1021 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1022 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1023 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1024 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1025 
1026 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1027 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1028 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1029 
1030 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1031 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1032 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1033 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1034 
1035 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1036 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1037 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1038  SND_SOC_DAPM_POST_PMU),
1039 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1040  rmv_short_event,
1041  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1042 
1043 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1044 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1045 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1046  SND_SOC_DAPM_POST_PMU),
1047 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1048  rmv_short_event,
1049  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1050 
1051 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1052 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1053 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1054  SND_SOC_DAPM_POST_PMU),
1055 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1056  rmv_short_event,
1057  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1058 
1059 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1060 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1061 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1062  SND_SOC_DAPM_POST_PMU),
1063 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1064  rmv_short_event,
1065  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1066 
1067 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1068 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1069 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1070 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1071 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1072 };
1073 
1074 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1075  { "AIFCLK", NULL, "SYSCLK" },
1076  { "SYSDSPCLK", NULL, "SYSCLK" },
1077  { "Charge Pump", NULL, "SYSCLK" },
1078  { "Charge Pump", NULL, "CPVDD" },
1079 
1080  { "MICB1", NULL, "LDO2" },
1081  { "MICB1", NULL, "MICB1 Audio" },
1082  { "MICB1", NULL, "Bandgap" },
1083  { "MICB2", NULL, "LDO2" },
1084  { "MICB2", NULL, "MICB2 Audio" },
1085  { "MICB2", NULL, "Bandgap" },
1086 
1087  { "AIF1RX0", NULL, "AIF1 Playback" },
1088  { "AIF1RX1", NULL, "AIF1 Playback" },
1089  { "AIF1RX2", NULL, "AIF1 Playback" },
1090  { "AIF1RX3", NULL, "AIF1 Playback" },
1091  { "AIF1RX4", NULL, "AIF1 Playback" },
1092  { "AIF1RX5", NULL, "AIF1 Playback" },
1093 
1094  { "AIF2RX0", NULL, "AIF2 Playback" },
1095  { "AIF2RX1", NULL, "AIF2 Playback" },
1096 
1097  { "AIF1 Capture", NULL, "AIF1TX0" },
1098  { "AIF1 Capture", NULL, "AIF1TX1" },
1099  { "AIF1 Capture", NULL, "AIF1TX2" },
1100  { "AIF1 Capture", NULL, "AIF1TX3" },
1101  { "AIF1 Capture", NULL, "AIF1TX4" },
1102  { "AIF1 Capture", NULL, "AIF1TX5" },
1103 
1104  { "AIF2 Capture", NULL, "AIF2TX0" },
1105  { "AIF2 Capture", NULL, "AIF2TX1" },
1106 
1107  { "IN1L PGA", NULL, "IN2LN" },
1108  { "IN1L PGA", NULL, "IN2LP" },
1109  { "IN1L PGA", NULL, "IN1LN" },
1110  { "IN1L PGA", NULL, "IN1LP" },
1111  { "IN1L PGA", NULL, "Bandgap" },
1112 
1113  { "IN1R PGA", NULL, "IN2RN" },
1114  { "IN1R PGA", NULL, "IN2RP" },
1115  { "IN1R PGA", NULL, "IN1RN" },
1116  { "IN1R PGA", NULL, "IN1RP" },
1117  { "IN1R PGA", NULL, "Bandgap" },
1118 
1119  { "ADCL", NULL, "IN1L PGA" },
1120 
1121  { "ADCR", NULL, "IN1R PGA" },
1122 
1123  { "DMIC1L", NULL, "DMIC1DAT" },
1124  { "DMIC1R", NULL, "DMIC1DAT" },
1125  { "DMIC2L", NULL, "DMIC2DAT" },
1126  { "DMIC2R", NULL, "DMIC2DAT" },
1127 
1128  { "DMIC2L", NULL, "DMIC2" },
1129  { "DMIC2R", NULL, "DMIC2" },
1130  { "DMIC1L", NULL, "DMIC1" },
1131  { "DMIC1R", NULL, "DMIC1" },
1132 
1133  { "IN1L Mux", "ADC", "ADCL" },
1134  { "IN1L Mux", "DMIC1", "DMIC1L" },
1135  { "IN1L Mux", "DMIC2", "DMIC2L" },
1136 
1137  { "IN1R Mux", "ADC", "ADCR" },
1138  { "IN1R Mux", "DMIC1", "DMIC1R" },
1139  { "IN1R Mux", "DMIC2", "DMIC2R" },
1140 
1141  { "IN2L Mux", "ADC", "ADCL" },
1142  { "IN2L Mux", "DMIC1", "DMIC1L" },
1143  { "IN2L Mux", "DMIC2", "DMIC2L" },
1144 
1145  { "IN2R Mux", "ADC", "ADCR" },
1146  { "IN2R Mux", "DMIC1", "DMIC1R" },
1147  { "IN2R Mux", "DMIC2", "DMIC2R" },
1148 
1149  { "Left Sidetone", "IN1", "IN1L Mux" },
1150  { "Left Sidetone", "IN2", "IN2L Mux" },
1151 
1152  { "Right Sidetone", "IN1", "IN1R Mux" },
1153  { "Right Sidetone", "IN2", "IN2R Mux" },
1154 
1155  { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1156  { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1157 
1158  { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1159  { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1160 
1161  { "AIF1TX0", NULL, "DSP1TXL" },
1162  { "AIF1TX1", NULL, "DSP1TXR" },
1163  { "AIF1TX2", NULL, "DSP2TXL" },
1164  { "AIF1TX3", NULL, "DSP2TXR" },
1165  { "AIF1TX4", NULL, "AIF2RX0" },
1166  { "AIF1TX5", NULL, "AIF2RX1" },
1167 
1168  { "AIF1RX0", NULL, "AIFCLK" },
1169  { "AIF1RX1", NULL, "AIFCLK" },
1170  { "AIF1RX2", NULL, "AIFCLK" },
1171  { "AIF1RX3", NULL, "AIFCLK" },
1172  { "AIF1RX4", NULL, "AIFCLK" },
1173  { "AIF1RX5", NULL, "AIFCLK" },
1174 
1175  { "AIF2RX0", NULL, "AIFCLK" },
1176  { "AIF2RX1", NULL, "AIFCLK" },
1177 
1178  { "AIF1TX0", NULL, "AIFCLK" },
1179  { "AIF1TX1", NULL, "AIFCLK" },
1180  { "AIF1TX2", NULL, "AIFCLK" },
1181  { "AIF1TX3", NULL, "AIFCLK" },
1182  { "AIF1TX4", NULL, "AIFCLK" },
1183  { "AIF1TX5", NULL, "AIFCLK" },
1184 
1185  { "AIF2TX0", NULL, "AIFCLK" },
1186  { "AIF2TX1", NULL, "AIFCLK" },
1187 
1188  { "DSP1RXL", NULL, "SYSDSPCLK" },
1189  { "DSP1RXR", NULL, "SYSDSPCLK" },
1190  { "DSP2RXL", NULL, "SYSDSPCLK" },
1191  { "DSP2RXR", NULL, "SYSDSPCLK" },
1192  { "DSP1TXL", NULL, "SYSDSPCLK" },
1193  { "DSP1TXR", NULL, "SYSDSPCLK" },
1194  { "DSP2TXL", NULL, "SYSDSPCLK" },
1195  { "DSP2TXR", NULL, "SYSDSPCLK" },
1196 
1197  { "AIF1RXA", NULL, "AIF1RX0" },
1198  { "AIF1RXA", NULL, "AIF1RX1" },
1199  { "AIF1RXB", NULL, "AIF1RX2" },
1200  { "AIF1RXB", NULL, "AIF1RX3" },
1201  { "AIF1RXC", NULL, "AIF1RX4" },
1202  { "AIF1RXC", NULL, "AIF1RX5" },
1203 
1204  { "AIF2RX", NULL, "AIF2RX0" },
1205  { "AIF2RX", NULL, "AIF2RX1" },
1206 
1207  { "AIF2TX", "DSP2", "DSP2TX" },
1208  { "AIF2TX", "DSP1", "DSP1RX" },
1209  { "AIF2TX", "AIF1", "AIF1RXC" },
1210 
1211  { "DSP1RXL", NULL, "DSP1RX" },
1212  { "DSP1RXR", NULL, "DSP1RX" },
1213  { "DSP2RXL", NULL, "DSP2RX" },
1214  { "DSP2RXR", NULL, "DSP2RX" },
1215 
1216  { "DSP2TX", NULL, "DSP2TXL" },
1217  { "DSP2TX", NULL, "DSP2TXR" },
1218 
1219  { "DSP1RX", "AIF1", "AIF1RXA" },
1220  { "DSP1RX", "AIF2", "AIF2RX" },
1221 
1222  { "DSP2RX", "AIF1", "AIF1RXB" },
1223  { "DSP2RX", "AIF2", "AIF2RX" },
1224 
1225  { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1226  { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1227  { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1228  { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1229 
1230  { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1231  { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1232  { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1233  { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1234 
1235  { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1236  { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1237  { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1238  { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1239 
1240  { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1241  { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1242  { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1243  { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1244 
1245  { "DAC1L", NULL, "DAC1L Mixer" },
1246  { "DAC1R", NULL, "DAC1R Mixer" },
1247  { "DAC2L", NULL, "DAC2L Mixer" },
1248  { "DAC2R", NULL, "DAC2R Mixer" },
1249 
1250  { "HPOUT2L PGA", NULL, "Charge Pump" },
1251  { "HPOUT2L PGA", NULL, "Bandgap" },
1252  { "HPOUT2L PGA", NULL, "DAC2L" },
1253  { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1254  { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1255  { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" },
1256 
1257  { "HPOUT2R PGA", NULL, "Charge Pump" },
1258  { "HPOUT2R PGA", NULL, "Bandgap" },
1259  { "HPOUT2R PGA", NULL, "DAC2R" },
1260  { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1261  { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1262  { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" },
1263 
1264  { "HPOUT1L PGA", NULL, "Charge Pump" },
1265  { "HPOUT1L PGA", NULL, "Bandgap" },
1266  { "HPOUT1L PGA", NULL, "DAC1L" },
1267  { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1268  { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1269  { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" },
1270 
1271  { "HPOUT1R PGA", NULL, "Charge Pump" },
1272  { "HPOUT1R PGA", NULL, "Bandgap" },
1273  { "HPOUT1R PGA", NULL, "DAC1R" },
1274  { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1275  { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1276  { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" },
1277 
1278  { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1279  { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1280  { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1281  { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1282 
1283  { "SPKL", "DAC1L", "DAC1L" },
1284  { "SPKL", "DAC1R", "DAC1R" },
1285  { "SPKL", "DAC2L", "DAC2L" },
1286  { "SPKL", "DAC2R", "DAC2R" },
1287 
1288  { "SPKR", "DAC1L", "DAC1L" },
1289  { "SPKR", "DAC1R", "DAC1R" },
1290  { "SPKR", "DAC2L", "DAC2L" },
1291  { "SPKR", "DAC2R", "DAC2R" },
1292 
1293  { "SPKL PGA", NULL, "SPKL" },
1294  { "SPKR PGA", NULL, "SPKR" },
1295 
1296  { "SPKDAT", NULL, "SPKL PGA" },
1297  { "SPKDAT", NULL, "SPKR PGA" },
1298 };
1299 
1300 static bool wm8996_readable_register(struct device *dev, unsigned int reg)
1301 {
1302  /* Due to the sparseness of the register map the compiler
1303  * output from an explicit switch statement ends up being much
1304  * more efficient than a table.
1305  */
1306  switch (reg) {
1307  case WM8996_SOFTWARE_RESET:
1308  case WM8996_POWER_MANAGEMENT_1:
1309  case WM8996_POWER_MANAGEMENT_2:
1310  case WM8996_POWER_MANAGEMENT_3:
1311  case WM8996_POWER_MANAGEMENT_4:
1312  case WM8996_POWER_MANAGEMENT_5:
1313  case WM8996_POWER_MANAGEMENT_6:
1314  case WM8996_POWER_MANAGEMENT_7:
1315  case WM8996_POWER_MANAGEMENT_8:
1316  case WM8996_LEFT_LINE_INPUT_VOLUME:
1317  case WM8996_RIGHT_LINE_INPUT_VOLUME:
1318  case WM8996_LINE_INPUT_CONTROL:
1319  case WM8996_DAC1_HPOUT1_VOLUME:
1320  case WM8996_DAC2_HPOUT2_VOLUME:
1321  case WM8996_DAC1_LEFT_VOLUME:
1322  case WM8996_DAC1_RIGHT_VOLUME:
1323  case WM8996_DAC2_LEFT_VOLUME:
1324  case WM8996_DAC2_RIGHT_VOLUME:
1325  case WM8996_OUTPUT1_LEFT_VOLUME:
1326  case WM8996_OUTPUT1_RIGHT_VOLUME:
1327  case WM8996_OUTPUT2_LEFT_VOLUME:
1328  case WM8996_OUTPUT2_RIGHT_VOLUME:
1329  case WM8996_MICBIAS_1:
1330  case WM8996_MICBIAS_2:
1331  case WM8996_LDO_1:
1332  case WM8996_LDO_2:
1333  case WM8996_ACCESSORY_DETECT_MODE_1:
1334  case WM8996_ACCESSORY_DETECT_MODE_2:
1335  case WM8996_HEADPHONE_DETECT_1:
1336  case WM8996_HEADPHONE_DETECT_2:
1337  case WM8996_MIC_DETECT_1:
1338  case WM8996_MIC_DETECT_2:
1339  case WM8996_MIC_DETECT_3:
1340  case WM8996_CHARGE_PUMP_1:
1341  case WM8996_CHARGE_PUMP_2:
1342  case WM8996_DC_SERVO_1:
1343  case WM8996_DC_SERVO_2:
1344  case WM8996_DC_SERVO_3:
1345  case WM8996_DC_SERVO_5:
1346  case WM8996_DC_SERVO_6:
1347  case WM8996_DC_SERVO_7:
1348  case WM8996_DC_SERVO_READBACK_0:
1349  case WM8996_ANALOGUE_HP_1:
1350  case WM8996_ANALOGUE_HP_2:
1351  case WM8996_CHIP_REVISION:
1352  case WM8996_CONTROL_INTERFACE_1:
1353  case WM8996_WRITE_SEQUENCER_CTRL_1:
1354  case WM8996_WRITE_SEQUENCER_CTRL_2:
1355  case WM8996_AIF_CLOCKING_1:
1356  case WM8996_AIF_CLOCKING_2:
1357  case WM8996_CLOCKING_1:
1358  case WM8996_CLOCKING_2:
1359  case WM8996_AIF_RATE:
1360  case WM8996_FLL_CONTROL_1:
1361  case WM8996_FLL_CONTROL_2:
1362  case WM8996_FLL_CONTROL_3:
1363  case WM8996_FLL_CONTROL_4:
1364  case WM8996_FLL_CONTROL_5:
1365  case WM8996_FLL_CONTROL_6:
1366  case WM8996_FLL_EFS_1:
1367  case WM8996_FLL_EFS_2:
1368  case WM8996_AIF1_CONTROL:
1369  case WM8996_AIF1_BCLK:
1370  case WM8996_AIF1_TX_LRCLK_1:
1371  case WM8996_AIF1_TX_LRCLK_2:
1372  case WM8996_AIF1_RX_LRCLK_1:
1373  case WM8996_AIF1_RX_LRCLK_2:
1374  case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1375  case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1376  case WM8996_AIF1RX_DATA_CONFIGURATION:
1377  case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1378  case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1379  case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1380  case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1381  case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1382  case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1383  case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1384  case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1385  case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1386  case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1387  case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1388  case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1389  case WM8996_AIF1RX_MONO_CONFIGURATION:
1390  case WM8996_AIF1TX_TEST:
1391  case WM8996_AIF2_CONTROL:
1392  case WM8996_AIF2_BCLK:
1393  case WM8996_AIF2_TX_LRCLK_1:
1394  case WM8996_AIF2_TX_LRCLK_2:
1395  case WM8996_AIF2_RX_LRCLK_1:
1396  case WM8996_AIF2_RX_LRCLK_2:
1397  case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1398  case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1399  case WM8996_AIF2RX_DATA_CONFIGURATION:
1400  case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1401  case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1402  case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1403  case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1404  case WM8996_AIF2RX_MONO_CONFIGURATION:
1405  case WM8996_AIF2TX_TEST:
1406  case WM8996_DSP1_TX_LEFT_VOLUME:
1407  case WM8996_DSP1_TX_RIGHT_VOLUME:
1408  case WM8996_DSP1_RX_LEFT_VOLUME:
1409  case WM8996_DSP1_RX_RIGHT_VOLUME:
1410  case WM8996_DSP1_TX_FILTERS:
1411  case WM8996_DSP1_RX_FILTERS_1:
1412  case WM8996_DSP1_RX_FILTERS_2:
1413  case WM8996_DSP1_DRC_1:
1414  case WM8996_DSP1_DRC_2:
1415  case WM8996_DSP1_DRC_3:
1416  case WM8996_DSP1_DRC_4:
1417  case WM8996_DSP1_DRC_5:
1418  case WM8996_DSP1_RX_EQ_GAINS_1:
1419  case WM8996_DSP1_RX_EQ_GAINS_2:
1420  case WM8996_DSP1_RX_EQ_BAND_1_A:
1421  case WM8996_DSP1_RX_EQ_BAND_1_B:
1422  case WM8996_DSP1_RX_EQ_BAND_1_PG:
1423  case WM8996_DSP1_RX_EQ_BAND_2_A:
1424  case WM8996_DSP1_RX_EQ_BAND_2_B:
1425  case WM8996_DSP1_RX_EQ_BAND_2_C:
1426  case WM8996_DSP1_RX_EQ_BAND_2_PG:
1427  case WM8996_DSP1_RX_EQ_BAND_3_A:
1428  case WM8996_DSP1_RX_EQ_BAND_3_B:
1429  case WM8996_DSP1_RX_EQ_BAND_3_C:
1430  case WM8996_DSP1_RX_EQ_BAND_3_PG:
1431  case WM8996_DSP1_RX_EQ_BAND_4_A:
1432  case WM8996_DSP1_RX_EQ_BAND_4_B:
1433  case WM8996_DSP1_RX_EQ_BAND_4_C:
1434  case WM8996_DSP1_RX_EQ_BAND_4_PG:
1435  case WM8996_DSP1_RX_EQ_BAND_5_A:
1436  case WM8996_DSP1_RX_EQ_BAND_5_B:
1437  case WM8996_DSP1_RX_EQ_BAND_5_PG:
1438  case WM8996_DSP2_TX_LEFT_VOLUME:
1439  case WM8996_DSP2_TX_RIGHT_VOLUME:
1440  case WM8996_DSP2_RX_LEFT_VOLUME:
1441  case WM8996_DSP2_RX_RIGHT_VOLUME:
1442  case WM8996_DSP2_TX_FILTERS:
1443  case WM8996_DSP2_RX_FILTERS_1:
1444  case WM8996_DSP2_RX_FILTERS_2:
1445  case WM8996_DSP2_DRC_1:
1446  case WM8996_DSP2_DRC_2:
1447  case WM8996_DSP2_DRC_3:
1448  case WM8996_DSP2_DRC_4:
1449  case WM8996_DSP2_DRC_5:
1450  case WM8996_DSP2_RX_EQ_GAINS_1:
1451  case WM8996_DSP2_RX_EQ_GAINS_2:
1452  case WM8996_DSP2_RX_EQ_BAND_1_A:
1453  case WM8996_DSP2_RX_EQ_BAND_1_B:
1454  case WM8996_DSP2_RX_EQ_BAND_1_PG:
1455  case WM8996_DSP2_RX_EQ_BAND_2_A:
1456  case WM8996_DSP2_RX_EQ_BAND_2_B:
1457  case WM8996_DSP2_RX_EQ_BAND_2_C:
1458  case WM8996_DSP2_RX_EQ_BAND_2_PG:
1459  case WM8996_DSP2_RX_EQ_BAND_3_A:
1460  case WM8996_DSP2_RX_EQ_BAND_3_B:
1461  case WM8996_DSP2_RX_EQ_BAND_3_C:
1462  case WM8996_DSP2_RX_EQ_BAND_3_PG:
1463  case WM8996_DSP2_RX_EQ_BAND_4_A:
1464  case WM8996_DSP2_RX_EQ_BAND_4_B:
1465  case WM8996_DSP2_RX_EQ_BAND_4_C:
1466  case WM8996_DSP2_RX_EQ_BAND_4_PG:
1467  case WM8996_DSP2_RX_EQ_BAND_5_A:
1468  case WM8996_DSP2_RX_EQ_BAND_5_B:
1469  case WM8996_DSP2_RX_EQ_BAND_5_PG:
1470  case WM8996_DAC1_MIXER_VOLUMES:
1471  case WM8996_DAC1_LEFT_MIXER_ROUTING:
1472  case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1473  case WM8996_DAC2_MIXER_VOLUMES:
1474  case WM8996_DAC2_LEFT_MIXER_ROUTING:
1475  case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1476  case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1477  case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1478  case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1479  case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1480  case WM8996_DSP_TX_MIXER_SELECT:
1481  case WM8996_DAC_SOFTMUTE:
1482  case WM8996_OVERSAMPLING:
1483  case WM8996_SIDETONE:
1484  case WM8996_GPIO_1:
1485  case WM8996_GPIO_2:
1486  case WM8996_GPIO_3:
1487  case WM8996_GPIO_4:
1488  case WM8996_GPIO_5:
1489  case WM8996_PULL_CONTROL_1:
1490  case WM8996_PULL_CONTROL_2:
1491  case WM8996_INTERRUPT_STATUS_1:
1492  case WM8996_INTERRUPT_STATUS_2:
1493  case WM8996_INTERRUPT_RAW_STATUS_2:
1494  case WM8996_INTERRUPT_STATUS_1_MASK:
1495  case WM8996_INTERRUPT_STATUS_2_MASK:
1496  case WM8996_INTERRUPT_CONTROL:
1497  case WM8996_LEFT_PDM_SPEAKER:
1498  case WM8996_RIGHT_PDM_SPEAKER:
1499  case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1500  case WM8996_PDM_SPEAKER_VOLUME:
1501  return 1;
1502  default:
1503  return 0;
1504  }
1505 }
1506 
1507 static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
1508 {
1509  switch (reg) {
1510  case WM8996_SOFTWARE_RESET:
1511  case WM8996_CHIP_REVISION:
1512  case WM8996_LDO_1:
1513  case WM8996_LDO_2:
1514  case WM8996_INTERRUPT_STATUS_1:
1515  case WM8996_INTERRUPT_STATUS_2:
1516  case WM8996_INTERRUPT_RAW_STATUS_2:
1517  case WM8996_DC_SERVO_READBACK_0:
1518  case WM8996_DC_SERVO_2:
1519  case WM8996_DC_SERVO_6:
1520  case WM8996_DC_SERVO_7:
1521  case WM8996_FLL_CONTROL_6:
1522  case WM8996_MIC_DETECT_3:
1523  case WM8996_HEADPHONE_DETECT_1:
1524  case WM8996_HEADPHONE_DETECT_2:
1525  return 1;
1526  default:
1527  return 0;
1528  }
1529 }
1530 
1531 static const int bclk_divs[] = {
1532  1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1533 };
1534 
1535 static void wm8996_update_bclk(struct snd_soc_codec *codec)
1536 {
1537  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1538  int aif, best, cur_val, bclk_rate, bclk_reg, i;
1539 
1540  /* Don't bother if we're in a low frequency idle mode that
1541  * can't support audio.
1542  */
1543  if (wm8996->sysclk < 64000)
1544  return;
1545 
1546  for (aif = 0; aif < WM8996_AIFS; aif++) {
1547  switch (aif) {
1548  case 0:
1549  bclk_reg = WM8996_AIF1_BCLK;
1550  break;
1551  case 1:
1552  bclk_reg = WM8996_AIF2_BCLK;
1553  break;
1554  }
1555 
1556  bclk_rate = wm8996->bclk_rate[aif];
1557 
1558  /* Pick a divisor for BCLK as close as we can get to ideal */
1559  best = 0;
1560  for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1561  cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1562  if (cur_val < 0) /* BCLK table is sorted */
1563  break;
1564  best = i;
1565  }
1566  bclk_rate = wm8996->sysclk / bclk_divs[best];
1567  dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1568  bclk_divs[best], bclk_rate);
1569 
1570  snd_soc_update_bits(codec, bclk_reg,
1571  WM8996_AIF1_BCLK_DIV_MASK, best);
1572  }
1573 }
1574 
1575 static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1576  enum snd_soc_bias_level level)
1577 {
1578  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1579  int ret;
1580 
1581  switch (level) {
1582  case SND_SOC_BIAS_ON:
1583  break;
1584  case SND_SOC_BIAS_PREPARE:
1585  /* Put the MICBIASes into regulating mode */
1586  snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1587  WM8996_MICB1_MODE, 0);
1588  snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1589  WM8996_MICB2_MODE, 0);
1590  break;
1591 
1592  case SND_SOC_BIAS_STANDBY:
1593  if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1594  ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1595  wm8996->supplies);
1596  if (ret != 0) {
1597  dev_err(codec->dev,
1598  "Failed to enable supplies: %d\n",
1599  ret);
1600  return ret;
1601  }
1602 
1603  if (wm8996->pdata.ldo_ena >= 0) {
1604  gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1605  1);
1606  msleep(5);
1607  }
1608 
1609  regcache_cache_only(codec->control_data, false);
1610  regcache_sync(codec->control_data);
1611  }
1612 
1613  /* Bypass the MICBIASes for lowest power */
1614  snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1615  WM8996_MICB1_MODE, WM8996_MICB1_MODE);
1616  snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1617  WM8996_MICB2_MODE, WM8996_MICB2_MODE);
1618  break;
1619 
1620  case SND_SOC_BIAS_OFF:
1621  regcache_cache_only(codec->control_data, true);
1622  if (wm8996->pdata.ldo_ena >= 0) {
1623  gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1624  regcache_cache_only(codec->control_data, true);
1625  }
1626  regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1627  wm8996->supplies);
1628  break;
1629  }
1630 
1631  codec->dapm.bias_level = level;
1632 
1633  return 0;
1634 }
1635 
1636 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1637 {
1638  struct snd_soc_codec *codec = dai->codec;
1639  int aifctrl = 0;
1640  int bclk = 0;
1641  int lrclk_tx = 0;
1642  int lrclk_rx = 0;
1643  int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1644 
1645  switch (dai->id) {
1646  case 0:
1647  aifctrl_reg = WM8996_AIF1_CONTROL;
1648  bclk_reg = WM8996_AIF1_BCLK;
1649  lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1650  lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1651  break;
1652  case 1:
1653  aifctrl_reg = WM8996_AIF2_CONTROL;
1654  bclk_reg = WM8996_AIF2_BCLK;
1655  lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1656  lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1657  break;
1658  default:
1659  BUG();
1660  return -EINVAL;
1661  }
1662 
1663  switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1664  case SND_SOC_DAIFMT_NB_NF:
1665  break;
1666  case SND_SOC_DAIFMT_IB_NF:
1667  bclk |= WM8996_AIF1_BCLK_INV;
1668  break;
1669  case SND_SOC_DAIFMT_NB_IF:
1670  lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1671  lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1672  break;
1673  case SND_SOC_DAIFMT_IB_IF:
1674  bclk |= WM8996_AIF1_BCLK_INV;
1675  lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1676  lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1677  break;
1678  }
1679 
1680  switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1681  case SND_SOC_DAIFMT_CBS_CFS:
1682  break;
1683  case SND_SOC_DAIFMT_CBS_CFM:
1684  lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1685  lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1686  break;
1687  case SND_SOC_DAIFMT_CBM_CFS:
1688  bclk |= WM8996_AIF1_BCLK_MSTR;
1689  break;
1690  case SND_SOC_DAIFMT_CBM_CFM:
1691  bclk |= WM8996_AIF1_BCLK_MSTR;
1692  lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1693  lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1694  break;
1695  default:
1696  return -EINVAL;
1697  }
1698 
1699  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1700  case SND_SOC_DAIFMT_DSP_A:
1701  break;
1702  case SND_SOC_DAIFMT_DSP_B:
1703  aifctrl |= 1;
1704  break;
1705  case SND_SOC_DAIFMT_I2S:
1706  aifctrl |= 2;
1707  break;
1708  case SND_SOC_DAIFMT_LEFT_J:
1709  aifctrl |= 3;
1710  break;
1711  default:
1712  return -EINVAL;
1713  }
1714 
1715  snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1716  snd_soc_update_bits(codec, bclk_reg,
1717  WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1718  bclk);
1719  snd_soc_update_bits(codec, lrclk_tx_reg,
1720  WM8996_AIF1TX_LRCLK_INV |
1721  WM8996_AIF1TX_LRCLK_MSTR,
1722  lrclk_tx);
1723  snd_soc_update_bits(codec, lrclk_rx_reg,
1724  WM8996_AIF1RX_LRCLK_INV |
1725  WM8996_AIF1RX_LRCLK_MSTR,
1726  lrclk_rx);
1727 
1728  return 0;
1729 }
1730 
1731 static const int dsp_divs[] = {
1732  48000, 32000, 16000, 8000
1733 };
1734 
1735 static int wm8996_hw_params(struct snd_pcm_substream *substream,
1736  struct snd_pcm_hw_params *params,
1737  struct snd_soc_dai *dai)
1738 {
1739  struct snd_soc_codec *codec = dai->codec;
1740  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1741  int bits, i, bclk_rate, best;
1742  int aifdata = 0;
1743  int lrclk = 0;
1744  int dsp = 0;
1745  int aifdata_reg, lrclk_reg, dsp_shift;
1746 
1747  switch (dai->id) {
1748  case 0:
1749  if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1750  (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1751  aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1752  lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1753  } else {
1754  aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1755  lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1756  }
1757  dsp_shift = 0;
1758  break;
1759  case 1:
1760  if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1761  (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1762  aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1763  lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1764  } else {
1765  aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1766  lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1767  }
1768  dsp_shift = WM8996_DSP2_DIV_SHIFT;
1769  break;
1770  default:
1771  BUG();
1772  return -EINVAL;
1773  }
1774 
1775  bclk_rate = snd_soc_params_to_bclk(params);
1776  if (bclk_rate < 0) {
1777  dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1778  return bclk_rate;
1779  }
1780 
1781  wm8996->bclk_rate[dai->id] = bclk_rate;
1782  wm8996->rx_rate[dai->id] = params_rate(params);
1783 
1784  /* Needs looking at for TDM */
1785  bits = snd_pcm_format_width(params_format(params));
1786  if (bits < 0)
1787  return bits;
1788  aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1789 
1790  best = 0;
1791  for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1792  if (abs(dsp_divs[i] - params_rate(params)) <
1793  abs(dsp_divs[best] - params_rate(params)))
1794  best = i;
1795  }
1796  dsp |= i << dsp_shift;
1797 
1798  wm8996_update_bclk(codec);
1799 
1800  lrclk = bclk_rate / params_rate(params);
1801  dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1802  lrclk, bclk_rate / lrclk);
1803 
1804  snd_soc_update_bits(codec, aifdata_reg,
1805  WM8996_AIF1TX_WL_MASK |
1806  WM8996_AIF1TX_SLOT_LEN_MASK,
1807  aifdata);
1808  snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1809  lrclk);
1810  snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1811  WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
1812 
1813  return 0;
1814 }
1815 
1816 static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1817  int clk_id, unsigned int freq, int dir)
1818 {
1819  struct snd_soc_codec *codec = dai->codec;
1820  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1821  int lfclk = 0;
1822  int ratediv = 0;
1823  int sync = WM8996_REG_SYNC;
1824  int src;
1825  int old;
1826 
1827  if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1828  return 0;
1829 
1830  /* Disable SYSCLK while we reconfigure */
1831  old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1832  snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1833  WM8996_SYSCLK_ENA, 0);
1834 
1835  switch (clk_id) {
1836  case WM8996_SYSCLK_MCLK1:
1837  wm8996->sysclk = freq;
1838  src = 0;
1839  break;
1840  case WM8996_SYSCLK_MCLK2:
1841  wm8996->sysclk = freq;
1842  src = 1;
1843  break;
1844  case WM8996_SYSCLK_FLL:
1845  wm8996->sysclk = freq;
1846  src = 2;
1847  break;
1848  default:
1849  dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1850  return -EINVAL;
1851  }
1852 
1853  switch (wm8996->sysclk) {
1854  case 5644800:
1855  case 6144000:
1856  snd_soc_update_bits(codec, WM8996_AIF_RATE,
1857  WM8996_SYSCLK_RATE, 0);
1858  break;
1859  case 22579200:
1860  case 24576000:
1861  ratediv = WM8996_SYSCLK_DIV;
1862  wm8996->sysclk /= 2;
1863  case 11289600:
1864  case 12288000:
1865  snd_soc_update_bits(codec, WM8996_AIF_RATE,
1866  WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1867  break;
1868  case 32000:
1869  case 32768:
1870  lfclk = WM8996_LFCLK_ENA;
1871  sync = 0;
1872  break;
1873  default:
1874  dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1875  wm8996->sysclk);
1876  return -EINVAL;
1877  }
1878 
1879  wm8996_update_bclk(codec);
1880 
1881  snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1882  WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1883  src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1884  snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1885  snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
1886  WM8996_REG_SYNC, sync);
1887  snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1888  WM8996_SYSCLK_ENA, old);
1889 
1890  wm8996->sysclk_src = clk_id;
1891 
1892  return 0;
1893 }
1894 
1895 struct _fll_div {
1896  u16 fll_fratio;
1897  u16 fll_outdiv;
1898  u16 fll_refclk_div;
1899  u16 fll_loop_gain;
1900  u16 fll_ref_freq;
1901  u16 n;
1902  u16 theta;
1903  u16 lambda;
1904 };
1905 
1906 static struct {
1907  unsigned int min;
1908  unsigned int max;
1909  u16 fll_fratio;
1910  int ratio;
1911 } fll_fratios[] = {
1912  { 0, 64000, 4, 16 },
1913  { 64000, 128000, 3, 8 },
1914  { 128000, 256000, 2, 4 },
1915  { 256000, 1000000, 1, 2 },
1916  { 1000000, 13500000, 0, 1 },
1917 };
1918 
1919 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1920  unsigned int Fout)
1921 {
1922  unsigned int target;
1923  unsigned int div;
1924  unsigned int fratio, gcd_fll;
1925  int i;
1926 
1927  /* Fref must be <=13.5MHz */
1928  div = 1;
1929  fll_div->fll_refclk_div = 0;
1930  while ((Fref / div) > 13500000) {
1931  div *= 2;
1932  fll_div->fll_refclk_div++;
1933 
1934  if (div > 8) {
1935  pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1936  Fref);
1937  return -EINVAL;
1938  }
1939  }
1940 
1941  pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1942 
1943  /* Apply the division for our remaining calculations */
1944  Fref /= div;
1945 
1946  if (Fref >= 3000000)
1947  fll_div->fll_loop_gain = 5;
1948  else
1949  fll_div->fll_loop_gain = 0;
1950 
1951  if (Fref >= 48000)
1952  fll_div->fll_ref_freq = 0;
1953  else
1954  fll_div->fll_ref_freq = 1;
1955 
1956  /* Fvco should be 90-100MHz; don't check the upper bound */
1957  div = 2;
1958  while (Fout * div < 90000000) {
1959  div++;
1960  if (div > 64) {
1961  pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1962  Fout);
1963  return -EINVAL;
1964  }
1965  }
1966  target = Fout * div;
1967  fll_div->fll_outdiv = div - 1;
1968 
1969  pr_debug("FLL Fvco=%dHz\n", target);
1970 
1971  /* Find an appropraite FLL_FRATIO and factor it out of the target */
1972  for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1973  if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1974  fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1975  fratio = fll_fratios[i].ratio;
1976  break;
1977  }
1978  }
1979  if (i == ARRAY_SIZE(fll_fratios)) {
1980  pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1981  return -EINVAL;
1982  }
1983 
1984  fll_div->n = target / (fratio * Fref);
1985 
1986  if (target % Fref == 0) {
1987  fll_div->theta = 0;
1988  fll_div->lambda = 0;
1989  } else {
1990  gcd_fll = gcd(target, fratio * Fref);
1991 
1992  fll_div->theta = (target - (fll_div->n * fratio * Fref))
1993  / gcd_fll;
1994  fll_div->lambda = (fratio * Fref) / gcd_fll;
1995  }
1996 
1997  pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1998  fll_div->n, fll_div->theta, fll_div->lambda);
1999  pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2000  fll_div->fll_fratio, fll_div->fll_outdiv,
2001  fll_div->fll_refclk_div);
2002 
2003  return 0;
2004 }
2005 
2006 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2007  unsigned int Fref, unsigned int Fout)
2008 {
2009  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2010  struct i2c_client *i2c = to_i2c_client(codec->dev);
2011  struct _fll_div fll_div;
2012  unsigned long timeout;
2013  int ret, reg, retry;
2014 
2015  /* Any change? */
2016  if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2017  Fout == wm8996->fll_fout)
2018  return 0;
2019 
2020  if (Fout == 0) {
2021  dev_dbg(codec->dev, "FLL disabled\n");
2022 
2023  wm8996->fll_fref = 0;
2024  wm8996->fll_fout = 0;
2025 
2026  snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2027  WM8996_FLL_ENA, 0);
2028 
2029  wm8996_bg_disable(codec);
2030 
2031  return 0;
2032  }
2033 
2034  ret = fll_factors(&fll_div, Fref, Fout);
2035  if (ret != 0)
2036  return ret;
2037 
2038  switch (source) {
2039  case WM8996_FLL_MCLK1:
2040  reg = 0;
2041  break;
2042  case WM8996_FLL_MCLK2:
2043  reg = 1;
2044  break;
2045  case WM8996_FLL_DACLRCLK1:
2046  reg = 2;
2047  break;
2048  case WM8996_FLL_BCLK1:
2049  reg = 3;
2050  break;
2051  default:
2052  dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2053  return -EINVAL;
2054  }
2055 
2056  reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2057  reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2058 
2059  snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2060  WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2061  WM8996_FLL_REFCLK_SRC_MASK, reg);
2062 
2063  reg = 0;
2064  if (fll_div.theta || fll_div.lambda)
2065  reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2066  else
2067  reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2068  snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2069 
2070  snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2071  WM8996_FLL_OUTDIV_MASK |
2072  WM8996_FLL_FRATIO_MASK,
2073  (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2074  (fll_div.fll_fratio));
2075 
2076  snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2077 
2078  snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2079  WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2080  (fll_div.n << WM8996_FLL_N_SHIFT) |
2081  fll_div.fll_loop_gain);
2082 
2083  snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2084 
2085  /* Enable the bandgap if it's not already enabled */
2086  ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2087  if (!(ret & WM8996_FLL_ENA))
2088  wm8996_bg_enable(codec);
2089 
2090  /* Clear any pending completions (eg, from failed startups) */
2091  try_wait_for_completion(&wm8996->fll_lock);
2092 
2093  snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2094  WM8996_FLL_ENA, WM8996_FLL_ENA);
2095 
2096  /* The FLL supports live reconfiguration - kick that in case we were
2097  * already enabled.
2098  */
2099  snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2100 
2101  /* Wait for the FLL to lock, using the interrupt if possible */
2102  if (Fref > 1000000)
2103  timeout = usecs_to_jiffies(300);
2104  else
2105  timeout = msecs_to_jiffies(2);
2106 
2107  /* Allow substantially longer if we've actually got the IRQ, poll
2108  * at a slightly higher rate if we don't.
2109  */
2110  if (i2c->irq)
2111  timeout *= 10;
2112  else
2113  timeout /= 2;
2114 
2115  for (retry = 0; retry < 10; retry++) {
2116  ret = wait_for_completion_timeout(&wm8996->fll_lock,
2117  timeout);
2118  if (ret != 0) {
2119  WARN_ON(!i2c->irq);
2120  break;
2121  }
2122 
2123  ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2124  if (ret & WM8996_FLL_LOCK_STS)
2125  break;
2126  }
2127  if (retry == 10) {
2128  dev_err(codec->dev, "Timed out waiting for FLL\n");
2129  ret = -ETIMEDOUT;
2130  }
2131 
2132  dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2133 
2134  wm8996->fll_fref = Fref;
2135  wm8996->fll_fout = Fout;
2136  wm8996->fll_src = source;
2137 
2138  return ret;
2139 }
2140 
2141 #ifdef CONFIG_GPIOLIB
2142 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2143 {
2144  return container_of(chip, struct wm8996_priv, gpio_chip);
2145 }
2146 
2147 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2148 {
2149  struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2150 
2151  regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2152  WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2153 }
2154 
2155 static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2156  unsigned offset, int value)
2157 {
2158  struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2159  int val;
2160 
2161  val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2162 
2163  return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2164  WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2165  WM8996_GP1_LVL, val);
2166 }
2167 
2168 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2169 {
2170  struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2171  unsigned int reg;
2172  int ret;
2173 
2174  ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
2175  if (ret < 0)
2176  return ret;
2177 
2178  return (reg & WM8996_GP1_LVL) != 0;
2179 }
2180 
2181 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2182 {
2183  struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2184 
2185  return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2186  WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2187  (1 << WM8996_GP1_FN_SHIFT) |
2188  (1 << WM8996_GP1_DIR_SHIFT));
2189 }
2190 
2191 static struct gpio_chip wm8996_template_chip = {
2192  .label = "wm8996",
2193  .owner = THIS_MODULE,
2194  .direction_output = wm8996_gpio_direction_out,
2195  .set = wm8996_gpio_set,
2196  .direction_input = wm8996_gpio_direction_in,
2197  .get = wm8996_gpio_get,
2198  .can_sleep = 1,
2199 };
2200 
2201 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2202 {
2203  int ret;
2204 
2205  wm8996->gpio_chip = wm8996_template_chip;
2206  wm8996->gpio_chip.ngpio = 5;
2207  wm8996->gpio_chip.dev = wm8996->dev;
2208 
2209  if (wm8996->pdata.gpio_base)
2210  wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2211  else
2212  wm8996->gpio_chip.base = -1;
2213 
2214  ret = gpiochip_add(&wm8996->gpio_chip);
2215  if (ret != 0)
2216  dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
2217 }
2218 
2219 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2220 {
2221  int ret;
2222 
2223  ret = gpiochip_remove(&wm8996->gpio_chip);
2224  if (ret != 0)
2225  dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret);
2226 }
2227 #else
2228 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2229 {
2230 }
2231 
2232 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2233 {
2234 }
2235 #endif
2236 
2248 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2249  wm8996_polarity_fn polarity_cb)
2250 {
2251  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2252 
2253  wm8996->jack = jack;
2254  wm8996->detecting = true;
2255  wm8996->polarity_cb = polarity_cb;
2256  wm8996->jack_flips = 0;
2257 
2258  if (wm8996->polarity_cb)
2259  wm8996->polarity_cb(codec, 0);
2260 
2261  /* Clear discarge to avoid noise during detection */
2262  snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2263  WM8996_MICB1_DISCH, 0);
2264  snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2265  WM8996_MICB2_DISCH, 0);
2266 
2267  /* LDO2 powers the microphones, SYSCLK clocks detection */
2268  snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2269  snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2270 
2271  /* We start off just enabling microphone detection - even a
2272  * plain headphone will trigger detection.
2273  */
2274  snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2275  WM8996_MICD_ENA, WM8996_MICD_ENA);
2276 
2277  /* Slowest detection rate, gives debounce for initial detection */
2278  snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2279  WM8996_MICD_RATE_MASK,
2280  WM8996_MICD_RATE_MASK);
2281 
2282  /* Enable interrupts and we're off */
2283  snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2284  WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
2285 
2286  return 0;
2287 }
2288 EXPORT_SYMBOL_GPL(wm8996_detect);
2289 
2290 static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2291 {
2292  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2293  int val, reg, report;
2294 
2295  /* Assume headphone in error conditions; we need to report
2296  * something or we stall our state machine.
2297  */
2298  report = SND_JACK_HEADPHONE;
2299 
2300  reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2301  if (reg < 0) {
2302  dev_err(codec->dev, "Failed to read HPDET status\n");
2303  goto out;
2304  }
2305 
2306  if (!(reg & WM8996_HP_DONE)) {
2307  dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2308  goto out;
2309  }
2310 
2311  val = reg & WM8996_HP_LVL_MASK;
2312 
2313  dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2314 
2315  /* If we've got high enough impedence then report as line,
2316  * otherwise assume headphone.
2317  */
2318  if (val >= 126)
2319  report = SND_JACK_LINEOUT;
2320  else
2321  report = SND_JACK_HEADPHONE;
2322 
2323 out:
2324  if (wm8996->jack_mic)
2325  report |= SND_JACK_MICROPHONE;
2326 
2327  snd_soc_jack_report(wm8996->jack, report,
2328  SND_JACK_LINEOUT | SND_JACK_HEADSET);
2329 
2330  wm8996->detecting = false;
2331 
2332  /* If the output isn't running re-clamp it */
2333  if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2334  (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2335  snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2336  WM8996_HPOUT1L_RMV_SHORT |
2337  WM8996_HPOUT1R_RMV_SHORT, 0);
2338 
2339  /* Go back to looking at the microphone */
2340  snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2341  WM8996_JD_MODE_MASK, 0);
2342  snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2343  WM8996_MICD_ENA);
2344 
2345  snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2346  snd_soc_dapm_sync(&codec->dapm);
2347 }
2348 
2349 static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2350 {
2351  /* Unclamp the output, we can't measure while we're shorting it */
2352  snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2353  WM8996_HPOUT1L_RMV_SHORT |
2354  WM8996_HPOUT1R_RMV_SHORT,
2355  WM8996_HPOUT1L_RMV_SHORT |
2356  WM8996_HPOUT1R_RMV_SHORT);
2357 
2358  /* We need bandgap for HPDET */
2359  snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2360  snd_soc_dapm_sync(&codec->dapm);
2361 
2362  /* Go into headphone detect left mode */
2363  snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2364  snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2365  WM8996_JD_MODE_MASK, 1);
2366 
2367  /* Trigger a measurement */
2368  snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2369  WM8996_HP_POLL, WM8996_HP_POLL);
2370 }
2371 
2372 static void wm8996_report_headphone(struct snd_soc_codec *codec)
2373 {
2374  dev_dbg(codec->dev, "Headphone detected\n");
2375  wm8996_hpdet_start(codec);
2376 
2377  /* Increase the detection rate a bit for responsiveness. */
2378  snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2379  WM8996_MICD_RATE_MASK |
2380  WM8996_MICD_BIAS_STARTTIME_MASK,
2381  7 << WM8996_MICD_RATE_SHIFT |
2382  7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2383 }
2384 
2385 static void wm8996_micd(struct snd_soc_codec *codec)
2386 {
2387  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2388  int val, reg;
2389 
2390  val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2391 
2392  dev_dbg(codec->dev, "Microphone event: %x\n", val);
2393 
2394  if (!(val & WM8996_MICD_VALID)) {
2395  dev_warn(codec->dev, "Microphone detection state invalid\n");
2396  return;
2397  }
2398 
2399  /* No accessory, reset everything and report removal */
2400  if (!(val & WM8996_MICD_STS)) {
2401  dev_dbg(codec->dev, "Jack removal detected\n");
2402  wm8996->jack_mic = false;
2403  wm8996->detecting = true;
2404  wm8996->jack_flips = 0;
2405  snd_soc_jack_report(wm8996->jack, 0,
2406  SND_JACK_LINEOUT | SND_JACK_HEADSET |
2407  SND_JACK_BTN_0);
2408 
2409  snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2410  WM8996_MICD_RATE_MASK |
2411  WM8996_MICD_BIAS_STARTTIME_MASK,
2412  WM8996_MICD_RATE_MASK |
2413  9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2414  return;
2415  }
2416 
2417  /* If the measurement is very high we've got a microphone,
2418  * either we just detected one or if we already reported then
2419  * we've got a button release event.
2420  */
2421  if (val & 0x400) {
2422  if (wm8996->detecting) {
2423  dev_dbg(codec->dev, "Microphone detected\n");
2424  wm8996->jack_mic = true;
2425  wm8996_hpdet_start(codec);
2426 
2427  /* Increase poll rate to give better responsiveness
2428  * for buttons */
2429  snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2430  WM8996_MICD_RATE_MASK |
2431  WM8996_MICD_BIAS_STARTTIME_MASK,
2432  5 << WM8996_MICD_RATE_SHIFT |
2433  7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2434  } else {
2435  dev_dbg(codec->dev, "Mic button up\n");
2436  snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2437  }
2438 
2439  return;
2440  }
2441 
2442  /* If we detected a lower impedence during initial startup
2443  * then we probably have the wrong polarity, flip it. Don't
2444  * do this for the lowest impedences to speed up detection of
2445  * plain headphones. If both polarities report a low
2446  * impedence then give up and report headphones.
2447  */
2448  if (wm8996->detecting && (val & 0x3f0)) {
2449  wm8996->jack_flips++;
2450 
2451  if (wm8996->jack_flips > 1) {
2452  wm8996_report_headphone(codec);
2453  return;
2454  }
2455 
2456  reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2457  reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2458  WM8996_MICD_BIAS_SRC;
2459  snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2460  WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2461  WM8996_MICD_BIAS_SRC, reg);
2462 
2463  if (wm8996->polarity_cb)
2464  wm8996->polarity_cb(codec,
2465  (reg & WM8996_MICD_SRC) != 0);
2466 
2467  dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2468  (reg & WM8996_MICD_SRC) != 0);
2469 
2470  return;
2471  }
2472 
2473  /* Don't distinguish between buttons, just report any low
2474  * impedence as BTN_0.
2475  */
2476  if (val & 0x3fc) {
2477  if (wm8996->jack_mic) {
2478  dev_dbg(codec->dev, "Mic button detected\n");
2479  snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
2480  SND_JACK_BTN_0);
2481  } else if (wm8996->detecting) {
2482  wm8996_report_headphone(codec);
2483  }
2484  }
2485 }
2486 
2487 static irqreturn_t wm8996_irq(int irq, void *data)
2488 {
2489  struct snd_soc_codec *codec = data;
2490  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2491  int irq_val;
2492 
2493  irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2494  if (irq_val < 0) {
2495  dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2496  irq_val);
2497  return IRQ_NONE;
2498  }
2499  irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2500 
2501  if (!irq_val)
2502  return IRQ_NONE;
2503 
2504  snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2505 
2506  if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2507  dev_dbg(codec->dev, "DC servo IRQ\n");
2508  complete(&wm8996->dcs_done);
2509  }
2510 
2511  if (irq_val & WM8996_FIFOS_ERR_EINT)
2512  dev_err(codec->dev, "Digital core FIFO error\n");
2513 
2514  if (irq_val & WM8996_FLL_LOCK_EINT) {
2515  dev_dbg(codec->dev, "FLL locked\n");
2516  complete(&wm8996->fll_lock);
2517  }
2518 
2519  if (irq_val & WM8996_MICD_EINT)
2520  wm8996_micd(codec);
2521 
2522  if (irq_val & WM8996_HP_DONE_EINT)
2523  wm8996_hpdet_irq(codec);
2524 
2525  return IRQ_HANDLED;
2526 }
2527 
2528 static irqreturn_t wm8996_edge_irq(int irq, void *data)
2529 {
2530  irqreturn_t ret = IRQ_NONE;
2531  irqreturn_t val;
2532 
2533  do {
2534  val = wm8996_irq(irq, data);
2535  if (val != IRQ_NONE)
2536  ret = val;
2537  } while (val != IRQ_NONE);
2538 
2539  return ret;
2540 }
2541 
2542 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2543 {
2544  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2545  struct wm8996_pdata *pdata = &wm8996->pdata;
2546 
2547  struct snd_kcontrol_new controls[] = {
2548  SOC_ENUM_EXT("DSP1 EQ Mode",
2549  wm8996->retune_mobile_enum,
2550  wm8996_get_retune_mobile_enum,
2551  wm8996_put_retune_mobile_enum),
2552  SOC_ENUM_EXT("DSP2 EQ Mode",
2553  wm8996->retune_mobile_enum,
2554  wm8996_get_retune_mobile_enum,
2555  wm8996_put_retune_mobile_enum),
2556  };
2557  int ret, i, j;
2558  const char **t;
2559 
2560  /* We need an array of texts for the enum API but the number
2561  * of texts is likely to be less than the number of
2562  * configurations due to the sample rate dependency of the
2563  * configurations. */
2564  wm8996->num_retune_mobile_texts = 0;
2565  wm8996->retune_mobile_texts = NULL;
2566  for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2567  for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2568  if (strcmp(pdata->retune_mobile_cfgs[i].name,
2569  wm8996->retune_mobile_texts[j]) == 0)
2570  break;
2571  }
2572 
2573  if (j != wm8996->num_retune_mobile_texts)
2574  continue;
2575 
2576  /* Expand the array... */
2577  t = krealloc(wm8996->retune_mobile_texts,
2578  sizeof(char *) *
2579  (wm8996->num_retune_mobile_texts + 1),
2580  GFP_KERNEL);
2581  if (t == NULL)
2582  continue;
2583 
2584  /* ...store the new entry... */
2585  t[wm8996->num_retune_mobile_texts] =
2586  pdata->retune_mobile_cfgs[i].name;
2587 
2588  /* ...and remember the new version. */
2589  wm8996->num_retune_mobile_texts++;
2590  wm8996->retune_mobile_texts = t;
2591  }
2592 
2593  dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2594  wm8996->num_retune_mobile_texts);
2595 
2596  wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2597  wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2598 
2599  ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
2600  if (ret != 0)
2601  dev_err(codec->dev,
2602  "Failed to add ReTune Mobile controls: %d\n", ret);
2603 }
2604 
2605 static const struct regmap_config wm8996_regmap = {
2606  .reg_bits = 16,
2607  .val_bits = 16,
2608 
2609  .max_register = WM8996_MAX_REGISTER,
2610  .reg_defaults = wm8996_reg,
2611  .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2612  .volatile_reg = wm8996_volatile_register,
2613  .readable_reg = wm8996_readable_register,
2614  .cache_type = REGCACHE_RBTREE,
2615 };
2616 
2617 static int wm8996_probe(struct snd_soc_codec *codec)
2618 {
2619  int ret;
2620  struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2621  struct i2c_client *i2c = to_i2c_client(codec->dev);
2622  int irq_flags;
2623 
2624  wm8996->codec = codec;
2625 
2626  init_completion(&wm8996->dcs_done);
2627  init_completion(&wm8996->fll_lock);
2628 
2629  codec->control_data = wm8996->regmap;
2630 
2631  ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2632  if (ret != 0) {
2633  dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2634  goto err;
2635  }
2636 
2637  if (wm8996->pdata.num_retune_mobile_cfgs)
2638  wm8996_retune_mobile_pdata(codec);
2639  else
2640  snd_soc_add_codec_controls(codec, wm8996_eq_controls,
2641  ARRAY_SIZE(wm8996_eq_controls));
2642 
2643  if (i2c->irq) {
2644  if (wm8996->pdata.irq_flags)
2645  irq_flags = wm8996->pdata.irq_flags;
2646  else
2647  irq_flags = IRQF_TRIGGER_LOW;
2648 
2649  irq_flags |= IRQF_ONESHOT;
2650 
2651  if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2652  ret = request_threaded_irq(i2c->irq, NULL,
2653  wm8996_edge_irq,
2654  irq_flags, "wm8996", codec);
2655  else
2656  ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2657  irq_flags, "wm8996", codec);
2658 
2659  if (ret == 0) {
2660  /* Unmask the interrupt */
2661  snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2662  WM8996_IM_IRQ, 0);
2663 
2664  /* Enable error reporting and DC servo status */
2665  snd_soc_update_bits(codec,
2666  WM8996_INTERRUPT_STATUS_2_MASK,
2667  WM8996_IM_DCS_DONE_23_EINT |
2668  WM8996_IM_DCS_DONE_01_EINT |
2669  WM8996_IM_FLL_LOCK_EINT |
2670  WM8996_IM_FIFOS_ERR_EINT,
2671  0);
2672  } else {
2673  dev_err(codec->dev, "Failed to request IRQ: %d\n",
2674  ret);
2675  }
2676  }
2677 
2678  return 0;
2679 
2680 err:
2681  return ret;
2682 }
2683 
2684 static int wm8996_remove(struct snd_soc_codec *codec)
2685 {
2686  struct i2c_client *i2c = to_i2c_client(codec->dev);
2687 
2688  snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2689  WM8996_IM_IRQ, WM8996_IM_IRQ);
2690 
2691  if (i2c->irq)
2692  free_irq(i2c->irq, codec);
2693 
2694  return 0;
2695 }
2696 
2697 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
2698  .probe = wm8996_probe,
2699  .remove = wm8996_remove,
2700  .set_bias_level = wm8996_set_bias_level,
2701  .idle_bias_off = true,
2702  .seq_notifier = wm8996_seq_notifier,
2703  .controls = wm8996_snd_controls,
2704  .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2705  .dapm_widgets = wm8996_dapm_widgets,
2706  .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
2707  .dapm_routes = wm8996_dapm_routes,
2708  .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
2709  .set_pll = wm8996_set_fll,
2710 };
2711 
2712 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2713  SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
2714  SNDRV_PCM_RATE_48000)
2715 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2716  SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2717  SNDRV_PCM_FMTBIT_S32_LE)
2718 
2719 static const struct snd_soc_dai_ops wm8996_dai_ops = {
2720  .set_fmt = wm8996_set_fmt,
2721  .hw_params = wm8996_hw_params,
2722  .set_sysclk = wm8996_set_sysclk,
2723 };
2724 
2725 static struct snd_soc_dai_driver wm8996_dai[] = {
2726  {
2727  .name = "wm8996-aif1",
2728  .playback = {
2729  .stream_name = "AIF1 Playback",
2730  .channels_min = 1,
2731  .channels_max = 6,
2732  .rates = WM8996_RATES,
2733  .formats = WM8996_FORMATS,
2734  .sig_bits = 24,
2735  },
2736  .capture = {
2737  .stream_name = "AIF1 Capture",
2738  .channels_min = 1,
2739  .channels_max = 6,
2740  .rates = WM8996_RATES,
2741  .formats = WM8996_FORMATS,
2742  .sig_bits = 24,
2743  },
2744  .ops = &wm8996_dai_ops,
2745  },
2746  {
2747  .name = "wm8996-aif2",
2748  .playback = {
2749  .stream_name = "AIF2 Playback",
2750  .channels_min = 1,
2751  .channels_max = 2,
2752  .rates = WM8996_RATES,
2753  .formats = WM8996_FORMATS,
2754  .sig_bits = 24,
2755  },
2756  .capture = {
2757  .stream_name = "AIF2 Capture",
2758  .channels_min = 1,
2759  .channels_max = 2,
2760  .rates = WM8996_RATES,
2761  .formats = WM8996_FORMATS,
2762  .sig_bits = 24,
2763  },
2764  .ops = &wm8996_dai_ops,
2765  },
2766 };
2767 
2768 static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
2769  const struct i2c_device_id *id)
2770 {
2771  struct wm8996_priv *wm8996;
2772  int ret, i;
2773  unsigned int reg;
2774 
2775  wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
2776  GFP_KERNEL);
2777  if (wm8996 == NULL)
2778  return -ENOMEM;
2779 
2780  i2c_set_clientdata(i2c, wm8996);
2781  wm8996->dev = &i2c->dev;
2782 
2783  if (dev_get_platdata(&i2c->dev))
2784  memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
2785  sizeof(wm8996->pdata));
2786 
2787  if (wm8996->pdata.ldo_ena > 0) {
2788  ret = gpio_request_one(wm8996->pdata.ldo_ena,
2789  GPIOF_OUT_INIT_LOW, "WM8996 ENA");
2790  if (ret < 0) {
2791  dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2792  wm8996->pdata.ldo_ena, ret);
2793  goto err;
2794  }
2795  }
2796 
2797  for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2798  wm8996->supplies[i].supply = wm8996_supply_names[i];
2799 
2800  ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
2801  wm8996->supplies);
2802  if (ret != 0) {
2803  dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2804  goto err_gpio;
2805  }
2806 
2807  wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2808  wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2809  wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2810 
2811  /* This should really be moved into the regulator core */
2812  for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2813  ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2814  &wm8996->disable_nb[i]);
2815  if (ret != 0) {
2816  dev_err(&i2c->dev,
2817  "Failed to register regulator notifier: %d\n",
2818  ret);
2819  }
2820  }
2821 
2822  ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2823  wm8996->supplies);
2824  if (ret != 0) {
2825  dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2826  goto err_gpio;
2827  }
2828 
2829  if (wm8996->pdata.ldo_ena > 0) {
2830  gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2831  msleep(5);
2832  }
2833 
2834  wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap);
2835  if (IS_ERR(wm8996->regmap)) {
2836  ret = PTR_ERR(wm8996->regmap);
2837  dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
2838  goto err_enable;
2839  }
2840 
2841  ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
2842  if (ret < 0) {
2843  dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2844  goto err_regmap;
2845  }
2846  if (reg != 0x8915) {
2847  dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
2848  ret = -EINVAL;
2849  goto err_regmap;
2850  }
2851 
2852  ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
2853  if (ret < 0) {
2854  dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2855  ret);
2856  goto err_regmap;
2857  }
2858 
2859  dev_info(&i2c->dev, "revision %c\n",
2860  (reg & WM8996_CHIP_REV_MASK) + 'A');
2861 
2862  if (wm8996->pdata.ldo_ena > 0) {
2863  gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2864  regcache_cache_only(wm8996->regmap, true);
2865  } else {
2866  ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
2867  0x8915);
2868  if (ret != 0) {
2869  dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2870  goto err_regmap;
2871  }
2872  }
2873 
2874  regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2875 
2876  /* Apply platform data settings */
2877  regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL,
2878  WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2879  wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2880  wm8996->pdata.inr_mode);
2881 
2882  for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2883  if (!wm8996->pdata.gpio_default[i])
2884  continue;
2885 
2886  regmap_write(wm8996->regmap, WM8996_GPIO_1 + i,
2887  wm8996->pdata.gpio_default[i] & 0xffff);
2888  }
2889 
2890  if (wm8996->pdata.spkmute_seq)
2891  regmap_update_bits(wm8996->regmap,
2892  WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2893  WM8996_SPK_MUTE_ENDIAN |
2894  WM8996_SPK_MUTE_SEQ1_MASK,
2895  wm8996->pdata.spkmute_seq);
2896 
2897  regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2,
2898  WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2899  WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2900 
2901  /* Latch volume update bits */
2902  regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME,
2903  WM8996_IN1_VU, WM8996_IN1_VU);
2904  regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME,
2905  WM8996_IN1_VU, WM8996_IN1_VU);
2906 
2907  regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME,
2908  WM8996_DAC1_VU, WM8996_DAC1_VU);
2909  regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME,
2910  WM8996_DAC1_VU, WM8996_DAC1_VU);
2911  regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME,
2912  WM8996_DAC2_VU, WM8996_DAC2_VU);
2913  regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME,
2914  WM8996_DAC2_VU, WM8996_DAC2_VU);
2915 
2916  regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME,
2917  WM8996_DAC1_VU, WM8996_DAC1_VU);
2918  regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME,
2919  WM8996_DAC1_VU, WM8996_DAC1_VU);
2920  regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME,
2921  WM8996_DAC2_VU, WM8996_DAC2_VU);
2922  regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME,
2923  WM8996_DAC2_VU, WM8996_DAC2_VU);
2924 
2925  regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME,
2926  WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2927  regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME,
2928  WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2929  regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME,
2930  WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2931  regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME,
2932  WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2933 
2934  regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME,
2935  WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2936  regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME,
2937  WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2938  regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME,
2939  WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2940  regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME,
2941  WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2942 
2943  /* No support currently for the underclocked TDM modes and
2944  * pick a default TDM layout with each channel pair working with
2945  * slots 0 and 1. */
2946  regmap_update_bits(wm8996->regmap,
2947  WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2948  WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2949  WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2950  1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2951  regmap_update_bits(wm8996->regmap,
2952  WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2953  WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2954  WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2955  1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2956  regmap_update_bits(wm8996->regmap,
2957  WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2958  WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2959  WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2960  1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2961  regmap_update_bits(wm8996->regmap,
2962  WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2963  WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2964  WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2965  1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2966  regmap_update_bits(wm8996->regmap,
2967  WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2968  WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2969  WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2970  1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2971  regmap_update_bits(wm8996->regmap,
2972  WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2973  WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2974  WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2975  1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2976 
2977  regmap_update_bits(wm8996->regmap,
2978  WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2979  WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2980  WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2981  1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2982  regmap_update_bits(wm8996->regmap,
2983  WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2984  WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2985  WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2986  1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2987 
2988  regmap_update_bits(wm8996->regmap,
2989  WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2990  WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2991  WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2992  1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2993  regmap_update_bits(wm8996->regmap,
2994  WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2995  WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2996  WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2997  1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2998  regmap_update_bits(wm8996->regmap,
2999  WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
3000  WM8996_AIF1TX_CHAN2_SLOTS_MASK |
3001  WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3002  1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
3003  regmap_update_bits(wm8996->regmap,
3004  WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
3005  WM8996_AIF1TX_CHAN3_SLOTS_MASK |
3006  WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3007  1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
3008  regmap_update_bits(wm8996->regmap,
3009  WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
3010  WM8996_AIF1TX_CHAN4_SLOTS_MASK |
3011  WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3012  1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
3013  regmap_update_bits(wm8996->regmap,
3014  WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
3015  WM8996_AIF1TX_CHAN5_SLOTS_MASK |
3016  WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3017  1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
3018 
3019  regmap_update_bits(wm8996->regmap,
3020  WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
3021  WM8996_AIF2TX_CHAN0_SLOTS_MASK |
3022  WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
3023  1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
3024  regmap_update_bits(wm8996->regmap,
3025  WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
3026  WM8996_AIF2TX_CHAN1_SLOTS_MASK |
3027  WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
3028  1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
3029 
3030  /* If the TX LRCLK pins are not in LRCLK mode configure the
3031  * AIFs to source their clocks from the RX LRCLKs.
3032  */
3033  ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, &reg);
3034  if (ret != 0) {
3035  dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret);
3036  goto err_regmap;
3037  }
3038 
3039  if (reg & WM8996_GP1_FN_MASK)
3040  regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2,
3041  WM8996_AIF1TX_LRCLK_MODE,
3042  WM8996_AIF1TX_LRCLK_MODE);
3043 
3044  ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, &reg);
3045  if (ret != 0) {
3046  dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret);
3047  goto err_regmap;
3048  }
3049 
3050  if (reg & WM8996_GP2_FN_MASK)
3051  regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2,
3052  WM8996_AIF2TX_LRCLK_MODE,
3053  WM8996_AIF2TX_LRCLK_MODE);
3054 
3055  wm8996_init_gpio(wm8996);
3056 
3057  ret = snd_soc_register_codec(&i2c->dev,
3058  &soc_codec_dev_wm8996, wm8996_dai,
3059  ARRAY_SIZE(wm8996_dai));
3060  if (ret < 0)
3061  goto err_gpiolib;
3062 
3063  return ret;
3064 
3065 err_gpiolib:
3066  wm8996_free_gpio(wm8996);
3067 err_regmap:
3068 err_enable:
3069  if (wm8996->pdata.ldo_ena > 0)
3070  gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3071  regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3072 err_gpio:
3073  if (wm8996->pdata.ldo_ena > 0)
3074  gpio_free(wm8996->pdata.ldo_ena);
3075 err:
3076 
3077  return ret;
3078 }
3079 
3080 static __devexit int wm8996_i2c_remove(struct i2c_client *client)
3081 {
3082  struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3083  int i;
3084 
3085  snd_soc_unregister_codec(&client->dev);
3086  wm8996_free_gpio(wm8996);
3087  if (wm8996->pdata.ldo_ena > 0) {
3088  gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3089  gpio_free(wm8996->pdata.ldo_ena);
3090  }
3091  for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3092  regulator_unregister_notifier(wm8996->supplies[i].consumer,
3093  &wm8996->disable_nb[i]);
3094 
3095  return 0;
3096 }
3097 
3098 static const struct i2c_device_id wm8996_i2c_id[] = {
3099  { "wm8996", 0 },
3100  { }
3101 };
3102 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3103 
3104 static struct i2c_driver wm8996_i2c_driver = {
3105  .driver = {
3106  .name = "wm8996",
3107  .owner = THIS_MODULE,
3108  },
3109  .probe = wm8996_i2c_probe,
3110  .remove = __devexit_p(wm8996_i2c_remove),
3111  .id_table = wm8996_i2c_id,
3112 };
3113 
3114 module_i2c_driver(wm8996_i2c_driver);
3115 
3116 MODULE_DESCRIPTION("ASoC WM8996 driver");
3117 MODULE_AUTHOR("Mark Brown <[email protected]>");
3118 MODULE_LICENSE("GPL");
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