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1
Introduction
1.1
What is Covered?
1.2
What can code coverage do?
1.3
What can't code coverage do?
1.4
What does Covered do?
1.5
What does Covered NOT do?
1.6
What makes Covered different?
2
Coverage Metrics
2.1
Line Coverage
2.2
Toggle Coverage
2.3
Memory Coverage
2.4
Combinational Coverage
2.5
Finite State Machine (FSM) Coverage
2.6
Assertion Coverage
3
Coverage Boundaries
3.1
What logic can be analyzed?
3.2
What logic cannot be currently analyzed?
4
Race Condition Checking
4.1
Checked Coding Guidelines
4.2
Race Condition Handling
4.3
Reporting Race Conditions
4.4
Skipping Race Condition Checking
5
Installation
5.1
Prerequisites
5.2
Downloading source
5.3
Installing from source
6
Getting Started
6.1
What is needed for dumpfile scoring?
6.1.1
Creating a VCD dumpfile
6.1.2
Creating an LXT dumpfile
6.2
What is needed for VPI scoring?
6.2.1
Compiling for Icarus Verilog
6.2.2
Compiling for Cver
6.2.3
Compiling for VCS
7
Using Covered
7.1
Work Flow
7.2
Covered usage
7.3
Covered options
8
Inline Attributes
8.1
What are inline attributes?
8.2
Adding FSM attributes
9
The score Command
9.1
Usage
9.2
Options
9.3
Specifying What to Cover
9.4
Overriding Parameters (-P option)
9.5
Scoring FSMs
9.6
Other Notes
10
The merge Command
10.1
Usage
10.2
Options
11
The report Command
11.1
Usage
11.2
Options
11.3
Summary Vs. Detailed Vs. Verbose
11.4
Module Vs. Instance
11.5
Covered Vs. Uncovered
12
Reading the Report
12.1
Reading Line Coverage
12.2
Reading Toggle Coverage
12.3
Reading Memory Coverage
12.4
Reading Combinational Logic Coverage
12.5
Reading FSM Coverage
12.6
Reading Assertion Coverage
13
Debugging
13.1
Verbose Debug Output
13.2
Command-Line Interface
13.3
Source Code Profiling
14
FAQ
15
Epilogue
15.1
Author
15.2
Special Thanks
15.3
Reporting Bugs
15.4
Mailing List
15.5
Homepage
15.6
Copyright and Licensing
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