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3   Coverage Boundaries

To properly evaluate the effectiveness of any coverage tool, it is necessary to understand what kinds of logic are able to be analyzed and which kinds of logic are unable to be analyzed (along with a reason for why the logic cannot be adequately covered). Understanding the limitations of tools up front can often guide the user of those tools to make better decisions in their usage. In the case of Covered and the open source community, it may also help drive ideas to how to correct or get around these limitations.

For these reasons, a list of what type of logic can be analyzed and what type of logic cannot be currently analyzed is listed below. Note that both of these lists may not be exhaustive and are subject to change between releases of the tool. Also note that it is the goal of Covered to be able to parse all of the Verilog-1995, Verilog-2001, and a subset of SystemVerilog constructs though some portions of these may be ignored for coverage purposes.

3.1  What logic can be analyzed?

3.1.1  Verilog-1995 constructs

1. All expressional logic which is comprised of the following data types and operators which exist in an assign block, always block, initial block, task, function or named begin/end block:
   • Nets: wire, tri, tri0, tri1, wor, wand, trior, triand, supply0, suppl1
   • Triregs: trireg
   • Registers: reg
   • Parameter values
   • String values
   • Integer values
   • Unary operators: +, -, ~, &, |, ^, ~&, ~|, ~^
   • Arithmetic operators: +, -, *, /, %
   • Logical operators: &&, ||, !
   • Relational operators: > < >= <=
   • Equality operators: ==, ===, !=, !==
   • Bitwise operators: &, |, ^, ~&, ~|, ~^
   • Shift operators: << >>
   • Concatentation/replication operators: {}, {{}}
   • Bit select operators: [], [:]
   • Conditional operator: ?:
2. case, casex, casez statements
3. if, if/else statements
4. Delays when delay value is integer
5. Delayed procedural assignments (i.e., "a = #5 b;" or "a = @(c) b;")
6. Event waits and triggers: wait, @(posedge), @(negedge), @(), ->
7. Repetition statements (for, while and repeat)
8. Fork/join statements
9. Memories

3.1.2  Verilog-2001 constructs

1. `ifndef and `elsif directives
2. `file and `line directives
3. Constant functions calls
4. Inline parameter passing by name
5. Localparam support
6. Implicit event sensitivity lists (@*)
7. Comma-separated event lists (alternative to the "or" keyword)
8. Signed value support
9. Immediate register assignment (reg a = 1'b0)
10. Variable multi-bit selects (a[b+:3], a[b-:3]
11. Exponential power operator (a**b)
12. The "<<<" and ">>>" shift operators
13. Pre-port parameter listing (module foo #(parameter a=0) (...);)
14. Inline port listing (module foo (input wire a, output reg b);)
15. Attributes (note: Covered only performs attributes that it recognizes)
16. Arrays of instances
17. Generate blocks
18. "Automatic" or reentrant tasks/recursive functions

3.1.3  SystemVerilog constructs

1. New integer types: char, byte, bit, logic, int, shortint, longint
2. Op-and-assign statements: +=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, >>>=, ++, --
3. Proper support for always_comb, always_latch and always_ff blocks
4. do..while loops
5. Enumerations
6. Typedefs
7. $root scope support
8. Unnamed scope support
9. Multi-dimensional arrays including packed/unpacked dimensions and bit-select, part-select and slicing
10. Parsing support for unique and priority if/case labels
11. Parsing support for implicit .name ports (ex. "foo f( .a, .b, .c );")
12. Parsing support for implicit .* ports (ex. "foo f( .* );")
13. Parsing support for assertions, properties and sequences

3.2  What logic cannot be currently analyzed?

3.2.1  Verilog-1995 constructs

1. All gate types (i.e., buf, not, or, and, etc.)
2. All user defined primitives (UDPs)
3. All expressions containing types: time, real, realtime
4. System task calls (or any $... call)

3.2.2  Verilog-2001 constructs

1. Configuration statements

When logic is encountered that cannot be analyzed within an always, initial, task, function or named block, Covered will disregard the entire always block. If the entire block cannot be analyzed, it does not try to get coverage statistics as these will most likely be incorrect (i.e., disregarded logic could affect the state of the logic that is being covered).

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