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Line coverage simply answers the question, "Was this line of code executed during simulation?" |
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Covered will display the number of logical lines of code that exist in a particular file with the number of logical lines that were executed during the simulation along with a percentage indicating the percentage of lines executed. If verbose mode is selected for a report, Covered will display the lines of logic that were not executed during the simulation run. |
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Example |
Suppose that the following module was specified in your DUT that is being analyzed: |
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module test; reg a, b, c; initial begin a = 0; // Line 1 b = 1; // Line 2 if( a ) c = b; // Line 3 else c = ~b; // Line 4 end endmodule |
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If this code were simulated as stated, the simulator would execute lines 1 and 2, and due to the value assigned to a, line 4 would be executed. This means that during execution, out of a possibility of 4 lines, only 3 were executed. Therefore, Covered would state that for this module the line coverage percentage would be 75% (or 3 out of 4). |
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Recommendations |
For a design to pass full coverage, it is recommended that the line coverage for all modules in a design receive 100% coverage. If a line of logic is not executed during simulation, the design has not been fully exercised. Line coverage is useful for determining holes in the test suite. |
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[ 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 ] License: GPL This Manual was originally created with ManStyle. |