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12.2  Reading Toggle Coverage

12.2.1 Summary Information Description - Module-based

For module-based reports, the summary table for toggle metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 41 through 51 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v".

12.2.2 Summary Information Description - Instance-based

For instance-based reports, the summary table for toggle metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 41 through 51 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2".

12.2.3 Summary Information Description - Both

On the right-hand side of each row in the table are the hit, miss and total numbers for the toggle 0->1 coverage, followed by a calculated percent of the signal bits that toggled from a value of 0 to a value of 1 (calculated by taking the number of bits that toggled from 0 to 1 during simulation divided by the total number of signal bits). The hit value indicates how many signal bits were toggle from a value of 0 to 1 during simulation; the miss value indicates the number of signal bits that were not toggled from a value of 0 to 1 during simulation; and the total value indicates the total number of signal bits within the specified module/instance that Covered was able to simulate.

To the right of this information is the hit, miss and total statistics for signal bits that toggled from a value of 1 to a value of 0.

If the percentage values in the right of the summary table are 100%, this indicates that all signal bits toggled from a value of 0 to 1 and back to 0 during simulating (for the module/instance of this row). If the values of the percentage are less than 100%, this indicates that some signal bits did not fully toggle during simulation and full toggle coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any signals in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.

12.2.4 Verbose Information Description - Both

If the miss value for a particular module/instance was not 0 (indicating that one or more signal bits did not fully toggle during simulation) and the '-d v' option was specified on the command-line (specifying to output verbose reporting information), the signals that were missed during simulation will be output below the summary information per module/instance that contained missed signal bit toggles. In our sample module-based report, there were three signals in module "main" ("go", "state", and "error"), three signals in module "fsma" ("go", "state" and "next_state"), and three signals in module "fsmb" ("go", "next_state" and "state") that were not fully toggled (see lines 53 through 90).

For each signal in the verbose toggle table, the format is the following:

Signal toggle verbose output example

      <signal_name>          0->1: <hexidecimal_value>
      .......................1->0: <hexidecimal_value>

The name of the signal is specified in the upper left corner. The bitwise toggle information for the signal from a value of 0 to a value of 1 is specified in the upper right corner. The hexidecimal value represents bits in the signal, each bit corresponding to the matching bit of the signal. If a bit value is set to the value 1, this indicates that this bit in the signal toggled from a value of 0 to a value of 1. If a bit value is set to the value 0, this indicates that this bit in the signal did NOT toggle from a value of 0 to a value of 1; therefore, full toggle coverage was not achieved for this signal. For example, for the signal called "go" in the module/instance "main", the verbose toggle information looks like:

      go         0->1: 1'b1
      ...........1->0: 1'b0

This is indicating that bit 0 of the signal called "go" successfully toggled from a value of 0 to 1 during simulation (because the bit value at bit location 0 is a value of 1). However, the signal did not toggle from a value of 1 to a value of 0 during simulation, thus the signal was not considered fully toggled.

It is important to note that the hexidecimal values are displayed with the least-significant bit of the signal being output on the far right of the value while the most-significant bit of the signal is output on the far left of the value.

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