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2.4  Combinational Coverage

Combinational logic coverage answers the question, "What values did an expression (or subexpression) evaluate to (or not evaluate to) during the course of the simulation?"

This type of coverage is extremely useful in determining logical combinations of signals that were not tried during simulation, exposing potential holes in verification.

2.4.1 Example

Example

Suppose the DUT comprised of the following module

module test;

reg  a;
reg  b;
wire c;

initial
  begin
    a = 1'b0;
    b = 1'b1;
    #10;
    a = 1'b1;
    #10;
  end

assign c = a | b;

endmodule

This module comprises of only one expression: a | b. If this module were simulated it would result in a combinational coverage value of 50% (2 out of 4). Can you determine which cases are not being covered?

The expression "a | b" can result in two values, 0 and 1, but can do so in four combinations:

1. a = 0, b = 0, c = 0
2. a = 0, b = 1, c = 1
3. a = 1, b = 0, c = 1
4. a = 1, b = 1, c = 1

Noticing the values assigned to a and b during simulation, shows that combinations (2) and (4) were hit during execution while combinations (1) and (3) were not (2 out of 4 - 50%). This also shows us that the value of c was never 0 during simulation.

2.4.2 Recommendations

Recommendations

For a design to pass full coverage, it is recommended that the combinational logic coverage for all modules be 80% or higher. If the expression coverage for an expression is not 100%, it is recommended that the verification engineer closely examine these missed cases to determine if more testing is required. Sometimes certain combinations of signals are unachievable due to design constraints, keeping the expression coverage from ever reaching a value of 100% but still can be considered fully covered.

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