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8250_pci.c
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1 /*
2  * Probe module for 8250/16550-type PCI serial ports.
3  *
4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5  *
6  * Copyright (C) 2001 Russell King, All Rights Reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License.
11  */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27 
28 #include "8250.h"
29 
30 #undef SERIAL_DEBUG_PCI
31 
32 /*
33  * init function returns:
34  * > 0 - number of ports
35  * = 0 - use board->num_ports
36  * < 0 - error
37  */
38 struct pci_serial_quirk {
39  u32 vendor;
40  u32 device;
41  u32 subvendor;
42  u32 subdevice;
43  int (*probe)(struct pci_dev *dev);
44  int (*init)(struct pci_dev *dev);
45  int (*setup)(struct serial_private *,
46  const struct pciserial_board *,
47  struct uart_8250_port *, int);
48  void (*exit)(struct pci_dev *dev);
49 };
50 
51 #define PCI_NUM_BAR_RESOURCES 6
52 
53 struct serial_private {
54  struct pci_dev *dev;
55  unsigned int nr;
56  void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57  struct pci_serial_quirk *quirk;
58  int line[0];
59 };
60 
61 static int pci_default_setup(struct serial_private*,
62  const struct pciserial_board*, struct uart_8250_port *, int);
63 
64 static void moan_device(const char *str, struct pci_dev *dev)
65 {
66  printk(KERN_WARNING
67  "%s: %s\n"
68  "Please send the output of lspci -vv, this\n"
69  "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70  "manufacturer and name of serial board or\n"
71  "modem board to [email protected].\n",
72  pci_name(dev), str, dev->vendor, dev->device,
73  dev->subsystem_vendor, dev->subsystem_device);
74 }
75 
76 static int
77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
78  int bar, int offset, int regshift)
79 {
80  struct pci_dev *dev = priv->dev;
81  unsigned long base, len;
82 
83  if (bar >= PCI_NUM_BAR_RESOURCES)
84  return -EINVAL;
85 
86  base = pci_resource_start(dev, bar);
87 
88  if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89  len = pci_resource_len(dev, bar);
90 
91  if (!priv->remapped_bar[bar])
92  priv->remapped_bar[bar] = ioremap_nocache(base, len);
93  if (!priv->remapped_bar[bar])
94  return -ENOMEM;
95 
96  port->port.iotype = UPIO_MEM;
97  port->port.iobase = 0;
98  port->port.mapbase = base + offset;
99  port->port.membase = priv->remapped_bar[bar] + offset;
100  port->port.regshift = regshift;
101  } else {
102  port->port.iotype = UPIO_PORT;
103  port->port.iobase = base + offset;
104  port->port.mapbase = 0;
105  port->port.membase = NULL;
106  port->port.regshift = 0;
107  }
108  return 0;
109 }
110 
111 /*
112  * ADDI-DATA GmbH communication cards <[email protected]>
113  */
114 static int addidata_apci7800_setup(struct serial_private *priv,
115  const struct pciserial_board *board,
116  struct uart_8250_port *port, int idx)
117 {
118  unsigned int bar = 0, offset = board->first_offset;
119  bar = FL_GET_BASE(board->flags);
120 
121  if (idx < 2) {
122  offset += idx * board->uart_offset;
123  } else if ((idx >= 2) && (idx < 4)) {
124  bar += 1;
125  offset += ((idx - 2) * board->uart_offset);
126  } else if ((idx >= 4) && (idx < 6)) {
127  bar += 2;
128  offset += ((idx - 4) * board->uart_offset);
129  } else if (idx >= 6) {
130  bar += 3;
131  offset += ((idx - 6) * board->uart_offset);
132  }
133 
134  return setup_port(priv, port, bar, offset, board->reg_shift);
135 }
136 
137 /*
138  * AFAVLAB uses a different mixture of BARs and offsets
139  * Not that ugly ;) -- HW
140  */
141 static int
142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143  struct uart_8250_port *port, int idx)
144 {
145  unsigned int bar, offset = board->first_offset;
146 
147  bar = FL_GET_BASE(board->flags);
148  if (idx < 4)
149  bar += idx;
150  else {
151  bar = 4;
152  offset += (idx - 4) * board->uart_offset;
153  }
154 
155  return setup_port(priv, port, bar, offset, board->reg_shift);
156 }
157 
158 /*
159  * HP's Remote Management Console. The Diva chip came in several
160  * different versions. N-class, L2000 and A500 have two Diva chips, each
161  * with 3 UARTs (the third UART on the second chip is unused). Superdome
162  * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163  * one Diva chip, but it has been expanded to 5 UARTs.
164  */
165 static int pci_hp_diva_init(struct pci_dev *dev)
166 {
167  int rc = 0;
168 
169  switch (dev->subsystem_device) {
170  case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171  case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172  case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173  case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174  rc = 3;
175  break;
176  case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177  rc = 2;
178  break;
179  case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180  rc = 4;
181  break;
182  case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
183  case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
184  rc = 1;
185  break;
186  }
187 
188  return rc;
189 }
190 
191 /*
192  * HP's Diva chip puts the 4th/5th serial port further out, and
193  * some serial ports are supposed to be hidden on certain models.
194  */
195 static int
196 pci_hp_diva_setup(struct serial_private *priv,
197  const struct pciserial_board *board,
198  struct uart_8250_port *port, int idx)
199 {
200  unsigned int offset = board->first_offset;
201  unsigned int bar = FL_GET_BASE(board->flags);
202 
203  switch (priv->dev->subsystem_device) {
204  case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205  if (idx == 3)
206  idx++;
207  break;
208  case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209  if (idx > 0)
210  idx++;
211  if (idx > 2)
212  idx++;
213  break;
214  }
215  if (idx > 2)
216  offset = 0x18;
217 
218  offset += idx * board->uart_offset;
219 
220  return setup_port(priv, port, bar, offset, board->reg_shift);
221 }
222 
223 /*
224  * Added for EKF Intel i960 serial boards
225  */
226 static int pci_inteli960ni_init(struct pci_dev *dev)
227 {
228  unsigned long oldval;
229 
230  if (!(dev->subsystem_device & 0x1000))
231  return -ENODEV;
232 
233  /* is firmware started? */
234  pci_read_config_dword(dev, 0x44, (void *)&oldval);
235  if (oldval == 0x00001000L) { /* RESET value */
236  printk(KERN_DEBUG "Local i960 firmware missing");
237  return -ENODEV;
238  }
239  return 0;
240 }
241 
242 /*
243  * Some PCI serial cards using the PLX 9050 PCI interface chip require
244  * that the card interrupt be explicitly enabled or disabled. This
245  * seems to be mainly needed on card using the PLX which also use I/O
246  * mapped memory.
247  */
248 static int pci_plx9050_init(struct pci_dev *dev)
249 {
250  u8 irq_config;
251  void __iomem *p;
252 
253  if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254  moan_device("no memory in bar 0", dev);
255  return 0;
256  }
257 
258  irq_config = 0x41;
259  if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
260  dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
261  irq_config = 0x43;
262 
263  if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
264  (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
265  /*
266  * As the megawolf cards have the int pins active
267  * high, and have 2 UART chips, both ints must be
268  * enabled on the 9050. Also, the UARTS are set in
269  * 16450 mode by default, so we have to enable the
270  * 16C950 'enhanced' mode so that we can use the
271  * deep FIFOs
272  */
273  irq_config = 0x5b;
274  /*
275  * enable/disable interrupts
276  */
277  p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
278  if (p == NULL)
279  return -ENOMEM;
280  writel(irq_config, p + 0x4c);
281 
282  /*
283  * Read the register back to ensure that it took effect.
284  */
285  readl(p + 0x4c);
286  iounmap(p);
287 
288  return 0;
289 }
290 
291 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
292 {
293  u8 __iomem *p;
294 
295  if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296  return;
297 
298  /*
299  * disable interrupts
300  */
301  p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302  if (p != NULL) {
303  writel(0, p + 0x4c);
304 
305  /*
306  * Read the register back to ensure that it took effect.
307  */
308  readl(p + 0x4c);
309  iounmap(p);
310  }
311 }
312 
313 #define NI8420_INT_ENABLE_REG 0x38
314 #define NI8420_INT_ENABLE_BIT 0x2000
315 
316 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
317 {
318  void __iomem *p;
319  unsigned long base, len;
320  unsigned int bar = 0;
321 
322  if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323  moan_device("no memory in bar", dev);
324  return;
325  }
326 
327  base = pci_resource_start(dev, bar);
328  len = pci_resource_len(dev, bar);
329  p = ioremap_nocache(base, len);
330  if (p == NULL)
331  return;
332 
333  /* Disable the CPU Interrupt */
334  writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335  p + NI8420_INT_ENABLE_REG);
336  iounmap(p);
337 }
338 
339 
340 /* MITE registers */
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
345 
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347 
348 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
349 {
350  void __iomem *p;
351  unsigned long base, len;
352  unsigned int bar = 0;
353 
354  if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355  moan_device("no memory in bar", dev);
356  return;
357  }
358 
359  base = pci_resource_start(dev, bar);
360  len = pci_resource_len(dev, bar);
361  p = ioremap_nocache(base, len);
362  if (p == NULL)
363  return;
364 
365  /* Disable the CPU Interrupt */
366  writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367  iounmap(p);
368 }
369 
370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371 static int
372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373  struct uart_8250_port *port, int idx)
374 {
375  unsigned int bar, offset = board->first_offset;
376 
377  bar = 0;
378 
379  if (idx < 4) {
380  /* first four channels map to 0, 0x100, 0x200, 0x300 */
381  offset += idx * board->uart_offset;
382  } else if (idx < 8) {
383  /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384  offset += idx * board->uart_offset + 0xC00;
385  } else /* we have only 8 ports on PMC-OCTALPRO */
386  return 1;
387 
388  return setup_port(priv, port, bar, offset, board->reg_shift);
389 }
390 
391 /*
392 * This does initialization for PMC OCTALPRO cards:
393 * maps the device memory, resets the UARTs (needed, bc
394 * if the module is removed and inserted again, the card
395 * is in the sleep mode) and enables global interrupt.
396 */
397 
398 /* global control register offset for SBS PMC-OctalPro */
399 #define OCT_REG_CR_OFF 0x500
400 
401 static int sbs_init(struct pci_dev *dev)
402 {
403  u8 __iomem *p;
404 
405  p = pci_ioremap_bar(dev, 0);
406 
407  if (p == NULL)
408  return -ENOMEM;
409  /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
410  writeb(0x10, p + OCT_REG_CR_OFF);
411  udelay(50);
412  writeb(0x0, p + OCT_REG_CR_OFF);
413 
414  /* Set bit-2 (INTENABLE) of Control Register */
415  writeb(0x4, p + OCT_REG_CR_OFF);
416  iounmap(p);
417 
418  return 0;
419 }
420 
421 /*
422  * Disables the global interrupt of PMC-OctalPro
423  */
424 
425 static void __devexit sbs_exit(struct pci_dev *dev)
426 {
427  u8 __iomem *p;
428 
429  p = pci_ioremap_bar(dev, 0);
430  /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431  if (p != NULL)
432  writeb(0, p + OCT_REG_CR_OFF);
433  iounmap(p);
434 }
435 
436 /*
437  * SIIG serial cards have an PCI interface chip which also controls
438  * the UART clocking frequency. Each UART can be clocked independently
439  * (except cards equipped with 4 UARTs) and initial clocking settings
440  * are stored in the EEPROM chip. It can cause problems because this
441  * version of serial driver doesn't support differently clocked UART's
442  * on single PCI card. To prevent this, initialization functions set
443  * high frequency clocking for all UART's on given card. It is safe (I
444  * hope) because it doesn't touch EEPROM settings to prevent conflicts
445  * with other OSes (like M$ DOS).
446  *
447  * SIIG support added by Andrey Panin <[email protected]>, 10/1999
448  *
449  * There is two family of SIIG serial cards with different PCI
450  * interface chip and different configuration methods:
451  * - 10x cards have control registers in IO and/or memory space;
452  * - 20x cards have control registers in standard PCI configuration space.
453  *
454  * Note: all 10x cards have PCI device ids 0x10..
455  * all 20x cards have PCI device ids 0x20..
456  *
457  * There are also Quartet Serial cards which use Oxford Semiconductor
458  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459  *
460  * Note: some SIIG cards are probed by the parport_serial object.
461  */
462 
463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465 
466 static int pci_siig10x_init(struct pci_dev *dev)
467 {
468  u16 data;
469  void __iomem *p;
470 
471  switch (dev->device & 0xfff8) {
472  case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473  data = 0xffdf;
474  break;
475  case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476  data = 0xf7ff;
477  break;
478  default: /* 1S1P, 4S */
479  data = 0xfffb;
480  break;
481  }
482 
483  p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
484  if (p == NULL)
485  return -ENOMEM;
486 
487  writew(readw(p + 0x28) & data, p + 0x28);
488  readw(p + 0x28);
489  iounmap(p);
490  return 0;
491 }
492 
493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495 
496 static int pci_siig20x_init(struct pci_dev *dev)
497 {
498  u8 data;
499 
500  /* Change clock frequency for the first UART. */
501  pci_read_config_byte(dev, 0x6f, &data);
502  pci_write_config_byte(dev, 0x6f, data & 0xef);
503 
504  /* If this card has 2 UART, we have to do the same with second UART. */
505  if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506  ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507  pci_read_config_byte(dev, 0x73, &data);
508  pci_write_config_byte(dev, 0x73, data & 0xef);
509  }
510  return 0;
511 }
512 
513 static int pci_siig_init(struct pci_dev *dev)
514 {
515  unsigned int type = dev->device & 0xff00;
516 
517  if (type == 0x1000)
518  return pci_siig10x_init(dev);
519  else if (type == 0x2000)
520  return pci_siig20x_init(dev);
521 
522  moan_device("Unknown SIIG card", dev);
523  return -ENODEV;
524 }
525 
526 static int pci_siig_setup(struct serial_private *priv,
527  const struct pciserial_board *board,
528  struct uart_8250_port *port, int idx)
529 {
530  unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531 
532  if (idx > 3) {
533  bar = 4;
534  offset = (idx - 4) * 8;
535  }
536 
537  return setup_port(priv, port, bar, offset, 0);
538 }
539 
540 /*
541  * Timedia has an explosion of boards, and to avoid the PCI table from
542  * growing *huge*, we use this function to collapse some 70 entries
543  * in the PCI table into one, for sanity's and compactness's sake.
544  */
545 static const unsigned short timedia_single_port[] = {
546  0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547 };
548 
549 static const unsigned short timedia_dual_port[] = {
550  0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
551  0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552  0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
553  0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554  0xD079, 0
555 };
556 
557 static const unsigned short timedia_quad_port[] = {
558  0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559  0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
560  0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561  0xB157, 0
562 };
563 
564 static const unsigned short timedia_eight_port[] = {
565  0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
566  0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567 };
568 
569 static const struct timedia_struct {
570  int num;
571  const unsigned short *ids;
572 } timedia_data[] = {
573  { 1, timedia_single_port },
574  { 2, timedia_dual_port },
575  { 4, timedia_quad_port },
576  { 8, timedia_eight_port }
577 };
578 
579 /*
580  * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581  * listing them individually, this driver merely grabs them all with
582  * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583  * and should be left free to be claimed by parport_serial instead.
584  */
585 static int pci_timedia_probe(struct pci_dev *dev)
586 {
587  /*
588  * Check the third digit of the subdevice ID
589  * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590  */
591  if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592  dev_info(&dev->dev,
593  "ignoring Timedia subdevice %04x for parport_serial\n",
594  dev->subsystem_device);
595  return -ENODEV;
596  }
597 
598  return 0;
599 }
600 
601 static int pci_timedia_init(struct pci_dev *dev)
602 {
603  const unsigned short *ids;
604  int i, j;
605 
606  for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
607  ids = timedia_data[i].ids;
608  for (j = 0; ids[j]; j++)
609  if (dev->subsystem_device == ids[j])
610  return timedia_data[i].num;
611  }
612  return 0;
613 }
614 
615 /*
616  * Timedia/SUNIX uses a mixture of BARs and offsets
617  * Ugh, this is ugly as all hell --- TYT
618  */
619 static int
620 pci_timedia_setup(struct serial_private *priv,
621  const struct pciserial_board *board,
622  struct uart_8250_port *port, int idx)
623 {
624  unsigned int bar = 0, offset = board->first_offset;
625 
626  switch (idx) {
627  case 0:
628  bar = 0;
629  break;
630  case 1:
631  offset = board->uart_offset;
632  bar = 0;
633  break;
634  case 2:
635  bar = 1;
636  break;
637  case 3:
638  offset = board->uart_offset;
639  /* FALLTHROUGH */
640  case 4: /* BAR 2 */
641  case 5: /* BAR 3 */
642  case 6: /* BAR 4 */
643  case 7: /* BAR 5 */
644  bar = idx - 2;
645  }
646 
647  return setup_port(priv, port, bar, offset, board->reg_shift);
648 }
649 
650 /*
651  * Some Titan cards are also a little weird
652  */
653 static int
654 titan_400l_800l_setup(struct serial_private *priv,
655  const struct pciserial_board *board,
656  struct uart_8250_port *port, int idx)
657 {
658  unsigned int bar, offset = board->first_offset;
659 
660  switch (idx) {
661  case 0:
662  bar = 1;
663  break;
664  case 1:
665  bar = 2;
666  break;
667  default:
668  bar = 4;
669  offset = (idx - 2) * board->uart_offset;
670  }
671 
672  return setup_port(priv, port, bar, offset, board->reg_shift);
673 }
674 
675 static int pci_xircom_init(struct pci_dev *dev)
676 {
677  msleep(100);
678  return 0;
679 }
680 
681 static int pci_ni8420_init(struct pci_dev *dev)
682 {
683  void __iomem *p;
684  unsigned long base, len;
685  unsigned int bar = 0;
686 
687  if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688  moan_device("no memory in bar", dev);
689  return 0;
690  }
691 
692  base = pci_resource_start(dev, bar);
693  len = pci_resource_len(dev, bar);
694  p = ioremap_nocache(base, len);
695  if (p == NULL)
696  return -ENOMEM;
697 
698  /* Enable CPU Interrupt */
699  writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700  p + NI8420_INT_ENABLE_REG);
701 
702  iounmap(p);
703  return 0;
704 }
705 
706 #define MITE_IOWBSR1_WSIZE 0xa
707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
708 #define MITE_IOWBSR1_WENAB (1 << 7)
709 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712 
713 static int pci_ni8430_init(struct pci_dev *dev)
714 {
715  void __iomem *p;
716  unsigned long base, len;
717  u32 device_window;
718  unsigned int bar = 0;
719 
720  if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721  moan_device("no memory in bar", dev);
722  return 0;
723  }
724 
725  base = pci_resource_start(dev, bar);
726  len = pci_resource_len(dev, bar);
727  p = ioremap_nocache(base, len);
728  if (p == NULL)
729  return -ENOMEM;
730 
731  /* Set device window address and size in BAR0 */
732  device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733  | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734  writel(device_window, p + MITE_IOWBSR1);
735 
736  /* Set window access to go to RAMSEL IO address space */
737  writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738  p + MITE_IOWCR1);
739 
740  /* Enable IO Bus Interrupt 0 */
741  writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742 
743  /* Enable CPU Interrupt */
744  writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745 
746  iounmap(p);
747  return 0;
748 }
749 
750 /* UART Port Control Register */
751 #define NI8430_PORTCON 0x0f
752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753 
754 static int
755 pci_ni8430_setup(struct serial_private *priv,
756  const struct pciserial_board *board,
757  struct uart_8250_port *port, int idx)
758 {
759  void __iomem *p;
760  unsigned long base, len;
761  unsigned int bar, offset = board->first_offset;
762 
763  if (idx >= board->num_ports)
764  return 1;
765 
766  bar = FL_GET_BASE(board->flags);
767  offset += idx * board->uart_offset;
768 
769  base = pci_resource_start(priv->dev, bar);
770  len = pci_resource_len(priv->dev, bar);
771  p = ioremap_nocache(base, len);
772 
773  /* enable the transceiver */
774  writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775  p + offset + NI8430_PORTCON);
776 
777  iounmap(p);
778 
779  return setup_port(priv, port, bar, offset, board->reg_shift);
780 }
781 
782 static int pci_netmos_9900_setup(struct serial_private *priv,
783  const struct pciserial_board *board,
784  struct uart_8250_port *port, int idx)
785 {
786  unsigned int bar;
787 
788  if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789  /* netmos apparently orders BARs by datasheet layout, so serial
790  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791  */
792  bar = 3 * idx;
793 
794  return setup_port(priv, port, bar, 0, board->reg_shift);
795  } else {
796  return pci_default_setup(priv, board, port, idx);
797  }
798 }
799 
800 /* the 99xx series comes with a range of device IDs and a variety
801  * of capabilities:
802  *
803  * 9900 has varying capabilities and can cascade to sub-controllers
804  * (cascading should be purely internal)
805  * 9904 is hardwired with 4 serial ports
806  * 9912 and 9922 are hardwired with 2 serial ports
807  */
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 {
810  unsigned int c = dev->class;
811  unsigned int pi;
812  unsigned short sub_serports;
813 
814  pi = (c & 0xff);
815 
816  if (pi == 2) {
817  return 1;
818  } else if ((pi == 0) &&
819  (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820  /* two possibilities: 0x30ps encodes number of parallel and
821  * serial ports, or 0x1000 indicates *something*. This is not
822  * immediately obvious, since the 2s1p+4s configuration seems
823  * to offer all functionality on functions 0..2, while still
824  * advertising the same function 3 as the 4s+2s1p config.
825  */
826  sub_serports = dev->subsystem_device & 0xf;
827  if (sub_serports > 0) {
828  return sub_serports;
829  } else {
830  printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831  return 0;
832  }
833  }
834 
835  moan_device("unknown NetMos/Mostech program interface", dev);
836  return 0;
837 }
838 
839 static int pci_netmos_init(struct pci_dev *dev)
840 {
841  /* subdevice 0x00PS means <P> parallel, <S> serial */
842  unsigned int num_serial = dev->subsystem_device & 0xf;
843 
844  if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845  (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846  return 0;
847 
848  if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849  dev->subsystem_device == 0x0299)
850  return 0;
851 
852  switch (dev->device) { /* FALLTHROUGH on all */
853  case PCI_DEVICE_ID_NETMOS_9904:
854  case PCI_DEVICE_ID_NETMOS_9912:
855  case PCI_DEVICE_ID_NETMOS_9922:
856  case PCI_DEVICE_ID_NETMOS_9900:
857  num_serial = pci_netmos_9900_numports(dev);
858  break;
859 
860  default:
861  if (num_serial == 0 ) {
862  moan_device("unknown NetMos/Mostech device", dev);
863  }
864  }
865 
866  if (num_serial == 0)
867  return -ENODEV;
868 
869  return num_serial;
870 }
871 
872 /*
873  * These chips are available with optionally one parallel port and up to
874  * two serial ports. Unfortunately they all have the same product id.
875  *
876  * Basic configuration is done over a region of 32 I/O ports. The base
877  * ioport is called INTA or INTC, depending on docs/other drivers.
878  *
879  * The region of the 32 I/O ports is configured in POSIO0R...
880  */
881 
882 /* registers */
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
888 
889 /* I/O space size */
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
899 
900 static int pci_ite887x_init(struct pci_dev *dev)
901 {
902  /* inta_addr are the configuration addresses of the ITE */
903  static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904  0x200, 0x280, 0 };
905  int ret, i, type;
906  struct resource *iobase = NULL;
907  u32 miscr, uartbar, ioport;
908 
909  /* search for the base-ioport */
910  i = 0;
911  while (inta_addr[i] && iobase == NULL) {
912  iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913  "ite887x");
914  if (iobase != NULL) {
915  /* write POSIO0R - speed | size | ioport */
916  pci_write_config_dword(dev, ITE_887x_POSIO0,
917  ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918  ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919  /* write INTCBAR - ioport */
920  pci_write_config_dword(dev, ITE_887x_INTCBAR,
921  inta_addr[i]);
922  ret = inb(inta_addr[i]);
923  if (ret != 0xff) {
924  /* ioport connected */
925  break;
926  }
927  release_region(iobase->start, ITE_887x_IOSIZE);
928  iobase = NULL;
929  }
930  i++;
931  }
932 
933  if (!inta_addr[i]) {
934  printk(KERN_ERR "ite887x: could not find iobase\n");
935  return -ENODEV;
936  }
937 
938  /* start of undocumented type checking (see parport_pc.c) */
939  type = inb(iobase->start + 0x18) & 0x0f;
940 
941  switch (type) {
942  case 0x2: /* ITE8871 (1P) */
943  case 0xa: /* ITE8875 (1P) */
944  ret = 0;
945  break;
946  case 0xe: /* ITE8872 (2S1P) */
947  ret = 2;
948  break;
949  case 0x6: /* ITE8873 (1S) */
950  ret = 1;
951  break;
952  case 0x8: /* ITE8874 (2S) */
953  ret = 2;
954  break;
955  default:
956  moan_device("Unknown ITE887x", dev);
957  ret = -ENODEV;
958  }
959 
960  /* configure all serial ports */
961  for (i = 0; i < ret; i++) {
962  /* read the I/O port from the device */
963  pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964  &ioport);
965  ioport &= 0x0000FF00; /* the actual base address */
966  pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967  ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968  ITE_887x_POSIO_IOSIZE_8 | ioport);
969 
970  /* write the ioport to the UARTBAR */
971  pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972  uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973  uartbar |= (ioport << (16 * i)); /* set the ioport */
974  pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975 
976  /* get current config */
977  pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978  /* disable interrupts (UARTx_Routing[3:0]) */
979  miscr &= ~(0xf << (12 - 4 * i));
980  /* activate the UART (UARTx_En) */
981  miscr |= 1 << (23 - i);
982  /* write new config with activated UART */
983  pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984  }
985 
986  if (ret <= 0) {
987  /* the device has no UARTs if we get here */
988  release_region(iobase->start, ITE_887x_IOSIZE);
989  }
990 
991  return ret;
992 }
993 
994 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
995 {
996  u32 ioport;
997  /* the ioport is bit 0-15 in POSIO0R */
998  pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999  ioport &= 0xffff;
1000  release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002 
1003 /*
1004  * Oxford Semiconductor Inc.
1005  * Check that device is part of the Tornado range of devices, then determine
1006  * the number of ports available on the device.
1007  */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010  u8 __iomem *p;
1011  unsigned long deviceID;
1012  unsigned int number_uarts = 0;
1013 
1014  /* OxSemi Tornado devices are all 0xCxxx */
1015  if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016  (dev->device & 0xF000) != 0xC000)
1017  return 0;
1018 
1019  p = pci_iomap(dev, 0, 5);
1020  if (p == NULL)
1021  return -ENOMEM;
1022 
1023  deviceID = ioread32(p);
1024  /* Tornado device */
1025  if (deviceID == 0x07000200) {
1026  number_uarts = ioread8(p + 4);
1027  printk(KERN_DEBUG
1028  "%d ports detected on Oxford PCI Express device\n",
1029  number_uarts);
1030  }
1031  pci_iounmap(dev, p);
1032  return number_uarts;
1033 }
1034 
1035 static int pci_asix_setup(struct serial_private *priv,
1036  const struct pciserial_board *board,
1037  struct uart_8250_port *port, int idx)
1038 {
1039  port->bugs |= UART_BUG_PARITY;
1040  return pci_default_setup(priv, board, port, idx);
1041 }
1042 
1043 static int pci_default_setup(struct serial_private *priv,
1044  const struct pciserial_board *board,
1045  struct uart_8250_port *port, int idx)
1046 {
1047  unsigned int bar, offset = board->first_offset, maxnr;
1048 
1049  bar = FL_GET_BASE(board->flags);
1050  if (board->flags & FL_BASE_BARS)
1051  bar += idx;
1052  else
1053  offset += idx * board->uart_offset;
1054 
1055  maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1056  (board->reg_shift + 3);
1057 
1058  if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1059  return 1;
1060 
1061  return setup_port(priv, port, bar, offset, board->reg_shift);
1062 }
1063 
1064 static int
1065 ce4100_serial_setup(struct serial_private *priv,
1066  const struct pciserial_board *board,
1067  struct uart_8250_port *port, int idx)
1068 {
1069  int ret;
1070 
1071  ret = setup_port(priv, port, 0, 0, board->reg_shift);
1072  port->port.iotype = UPIO_MEM32;
1073  port->port.type = PORT_XSCALE;
1074  port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1075  port->port.regshift = 2;
1076 
1077  return ret;
1078 }
1079 
1080 static int
1081 pci_omegapci_setup(struct serial_private *priv,
1082  const struct pciserial_board *board,
1083  struct uart_8250_port *port, int idx)
1084 {
1085  return setup_port(priv, port, 2, idx * 8, 0);
1086 }
1087 
1088 static int skip_tx_en_setup(struct serial_private *priv,
1089  const struct pciserial_board *board,
1090  struct uart_8250_port *port, int idx)
1091 {
1092  port->port.flags |= UPF_NO_TXEN_TEST;
1093  printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1094  "[%04x:%04x] subsystem [%04x:%04x]\n",
1095  priv->dev->vendor,
1096  priv->dev->device,
1097  priv->dev->subsystem_vendor,
1098  priv->dev->subsystem_device);
1099 
1100  return pci_default_setup(priv, board, port, idx);
1101 }
1102 
1103 static void kt_handle_break(struct uart_port *p)
1104 {
1105  struct uart_8250_port *up =
1106  container_of(p, struct uart_8250_port, port);
1107  /*
1108  * On receipt of a BI, serial device in Intel ME (Intel
1109  * management engine) needs to have its fifos cleared for sane
1110  * SOL (Serial Over Lan) output.
1111  */
1112  serial8250_clear_and_reinit_fifos(up);
1113 }
1114 
1115 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1116 {
1117  struct uart_8250_port *up =
1118  container_of(p, struct uart_8250_port, port);
1119  unsigned int val;
1120 
1121  /*
1122  * When the Intel ME (management engine) gets reset its serial
1123  * port registers could return 0 momentarily. Functions like
1124  * serial8250_console_write, read and save the IER, perform
1125  * some operation and then restore it. In order to avoid
1126  * setting IER register inadvertently to 0, if the value read
1127  * is 0, double check with ier value in uart_8250_port and use
1128  * that instead. up->ier should be the same value as what is
1129  * currently configured.
1130  */
1131  val = inb(p->iobase + offset);
1132  if (offset == UART_IER) {
1133  if (val == 0)
1134  val = up->ier;
1135  }
1136  return val;
1137 }
1138 
1139 static int kt_serial_setup(struct serial_private *priv,
1140  const struct pciserial_board *board,
1141  struct uart_8250_port *port, int idx)
1142 {
1143  port->port.flags |= UPF_BUG_THRE;
1144  port->port.serial_in = kt_serial_in;
1145  port->port.handle_break = kt_handle_break;
1146  return skip_tx_en_setup(priv, board, port, idx);
1147 }
1148 
1149 static int pci_eg20t_init(struct pci_dev *dev)
1150 {
1151 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1152  return -ENODEV;
1153 #else
1154  return 0;
1155 #endif
1156 }
1157 
1158 static int
1159 pci_xr17c154_setup(struct serial_private *priv,
1160  const struct pciserial_board *board,
1161  struct uart_8250_port *port, int idx)
1162 {
1163  port->port.flags |= UPF_EXAR_EFR;
1164  return pci_default_setup(priv, board, port, idx);
1165 }
1166 
1167 static int
1168 pci_wch_ch353_setup(struct serial_private *priv,
1169  const struct pciserial_board *board,
1170  struct uart_8250_port *port, int idx)
1171 {
1172  port->port.flags |= UPF_FIXED_TYPE;
1173  port->port.type = PORT_16550A;
1174  return pci_default_setup(priv, board, port, idx);
1175 }
1176 
1177 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1178 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1179 #define PCI_DEVICE_ID_OCTPRO 0x0001
1180 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1181 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1182 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1183 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1184 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1185 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1186 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1187 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1188 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1189 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1190 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1191 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1192 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1193 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1194 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1195 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1196 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1197 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1198 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1199 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1200 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1201 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1202 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1203 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1204 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1205 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1206 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1207 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1208 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1209 #define PCI_VENDOR_ID_WCH 0x4348
1210 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1211 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1212 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1213 #define PCI_VENDOR_ID_AGESTAR 0x5372
1214 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1215 #define PCI_VENDOR_ID_ASIX 0x9710
1216 
1217 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1218 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1219 
1220 /*
1221  * Master list of serial port init/setup/exit quirks.
1222  * This does not describe the general nature of the port.
1223  * (ie, baud base, number and location of ports, etc)
1224  *
1225  * This list is ordered alphabetically by vendor then device.
1226  * Specific entries must come before more generic entries.
1227  */
1228 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1229  /*
1230  * ADDI-DATA GmbH communication cards <[email protected]>
1231  */
1232  {
1233  .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1234  .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1235  .subvendor = PCI_ANY_ID,
1236  .subdevice = PCI_ANY_ID,
1237  .setup = addidata_apci7800_setup,
1238  },
1239  /*
1240  * AFAVLAB cards - these may be called via parport_serial
1241  * It is not clear whether this applies to all products.
1242  */
1243  {
1244  .vendor = PCI_VENDOR_ID_AFAVLAB,
1245  .device = PCI_ANY_ID,
1246  .subvendor = PCI_ANY_ID,
1247  .subdevice = PCI_ANY_ID,
1248  .setup = afavlab_setup,
1249  },
1250  /*
1251  * HP Diva
1252  */
1253  {
1254  .vendor = PCI_VENDOR_ID_HP,
1255  .device = PCI_DEVICE_ID_HP_DIVA,
1256  .subvendor = PCI_ANY_ID,
1257  .subdevice = PCI_ANY_ID,
1258  .init = pci_hp_diva_init,
1259  .setup = pci_hp_diva_setup,
1260  },
1261  /*
1262  * Intel
1263  */
1264  {
1265  .vendor = PCI_VENDOR_ID_INTEL,
1266  .device = PCI_DEVICE_ID_INTEL_80960_RP,
1267  .subvendor = 0xe4bf,
1268  .subdevice = PCI_ANY_ID,
1269  .init = pci_inteli960ni_init,
1270  .setup = pci_default_setup,
1271  },
1272  {
1273  .vendor = PCI_VENDOR_ID_INTEL,
1274  .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1275  .subvendor = PCI_ANY_ID,
1276  .subdevice = PCI_ANY_ID,
1277  .setup = skip_tx_en_setup,
1278  },
1279  {
1280  .vendor = PCI_VENDOR_ID_INTEL,
1281  .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1282  .subvendor = PCI_ANY_ID,
1283  .subdevice = PCI_ANY_ID,
1284  .setup = skip_tx_en_setup,
1285  },
1286  {
1287  .vendor = PCI_VENDOR_ID_INTEL,
1288  .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1289  .subvendor = PCI_ANY_ID,
1290  .subdevice = PCI_ANY_ID,
1291  .setup = skip_tx_en_setup,
1292  },
1293  {
1294  .vendor = PCI_VENDOR_ID_INTEL,
1295  .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1296  .subvendor = PCI_ANY_ID,
1297  .subdevice = PCI_ANY_ID,
1298  .setup = ce4100_serial_setup,
1299  },
1300  {
1301  .vendor = PCI_VENDOR_ID_INTEL,
1302  .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1303  .subvendor = PCI_ANY_ID,
1304  .subdevice = PCI_ANY_ID,
1305  .setup = kt_serial_setup,
1306  },
1307  /*
1308  * ITE
1309  */
1310  {
1311  .vendor = PCI_VENDOR_ID_ITE,
1312  .device = PCI_DEVICE_ID_ITE_8872,
1313  .subvendor = PCI_ANY_ID,
1314  .subdevice = PCI_ANY_ID,
1315  .init = pci_ite887x_init,
1316  .setup = pci_default_setup,
1317  .exit = __devexit_p(pci_ite887x_exit),
1318  },
1319  /*
1320  * National Instruments
1321  */
1322  {
1323  .vendor = PCI_VENDOR_ID_NI,
1324  .device = PCI_DEVICE_ID_NI_PCI23216,
1325  .subvendor = PCI_ANY_ID,
1326  .subdevice = PCI_ANY_ID,
1327  .init = pci_ni8420_init,
1328  .setup = pci_default_setup,
1329  .exit = __devexit_p(pci_ni8420_exit),
1330  },
1331  {
1332  .vendor = PCI_VENDOR_ID_NI,
1333  .device = PCI_DEVICE_ID_NI_PCI2328,
1334  .subvendor = PCI_ANY_ID,
1335  .subdevice = PCI_ANY_ID,
1336  .init = pci_ni8420_init,
1337  .setup = pci_default_setup,
1338  .exit = __devexit_p(pci_ni8420_exit),
1339  },
1340  {
1341  .vendor = PCI_VENDOR_ID_NI,
1342  .device = PCI_DEVICE_ID_NI_PCI2324,
1343  .subvendor = PCI_ANY_ID,
1344  .subdevice = PCI_ANY_ID,
1345  .init = pci_ni8420_init,
1346  .setup = pci_default_setup,
1347  .exit = __devexit_p(pci_ni8420_exit),
1348  },
1349  {
1350  .vendor = PCI_VENDOR_ID_NI,
1351  .device = PCI_DEVICE_ID_NI_PCI2322,
1352  .subvendor = PCI_ANY_ID,
1353  .subdevice = PCI_ANY_ID,
1354  .init = pci_ni8420_init,
1355  .setup = pci_default_setup,
1356  .exit = __devexit_p(pci_ni8420_exit),
1357  },
1358  {
1359  .vendor = PCI_VENDOR_ID_NI,
1360  .device = PCI_DEVICE_ID_NI_PCI2324I,
1361  .subvendor = PCI_ANY_ID,
1362  .subdevice = PCI_ANY_ID,
1363  .init = pci_ni8420_init,
1364  .setup = pci_default_setup,
1365  .exit = __devexit_p(pci_ni8420_exit),
1366  },
1367  {
1368  .vendor = PCI_VENDOR_ID_NI,
1369  .device = PCI_DEVICE_ID_NI_PCI2322I,
1370  .subvendor = PCI_ANY_ID,
1371  .subdevice = PCI_ANY_ID,
1372  .init = pci_ni8420_init,
1373  .setup = pci_default_setup,
1374  .exit = __devexit_p(pci_ni8420_exit),
1375  },
1376  {
1377  .vendor = PCI_VENDOR_ID_NI,
1378  .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1379  .subvendor = PCI_ANY_ID,
1380  .subdevice = PCI_ANY_ID,
1381  .init = pci_ni8420_init,
1382  .setup = pci_default_setup,
1383  .exit = __devexit_p(pci_ni8420_exit),
1384  },
1385  {
1386  .vendor = PCI_VENDOR_ID_NI,
1387  .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1388  .subvendor = PCI_ANY_ID,
1389  .subdevice = PCI_ANY_ID,
1390  .init = pci_ni8420_init,
1391  .setup = pci_default_setup,
1392  .exit = __devexit_p(pci_ni8420_exit),
1393  },
1394  {
1395  .vendor = PCI_VENDOR_ID_NI,
1396  .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1397  .subvendor = PCI_ANY_ID,
1398  .subdevice = PCI_ANY_ID,
1399  .init = pci_ni8420_init,
1400  .setup = pci_default_setup,
1401  .exit = __devexit_p(pci_ni8420_exit),
1402  },
1403  {
1404  .vendor = PCI_VENDOR_ID_NI,
1405  .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1406  .subvendor = PCI_ANY_ID,
1407  .subdevice = PCI_ANY_ID,
1408  .init = pci_ni8420_init,
1409  .setup = pci_default_setup,
1410  .exit = __devexit_p(pci_ni8420_exit),
1411  },
1412  {
1413  .vendor = PCI_VENDOR_ID_NI,
1414  .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1415  .subvendor = PCI_ANY_ID,
1416  .subdevice = PCI_ANY_ID,
1417  .init = pci_ni8420_init,
1418  .setup = pci_default_setup,
1419  .exit = __devexit_p(pci_ni8420_exit),
1420  },
1421  {
1422  .vendor = PCI_VENDOR_ID_NI,
1423  .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1424  .subvendor = PCI_ANY_ID,
1425  .subdevice = PCI_ANY_ID,
1426  .init = pci_ni8420_init,
1427  .setup = pci_default_setup,
1428  .exit = __devexit_p(pci_ni8420_exit),
1429  },
1430  {
1431  .vendor = PCI_VENDOR_ID_NI,
1432  .device = PCI_ANY_ID,
1433  .subvendor = PCI_ANY_ID,
1434  .subdevice = PCI_ANY_ID,
1435  .init = pci_ni8430_init,
1436  .setup = pci_ni8430_setup,
1437  .exit = __devexit_p(pci_ni8430_exit),
1438  },
1439  /*
1440  * Panacom
1441  */
1442  {
1443  .vendor = PCI_VENDOR_ID_PANACOM,
1444  .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1445  .subvendor = PCI_ANY_ID,
1446  .subdevice = PCI_ANY_ID,
1447  .init = pci_plx9050_init,
1448  .setup = pci_default_setup,
1449  .exit = __devexit_p(pci_plx9050_exit),
1450  },
1451  {
1452  .vendor = PCI_VENDOR_ID_PANACOM,
1453  .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1454  .subvendor = PCI_ANY_ID,
1455  .subdevice = PCI_ANY_ID,
1456  .init = pci_plx9050_init,
1457  .setup = pci_default_setup,
1458  .exit = __devexit_p(pci_plx9050_exit),
1459  },
1460  /*
1461  * PLX
1462  */
1463  {
1464  .vendor = PCI_VENDOR_ID_PLX,
1465  .device = PCI_DEVICE_ID_PLX_9030,
1466  .subvendor = PCI_SUBVENDOR_ID_PERLE,
1467  .subdevice = PCI_ANY_ID,
1468  .setup = pci_default_setup,
1469  },
1470  {
1471  .vendor = PCI_VENDOR_ID_PLX,
1472  .device = PCI_DEVICE_ID_PLX_9050,
1473  .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1474  .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1475  .init = pci_plx9050_init,
1476  .setup = pci_default_setup,
1477  .exit = __devexit_p(pci_plx9050_exit),
1478  },
1479  {
1480  .vendor = PCI_VENDOR_ID_PLX,
1481  .device = PCI_DEVICE_ID_PLX_9050,
1482  .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1483  .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1484  .init = pci_plx9050_init,
1485  .setup = pci_default_setup,
1486  .exit = __devexit_p(pci_plx9050_exit),
1487  },
1488  {
1489  .vendor = PCI_VENDOR_ID_PLX,
1490  .device = PCI_DEVICE_ID_PLX_9050,
1491  .subvendor = PCI_VENDOR_ID_PLX,
1492  .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1493  .init = pci_plx9050_init,
1494  .setup = pci_default_setup,
1495  .exit = __devexit_p(pci_plx9050_exit),
1496  },
1497  {
1498  .vendor = PCI_VENDOR_ID_PLX,
1499  .device = PCI_DEVICE_ID_PLX_ROMULUS,
1500  .subvendor = PCI_VENDOR_ID_PLX,
1501  .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1502  .init = pci_plx9050_init,
1503  .setup = pci_default_setup,
1504  .exit = __devexit_p(pci_plx9050_exit),
1505  },
1506  /*
1507  * SBS Technologies, Inc., PMC-OCTALPRO 232
1508  */
1509  {
1510  .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1511  .device = PCI_DEVICE_ID_OCTPRO,
1512  .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1513  .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1514  .init = sbs_init,
1515  .setup = sbs_setup,
1516  .exit = __devexit_p(sbs_exit),
1517  },
1518  /*
1519  * SBS Technologies, Inc., PMC-OCTALPRO 422
1520  */
1521  {
1522  .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1523  .device = PCI_DEVICE_ID_OCTPRO,
1524  .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1525  .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1526  .init = sbs_init,
1527  .setup = sbs_setup,
1528  .exit = __devexit_p(sbs_exit),
1529  },
1530  /*
1531  * SBS Technologies, Inc., P-Octal 232
1532  */
1533  {
1534  .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1535  .device = PCI_DEVICE_ID_OCTPRO,
1536  .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1537  .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1538  .init = sbs_init,
1539  .setup = sbs_setup,
1540  .exit = __devexit_p(sbs_exit),
1541  },
1542  /*
1543  * SBS Technologies, Inc., P-Octal 422
1544  */
1545  {
1546  .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1547  .device = PCI_DEVICE_ID_OCTPRO,
1548  .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1549  .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1550  .init = sbs_init,
1551  .setup = sbs_setup,
1552  .exit = __devexit_p(sbs_exit),
1553  },
1554  /*
1555  * SIIG cards - these may be called via parport_serial
1556  */
1557  {
1558  .vendor = PCI_VENDOR_ID_SIIG,
1559  .device = PCI_ANY_ID,
1560  .subvendor = PCI_ANY_ID,
1561  .subdevice = PCI_ANY_ID,
1562  .init = pci_siig_init,
1563  .setup = pci_siig_setup,
1564  },
1565  /*
1566  * Titan cards
1567  */
1568  {
1569  .vendor = PCI_VENDOR_ID_TITAN,
1570  .device = PCI_DEVICE_ID_TITAN_400L,
1571  .subvendor = PCI_ANY_ID,
1572  .subdevice = PCI_ANY_ID,
1573  .setup = titan_400l_800l_setup,
1574  },
1575  {
1576  .vendor = PCI_VENDOR_ID_TITAN,
1577  .device = PCI_DEVICE_ID_TITAN_800L,
1578  .subvendor = PCI_ANY_ID,
1579  .subdevice = PCI_ANY_ID,
1580  .setup = titan_400l_800l_setup,
1581  },
1582  /*
1583  * Timedia cards
1584  */
1585  {
1586  .vendor = PCI_VENDOR_ID_TIMEDIA,
1587  .device = PCI_DEVICE_ID_TIMEDIA_1889,
1588  .subvendor = PCI_VENDOR_ID_TIMEDIA,
1589  .subdevice = PCI_ANY_ID,
1590  .probe = pci_timedia_probe,
1591  .init = pci_timedia_init,
1592  .setup = pci_timedia_setup,
1593  },
1594  {
1595  .vendor = PCI_VENDOR_ID_TIMEDIA,
1596  .device = PCI_ANY_ID,
1597  .subvendor = PCI_ANY_ID,
1598  .subdevice = PCI_ANY_ID,
1599  .setup = pci_timedia_setup,
1600  },
1601  /*
1602  * Exar cards
1603  */
1604  {
1605  .vendor = PCI_VENDOR_ID_EXAR,
1606  .device = PCI_DEVICE_ID_EXAR_XR17C152,
1607  .subvendor = PCI_ANY_ID,
1608  .subdevice = PCI_ANY_ID,
1609  .setup = pci_xr17c154_setup,
1610  },
1611  {
1612  .vendor = PCI_VENDOR_ID_EXAR,
1613  .device = PCI_DEVICE_ID_EXAR_XR17C154,
1614  .subvendor = PCI_ANY_ID,
1615  .subdevice = PCI_ANY_ID,
1616  .setup = pci_xr17c154_setup,
1617  },
1618  {
1619  .vendor = PCI_VENDOR_ID_EXAR,
1620  .device = PCI_DEVICE_ID_EXAR_XR17C158,
1621  .subvendor = PCI_ANY_ID,
1622  .subdevice = PCI_ANY_ID,
1623  .setup = pci_xr17c154_setup,
1624  },
1625  /*
1626  * Xircom cards
1627  */
1628  {
1629  .vendor = PCI_VENDOR_ID_XIRCOM,
1630  .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1631  .subvendor = PCI_ANY_ID,
1632  .subdevice = PCI_ANY_ID,
1633  .init = pci_xircom_init,
1634  .setup = pci_default_setup,
1635  },
1636  /*
1637  * Netmos cards - these may be called via parport_serial
1638  */
1639  {
1640  .vendor = PCI_VENDOR_ID_NETMOS,
1641  .device = PCI_ANY_ID,
1642  .subvendor = PCI_ANY_ID,
1643  .subdevice = PCI_ANY_ID,
1644  .init = pci_netmos_init,
1645  .setup = pci_netmos_9900_setup,
1646  },
1647  /*
1648  * For Oxford Semiconductor Tornado based devices
1649  */
1650  {
1651  .vendor = PCI_VENDOR_ID_OXSEMI,
1652  .device = PCI_ANY_ID,
1653  .subvendor = PCI_ANY_ID,
1654  .subdevice = PCI_ANY_ID,
1655  .init = pci_oxsemi_tornado_init,
1656  .setup = pci_default_setup,
1657  },
1658  {
1659  .vendor = PCI_VENDOR_ID_MAINPINE,
1660  .device = PCI_ANY_ID,
1661  .subvendor = PCI_ANY_ID,
1662  .subdevice = PCI_ANY_ID,
1663  .init = pci_oxsemi_tornado_init,
1664  .setup = pci_default_setup,
1665  },
1666  {
1667  .vendor = PCI_VENDOR_ID_DIGI,
1668  .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1669  .subvendor = PCI_SUBVENDOR_ID_IBM,
1670  .subdevice = PCI_ANY_ID,
1671  .init = pci_oxsemi_tornado_init,
1672  .setup = pci_default_setup,
1673  },
1674  {
1675  .vendor = PCI_VENDOR_ID_INTEL,
1676  .device = 0x8811,
1677  .subvendor = PCI_ANY_ID,
1678  .subdevice = PCI_ANY_ID,
1679  .init = pci_eg20t_init,
1680  .setup = pci_default_setup,
1681  },
1682  {
1683  .vendor = PCI_VENDOR_ID_INTEL,
1684  .device = 0x8812,
1685  .subvendor = PCI_ANY_ID,
1686  .subdevice = PCI_ANY_ID,
1687  .init = pci_eg20t_init,
1688  .setup = pci_default_setup,
1689  },
1690  {
1691  .vendor = PCI_VENDOR_ID_INTEL,
1692  .device = 0x8813,
1693  .subvendor = PCI_ANY_ID,
1694  .subdevice = PCI_ANY_ID,
1695  .init = pci_eg20t_init,
1696  .setup = pci_default_setup,
1697  },
1698  {
1699  .vendor = PCI_VENDOR_ID_INTEL,
1700  .device = 0x8814,
1701  .subvendor = PCI_ANY_ID,
1702  .subdevice = PCI_ANY_ID,
1703  .init = pci_eg20t_init,
1704  .setup = pci_default_setup,
1705  },
1706  {
1707  .vendor = 0x10DB,
1708  .device = 0x8027,
1709  .subvendor = PCI_ANY_ID,
1710  .subdevice = PCI_ANY_ID,
1711  .init = pci_eg20t_init,
1712  .setup = pci_default_setup,
1713  },
1714  {
1715  .vendor = 0x10DB,
1716  .device = 0x8028,
1717  .subvendor = PCI_ANY_ID,
1718  .subdevice = PCI_ANY_ID,
1719  .init = pci_eg20t_init,
1720  .setup = pci_default_setup,
1721  },
1722  {
1723  .vendor = 0x10DB,
1724  .device = 0x8029,
1725  .subvendor = PCI_ANY_ID,
1726  .subdevice = PCI_ANY_ID,
1727  .init = pci_eg20t_init,
1728  .setup = pci_default_setup,
1729  },
1730  {
1731  .vendor = 0x10DB,
1732  .device = 0x800C,
1733  .subvendor = PCI_ANY_ID,
1734  .subdevice = PCI_ANY_ID,
1735  .init = pci_eg20t_init,
1736  .setup = pci_default_setup,
1737  },
1738  {
1739  .vendor = 0x10DB,
1740  .device = 0x800D,
1741  .subvendor = PCI_ANY_ID,
1742  .subdevice = PCI_ANY_ID,
1743  .init = pci_eg20t_init,
1744  .setup = pci_default_setup,
1745  },
1746  /*
1747  * Cronyx Omega PCI (PLX-chip based)
1748  */
1749  {
1750  .vendor = PCI_VENDOR_ID_PLX,
1751  .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1752  .subvendor = PCI_ANY_ID,
1753  .subdevice = PCI_ANY_ID,
1754  .setup = pci_omegapci_setup,
1755  },
1756  /* WCH CH353 2S1P card (16550 clone) */
1757  {
1758  .vendor = PCI_VENDOR_ID_WCH,
1759  .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
1760  .subvendor = PCI_ANY_ID,
1761  .subdevice = PCI_ANY_ID,
1762  .setup = pci_wch_ch353_setup,
1763  },
1764  /* WCH CH353 4S card (16550 clone) */
1765  {
1766  .vendor = PCI_VENDOR_ID_WCH,
1767  .device = PCI_DEVICE_ID_WCH_CH353_4S,
1768  .subvendor = PCI_ANY_ID,
1769  .subdevice = PCI_ANY_ID,
1770  .setup = pci_wch_ch353_setup,
1771  },
1772  /* WCH CH353 2S1PF card (16550 clone) */
1773  {
1774  .vendor = PCI_VENDOR_ID_WCH,
1775  .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
1776  .subvendor = PCI_ANY_ID,
1777  .subdevice = PCI_ANY_ID,
1778  .setup = pci_wch_ch353_setup,
1779  },
1780  /*
1781  * ASIX devices with FIFO bug
1782  */
1783  {
1784  .vendor = PCI_VENDOR_ID_ASIX,
1785  .device = PCI_ANY_ID,
1786  .subvendor = PCI_ANY_ID,
1787  .subdevice = PCI_ANY_ID,
1788  .setup = pci_asix_setup,
1789  },
1790  /*
1791  * Default "match everything" terminator entry
1792  */
1793  {
1794  .vendor = PCI_ANY_ID,
1795  .device = PCI_ANY_ID,
1796  .subvendor = PCI_ANY_ID,
1797  .subdevice = PCI_ANY_ID,
1798  .setup = pci_default_setup,
1799  }
1800 };
1801 
1802 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1803 {
1804  return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1805 }
1806 
1807 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1808 {
1809  struct pci_serial_quirk *quirk;
1810 
1811  for (quirk = pci_serial_quirks; ; quirk++)
1812  if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1813  quirk_id_matches(quirk->device, dev->device) &&
1814  quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1815  quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1816  break;
1817  return quirk;
1818 }
1819 
1820 static inline int get_pci_irq(struct pci_dev *dev,
1821  const struct pciserial_board *board)
1822 {
1823  if (board->flags & FL_NOIRQ)
1824  return 0;
1825  else
1826  return dev->irq;
1827 }
1828 
1829 /*
1830  * This is the configuration table for all of the PCI serial boards
1831  * which we support. It is directly indexed by the pci_board_num_t enum
1832  * value, which is encoded in the pci_device_id PCI probe table's
1833  * driver_data member.
1834  *
1835  * The makeup of these names are:
1836  * pbn_bn{_bt}_n_baud{_offsetinhex}
1837  *
1838  * bn = PCI BAR number
1839  * bt = Index using PCI BARs
1840  * n = number of serial ports
1841  * baud = baud rate
1842  * offsetinhex = offset for each sequential port (in hex)
1843  *
1844  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1845  *
1846  * Please note: in theory if n = 1, _bt infix should make no difference.
1847  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1848  */
1849 enum pci_board_num_t {
1850  pbn_default = 0,
1851 
1852  pbn_b0_1_115200,
1853  pbn_b0_2_115200,
1854  pbn_b0_4_115200,
1855  pbn_b0_5_115200,
1856  pbn_b0_8_115200,
1857 
1858  pbn_b0_1_921600,
1859  pbn_b0_2_921600,
1860  pbn_b0_4_921600,
1861 
1862  pbn_b0_2_1130000,
1863 
1864  pbn_b0_4_1152000,
1865 
1866  pbn_b0_2_1843200,
1867  pbn_b0_4_1843200,
1868 
1869  pbn_b0_2_1843200_200,
1870  pbn_b0_4_1843200_200,
1871  pbn_b0_8_1843200_200,
1872 
1873  pbn_b0_1_4000000,
1874 
1875  pbn_b0_bt_1_115200,
1876  pbn_b0_bt_2_115200,
1877  pbn_b0_bt_4_115200,
1878  pbn_b0_bt_8_115200,
1879 
1880  pbn_b0_bt_1_460800,
1881  pbn_b0_bt_2_460800,
1882  pbn_b0_bt_4_460800,
1883 
1884  pbn_b0_bt_1_921600,
1885  pbn_b0_bt_2_921600,
1886  pbn_b0_bt_4_921600,
1887  pbn_b0_bt_8_921600,
1888 
1889  pbn_b1_1_115200,
1890  pbn_b1_2_115200,
1891  pbn_b1_4_115200,
1892  pbn_b1_8_115200,
1893  pbn_b1_16_115200,
1894 
1895  pbn_b1_1_921600,
1896  pbn_b1_2_921600,
1897  pbn_b1_4_921600,
1898  pbn_b1_8_921600,
1899 
1900  pbn_b1_2_1250000,
1901 
1902  pbn_b1_bt_1_115200,
1903  pbn_b1_bt_2_115200,
1904  pbn_b1_bt_4_115200,
1905 
1906  pbn_b1_bt_2_921600,
1907 
1908  pbn_b1_1_1382400,
1909  pbn_b1_2_1382400,
1910  pbn_b1_4_1382400,
1911  pbn_b1_8_1382400,
1912 
1913  pbn_b2_1_115200,
1914  pbn_b2_2_115200,
1915  pbn_b2_4_115200,
1916  pbn_b2_8_115200,
1917 
1918  pbn_b2_1_460800,
1919  pbn_b2_4_460800,
1920  pbn_b2_8_460800,
1921  pbn_b2_16_460800,
1922 
1923  pbn_b2_1_921600,
1924  pbn_b2_4_921600,
1925  pbn_b2_8_921600,
1926 
1927  pbn_b2_8_1152000,
1928 
1929  pbn_b2_bt_1_115200,
1930  pbn_b2_bt_2_115200,
1931  pbn_b2_bt_4_115200,
1932 
1933  pbn_b2_bt_2_921600,
1934  pbn_b2_bt_4_921600,
1935 
1936  pbn_b3_2_115200,
1937  pbn_b3_4_115200,
1938  pbn_b3_8_115200,
1939 
1940  pbn_b4_bt_2_921600,
1941  pbn_b4_bt_4_921600,
1942  pbn_b4_bt_8_921600,
1943 
1944  /*
1945  * Board-specific versions.
1946  */
1947  pbn_panacom,
1948  pbn_panacom2,
1949  pbn_panacom4,
1950  pbn_plx_romulus,
1951  pbn_oxsemi,
1952  pbn_oxsemi_1_4000000,
1953  pbn_oxsemi_2_4000000,
1954  pbn_oxsemi_4_4000000,
1955  pbn_oxsemi_8_4000000,
1956  pbn_intel_i960,
1957  pbn_sgi_ioc3,
1958  pbn_computone_4,
1959  pbn_computone_6,
1960  pbn_computone_8,
1961  pbn_sbsxrsio,
1962  pbn_exar_XR17C152,
1963  pbn_exar_XR17C154,
1964  pbn_exar_XR17C158,
1965  pbn_exar_ibm_saturn,
1966  pbn_pasemi_1682M,
1967  pbn_ni8430_2,
1968  pbn_ni8430_4,
1969  pbn_ni8430_8,
1970  pbn_ni8430_16,
1971  pbn_ADDIDATA_PCIe_1_3906250,
1972  pbn_ADDIDATA_PCIe_2_3906250,
1973  pbn_ADDIDATA_PCIe_4_3906250,
1974  pbn_ADDIDATA_PCIe_8_3906250,
1975  pbn_ce4100_1_115200,
1976  pbn_omegapci,
1977  pbn_NETMOS9900_2s_115200,
1978 };
1979 
1980 /*
1981  * uart_offset - the space between channels
1982  * reg_shift - describes how the UART registers are mapped
1983  * to PCI memory by the card.
1984  * For example IER register on SBS, Inc. PMC-OctPro is located at
1985  * offset 0x10 from the UART base, while UART_IER is defined as 1
1986  * in include/linux/serial_reg.h,
1987  * see first lines of serial_in() and serial_out() in 8250.c
1988 */
1989 
1990 static struct pciserial_board pci_boards[] __devinitdata = {
1991  [pbn_default] = {
1992  .flags = FL_BASE0,
1993  .num_ports = 1,
1994  .base_baud = 115200,
1995  .uart_offset = 8,
1996  },
1997  [pbn_b0_1_115200] = {
1998  .flags = FL_BASE0,
1999  .num_ports = 1,
2000  .base_baud = 115200,
2001  .uart_offset = 8,
2002  },
2003  [pbn_b0_2_115200] = {
2004  .flags = FL_BASE0,
2005  .num_ports = 2,
2006  .base_baud = 115200,
2007  .uart_offset = 8,
2008  },
2009  [pbn_b0_4_115200] = {
2010  .flags = FL_BASE0,
2011  .num_ports = 4,
2012  .base_baud = 115200,
2013  .uart_offset = 8,
2014  },
2015  [pbn_b0_5_115200] = {
2016  .flags = FL_BASE0,
2017  .num_ports = 5,
2018  .base_baud = 115200,
2019  .uart_offset = 8,
2020  },
2021  [pbn_b0_8_115200] = {
2022  .flags = FL_BASE0,
2023  .num_ports = 8,
2024  .base_baud = 115200,
2025  .uart_offset = 8,
2026  },
2027  [pbn_b0_1_921600] = {
2028  .flags = FL_BASE0,
2029  .num_ports = 1,
2030  .base_baud = 921600,
2031  .uart_offset = 8,
2032  },
2033  [pbn_b0_2_921600] = {
2034  .flags = FL_BASE0,
2035  .num_ports = 2,
2036  .base_baud = 921600,
2037  .uart_offset = 8,
2038  },
2039  [pbn_b0_4_921600] = {
2040  .flags = FL_BASE0,
2041  .num_ports = 4,
2042  .base_baud = 921600,
2043  .uart_offset = 8,
2044  },
2045 
2046  [pbn_b0_2_1130000] = {
2047  .flags = FL_BASE0,
2048  .num_ports = 2,
2049  .base_baud = 1130000,
2050  .uart_offset = 8,
2051  },
2052 
2053  [pbn_b0_4_1152000] = {
2054  .flags = FL_BASE0,
2055  .num_ports = 4,
2056  .base_baud = 1152000,
2057  .uart_offset = 8,
2058  },
2059 
2060  [pbn_b0_2_1843200] = {
2061  .flags = FL_BASE0,
2062  .num_ports = 2,
2063  .base_baud = 1843200,
2064  .uart_offset = 8,
2065  },
2066  [pbn_b0_4_1843200] = {
2067  .flags = FL_BASE0,
2068  .num_ports = 4,
2069  .base_baud = 1843200,
2070  .uart_offset = 8,
2071  },
2072 
2073  [pbn_b0_2_1843200_200] = {
2074  .flags = FL_BASE0,
2075  .num_ports = 2,
2076  .base_baud = 1843200,
2077  .uart_offset = 0x200,
2078  },
2079  [pbn_b0_4_1843200_200] = {
2080  .flags = FL_BASE0,
2081  .num_ports = 4,
2082  .base_baud = 1843200,
2083  .uart_offset = 0x200,
2084  },
2085  [pbn_b0_8_1843200_200] = {
2086  .flags = FL_BASE0,
2087  .num_ports = 8,
2088  .base_baud = 1843200,
2089  .uart_offset = 0x200,
2090  },
2091  [pbn_b0_1_4000000] = {
2092  .flags = FL_BASE0,
2093  .num_ports = 1,
2094  .base_baud = 4000000,
2095  .uart_offset = 8,
2096  },
2097 
2098  [pbn_b0_bt_1_115200] = {
2099  .flags = FL_BASE0|FL_BASE_BARS,
2100  .num_ports = 1,
2101  .base_baud = 115200,
2102  .uart_offset = 8,
2103  },
2104  [pbn_b0_bt_2_115200] = {
2105  .flags = FL_BASE0|FL_BASE_BARS,
2106  .num_ports = 2,
2107  .base_baud = 115200,
2108  .uart_offset = 8,
2109  },
2110  [pbn_b0_bt_4_115200] = {
2111  .flags = FL_BASE0|FL_BASE_BARS,
2112  .num_ports = 4,
2113  .base_baud = 115200,
2114  .uart_offset = 8,
2115  },
2116  [pbn_b0_bt_8_115200] = {
2117  .flags = FL_BASE0|FL_BASE_BARS,
2118  .num_ports = 8,
2119  .base_baud = 115200,
2120  .uart_offset = 8,
2121  },
2122 
2123  [pbn_b0_bt_1_460800] = {
2124  .flags = FL_BASE0|FL_BASE_BARS,
2125  .num_ports = 1,
2126  .base_baud = 460800,
2127  .uart_offset = 8,
2128  },
2129  [pbn_b0_bt_2_460800] = {
2130  .flags = FL_BASE0|FL_BASE_BARS,
2131  .num_ports = 2,
2132  .base_baud = 460800,
2133  .uart_offset = 8,
2134  },
2135  [pbn_b0_bt_4_460800] = {
2136  .flags = FL_BASE0|FL_BASE_BARS,
2137  .num_ports = 4,
2138  .base_baud = 460800,
2139  .uart_offset = 8,
2140  },
2141 
2142  [pbn_b0_bt_1_921600] = {
2143  .flags = FL_BASE0|FL_BASE_BARS,
2144  .num_ports = 1,
2145  .base_baud = 921600,
2146  .uart_offset = 8,
2147  },
2148  [pbn_b0_bt_2_921600] = {
2149  .flags = FL_BASE0|FL_BASE_BARS,
2150  .num_ports = 2,
2151  .base_baud = 921600,
2152  .uart_offset = 8,
2153  },
2154  [pbn_b0_bt_4_921600] = {
2155  .flags = FL_BASE0|FL_BASE_BARS,
2156  .num_ports = 4,
2157  .base_baud = 921600,
2158  .uart_offset = 8,
2159  },
2160  [pbn_b0_bt_8_921600] = {
2161  .flags = FL_BASE0|FL_BASE_BARS,
2162  .num_ports = 8,
2163  .base_baud = 921600,
2164  .uart_offset = 8,
2165  },
2166 
2167  [pbn_b1_1_115200] = {
2168  .flags = FL_BASE1,
2169  .num_ports = 1,
2170  .base_baud = 115200,
2171  .uart_offset = 8,
2172  },
2173  [pbn_b1_2_115200] = {
2174  .flags = FL_BASE1,
2175  .num_ports = 2,
2176  .base_baud = 115200,
2177  .uart_offset = 8,
2178  },
2179  [pbn_b1_4_115200] = {
2180  .flags = FL_BASE1,
2181  .num_ports = 4,
2182  .base_baud = 115200,
2183  .uart_offset = 8,
2184  },
2185  [pbn_b1_8_115200] = {
2186  .flags = FL_BASE1,
2187  .num_ports = 8,
2188  .base_baud = 115200,
2189  .uart_offset = 8,
2190  },
2191  [pbn_b1_16_115200] = {
2192  .flags = FL_BASE1,
2193  .num_ports = 16,
2194  .base_baud = 115200,
2195  .uart_offset = 8,
2196  },
2197 
2198  [pbn_b1_1_921600] = {
2199  .flags = FL_BASE1,
2200  .num_ports = 1,
2201  .base_baud = 921600,
2202  .uart_offset = 8,
2203  },
2204  [pbn_b1_2_921600] = {
2205  .flags = FL_BASE1,
2206  .num_ports = 2,
2207  .base_baud = 921600,
2208  .uart_offset = 8,
2209  },
2210  [pbn_b1_4_921600] = {
2211  .flags = FL_BASE1,
2212  .num_ports = 4,
2213  .base_baud = 921600,
2214  .uart_offset = 8,
2215  },
2216  [pbn_b1_8_921600] = {
2217  .flags = FL_BASE1,
2218  .num_ports = 8,
2219  .base_baud = 921600,
2220  .uart_offset = 8,
2221  },
2222  [pbn_b1_2_1250000] = {
2223  .flags = FL_BASE1,
2224  .num_ports = 2,
2225  .base_baud = 1250000,
2226  .uart_offset = 8,
2227  },
2228 
2229  [pbn_b1_bt_1_115200] = {
2230  .flags = FL_BASE1|FL_BASE_BARS,
2231  .num_ports = 1,
2232  .base_baud = 115200,
2233  .uart_offset = 8,
2234  },
2235  [pbn_b1_bt_2_115200] = {
2236  .flags = FL_BASE1|FL_BASE_BARS,
2237  .num_ports = 2,
2238  .base_baud = 115200,
2239  .uart_offset = 8,
2240  },
2241  [pbn_b1_bt_4_115200] = {
2242  .flags = FL_BASE1|FL_BASE_BARS,
2243  .num_ports = 4,
2244  .base_baud = 115200,
2245  .uart_offset = 8,
2246  },
2247 
2248  [pbn_b1_bt_2_921600] = {
2249  .flags = FL_BASE1|FL_BASE_BARS,
2250  .num_ports = 2,
2251  .base_baud = 921600,
2252  .uart_offset = 8,
2253  },
2254 
2255  [pbn_b1_1_1382400] = {
2256  .flags = FL_BASE1,
2257  .num_ports = 1,
2258  .base_baud = 1382400,
2259  .uart_offset = 8,
2260  },
2261  [pbn_b1_2_1382400] = {
2262  .flags = FL_BASE1,
2263  .num_ports = 2,
2264  .base_baud = 1382400,
2265  .uart_offset = 8,
2266  },
2267  [pbn_b1_4_1382400] = {
2268  .flags = FL_BASE1,
2269  .num_ports = 4,
2270  .base_baud = 1382400,
2271  .uart_offset = 8,
2272  },
2273  [pbn_b1_8_1382400] = {
2274  .flags = FL_BASE1,
2275  .num_ports = 8,
2276  .base_baud = 1382400,
2277  .uart_offset = 8,
2278  },
2279 
2280  [pbn_b2_1_115200] = {
2281  .flags = FL_BASE2,
2282  .num_ports = 1,
2283  .base_baud = 115200,
2284  .uart_offset = 8,
2285  },
2286  [pbn_b2_2_115200] = {
2287  .flags = FL_BASE2,
2288  .num_ports = 2,
2289  .base_baud = 115200,
2290  .uart_offset = 8,
2291  },
2292  [pbn_b2_4_115200] = {
2293  .flags = FL_BASE2,
2294  .num_ports = 4,
2295  .base_baud = 115200,
2296  .uart_offset = 8,
2297  },
2298  [pbn_b2_8_115200] = {
2299  .flags = FL_BASE2,
2300  .num_ports = 8,
2301  .base_baud = 115200,
2302  .uart_offset = 8,
2303  },
2304 
2305  [pbn_b2_1_460800] = {
2306  .flags = FL_BASE2,
2307  .num_ports = 1,
2308  .base_baud = 460800,
2309  .uart_offset = 8,
2310  },
2311  [pbn_b2_4_460800] = {
2312  .flags = FL_BASE2,
2313  .num_ports = 4,
2314  .base_baud = 460800,
2315  .uart_offset = 8,
2316  },
2317  [pbn_b2_8_460800] = {
2318  .flags = FL_BASE2,
2319  .num_ports = 8,
2320  .base_baud = 460800,
2321  .uart_offset = 8,
2322  },
2323  [pbn_b2_16_460800] = {
2324  .flags = FL_BASE2,
2325  .num_ports = 16,
2326  .base_baud = 460800,
2327  .uart_offset = 8,
2328  },
2329 
2330  [pbn_b2_1_921600] = {
2331  .flags = FL_BASE2,
2332  .num_ports = 1,
2333  .base_baud = 921600,
2334  .uart_offset = 8,
2335  },
2336  [pbn_b2_4_921600] = {
2337  .flags = FL_BASE2,
2338  .num_ports = 4,
2339  .base_baud = 921600,
2340  .uart_offset = 8,
2341  },
2342  [pbn_b2_8_921600] = {
2343  .flags = FL_BASE2,
2344  .num_ports = 8,
2345  .base_baud = 921600,
2346  .uart_offset = 8,
2347  },
2348 
2349  [pbn_b2_8_1152000] = {
2350  .flags = FL_BASE2,
2351  .num_ports = 8,
2352  .base_baud = 1152000,
2353  .uart_offset = 8,
2354  },
2355 
2356  [pbn_b2_bt_1_115200] = {
2357  .flags = FL_BASE2|FL_BASE_BARS,
2358  .num_ports = 1,
2359  .base_baud = 115200,
2360  .uart_offset = 8,
2361  },
2362  [pbn_b2_bt_2_115200] = {
2363  .flags = FL_BASE2|FL_BASE_BARS,
2364  .num_ports = 2,
2365  .base_baud = 115200,
2366  .uart_offset = 8,
2367  },
2368  [pbn_b2_bt_4_115200] = {
2369  .flags = FL_BASE2|FL_BASE_BARS,
2370  .num_ports = 4,
2371  .base_baud = 115200,
2372  .uart_offset = 8,
2373  },
2374 
2375  [pbn_b2_bt_2_921600] = {
2376  .flags = FL_BASE2|FL_BASE_BARS,
2377  .num_ports = 2,
2378  .base_baud = 921600,
2379  .uart_offset = 8,
2380  },
2381  [pbn_b2_bt_4_921600] = {
2382  .flags = FL_BASE2|FL_BASE_BARS,
2383  .num_ports = 4,
2384  .base_baud = 921600,
2385  .uart_offset = 8,
2386  },
2387 
2388  [pbn_b3_2_115200] = {
2389  .flags = FL_BASE3,
2390  .num_ports = 2,
2391  .base_baud = 115200,
2392  .uart_offset = 8,
2393  },
2394  [pbn_b3_4_115200] = {
2395  .flags = FL_BASE3,
2396  .num_ports = 4,
2397  .base_baud = 115200,
2398  .uart_offset = 8,
2399  },
2400  [pbn_b3_8_115200] = {
2401  .flags = FL_BASE3,
2402  .num_ports = 8,
2403  .base_baud = 115200,
2404  .uart_offset = 8,
2405  },
2406 
2407  [pbn_b4_bt_2_921600] = {
2408  .flags = FL_BASE4,
2409  .num_ports = 2,
2410  .base_baud = 921600,
2411  .uart_offset = 8,
2412  },
2413  [pbn_b4_bt_4_921600] = {
2414  .flags = FL_BASE4,
2415  .num_ports = 4,
2416  .base_baud = 921600,
2417  .uart_offset = 8,
2418  },
2419  [pbn_b4_bt_8_921600] = {
2420  .flags = FL_BASE4,
2421  .num_ports = 8,
2422  .base_baud = 921600,
2423  .uart_offset = 8,
2424  },
2425 
2426  /*
2427  * Entries following this are board-specific.
2428  */
2429 
2430  /*
2431  * Panacom - IOMEM
2432  */
2433  [pbn_panacom] = {
2434  .flags = FL_BASE2,
2435  .num_ports = 2,
2436  .base_baud = 921600,
2437  .uart_offset = 0x400,
2438  .reg_shift = 7,
2439  },
2440  [pbn_panacom2] = {
2441  .flags = FL_BASE2|FL_BASE_BARS,
2442  .num_ports = 2,
2443  .base_baud = 921600,
2444  .uart_offset = 0x400,
2445  .reg_shift = 7,
2446  },
2447  [pbn_panacom4] = {
2448  .flags = FL_BASE2|FL_BASE_BARS,
2449  .num_ports = 4,
2450  .base_baud = 921600,
2451  .uart_offset = 0x400,
2452  .reg_shift = 7,
2453  },
2454 
2455  /* I think this entry is broken - the first_offset looks wrong --rmk */
2456  [pbn_plx_romulus] = {
2457  .flags = FL_BASE2,
2458  .num_ports = 4,
2459  .base_baud = 921600,
2460  .uart_offset = 8 << 2,
2461  .reg_shift = 2,
2462  .first_offset = 0x03,
2463  },
2464 
2465  /*
2466  * This board uses the size of PCI Base region 0 to
2467  * signal now many ports are available
2468  */
2469  [pbn_oxsemi] = {
2470  .flags = FL_BASE0|FL_REGION_SZ_CAP,
2471  .num_ports = 32,
2472  .base_baud = 115200,
2473  .uart_offset = 8,
2474  },
2475  [pbn_oxsemi_1_4000000] = {
2476  .flags = FL_BASE0,
2477  .num_ports = 1,
2478  .base_baud = 4000000,
2479  .uart_offset = 0x200,
2480  .first_offset = 0x1000,
2481  },
2482  [pbn_oxsemi_2_4000000] = {
2483  .flags = FL_BASE0,
2484  .num_ports = 2,
2485  .base_baud = 4000000,
2486  .uart_offset = 0x200,
2487  .first_offset = 0x1000,
2488  },
2489  [pbn_oxsemi_4_4000000] = {
2490  .flags = FL_BASE0,
2491  .num_ports = 4,
2492  .base_baud = 4000000,
2493  .uart_offset = 0x200,
2494  .first_offset = 0x1000,
2495  },
2496  [pbn_oxsemi_8_4000000] = {
2497  .flags = FL_BASE0,
2498  .num_ports = 8,
2499  .base_baud = 4000000,
2500  .uart_offset = 0x200,
2501  .first_offset = 0x1000,
2502  },
2503 
2504 
2505  /*
2506  * EKF addition for i960 Boards form EKF with serial port.
2507  * Max 256 ports.
2508  */
2509  [pbn_intel_i960] = {
2510  .flags = FL_BASE0,
2511  .num_ports = 32,
2512  .base_baud = 921600,
2513  .uart_offset = 8 << 2,
2514  .reg_shift = 2,
2515  .first_offset = 0x10000,
2516  },
2517  [pbn_sgi_ioc3] = {
2518  .flags = FL_BASE0|FL_NOIRQ,
2519  .num_ports = 1,
2520  .base_baud = 458333,
2521  .uart_offset = 8,
2522  .reg_shift = 0,
2523  .first_offset = 0x20178,
2524  },
2525 
2526  /*
2527  * Computone - uses IOMEM.
2528  */
2529  [pbn_computone_4] = {
2530  .flags = FL_BASE0,
2531  .num_ports = 4,
2532  .base_baud = 921600,
2533  .uart_offset = 0x40,
2534  .reg_shift = 2,
2535  .first_offset = 0x200,
2536  },
2537  [pbn_computone_6] = {
2538  .flags = FL_BASE0,
2539  .num_ports = 6,
2540  .base_baud = 921600,
2541  .uart_offset = 0x40,
2542  .reg_shift = 2,
2543  .first_offset = 0x200,
2544  },
2545  [pbn_computone_8] = {
2546  .flags = FL_BASE0,
2547  .num_ports = 8,
2548  .base_baud = 921600,
2549  .uart_offset = 0x40,
2550  .reg_shift = 2,
2551  .first_offset = 0x200,
2552  },
2553  [pbn_sbsxrsio] = {
2554  .flags = FL_BASE0,
2555  .num_ports = 8,
2556  .base_baud = 460800,
2557  .uart_offset = 256,
2558  .reg_shift = 4,
2559  },
2560  /*
2561  * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2562  * Only basic 16550A support.
2563  * XR17C15[24] are not tested, but they should work.
2564  */
2565  [pbn_exar_XR17C152] = {
2566  .flags = FL_BASE0,
2567  .num_ports = 2,
2568  .base_baud = 921600,
2569  .uart_offset = 0x200,
2570  },
2571  [pbn_exar_XR17C154] = {
2572  .flags = FL_BASE0,
2573  .num_ports = 4,
2574  .base_baud = 921600,
2575  .uart_offset = 0x200,
2576  },
2577  [pbn_exar_XR17C158] = {
2578  .flags = FL_BASE0,
2579  .num_ports = 8,
2580  .base_baud = 921600,
2581  .uart_offset = 0x200,
2582  },
2583  [pbn_exar_ibm_saturn] = {
2584  .flags = FL_BASE0,
2585  .num_ports = 1,
2586  .base_baud = 921600,
2587  .uart_offset = 0x200,
2588  },
2589 
2590  /*
2591  * PA Semi PWRficient PA6T-1682M on-chip UART
2592  */
2593  [pbn_pasemi_1682M] = {
2594  .flags = FL_BASE0,
2595  .num_ports = 1,
2596  .base_baud = 8333333,
2597  },
2598  /*
2599  * National Instruments 843x
2600  */
2601  [pbn_ni8430_16] = {
2602  .flags = FL_BASE0,
2603  .num_ports = 16,
2604  .base_baud = 3686400,
2605  .uart_offset = 0x10,
2606  .first_offset = 0x800,
2607  },
2608  [pbn_ni8430_8] = {
2609  .flags = FL_BASE0,
2610  .num_ports = 8,
2611  .base_baud = 3686400,
2612  .uart_offset = 0x10,
2613  .first_offset = 0x800,
2614  },
2615  [pbn_ni8430_4] = {
2616  .flags = FL_BASE0,
2617  .num_ports = 4,
2618  .base_baud = 3686400,
2619  .uart_offset = 0x10,
2620  .first_offset = 0x800,
2621  },
2622  [pbn_ni8430_2] = {
2623  .flags = FL_BASE0,
2624  .num_ports = 2,
2625  .base_baud = 3686400,
2626  .uart_offset = 0x10,
2627  .first_offset = 0x800,
2628  },
2629  /*
2630  * ADDI-DATA GmbH PCI-Express communication cards <[email protected]>
2631  */
2632  [pbn_ADDIDATA_PCIe_1_3906250] = {
2633  .flags = FL_BASE0,
2634  .num_ports = 1,
2635  .base_baud = 3906250,
2636  .uart_offset = 0x200,
2637  .first_offset = 0x1000,
2638  },
2639  [pbn_ADDIDATA_PCIe_2_3906250] = {
2640  .flags = FL_BASE0,
2641  .num_ports = 2,
2642  .base_baud = 3906250,
2643  .uart_offset = 0x200,
2644  .first_offset = 0x1000,
2645  },
2646  [pbn_ADDIDATA_PCIe_4_3906250] = {
2647  .flags = FL_BASE0,
2648  .num_ports = 4,
2649  .base_baud = 3906250,
2650  .uart_offset = 0x200,
2651  .first_offset = 0x1000,
2652  },
2653  [pbn_ADDIDATA_PCIe_8_3906250] = {
2654  .flags = FL_BASE0,
2655  .num_ports = 8,
2656  .base_baud = 3906250,
2657  .uart_offset = 0x200,
2658  .first_offset = 0x1000,
2659  },
2660  [pbn_ce4100_1_115200] = {
2661  .flags = FL_BASE0,
2662  .num_ports = 1,
2663  .base_baud = 921600,
2664  .reg_shift = 2,
2665  },
2666  [pbn_omegapci] = {
2667  .flags = FL_BASE0,
2668  .num_ports = 8,
2669  .base_baud = 115200,
2670  .uart_offset = 0x200,
2671  },
2672  [pbn_NETMOS9900_2s_115200] = {
2673  .flags = FL_BASE0,
2674  .num_ports = 2,
2675  .base_baud = 115200,
2676  },
2677 };
2678 
2679 static const struct pci_device_id blacklist[] = {
2680  /* softmodems */
2681  { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2682  { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2683  { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2684 
2685  /* multi-io cards handled by parport_serial */
2686  { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
2687 };
2688 
2689 /*
2690  * Given a complete unknown PCI device, try to use some heuristics to
2691  * guess what the configuration might be, based on the pitiful PCI
2692  * serial specs. Returns 0 on success, 1 on failure.
2693  */
2694 static int __devinit
2695 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2696 {
2697  const struct pci_device_id *bldev;
2698  int num_iomem, num_port, first_port = -1, i;
2699 
2700  /*
2701  * If it is not a communications device or the programming
2702  * interface is greater than 6, give up.
2703  *
2704  * (Should we try to make guesses for multiport serial devices
2705  * later?)
2706  */
2707  if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2708  ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2709  (dev->class & 0xff) > 6)
2710  return -ENODEV;
2711 
2712  /*
2713  * Do not access blacklisted devices that are known not to
2714  * feature serial ports or are handled by other modules.
2715  */
2716  for (bldev = blacklist;
2717  bldev < blacklist + ARRAY_SIZE(blacklist);
2718  bldev++) {
2719  if (dev->vendor == bldev->vendor &&
2720  dev->device == bldev->device)
2721  return -ENODEV;
2722  }
2723 
2724  num_iomem = num_port = 0;
2725  for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2726  if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2727  num_port++;
2728  if (first_port == -1)
2729  first_port = i;
2730  }
2731  if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2732  num_iomem++;
2733  }
2734 
2735  /*
2736  * If there is 1 or 0 iomem regions, and exactly one port,
2737  * use it. We guess the number of ports based on the IO
2738  * region size.
2739  */
2740  if (num_iomem <= 1 && num_port == 1) {
2741  board->flags = first_port;
2742  board->num_ports = pci_resource_len(dev, first_port) / 8;
2743  return 0;
2744  }
2745 
2746  /*
2747  * Now guess if we've got a board which indexes by BARs.
2748  * Each IO BAR should be 8 bytes, and they should follow
2749  * consecutively.
2750  */
2751  first_port = -1;
2752  num_port = 0;
2753  for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2754  if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2755  pci_resource_len(dev, i) == 8 &&
2756  (first_port == -1 || (first_port + num_port) == i)) {
2757  num_port++;
2758  if (first_port == -1)
2759  first_port = i;
2760  }
2761  }
2762 
2763  if (num_port > 1) {
2764  board->flags = first_port | FL_BASE_BARS;
2765  board->num_ports = num_port;
2766  return 0;
2767  }
2768 
2769  return -ENODEV;
2770 }
2771 
2772 static inline int
2773 serial_pci_matches(const struct pciserial_board *board,
2774  const struct pciserial_board *guessed)
2775 {
2776  return
2777  board->num_ports == guessed->num_ports &&
2778  board->base_baud == guessed->base_baud &&
2779  board->uart_offset == guessed->uart_offset &&
2780  board->reg_shift == guessed->reg_shift &&
2781  board->first_offset == guessed->first_offset;
2782 }
2783 
2784 struct serial_private *
2785 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2786 {
2787  struct uart_8250_port uart;
2788  struct serial_private *priv;
2789  struct pci_serial_quirk *quirk;
2790  int rc, nr_ports, i;
2791 
2792  nr_ports = board->num_ports;
2793 
2794  /*
2795  * Find an init and setup quirks.
2796  */
2797  quirk = find_quirk(dev);
2798 
2799  /*
2800  * Run the new-style initialization function.
2801  * The initialization function returns:
2802  * <0 - error
2803  * 0 - use board->num_ports
2804  * >0 - number of ports
2805  */
2806  if (quirk->init) {
2807  rc = quirk->init(dev);
2808  if (rc < 0) {
2809  priv = ERR_PTR(rc);
2810  goto err_out;
2811  }
2812  if (rc)
2813  nr_ports = rc;
2814  }
2815 
2816  priv = kzalloc(sizeof(struct serial_private) +
2817  sizeof(unsigned int) * nr_ports,
2818  GFP_KERNEL);
2819  if (!priv) {
2820  priv = ERR_PTR(-ENOMEM);
2821  goto err_deinit;
2822  }
2823 
2824  priv->dev = dev;
2825  priv->quirk = quirk;
2826 
2827  memset(&uart, 0, sizeof(uart));
2828  uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2829  uart.port.uartclk = board->base_baud * 16;
2830  uart.port.irq = get_pci_irq(dev, board);
2831  uart.port.dev = &dev->dev;
2832 
2833  for (i = 0; i < nr_ports; i++) {
2834  if (quirk->setup(priv, board, &uart, i))
2835  break;
2836 
2837 #ifdef SERIAL_DEBUG_PCI
2838  printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2839  uart.port.iobase, uart.port.irq, uart.port.iotype);
2840 #endif
2841 
2842  priv->line[i] = serial8250_register_8250_port(&uart);
2843  if (priv->line[i] < 0) {
2844  printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2845  break;
2846  }
2847  }
2848  priv->nr = i;
2849  return priv;
2850 
2851 err_deinit:
2852  if (quirk->exit)
2853  quirk->exit(dev);
2854 err_out:
2855  return priv;
2856 }
2857 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2858 
2859 void pciserial_remove_ports(struct serial_private *priv)
2860 {
2861  struct pci_serial_quirk *quirk;
2862  int i;
2863 
2864  for (i = 0; i < priv->nr; i++)
2865  serial8250_unregister_port(priv->line[i]);
2866 
2867  for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2868  if (priv->remapped_bar[i])
2869  iounmap(priv->remapped_bar[i]);
2870  priv->remapped_bar[i] = NULL;
2871  }
2872 
2873  /*
2874  * Find the exit quirks.
2875  */
2876  quirk = find_quirk(priv->dev);
2877  if (quirk->exit)
2878  quirk->exit(priv->dev);
2879 
2880  kfree(priv);
2881 }
2882 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2883 
2884 void pciserial_suspend_ports(struct serial_private *priv)
2885 {
2886  int i;
2887 
2888  for (i = 0; i < priv->nr; i++)
2889  if (priv->line[i] >= 0)
2890  serial8250_suspend_port(priv->line[i]);
2891 
2892  /*
2893  * Ensure that every init quirk is properly torn down
2894  */
2895  if (priv->quirk->exit)
2896  priv->quirk->exit(priv->dev);
2897 }
2898 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2899 
2900 void pciserial_resume_ports(struct serial_private *priv)
2901 {
2902  int i;
2903 
2904  /*
2905  * Ensure that the board is correctly configured.
2906  */
2907  if (priv->quirk->init)
2908  priv->quirk->init(priv->dev);
2909 
2910  for (i = 0; i < priv->nr; i++)
2911  if (priv->line[i] >= 0)
2912  serial8250_resume_port(priv->line[i]);
2913 }
2914 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2915 
2916 /*
2917  * Probe one serial board. Unfortunately, there is no rhyme nor reason
2918  * to the arrangement of serial ports on a PCI card.
2919  */
2920 static int __devinit
2921 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2922 {
2923  struct pci_serial_quirk *quirk;
2924  struct serial_private *priv;
2925  const struct pciserial_board *board;
2926  struct pciserial_board tmp;
2927  int rc;
2928 
2929  quirk = find_quirk(dev);
2930  if (quirk->probe) {
2931  rc = quirk->probe(dev);
2932  if (rc)
2933  return rc;
2934  }
2935 
2936  if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2937  printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2938  ent->driver_data);
2939  return -EINVAL;
2940  }
2941 
2942  board = &pci_boards[ent->driver_data];
2943 
2944  rc = pci_enable_device(dev);
2945  pci_save_state(dev);
2946  if (rc)
2947  return rc;
2948 
2949  if (ent->driver_data == pbn_default) {
2950  /*
2951  * Use a copy of the pci_board entry for this;
2952  * avoid changing entries in the table.
2953  */
2954  memcpy(&tmp, board, sizeof(struct pciserial_board));
2955  board = &tmp;
2956 
2957  /*
2958  * We matched one of our class entries. Try to
2959  * determine the parameters of this board.
2960  */
2961  rc = serial_pci_guess_board(dev, &tmp);
2962  if (rc)
2963  goto disable;
2964  } else {
2965  /*
2966  * We matched an explicit entry. If we are able to
2967  * detect this boards settings with our heuristic,
2968  * then we no longer need this entry.
2969  */
2970  memcpy(&tmp, &pci_boards[pbn_default],
2971  sizeof(struct pciserial_board));
2972  rc = serial_pci_guess_board(dev, &tmp);
2973  if (rc == 0 && serial_pci_matches(board, &tmp))
2974  moan_device("Redundant entry in serial pci_table.",
2975  dev);
2976  }
2977 
2978  priv = pciserial_init_ports(dev, board);
2979  if (!IS_ERR(priv)) {
2980  pci_set_drvdata(dev, priv);
2981  return 0;
2982  }
2983 
2984  rc = PTR_ERR(priv);
2985 
2986  disable:
2987  pci_disable_device(dev);
2988  return rc;
2989 }
2990 
2991 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2992 {
2993  struct serial_private *priv = pci_get_drvdata(dev);
2994 
2995  pci_set_drvdata(dev, NULL);
2996 
2997  pciserial_remove_ports(priv);
2998 
2999  pci_disable_device(dev);
3000 }
3001 
3002 #ifdef CONFIG_PM
3003 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3004 {
3005  struct serial_private *priv = pci_get_drvdata(dev);
3006 
3007  if (priv)
3008  pciserial_suspend_ports(priv);
3009 
3010  pci_save_state(dev);
3011  pci_set_power_state(dev, pci_choose_state(dev, state));
3012  return 0;
3013 }
3014 
3015 static int pciserial_resume_one(struct pci_dev *dev)
3016 {
3017  int err;
3018  struct serial_private *priv = pci_get_drvdata(dev);
3019 
3020  pci_set_power_state(dev, PCI_D0);
3021  pci_restore_state(dev);
3022 
3023  if (priv) {
3024  /*
3025  * The device may have been disabled. Re-enable it.
3026  */
3027  err = pci_enable_device(dev);
3028  /* FIXME: We cannot simply error out here */
3029  if (err)
3030  printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3031  pciserial_resume_ports(priv);
3032  }
3033  return 0;
3034 }
3035 #endif
3036 
3037 static struct pci_device_id serial_pci_tbl[] = {
3038  /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3039  { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3040  PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3041  pbn_b2_8_921600 },
3042  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3043  PCI_SUBVENDOR_ID_CONNECT_TECH,
3044  PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3045  pbn_b1_8_1382400 },
3046  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3047  PCI_SUBVENDOR_ID_CONNECT_TECH,
3048  PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3049  pbn_b1_4_1382400 },
3050  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3051  PCI_SUBVENDOR_ID_CONNECT_TECH,
3052  PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3053  pbn_b1_2_1382400 },
3054  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3055  PCI_SUBVENDOR_ID_CONNECT_TECH,
3056  PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3057  pbn_b1_8_1382400 },
3058  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3059  PCI_SUBVENDOR_ID_CONNECT_TECH,
3060  PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3061  pbn_b1_4_1382400 },
3062  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3063  PCI_SUBVENDOR_ID_CONNECT_TECH,
3064  PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3065  pbn_b1_2_1382400 },
3066  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3067  PCI_SUBVENDOR_ID_CONNECT_TECH,
3068  PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3069  pbn_b1_8_921600 },
3070  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3071  PCI_SUBVENDOR_ID_CONNECT_TECH,
3072  PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3073  pbn_b1_8_921600 },
3074  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3075  PCI_SUBVENDOR_ID_CONNECT_TECH,
3076  PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3077  pbn_b1_4_921600 },
3078  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3079  PCI_SUBVENDOR_ID_CONNECT_TECH,
3080  PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3081  pbn_b1_4_921600 },
3082  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3083  PCI_SUBVENDOR_ID_CONNECT_TECH,
3084  PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3085  pbn_b1_2_921600 },
3086  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3087  PCI_SUBVENDOR_ID_CONNECT_TECH,
3088  PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3089  pbn_b1_8_921600 },
3090  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3091  PCI_SUBVENDOR_ID_CONNECT_TECH,
3092  PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3093  pbn_b1_8_921600 },
3094  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3095  PCI_SUBVENDOR_ID_CONNECT_TECH,
3096  PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3097  pbn_b1_4_921600 },
3098  { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3099  PCI_SUBVENDOR_ID_CONNECT_TECH,
3100  PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3101  pbn_b1_2_1250000 },
3102  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3103  PCI_SUBVENDOR_ID_CONNECT_TECH,
3104  PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3105  pbn_b0_2_1843200 },
3106  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3107  PCI_SUBVENDOR_ID_CONNECT_TECH,
3108  PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3109  pbn_b0_4_1843200 },
3110  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3111  PCI_VENDOR_ID_AFAVLAB,
3112  PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3113  pbn_b0_4_1152000 },
3114  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3115  PCI_SUBVENDOR_ID_CONNECT_TECH,
3116  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3117  pbn_b0_2_1843200_200 },
3118  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3119  PCI_SUBVENDOR_ID_CONNECT_TECH,
3120  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3121  pbn_b0_4_1843200_200 },
3122  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3123  PCI_SUBVENDOR_ID_CONNECT_TECH,
3124  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3125  pbn_b0_8_1843200_200 },
3126  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3127  PCI_SUBVENDOR_ID_CONNECT_TECH,
3128  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3129  pbn_b0_2_1843200_200 },
3130  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3131  PCI_SUBVENDOR_ID_CONNECT_TECH,
3132  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3133  pbn_b0_4_1843200_200 },
3134  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3135  PCI_SUBVENDOR_ID_CONNECT_TECH,
3136  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3137  pbn_b0_8_1843200_200 },
3138  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3139  PCI_SUBVENDOR_ID_CONNECT_TECH,
3140  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3141  pbn_b0_2_1843200_200 },
3142  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3143  PCI_SUBVENDOR_ID_CONNECT_TECH,
3144  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3145  pbn_b0_4_1843200_200 },
3146  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3147  PCI_SUBVENDOR_ID_CONNECT_TECH,
3148  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3149  pbn_b0_8_1843200_200 },
3150  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3151  PCI_SUBVENDOR_ID_CONNECT_TECH,
3152  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3153  pbn_b0_2_1843200_200 },
3154  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3155  PCI_SUBVENDOR_ID_CONNECT_TECH,
3156  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3157  pbn_b0_4_1843200_200 },
3158  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3159  PCI_SUBVENDOR_ID_CONNECT_TECH,
3160  PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3161  pbn_b0_8_1843200_200 },
3162  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3163  PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3164  0, 0, pbn_exar_ibm_saturn },
3165 
3166  { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3167  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3168  pbn_b2_bt_1_115200 },
3169  { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3170  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3171  pbn_b2_bt_2_115200 },
3172  { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3173  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3174  pbn_b2_bt_4_115200 },
3175  { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3176  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3177  pbn_b2_bt_2_115200 },
3178  { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3179  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3180  pbn_b2_bt_4_115200 },
3181  { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3182  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3183  pbn_b2_8_115200 },
3184  { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3185  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3186  pbn_b2_8_460800 },
3187  { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3188  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3189  pbn_b2_8_115200 },
3190 
3191  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3192  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3193  pbn_b2_bt_2_115200 },
3194  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3195  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3196  pbn_b2_bt_2_921600 },
3197  /*
3198  * VScom SPCOM800, from [email protected]
3199  */
3200  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3201  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3202  pbn_b2_8_921600 },
3203  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3204  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3205  pbn_b2_4_921600 },
3206  /* Unknown card - subdevice 0x1584 */
3207  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3208  PCI_VENDOR_ID_PLX,
3209  PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3210  pbn_b0_4_115200 },
3211  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3212  PCI_SUBVENDOR_ID_KEYSPAN,
3213  PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3214  pbn_panacom },
3215  { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3216  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217  pbn_panacom4 },
3218  { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3219  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220  pbn_panacom2 },
3221  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3222  PCI_VENDOR_ID_ESDGMBH,
3223  PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3224  pbn_b2_4_115200 },
3225  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3226  PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3227  PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3228  pbn_b2_4_460800 },
3229  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3230  PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3231  PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3232  pbn_b2_8_460800 },
3233  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3234  PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3235  PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3236  pbn_b2_16_460800 },
3237  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3238  PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3239  PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3240  pbn_b2_16_460800 },
3241  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3242  PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3243  PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3244  pbn_b2_4_460800 },
3245  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3246  PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3247  PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3248  pbn_b2_8_460800 },
3249  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3250  PCI_SUBVENDOR_ID_EXSYS,
3251  PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3252  pbn_b2_4_115200 },
3253  /*
3254  * Megawolf Romulus PCI Serial Card, from Mike Hudson
3255  * ([email protected])
3256  */
3257  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3258  0x10b5, 0x106a, 0, 0,
3259  pbn_plx_romulus },
3260  { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3261  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262  pbn_b1_4_115200 },
3263  { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3264  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265  pbn_b1_2_115200 },
3266  { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3267  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268  pbn_b1_8_115200 },
3269  { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3270  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271  pbn_b1_8_115200 },
3272  { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3273  PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3274  0, 0,
3275  pbn_b0_4_921600 },
3276  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3277  PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3278  0, 0,
3279  pbn_b0_4_1152000 },
3280  { PCI_VENDOR_ID_OXSEMI, 0x9505,
3281  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3282  pbn_b0_bt_2_921600 },
3283 
3284  /*
3285  * The below card is a little controversial since it is the
3286  * subject of a PCI vendor/device ID clash. (See
3287  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3288  * For now just used the hex ID 0x950a.
3289  */
3290  { PCI_VENDOR_ID_OXSEMI, 0x950a,
3291  PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3292  0, 0, pbn_b0_2_115200 },
3293  { PCI_VENDOR_ID_OXSEMI, 0x950a,
3294  PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3295  0, 0, pbn_b0_2_115200 },
3296  { PCI_VENDOR_ID_OXSEMI, 0x950a,
3297  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298  pbn_b0_2_1130000 },
3299  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3300  PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3301  pbn_b0_1_921600 },
3302  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3303  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304  pbn_b0_4_115200 },
3305  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3306  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307  pbn_b0_bt_2_921600 },
3308  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3309  PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3310  pbn_b2_8_1152000 },
3311 
3312  /*
3313  * Oxford Semiconductor Inc. Tornado PCI express device range.
3314  */
3315  { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3316  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317  pbn_b0_1_4000000 },
3318  { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3319  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320  pbn_b0_1_4000000 },
3321  { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3322  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3323  pbn_oxsemi_1_4000000 },
3324  { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3325  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326  pbn_oxsemi_1_4000000 },
3327  { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3328  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3329  pbn_b0_1_4000000 },
3330  { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3331  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3332  pbn_b0_1_4000000 },
3333  { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3334  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3335  pbn_oxsemi_1_4000000 },
3336  { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3337  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3338  pbn_oxsemi_1_4000000 },
3339  { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3340  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3341  pbn_b0_1_4000000 },
3342  { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3343  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3344  pbn_b0_1_4000000 },
3345  { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3346  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3347  pbn_b0_1_4000000 },
3348  { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3349  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3350  pbn_b0_1_4000000 },
3351  { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3352  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3353  pbn_oxsemi_2_4000000 },
3354  { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3355  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3356  pbn_oxsemi_2_4000000 },
3357  { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3358  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359  pbn_oxsemi_4_4000000 },
3360  { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3361  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3362  pbn_oxsemi_4_4000000 },
3363  { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3364  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3365  pbn_oxsemi_8_4000000 },
3366  { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3367  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3368  pbn_oxsemi_8_4000000 },
3369  { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3370  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3371  pbn_oxsemi_1_4000000 },
3372  { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3373  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3374  pbn_oxsemi_1_4000000 },
3375  { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3376  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3377  pbn_oxsemi_1_4000000 },
3378  { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3379  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3380  pbn_oxsemi_1_4000000 },
3381  { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3382  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3383  pbn_oxsemi_1_4000000 },
3384  { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3385  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3386  pbn_oxsemi_1_4000000 },
3387  { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3388  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3389  pbn_oxsemi_1_4000000 },
3390  { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3391  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392  pbn_oxsemi_1_4000000 },
3393  { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3394  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395  pbn_oxsemi_1_4000000 },
3396  { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3397  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3398  pbn_oxsemi_1_4000000 },
3399  { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3400  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3401  pbn_oxsemi_1_4000000 },
3402  { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3403  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3404  pbn_oxsemi_1_4000000 },
3405  { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3406  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407  pbn_oxsemi_1_4000000 },
3408  { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3409  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3410  pbn_oxsemi_1_4000000 },
3411  { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3412  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413  pbn_oxsemi_1_4000000 },
3414  { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3415  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416  pbn_oxsemi_1_4000000 },
3417  { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3418  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419  pbn_oxsemi_1_4000000 },
3420  { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3421  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422  pbn_oxsemi_1_4000000 },
3423  { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3424  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425  pbn_oxsemi_1_4000000 },
3426  { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3427  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428  pbn_oxsemi_1_4000000 },
3429  { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3430  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431  pbn_oxsemi_1_4000000 },
3432  { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3433  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434  pbn_oxsemi_1_4000000 },
3435  { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3436  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437  pbn_oxsemi_1_4000000 },
3438  { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3439  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440  pbn_oxsemi_1_4000000 },
3441  { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3442  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443  pbn_oxsemi_1_4000000 },
3444  { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3445  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446  pbn_oxsemi_1_4000000 },
3447  /*
3448  * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3449  */
3450  { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3451  PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3452  pbn_oxsemi_1_4000000 },
3453  { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3454  PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3455  pbn_oxsemi_2_4000000 },
3456  { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3457  PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3458  pbn_oxsemi_4_4000000 },
3459  { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3460  PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3461  pbn_oxsemi_8_4000000 },
3462 
3463  /*
3464  * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3465  */
3466  { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3467  PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3468  pbn_oxsemi_2_4000000 },
3469 
3470  /*
3471  * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3472  * from [email protected]
3473  */
3474  { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3475  PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3476  pbn_sbsxrsio },
3477  { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3478  PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3479  pbn_sbsxrsio },
3480  { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3481  PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3482  pbn_sbsxrsio },
3483  { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3484  PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3485  pbn_sbsxrsio },
3486 
3487  /*
3488  * Digitan DS560-558, from [email protected]
3489  */
3490  { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3491  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492  pbn_b1_1_115200 },
3493 
3494  /*
3495  * Titan Electronic cards
3496  * The 400L and 800L have a custom setup quirk.
3497  */
3498  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3499  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3500  pbn_b0_1_921600 },
3501  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3502  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3503  pbn_b0_2_921600 },
3504  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3505  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3506  pbn_b0_4_921600 },
3507  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3508  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3509  pbn_b0_4_921600 },
3510  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3511  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3512  pbn_b1_1_921600 },
3513  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3514  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3515  pbn_b1_bt_2_921600 },
3516  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3517  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3518  pbn_b0_bt_4_921600 },
3519  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3520  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3521  pbn_b0_bt_8_921600 },
3522  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3523  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3524  pbn_b4_bt_2_921600 },
3525  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3526  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3527  pbn_b4_bt_4_921600 },
3528  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3529  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3530  pbn_b4_bt_8_921600 },
3531  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3532  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3533  pbn_b0_4_921600 },
3534  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3535  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3536  pbn_b0_4_921600 },
3537  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3538  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3539  pbn_b0_4_921600 },
3540  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3541  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3542  pbn_oxsemi_1_4000000 },
3543  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3544  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3545  pbn_oxsemi_2_4000000 },
3546  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3547  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548  pbn_oxsemi_4_4000000 },
3549  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3550  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551  pbn_oxsemi_8_4000000 },
3552  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3553  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554  pbn_oxsemi_2_4000000 },
3555  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3556  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557  pbn_oxsemi_2_4000000 },
3558  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3559  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560  pbn_b0_4_921600 },
3561  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3562  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3563  pbn_b0_4_921600 },
3564  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3565  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3566  pbn_b0_4_921600 },
3567  { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3568  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3569  pbn_b0_4_921600 },
3570 
3571  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3572  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3573  pbn_b2_1_460800 },
3574  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3575  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3576  pbn_b2_1_460800 },
3577  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3578  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3579  pbn_b2_1_460800 },
3580  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3581  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3582  pbn_b2_bt_2_921600 },
3583  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3584  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3585  pbn_b2_bt_2_921600 },
3586  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3587  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3588  pbn_b2_bt_2_921600 },
3589  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3590  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3591  pbn_b2_bt_4_921600 },
3592  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3593  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3594  pbn_b2_bt_4_921600 },
3595  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3596  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3597  pbn_b2_bt_4_921600 },
3598  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3599  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3600  pbn_b0_1_921600 },
3601  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3602  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3603  pbn_b0_1_921600 },
3604  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3605  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3606  pbn_b0_1_921600 },
3607  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3608  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3609  pbn_b0_bt_2_921600 },
3610  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3611  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3612  pbn_b0_bt_2_921600 },
3613  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3614  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3615  pbn_b0_bt_2_921600 },
3616  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3617  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3618  pbn_b0_bt_4_921600 },
3619  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3620  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3621  pbn_b0_bt_4_921600 },
3622  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3623  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3624  pbn_b0_bt_4_921600 },
3625  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3626  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3627  pbn_b0_bt_8_921600 },
3628  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3629  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3630  pbn_b0_bt_8_921600 },
3631  { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3632  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3633  pbn_b0_bt_8_921600 },
3634 
3635  /*
3636  * Computone devices submitted by Doug McNash [email protected]
3637  */
3638  { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3639  PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3640  0, 0, pbn_computone_4 },
3641  { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3642  PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3643  0, 0, pbn_computone_8 },
3644  { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3645  PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3646  0, 0, pbn_computone_6 },
3647 
3648  { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3649  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3650  pbn_oxsemi },
3651  { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3652  PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3653  pbn_b0_bt_1_921600 },
3654 
3655  /*
3656  * AFAVLAB serial card, from Harald Welte <[email protected]>
3657  */
3658  { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3659  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3660  pbn_b0_bt_8_115200 },
3661  { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3662  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3663  pbn_b0_bt_8_115200 },
3664 
3665  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3666  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3667  pbn_b0_bt_2_115200 },
3668  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3669  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3670  pbn_b0_bt_2_115200 },
3671  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3672  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3673  pbn_b0_bt_2_115200 },
3674  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3675  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3676  pbn_b0_bt_2_115200 },
3677  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3678  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3679  pbn_b0_bt_2_115200 },
3680  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3681  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3682  pbn_b0_bt_4_460800 },
3683  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3684  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3685  pbn_b0_bt_4_460800 },
3686  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3687  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3688  pbn_b0_bt_2_460800 },
3689  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3690  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3691  pbn_b0_bt_2_460800 },
3692  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3693  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3694  pbn_b0_bt_2_460800 },
3695  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3696  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3697  pbn_b0_bt_1_115200 },
3698  { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3699  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3700  pbn_b0_bt_1_460800 },
3701 
3702  /*
3703  * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3704  * Cards are identified by their subsystem vendor IDs, which
3705  * (in hex) match the model number.
3706  *
3707  * Note that JC140x are RS422/485 cards which require ox950
3708  * ACR = 0x10, and as such are not currently fully supported.
3709  */
3710  { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3711  0x1204, 0x0004, 0, 0,
3712  pbn_b0_4_921600 },
3713  { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3714  0x1208, 0x0004, 0, 0,
3715  pbn_b0_4_921600 },
3716 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3717  0x1402, 0x0002, 0, 0,
3718  pbn_b0_2_921600 }, */
3719 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3720  0x1404, 0x0004, 0, 0,
3721  pbn_b0_4_921600 }, */
3722  { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3723  0x1208, 0x0004, 0, 0,
3724  pbn_b0_4_921600 },
3725 
3726  { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3727  0x1204, 0x0004, 0, 0,
3728  pbn_b0_4_921600 },
3729  { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3730  0x1208, 0x0004, 0, 0,
3731  pbn_b0_4_921600 },
3732  { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3733  0x1208, 0x0004, 0, 0,
3734  pbn_b0_4_921600 },
3735  /*
3736  * Dell Remote Access Card 4 - [email protected]
3737  */
3738  { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3739  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3740  pbn_b1_1_1382400 },
3741 
3742  /*
3743  * Dell Remote Access Card III - [email protected]
3744  */
3745  { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3746  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3747  pbn_b1_1_1382400 },
3748 
3749  /*
3750  * RAStel 2 port modem, [email protected]
3751  */
3752  { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3753  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3754  pbn_b2_bt_2_115200 },
3755 
3756  /*
3757  * EKF addition for i960 Boards form EKF with serial port
3758  */
3759  { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3760  0xE4BF, PCI_ANY_ID, 0, 0,
3761  pbn_intel_i960 },
3762 
3763  /*
3764  * Xircom Cardbus/Ethernet combos
3765  */
3766  { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3767  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3768  pbn_b0_1_115200 },
3769  /*
3770  * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3771  */
3772  { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3773  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3774  pbn_b0_1_115200 },
3775 
3776  /*
3777  * Untested PCI modems, sent in from various folks...
3778  */
3779 
3780  /*
3781  * Elsa Model 56K PCI Modem, from Andreas Rath <[email protected]>
3782  */
3783  { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3784  0x1048, 0x1500, 0, 0,
3785  pbn_b1_1_115200 },
3786 
3787  { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3788  0xFF00, 0, 0, 0,
3789  pbn_sgi_ioc3 },
3790 
3791  /*
3792  * HP Diva card
3793  */
3794  { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3795  PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3796  pbn_b1_1_115200 },
3797  { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3798  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3799  pbn_b0_5_115200 },
3800  { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3801  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3802  pbn_b2_1_115200 },
3803 
3804  { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3805  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3806  pbn_b3_2_115200 },
3807  { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3808  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3809  pbn_b3_4_115200 },
3810  { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3811  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3812  pbn_b3_8_115200 },
3813 
3814  /*
3815  * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3816  */
3817  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3818  PCI_ANY_ID, PCI_ANY_ID,
3819  0,
3820  0, pbn_exar_XR17C152 },
3821  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3822  PCI_ANY_ID, PCI_ANY_ID,
3823  0,
3824  0, pbn_exar_XR17C154 },
3825  { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3826  PCI_ANY_ID, PCI_ANY_ID,
3827  0,
3828  0, pbn_exar_XR17C158 },
3829 
3830  /*
3831  * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3832  */
3833  { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3834  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3835  pbn_b0_1_115200 },
3836  /*
3837  * ITE
3838  */
3839  { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3840  PCI_ANY_ID, PCI_ANY_ID,
3841  0, 0,
3842  pbn_b1_bt_1_115200 },
3843 
3844  /*
3845  * IntaShield IS-200
3846  */
3847  { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3848  PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3849  pbn_b2_2_115200 },
3850  /*
3851  * IntaShield IS-400
3852  */
3853  { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3854  PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3855  pbn_b2_4_115200 },
3856  /*
3857  * Perle PCI-RAS cards
3858  */
3859  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3860  PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3861  0, 0, pbn_b2_4_921600 },
3862  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3863  PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3864  0, 0, pbn_b2_8_921600 },
3865 
3866  /*
3867  * Mainpine series cards: Fairly standard layout but fools
3868  * parts of the autodetect in some cases and uses otherwise
3869  * unmatched communications subclasses in the PCI Express case
3870  */
3871 
3872  { /* RockForceDUO */
3873  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3874  PCI_VENDOR_ID_MAINPINE, 0x0200,
3875  0, 0, pbn_b0_2_115200 },
3876  { /* RockForceQUATRO */
3877  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3878  PCI_VENDOR_ID_MAINPINE, 0x0300,
3879  0, 0, pbn_b0_4_115200 },
3880  { /* RockForceDUO+ */
3881  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3882  PCI_VENDOR_ID_MAINPINE, 0x0400,
3883  0, 0, pbn_b0_2_115200 },
3884  { /* RockForceQUATRO+ */
3885  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3886  PCI_VENDOR_ID_MAINPINE, 0x0500,
3887  0, 0, pbn_b0_4_115200 },
3888  { /* RockForce+ */
3889  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3890  PCI_VENDOR_ID_MAINPINE, 0x0600,
3891  0, 0, pbn_b0_2_115200 },
3892  { /* RockForce+ */
3893  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3894  PCI_VENDOR_ID_MAINPINE, 0x0700,
3895  0, 0, pbn_b0_4_115200 },
3896  { /* RockForceOCTO+ */
3897  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3898  PCI_VENDOR_ID_MAINPINE, 0x0800,
3899  0, 0, pbn_b0_8_115200 },
3900  { /* RockForceDUO+ */
3901  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3902  PCI_VENDOR_ID_MAINPINE, 0x0C00,
3903  0, 0, pbn_b0_2_115200 },
3904  { /* RockForceQUARTRO+ */
3905  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3906  PCI_VENDOR_ID_MAINPINE, 0x0D00,
3907  0, 0, pbn_b0_4_115200 },
3908  { /* RockForceOCTO+ */
3909  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3910  PCI_VENDOR_ID_MAINPINE, 0x1D00,
3911  0, 0, pbn_b0_8_115200 },
3912  { /* RockForceD1 */
3913  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3914  PCI_VENDOR_ID_MAINPINE, 0x2000,
3915  0, 0, pbn_b0_1_115200 },
3916  { /* RockForceF1 */
3917  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3918  PCI_VENDOR_ID_MAINPINE, 0x2100,
3919  0, 0, pbn_b0_1_115200 },
3920  { /* RockForceD2 */
3921  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3922  PCI_VENDOR_ID_MAINPINE, 0x2200,
3923  0, 0, pbn_b0_2_115200 },
3924  { /* RockForceF2 */
3925  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3926  PCI_VENDOR_ID_MAINPINE, 0x2300,
3927  0, 0, pbn_b0_2_115200 },
3928  { /* RockForceD4 */
3929  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3930  PCI_VENDOR_ID_MAINPINE, 0x2400,
3931  0, 0, pbn_b0_4_115200 },
3932  { /* RockForceF4 */
3933  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3934  PCI_VENDOR_ID_MAINPINE, 0x2500,
3935  0, 0, pbn_b0_4_115200 },
3936  { /* RockForceD8 */
3937  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3938  PCI_VENDOR_ID_MAINPINE, 0x2600,
3939  0, 0, pbn_b0_8_115200 },
3940  { /* RockForceF8 */
3941  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3942  PCI_VENDOR_ID_MAINPINE, 0x2700,
3943  0, 0, pbn_b0_8_115200 },
3944  { /* IQ Express D1 */
3945  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3946  PCI_VENDOR_ID_MAINPINE, 0x3000,
3947  0, 0, pbn_b0_1_115200 },
3948  { /* IQ Express F1 */
3949  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3950  PCI_VENDOR_ID_MAINPINE, 0x3100,
3951  0, 0, pbn_b0_1_115200 },
3952  { /* IQ Express D2 */
3953  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3954  PCI_VENDOR_ID_MAINPINE, 0x3200,
3955  0, 0, pbn_b0_2_115200 },
3956  { /* IQ Express F2 */
3957  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3958  PCI_VENDOR_ID_MAINPINE, 0x3300,
3959  0, 0, pbn_b0_2_115200 },
3960  { /* IQ Express D4 */
3961  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3962  PCI_VENDOR_ID_MAINPINE, 0x3400,
3963  0, 0, pbn_b0_4_115200 },
3964  { /* IQ Express F4 */
3965  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3966  PCI_VENDOR_ID_MAINPINE, 0x3500,
3967  0, 0, pbn_b0_4_115200 },
3968  { /* IQ Express D8 */
3969  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3970  PCI_VENDOR_ID_MAINPINE, 0x3C00,
3971  0, 0, pbn_b0_8_115200 },
3972  { /* IQ Express F8 */
3973  PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3974  PCI_VENDOR_ID_MAINPINE, 0x3D00,
3975  0, 0, pbn_b0_8_115200 },
3976 
3977 
3978  /*
3979  * PA Semi PA6T-1682M on-chip UART
3980  */
3981  { PCI_VENDOR_ID_PASEMI, 0xa004,
3982  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983  pbn_pasemi_1682M },
3984 
3985  /*
3986  * National Instruments
3987  */
3988  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3989  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3990  pbn_b1_16_115200 },
3991  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3992  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3993  pbn_b1_8_115200 },
3994  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3995  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3996  pbn_b1_bt_4_115200 },
3997  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3998  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3999  pbn_b1_bt_2_115200 },
4000  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4001  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4002  pbn_b1_bt_4_115200 },
4003  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4004  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4005  pbn_b1_bt_2_115200 },
4006  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4007  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4008  pbn_b1_16_115200 },
4009  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4010  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4011  pbn_b1_8_115200 },
4012  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4013  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4014  pbn_b1_bt_4_115200 },
4015  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4016  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4017  pbn_b1_bt_2_115200 },
4018  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4019  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4020  pbn_b1_bt_4_115200 },
4021  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4022  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4023  pbn_b1_bt_2_115200 },
4024  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4025  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4026  pbn_ni8430_2 },
4027  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4028  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4029  pbn_ni8430_2 },
4030  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4031  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4032  pbn_ni8430_4 },
4033  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4034  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4035  pbn_ni8430_4 },
4036  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4037  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4038  pbn_ni8430_8 },
4039  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4040  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4041  pbn_ni8430_8 },
4042  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4043  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4044  pbn_ni8430_16 },
4045  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4046  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4047  pbn_ni8430_16 },
4048  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4049  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4050  pbn_ni8430_2 },
4051  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4052  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4053  pbn_ni8430_2 },
4054  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4055  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4056  pbn_ni8430_4 },
4057  { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4058  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4059  pbn_ni8430_4 },
4060 
4061  /*
4062  * ADDI-DATA GmbH communication cards <[email protected]>
4063  */
4064  { PCI_VENDOR_ID_ADDIDATA,
4065  PCI_DEVICE_ID_ADDIDATA_APCI7500,
4066  PCI_ANY_ID,
4067  PCI_ANY_ID,
4068  0,
4069  0,
4070  pbn_b0_4_115200 },
4071 
4072  { PCI_VENDOR_ID_ADDIDATA,
4073  PCI_DEVICE_ID_ADDIDATA_APCI7420,
4074  PCI_ANY_ID,
4075  PCI_ANY_ID,
4076  0,
4077  0,
4078  pbn_b0_2_115200 },
4079 
4080  { PCI_VENDOR_ID_ADDIDATA,
4081  PCI_DEVICE_ID_ADDIDATA_APCI7300,
4082  PCI_ANY_ID,
4083  PCI_ANY_ID,
4084  0,
4085  0,
4086  pbn_b0_1_115200 },
4087 
4088  { PCI_VENDOR_ID_ADDIDATA_OLD,
4089  PCI_DEVICE_ID_ADDIDATA_APCI7800,
4090  PCI_ANY_ID,
4091  PCI_ANY_ID,
4092  0,
4093  0,
4094  pbn_b1_8_115200 },
4095 
4096  { PCI_VENDOR_ID_ADDIDATA,
4097  PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4098  PCI_ANY_ID,
4099  PCI_ANY_ID,
4100  0,
4101  0,
4102  pbn_b0_4_115200 },
4103 
4104  { PCI_VENDOR_ID_ADDIDATA,
4105  PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4106  PCI_ANY_ID,
4107  PCI_ANY_ID,
4108  0,
4109  0,
4110  pbn_b0_2_115200 },
4111 
4112  { PCI_VENDOR_ID_ADDIDATA,
4113  PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4114  PCI_ANY_ID,
4115  PCI_ANY_ID,
4116  0,
4117  0,
4118  pbn_b0_1_115200 },
4119 
4120  { PCI_VENDOR_ID_ADDIDATA,
4121  PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4122  PCI_ANY_ID,
4123  PCI_ANY_ID,
4124  0,
4125  0,
4126  pbn_b0_4_115200 },
4127 
4128  { PCI_VENDOR_ID_ADDIDATA,
4129  PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4130  PCI_ANY_ID,
4131  PCI_ANY_ID,
4132  0,
4133  0,
4134  pbn_b0_2_115200 },
4135 
4136  { PCI_VENDOR_ID_ADDIDATA,
4137  PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4138  PCI_ANY_ID,
4139  PCI_ANY_ID,
4140  0,
4141  0,
4142  pbn_b0_1_115200 },
4143 
4144  { PCI_VENDOR_ID_ADDIDATA,
4145  PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4146  PCI_ANY_ID,
4147  PCI_ANY_ID,
4148  0,
4149  0,
4150  pbn_b0_8_115200 },
4151 
4152  { PCI_VENDOR_ID_ADDIDATA,
4153  PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4154  PCI_ANY_ID,
4155  PCI_ANY_ID,
4156  0,
4157  0,
4158  pbn_ADDIDATA_PCIe_4_3906250 },
4159 
4160  { PCI_VENDOR_ID_ADDIDATA,
4161  PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4162  PCI_ANY_ID,
4163  PCI_ANY_ID,
4164  0,
4165  0,
4166  pbn_ADDIDATA_PCIe_2_3906250 },
4167 
4168  { PCI_VENDOR_ID_ADDIDATA,
4169  PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4170  PCI_ANY_ID,
4171  PCI_ANY_ID,
4172  0,
4173  0,
4174  pbn_ADDIDATA_PCIe_1_3906250 },
4175 
4176  { PCI_VENDOR_ID_ADDIDATA,
4177  PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4178  PCI_ANY_ID,
4179  PCI_ANY_ID,
4180  0,
4181  0,
4182  pbn_ADDIDATA_PCIe_8_3906250 },
4183 
4184  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4185  PCI_VENDOR_ID_IBM, 0x0299,
4186  0, 0, pbn_b0_bt_2_115200 },
4187 
4188  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4189  0xA000, 0x1000,
4190  0, 0, pbn_b0_1_115200 },
4191 
4192  /* the 9901 is a rebranded 9912 */
4193  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4194  0xA000, 0x1000,
4195  0, 0, pbn_b0_1_115200 },
4196 
4197  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4198  0xA000, 0x1000,
4199  0, 0, pbn_b0_1_115200 },
4200 
4201  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4202  0xA000, 0x1000,
4203  0, 0, pbn_b0_1_115200 },
4204 
4205  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4206  0xA000, 0x1000,
4207  0, 0, pbn_b0_1_115200 },
4208 
4209  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4210  0xA000, 0x3002,
4211  0, 0, pbn_NETMOS9900_2s_115200 },
4212 
4213  /*
4214  * Best Connectivity and Rosewill PCI Multi I/O cards
4215  */
4216 
4217  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4218  0xA000, 0x1000,
4219  0, 0, pbn_b0_1_115200 },
4220 
4221  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4222  0xA000, 0x3002,
4223  0, 0, pbn_b0_bt_2_115200 },
4224 
4225  { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4226  0xA000, 0x3004,
4227  0, 0, pbn_b0_bt_4_115200 },
4228  /* Intel CE4100 */
4229  { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4230  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231  pbn_ce4100_1_115200 },
4232 
4233  /*
4234  * Cronyx Omega PCI
4235  */
4236  { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4237  PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238  pbn_omegapci },
4239 
4240  /*
4241  * AgeStar as-prs2-009
4242  */
4243  { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4244  PCI_ANY_ID, PCI_ANY_ID,
4245  0, 0, pbn_b0_bt_2_115200 },
4246 
4247  /*
4248  * WCH CH353 series devices: The 2S1P is handled by parport_serial
4249  * so not listed here.
4250  */
4251  { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4252  PCI_ANY_ID, PCI_ANY_ID,
4253  0, 0, pbn_b0_bt_4_115200 },
4254 
4255  { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4256  PCI_ANY_ID, PCI_ANY_ID,
4257  0, 0, pbn_b0_bt_2_115200 },
4258 
4259  /*
4260  * These entries match devices with class COMMUNICATION_SERIAL,
4261  * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4262  */
4263  { PCI_ANY_ID, PCI_ANY_ID,
4264  PCI_ANY_ID, PCI_ANY_ID,
4265  PCI_CLASS_COMMUNICATION_SERIAL << 8,
4266  0xffff00, pbn_default },
4267  { PCI_ANY_ID, PCI_ANY_ID,
4268  PCI_ANY_ID, PCI_ANY_ID,
4269  PCI_CLASS_COMMUNICATION_MODEM << 8,
4270  0xffff00, pbn_default },
4271  { PCI_ANY_ID, PCI_ANY_ID,
4272  PCI_ANY_ID, PCI_ANY_ID,
4273  PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4274  0xffff00, pbn_default },
4275  { 0, }
4276 };
4277 
4278 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4279  pci_channel_state_t state)
4280 {
4281  struct serial_private *priv = pci_get_drvdata(dev);
4282 
4283  if (state == pci_channel_io_perm_failure)
4284  return PCI_ERS_RESULT_DISCONNECT;
4285 
4286  if (priv)
4287  pciserial_suspend_ports(priv);
4288 
4289  pci_disable_device(dev);
4290 
4291  return PCI_ERS_RESULT_NEED_RESET;
4292 }
4293 
4294 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4295 {
4296  int rc;
4297 
4298  rc = pci_enable_device(dev);
4299 
4300  if (rc)
4301  return PCI_ERS_RESULT_DISCONNECT;
4302 
4303  pci_restore_state(dev);
4304  pci_save_state(dev);
4305 
4306  return PCI_ERS_RESULT_RECOVERED;
4307 }
4308 
4309 static void serial8250_io_resume(struct pci_dev *dev)
4310 {
4311  struct serial_private *priv = pci_get_drvdata(dev);
4312 
4313  if (priv)
4314  pciserial_resume_ports(priv);
4315 }
4316 
4317 static const struct pci_error_handlers serial8250_err_handler = {
4318  .error_detected = serial8250_io_error_detected,
4319  .slot_reset = serial8250_io_slot_reset,
4320  .resume = serial8250_io_resume,
4321 };
4322 
4323 static struct pci_driver serial_pci_driver = {
4324  .name = "serial",
4325  .probe = pciserial_init_one,
4326  .remove = __devexit_p(pciserial_remove_one),
4327 #ifdef CONFIG_PM
4328  .suspend = pciserial_suspend_one,
4329  .resume = pciserial_resume_one,
4330 #endif
4331  .id_table = serial_pci_tbl,
4332  .err_handler = &serial8250_err_handler,
4333 };
4334 
4335 static int __init serial8250_pci_init(void)
4336 {
4337  return pci_register_driver(&serial_pci_driver);
4338 }
4339 
4340 static void __exit serial8250_pci_exit(void)
4341 {
4342  pci_unregister_driver(&serial_pci_driver);
4343 }
4344 
4345 module_init(serial8250_pci_init);
4346 module_exit(serial8250_pci_exit);
4347 
4348 MODULE_LICENSE("GPL");
4349 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4350 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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