#include "../comedidev.h"
#include <linux/delay.h>
#include <linux/interrupt.h>
#include "comedi_fc.h"
#include "8253.h"
#include "8255.h"

Data Structures
struct	pci230_board

struct	pci230_private

Macros
#define	PCI_VENDOR_ID_AMPLICON 0x14dc

#define	PCI_DEVICE_ID_PCI230 0x0000

#define	PCI_DEVICE_ID_PCI260 0x0006

#define	PCI_DEVICE_ID_INVALID 0xffff

#define	PCI230_IO1_SIZE 32 /* Size of I/O space 1 */

#define	PCI230_IO2_SIZE 16 /* Size of I/O space 2 */

#define	PCI230_PPI_X_BASE 0x00 /* User PPI (82C55) base */

#define	PCI230_PPI_X_A 0x00 /* User PPI (82C55) port A */

#define	PCI230_PPI_X_B 0x01 /* User PPI (82C55) port B */

#define	PCI230_PPI_X_C 0x02 /* User PPI (82C55) port C */

#define	PCI230_PPI_X_CMD 0x03 /* User PPI (82C55) control word */

#define	PCI230_Z2_CT_BASE 0x14 /* 82C54 counter/timer base */

#define	PCI230_Z2_CT0 0x14 /* 82C54 counter/timer 0 */

#define	PCI230_Z2_CT1 0x15 /* 82C54 counter/timer 1 */

#define	PCI230_Z2_CT2 0x16 /* 82C54 counter/timer 2 */

#define	PCI230_Z2_CTC 0x17 /* 82C54 counter/timer control word */

#define	PCI230_ZCLK_SCE 0x1A /* Group Z Clock Configuration */

#define	PCI230_ZGAT_SCE 0x1D /* Group Z Gate Configuration */

#define	PCI230_INT_SCE 0x1E /* Interrupt source mask (w) */

#define	PCI230_INT_STAT 0x1E /* Interrupt status (r) */

#define	PCI230_DACCON 0x00 /* DAC control */

#define	PCI230_DACOUT1 0x02 /* DAC channel 0 (w) */

#define	PCI230_DACOUT2 0x04 /* DAC channel 1 (w) (not FIFO mode) */

#define	PCI230_ADCDATA 0x08 /* ADC data (r) */

#define	PCI230_ADCSWTRIG 0x08 /* ADC software trigger (w) */

#define	PCI230_ADCCON 0x0A /* ADC control */

#define	PCI230_ADCEN 0x0C /* ADC channel enable bits */

#define	PCI230_ADCG 0x0E /* ADC gain control bits */

#define	PCI230P_ADCTRIG 0x10 /* ADC start acquisition trigger */

#define	PCI230P_ADCTH 0x12 /* ADC analog trigger threshold */

#define	PCI230P_ADCFFTH 0x14 /* ADC FIFO interrupt threshold */

#define	PCI230P_ADCFFLEV 0x16 /* ADC FIFO level (r) */

#define	PCI230P_ADCPTSC 0x18 /* ADC pre-trigger sample count (r) */

#define	PCI230P_ADCHYST 0x1A /* ADC analog trigger hysteresys */

#define	PCI230P_EXTFUNC 0x1C /* Extended functions */

#define	PCI230P_HWVER 0x1E /* Hardware version (r) */

#define	PCI230P2_DACDATA 0x02 /* DAC data (FIFO mode) (w) */

#define	PCI230P2_DACSWTRIG 0x02 /* DAC soft trigger (FIFO mode) (r) */

#define	PCI230P2_DACEN 0x06 /* DAC channel enable (FIFO mode) */

#define	PCI230_DAC_SETTLE 5 /* Analogue output settling time in µs */

#define	PCI230_ADC_SETTLE 1 /* Analogue input settling time in µs */

#define	PCI230_MUX_SETTLE 10 /* ADC MUX settling time in µS */

#define	PCI230_DAC_OR_UNI (0<<0) /* Output range unipolar */

#define	PCI230_DAC_OR_BIP (1<<0) /* Output range bipolar */

#define	PCI230_DAC_OR_MASK (1<<0)

#define	PCI230P2_DAC_FIFO_EN (1<<8) /* FIFO enable */

#define	PCI230P2_DAC_TRIG_NONE (0<<2) /* No trigger */

#define	PCI230P2_DAC_TRIG_SW (1<<2) /* Software trigger trigger */

#define	PCI230P2_DAC_TRIG_EXTP (2<<2) /* EXTTRIG +ve edge trigger */

#define	PCI230P2_DAC_TRIG_EXTN (3<<2) /* EXTTRIG -ve edge trigger */

#define	PCI230P2_DAC_TRIG_Z2CT0 (4<<2) /* CT0-OUT +ve edge trigger */

#define	PCI230P2_DAC_TRIG_Z2CT1 (5<<2) /* CT1-OUT +ve edge trigger */

#define	PCI230P2_DAC_TRIG_Z2CT2 (6<<2) /* CT2-OUT +ve edge trigger */

#define	PCI230P2_DAC_TRIG_MASK (7<<2)

#define	PCI230P2_DAC_FIFO_WRAP (1<<7) /* FIFO wraparound mode */

#define	PCI230P2_DAC_INT_FIFO_EMPTY (0<<9) /* FIFO interrupt empty */

#define	PCI230P2_DAC_INT_FIFO_NEMPTY (1<<9)

#define	PCI230P2_DAC_INT_FIFO_NHALF (2<<9) /* FIFO intr not half full */

#define	PCI230P2_DAC_INT_FIFO_HALF (3<<9)

#define	PCI230P2_DAC_INT_FIFO_NFULL (4<<9) /* FIFO interrupt not full */

#define	PCI230P2_DAC_INT_FIFO_FULL (5<<9)

#define	PCI230P2_DAC_INT_FIFO_MASK (7<<9)

#define	PCI230_DAC_BUSY (1<<1) /* DAC busy. */

#define	PCI230P2_DAC_FIFO_UNDERRUN_LATCHED (1<<5) /* Underrun error */

#define	PCI230P2_DAC_FIFO_EMPTY (1<<13) /* FIFO empty */

#define	PCI230P2_DAC_FIFO_FULL (1<<14) /* FIFO full */

#define	PCI230P2_DAC_FIFO_HALF (1<<15) /* FIFO half full */

#define	PCI230P2_DAC_FIFO_UNDERRUN_CLEAR (1<<5) /* Clear underrun */

#define	PCI230P2_DAC_FIFO_RESET (1<<12) /* FIFO reset */

#define	PCI230P2_DAC_FIFOLEVEL_HALF 512

#define	PCI230P2_DAC_FIFOLEVEL_FULL 1024

#define	PCI230P2_DAC_FIFOROOM_EMPTY PCI230P2_DAC_FIFOLEVEL_FULL

#define	PCI230P2_DAC_FIFOROOM_ONETOHALF (PCI230P2_DAC_FIFOLEVEL_FULL - PCI230P2_DAC_FIFOLEVEL_HALF)

#define	PCI230P2_DAC_FIFOROOM_HALFTOFULL 1

#define	PCI230P2_DAC_FIFOROOM_FULL 0

#define	PCI230_ADC_TRIG_NONE (0<<0) /* No trigger */

#define	PCI230_ADC_TRIG_SW (1<<0) /* Software trigger trigger */

#define	PCI230_ADC_TRIG_EXTP (2<<0) /* EXTTRIG +ve edge trigger */

#define	PCI230_ADC_TRIG_EXTN (3<<0) /* EXTTRIG -ve edge trigger */

#define	PCI230_ADC_TRIG_Z2CT0 (4<<0) /* CT0-OUT +ve edge trigger */

#define	PCI230_ADC_TRIG_Z2CT1 (5<<0) /* CT1-OUT +ve edge trigger */

#define	PCI230_ADC_TRIG_Z2CT2 (6<<0) /* CT2-OUT +ve edge trigger */

#define	PCI230_ADC_TRIG_MASK (7<<0)

#define	PCI230_ADC_IR_UNI (0<<3) /* Input range unipolar */

#define	PCI230_ADC_IR_BIP (1<<3) /* Input range bipolar */

#define	PCI230_ADC_IR_MASK (1<<3)

#define	PCI230_ADC_IM_SE (0<<4) /* Input mode single ended */

#define	PCI230_ADC_IM_DIF (1<<4) /* Input mode differential */

#define	PCI230_ADC_IM_MASK (1<<4)

#define	PCI230_ADC_FIFO_EN (1<<8) /* FIFO enable */

#define	PCI230_ADC_INT_FIFO_EMPTY (0<<9)

#define	PCI230_ADC_INT_FIFO_NEMPTY (1<<9) /* FIFO interrupt not empty */

#define	PCI230_ADC_INT_FIFO_NHALF (2<<9)

#define	PCI230_ADC_INT_FIFO_HALF (3<<9) /* FIFO interrupt half full */

#define	PCI230_ADC_INT_FIFO_NFULL (4<<9)

#define	PCI230_ADC_INT_FIFO_FULL (5<<9) /* FIFO interrupt full */

#define	PCI230P_ADC_INT_FIFO_THRESH (7<<9) /* FIFO interrupt threshold */

#define	PCI230_ADC_INT_FIFO_MASK (7<<9)

#define	PCI230_ADC_FIFO_RESET (1<<12) /* FIFO reset */

#define	PCI230_ADC_GLOB_RESET (1<<13) /* Global reset */

#define	PCI230_ADC_BUSY (1<<15) /* ADC busy */

#define	PCI230_ADC_FIFO_EMPTY (1<<12) /* FIFO empty */

#define	PCI230_ADC_FIFO_FULL (1<<13) /* FIFO full */

#define	PCI230_ADC_FIFO_HALF (1<<14) /* FIFO half full */

#define	PCI230_ADC_FIFO_FULL_LATCHED (1<<5) /* Indicates overrun occurred */

#define	PCI230_ADC_FIFOLEVEL_HALFFULL 2049 /* Value for FIFO half full */

#define	PCI230_ADC_FIFOLEVEL_FULL 4096 /* FIFO size */

#define	PCI230_ADC_CONV 0xffff

#define	PCI230P_EXTFUNC_GAT_EXTTRIG (1<<0)

#define	PCI230P2_EXTFUNC_DACFIFO (1<<1)

#define	CLK_CLK 0 /* reserved (channel-specific clock) */

#define	CLK_10MHZ 1 /* internal 10 MHz clock */

#define	CLK_1MHZ 2 /* internal 1 MHz clock */

#define	CLK_100KHZ 3 /* internal 100 kHz clock */

#define	CLK_10KHZ 4 /* internal 10 kHz clock */

#define	CLK_1KHZ 5 /* internal 1 kHz clock */

#define	CLK_OUTNM1 6 /* output of channel-1 modulo total */

#define	CLK_EXT 7 /* external clock */

#define	CLK_CONFIG(chan, src) ((((chan) & 3) << 3) \| ((src) & 7))

#define	TIMEBASE_10MHZ 100

#define	TIMEBASE_1MHZ 1000

#define	TIMEBASE_100KHZ 10000

#define	TIMEBASE_10KHZ 100000

#define	TIMEBASE_1KHZ 1000000

#define	GAT_VCC 0 /* VCC (i.e. enabled) */

#define	GAT_GND 1 /* GND (i.e. disabled) */

#define	GAT_EXT 2 /* external gate input (PPCn on PCI230) */

#define	GAT_NOUTNM2 3 /* inverted output of channel-2 modulo total */

#define	GAT_CONFIG(chan, src) ((((chan) & 3) << 3) \| ((src) & 7))

#define	PCI230_INT_DISABLE 0

#define	PCI230_INT_PPI_C0 (1<<0)

#define	PCI230_INT_PPI_C3 (1<<1)

#define	PCI230_INT_ADC (1<<2)

#define	PCI230_INT_ZCLK_CT1 (1<<5)

#define	PCI230P2_INT_DAC (1<<4)

#define	PCI230_TEST_BIT(val, n) ((val>>n)&1)

#define	COMBINE(old, new, mask) (((old) & ~(mask)) \| ((new) & (mask)))

#define	THISCPU smp_processor_id()

#define	AI_CMD_STARTED 0

#define	AO_CMD_STARTED 1

#define	TIMEOUT 100

#define	MAX_SPEED_AO 8000 /* 8000 ns => 125 kHz */

#define	MIN_SPEED_AO 4294967295u /* 4294967295ns = 4.29s */

#define	MAX_SPEED_AI_SE 3200 /* PCI230 SE: 3200 ns => 312.5 kHz */

#define	MAX_SPEED_AI_DIFF 8000 /* PCI230 DIFF: 8000 ns => 125 kHz */

#define	MAX_SPEED_AI_PLUS 4000 /* PCI230+: 4000 ns => 250 kHz */

#define	MIN_SPEED_AI 4294967295u /* 4294967295ns = 4.29s */

Enumerations
enum	{ RES_Z2CT0, RES_Z2CT1, RES_Z2CT2, NUM_RESOURCES }

enum	{ OWNER_NONE, OWNER_AICMD, OWNER_AOCMD }

Functions
	MODULE_DEVICE_TABLE (pci, amplc_pci230_pci_table)

	module_comedi_pci_driver (amplc_pci230_driver, amplc_pci230_pci_driver)

	MODULE_AUTHOR ("Comedi http://www.comedi.org")

	MODULE_DESCRIPTION ("Comedi low-level driver")

	MODULE_LICENSE ("GPL")

Macro Definition Documentation

#define AI_CMD_STARTED 0

Definition at line 438 of file amplc_pci230.c.

#define AO_CMD_STARTED 1

Definition at line 439 of file amplc_pci230.c.

#define CLK_100KHZ 3 /* internal 100 kHz clock */

Definition at line 365 of file amplc_pci230.c.

#define CLK_10KHZ 4 /* internal 10 kHz clock */

Definition at line 366 of file amplc_pci230.c.

#define CLK_10MHZ 1 /* internal 10 MHz clock */

Definition at line 363 of file amplc_pci230.c.

#define CLK_1KHZ 5 /* internal 1 kHz clock */

Definition at line 367 of file amplc_pci230.c.

#define CLK_1MHZ 2 /* internal 1 MHz clock */

Definition at line 364 of file amplc_pci230.c.

#define CLK_CLK 0 /* reserved (channel-specific clock) */

Definition at line 362 of file amplc_pci230.c.

#define CLK_CONFIG	(	chan,
		src
	)	((((chan) & 3) << 3) \| ((src) & 7))

Definition at line 371 of file amplc_pci230.c.

#define CLK_EXT 7 /* external clock */

Definition at line 369 of file amplc_pci230.c.

#define CLK_OUTNM1 6 /* output of channel-1 modulo total */

Definition at line 368 of file amplc_pci230.c.

#define COMBINE	(	old,
		new,
		mask
	)	(((old) & ~(mask)) \| ((new) & (mask)))

Definition at line 432 of file amplc_pci230.c.

#define GAT_CONFIG	(	chan,
		src
	)	((((chan) & 3) << 3) \| ((src) & 7))

Definition at line 387 of file amplc_pci230.c.

#define GAT_EXT 2 /* external gate input (PPCn on PCI230) */

Definition at line 384 of file amplc_pci230.c.

#define GAT_GND 1 /* GND (i.e. disabled) */

Definition at line 383 of file amplc_pci230.c.

#define GAT_NOUTNM2 3 /* inverted output of channel-2 modulo total */

Definition at line 385 of file amplc_pci230.c.

#define GAT_VCC 0 /* VCC (i.e. enabled) */

Definition at line 382 of file amplc_pci230.c.

#define MAX_SPEED_AI_DIFF 8000 /* PCI230 DIFF: 8000 ns => 125 kHz */

#define MAX_SPEED_AI_PLUS 4000 /* PCI230+: 4000 ns => 250 kHz */

#define MAX_SPEED_AI_SE 3200 /* PCI230 SE: 3200 ns => 312.5 kHz */

#define MAX_SPEED_AO 8000 /* 8000 ns => 125 kHz */

#define MIN_SPEED_AI 4294967295u /* 4294967295ns = 4.29s */

#define MIN_SPEED_AO 4294967295u /* 4294967295ns = 4.29s */

#define PCI230_ADC_BUSY (1<<15) /* ADC busy */

Definition at line 338 of file amplc_pci230.c.

#define PCI230_ADC_CONV 0xffff

Definition at line 350 of file amplc_pci230.c.

#define PCI230_ADC_FIFO_EMPTY (1<<12) /* FIFO empty */

Definition at line 339 of file amplc_pci230.c.

#define PCI230_ADC_FIFO_EN (1<<8) /* FIFO enable */

Definition at line 323 of file amplc_pci230.c.

#define PCI230_ADC_FIFO_FULL (1<<13) /* FIFO full */

Definition at line 340 of file amplc_pci230.c.

#define PCI230_ADC_FIFO_FULL_LATCHED (1<<5) /* Indicates overrun occurred */

Definition at line 342 of file amplc_pci230.c.

#define PCI230_ADC_FIFO_HALF (1<<14) /* FIFO half full */

Definition at line 341 of file amplc_pci230.c.

#define PCI230_ADC_FIFO_RESET (1<<12) /* FIFO reset */

Definition at line 334 of file amplc_pci230.c.

#define PCI230_ADC_FIFOLEVEL_FULL 4096 /* FIFO size */

Definition at line 346 of file amplc_pci230.c.

#define PCI230_ADC_FIFOLEVEL_HALFFULL 2049 /* Value for FIFO half full */

Definition at line 345 of file amplc_pci230.c.

#define PCI230_ADC_GLOB_RESET (1<<13) /* Global reset */

Definition at line 335 of file amplc_pci230.c.

#define PCI230_ADC_IM_DIF (1<<4) /* Input mode differential */

Definition at line 321 of file amplc_pci230.c.

#define PCI230_ADC_IM_MASK (1<<4)

Definition at line 322 of file amplc_pci230.c.

#define PCI230_ADC_IM_SE (0<<4) /* Input mode single ended */

Definition at line 320 of file amplc_pci230.c.

#define PCI230_ADC_INT_FIFO_EMPTY (0<<9)

Definition at line 324 of file amplc_pci230.c.

#define PCI230_ADC_INT_FIFO_FULL (5<<9) /* FIFO interrupt full */

Definition at line 329 of file amplc_pci230.c.

#define PCI230_ADC_INT_FIFO_HALF (3<<9) /* FIFO interrupt half full */

Definition at line 327 of file amplc_pci230.c.

#define PCI230_ADC_INT_FIFO_MASK (7<<9)

Definition at line 331 of file amplc_pci230.c.

#define PCI230_ADC_INT_FIFO_NEMPTY (1<<9) /* FIFO interrupt not empty */

Definition at line 325 of file amplc_pci230.c.

#define PCI230_ADC_INT_FIFO_NFULL (4<<9)

Definition at line 328 of file amplc_pci230.c.

#define PCI230_ADC_INT_FIFO_NHALF (2<<9)

Definition at line 326 of file amplc_pci230.c.

#define PCI230_ADC_IR_BIP (1<<3) /* Input range bipolar */

Definition at line 318 of file amplc_pci230.c.

#define PCI230_ADC_IR_MASK (1<<3)

Definition at line 319 of file amplc_pci230.c.

#define PCI230_ADC_IR_UNI (0<<3) /* Input range unipolar */

Definition at line 317 of file amplc_pci230.c.

#define PCI230_ADC_SETTLE 1 /* Analogue input settling time in µs */

Definition at line 251 of file amplc_pci230.c.

#define PCI230_ADC_TRIG_EXTN (3<<0) /* EXTTRIG -ve edge trigger */

Definition at line 312 of file amplc_pci230.c.

#define PCI230_ADC_TRIG_EXTP (2<<0) /* EXTTRIG +ve edge trigger */

Definition at line 311 of file amplc_pci230.c.

#define PCI230_ADC_TRIG_MASK (7<<0)

Definition at line 316 of file amplc_pci230.c.

#define PCI230_ADC_TRIG_NONE (0<<0) /* No trigger */

Definition at line 309 of file amplc_pci230.c.

#define PCI230_ADC_TRIG_SW (1<<0) /* Software trigger trigger */

Definition at line 310 of file amplc_pci230.c.

#define PCI230_ADC_TRIG_Z2CT0 (4<<0) /* CT0-OUT +ve edge trigger */

Definition at line 313 of file amplc_pci230.c.

#define PCI230_ADC_TRIG_Z2CT1 (5<<0) /* CT1-OUT +ve edge trigger */

Definition at line 314 of file amplc_pci230.c.

#define PCI230_ADC_TRIG_Z2CT2 (6<<0) /* CT2-OUT +ve edge trigger */

Definition at line 315 of file amplc_pci230.c.

#define PCI230_ADCCON 0x0A /* ADC control */

Definition at line 231 of file amplc_pci230.c.

#define PCI230_ADCDATA 0x08 /* ADC data (r) */

Definition at line 229 of file amplc_pci230.c.

#define PCI230_ADCEN 0x0C /* ADC channel enable bits */

Definition at line 232 of file amplc_pci230.c.

#define PCI230_ADCG 0x0E /* ADC gain control bits */

Definition at line 233 of file amplc_pci230.c.

#define PCI230_ADCSWTRIG 0x08 /* ADC software trigger (w) */

Definition at line 230 of file amplc_pci230.c.

#define PCI230_DAC_BUSY (1<<1) /* DAC busy. */

Definition at line 284 of file amplc_pci230.c.

#define PCI230_DAC_OR_BIP (1<<0) /* Output range bipolar */

Definition at line 259 of file amplc_pci230.c.

#define PCI230_DAC_OR_MASK (1<<0)

Definition at line 260 of file amplc_pci230.c.

#define PCI230_DAC_OR_UNI (0<<0) /* Output range unipolar */

Definition at line 258 of file amplc_pci230.c.

#define PCI230_DAC_SETTLE 5 /* Analogue output settling time in µs */

Definition at line 249 of file amplc_pci230.c.

#define PCI230_DACCON 0x00 /* DAC control */

Definition at line 226 of file amplc_pci230.c.

#define PCI230_DACOUT1 0x02 /* DAC channel 0 (w) */

Definition at line 227 of file amplc_pci230.c.

#define PCI230_DACOUT2 0x04 /* DAC channel 1 (w) (not FIFO mode) */

Definition at line 228 of file amplc_pci230.c.

#define PCI230_INT_ADC (1<<2)

Definition at line 405 of file amplc_pci230.c.

#define PCI230_INT_DISABLE 0

Definition at line 402 of file amplc_pci230.c.

#define PCI230_INT_PPI_C0 (1<<0)

Definition at line 403 of file amplc_pci230.c.

#define PCI230_INT_PPI_C3 (1<<1)

Definition at line 404 of file amplc_pci230.c.

#define PCI230_INT_SCE 0x1E /* Interrupt source mask (w) */

Definition at line 222 of file amplc_pci230.c.

#define PCI230_INT_STAT 0x1E /* Interrupt status (r) */

Definition at line 223 of file amplc_pci230.c.

#define PCI230_INT_ZCLK_CT1 (1<<5)

Definition at line 406 of file amplc_pci230.c.

#define PCI230_IO1_SIZE 32 /* Size of I/O space 1 */

Definition at line 206 of file amplc_pci230.c.

#define PCI230_IO2_SIZE 16 /* Size of I/O space 2 */

Definition at line 207 of file amplc_pci230.c.

#define PCI230_MUX_SETTLE 10 /* ADC MUX settling time in µS */

Definition at line 254 of file amplc_pci230.c.

#define PCI230_PPI_X_A 0x00 /* User PPI (82C55) port A */

Definition at line 211 of file amplc_pci230.c.

#define PCI230_PPI_X_B 0x01 /* User PPI (82C55) port B */

Definition at line 212 of file amplc_pci230.c.

#define PCI230_PPI_X_BASE 0x00 /* User PPI (82C55) base */

Definition at line 210 of file amplc_pci230.c.

#define PCI230_PPI_X_C 0x02 /* User PPI (82C55) port C */

Definition at line 213 of file amplc_pci230.c.

#define PCI230_PPI_X_CMD 0x03 /* User PPI (82C55) control word */

Definition at line 214 of file amplc_pci230.c.

#define PCI230_TEST_BIT	(	val,
		n
	)	((val>>n)&1)

Definition at line 410 of file amplc_pci230.c.

#define PCI230_Z2_CT0 0x14 /* 82C54 counter/timer 0 */

Definition at line 216 of file amplc_pci230.c.

#define PCI230_Z2_CT1 0x15 /* 82C54 counter/timer 1 */

Definition at line 217 of file amplc_pci230.c.

#define PCI230_Z2_CT2 0x16 /* 82C54 counter/timer 2 */

Definition at line 218 of file amplc_pci230.c.

#define PCI230_Z2_CT_BASE 0x14 /* 82C54 counter/timer base */

Definition at line 215 of file amplc_pci230.c.

#define PCI230_Z2_CTC 0x17 /* 82C54 counter/timer control word */

Definition at line 219 of file amplc_pci230.c.

#define PCI230_ZCLK_SCE 0x1A /* Group Z Clock Configuration */

Definition at line 220 of file amplc_pci230.c.

#define PCI230_ZGAT_SCE 0x1D /* Group Z Gate Configuration */

Definition at line 221 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFO_EMPTY (1<<13) /* FIFO empty */

Definition at line 288 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFO_EN (1<<8) /* FIFO enable */

Definition at line 263 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFO_FULL (1<<14) /* FIFO full */

Definition at line 289 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFO_HALF (1<<15) /* FIFO half full */

Definition at line 290 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFO_RESET (1<<12) /* FIFO reset */

Definition at line 296 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFO_UNDERRUN_CLEAR (1<<5) /* Clear underrun */

Definition at line 295 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFO_UNDERRUN_LATCHED (1<<5) /* Underrun error */

Definition at line 287 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFO_WRAP (1<<7) /* FIFO wraparound mode */

Definition at line 274 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFOLEVEL_FULL 1024

Definition at line 300 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFOLEVEL_HALF 512

Definition at line 299 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFOROOM_EMPTY PCI230P2_DAC_FIFOLEVEL_FULL

Definition at line 302 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFOROOM_FULL 0

Definition at line 306 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFOROOM_HALFTOFULL 1

Definition at line 305 of file amplc_pci230.c.

#define PCI230P2_DAC_FIFOROOM_ONETOHALF (PCI230P2_DAC_FIFOLEVEL_FULL - PCI230P2_DAC_FIFOLEVEL_HALF)

Definition at line 303 of file amplc_pci230.c.

#define PCI230P2_DAC_INT_FIFO_EMPTY (0<<9) /* FIFO interrupt empty */

Definition at line 275 of file amplc_pci230.c.

#define PCI230P2_DAC_INT_FIFO_FULL (5<<9)

Definition at line 280 of file amplc_pci230.c.

#define PCI230P2_DAC_INT_FIFO_HALF (3<<9)

Definition at line 278 of file amplc_pci230.c.

#define PCI230P2_DAC_INT_FIFO_MASK (7<<9)

Definition at line 281 of file amplc_pci230.c.

#define PCI230P2_DAC_INT_FIFO_NEMPTY (1<<9)

Definition at line 276 of file amplc_pci230.c.

#define PCI230P2_DAC_INT_FIFO_NFULL (4<<9) /* FIFO interrupt not full */

Definition at line 279 of file amplc_pci230.c.

#define PCI230P2_DAC_INT_FIFO_NHALF (2<<9) /* FIFO intr not half full */

Definition at line 277 of file amplc_pci230.c.

#define PCI230P2_DAC_TRIG_EXTN (3<<2) /* EXTTRIG -ve edge trigger */

Definition at line 269 of file amplc_pci230.c.

#define PCI230P2_DAC_TRIG_EXTP (2<<2) /* EXTTRIG +ve edge trigger */

Definition at line 268 of file amplc_pci230.c.

#define PCI230P2_DAC_TRIG_MASK (7<<2)

Definition at line 273 of file amplc_pci230.c.

#define PCI230P2_DAC_TRIG_NONE (0<<2) /* No trigger */

Definition at line 266 of file amplc_pci230.c.

#define PCI230P2_DAC_TRIG_SW (1<<2) /* Software trigger trigger */

Definition at line 267 of file amplc_pci230.c.

#define PCI230P2_DAC_TRIG_Z2CT0 (4<<2) /* CT0-OUT +ve edge trigger */

Definition at line 270 of file amplc_pci230.c.

#define PCI230P2_DAC_TRIG_Z2CT1 (5<<2) /* CT1-OUT +ve edge trigger */

Definition at line 271 of file amplc_pci230.c.

#define PCI230P2_DAC_TRIG_Z2CT2 (6<<2) /* CT2-OUT +ve edge trigger */

Definition at line 272 of file amplc_pci230.c.

#define PCI230P2_DACDATA 0x02 /* DAC data (FIFO mode) (w) */

Definition at line 244 of file amplc_pci230.c.

#define PCI230P2_DACEN 0x06 /* DAC channel enable (FIFO mode) */

Definition at line 246 of file amplc_pci230.c.

#define PCI230P2_DACSWTRIG 0x02 /* DAC soft trigger (FIFO mode) (r) */

Definition at line 245 of file amplc_pci230.c.

#define PCI230P2_EXTFUNC_DACFIFO (1<<1)

Definition at line 356 of file amplc_pci230.c.

#define PCI230P2_INT_DAC (1<<4)

Definition at line 408 of file amplc_pci230.c.

#define PCI230P_ADC_INT_FIFO_THRESH (7<<9) /* FIFO interrupt threshold */

Definition at line 330 of file amplc_pci230.c.

#define PCI230P_ADCFFLEV 0x16 /* ADC FIFO level (r) */

Definition at line 238 of file amplc_pci230.c.

#define PCI230P_ADCFFTH 0x14 /* ADC FIFO interrupt threshold */

Definition at line 237 of file amplc_pci230.c.

#define PCI230P_ADCHYST 0x1A /* ADC analog trigger hysteresys */

Definition at line 240 of file amplc_pci230.c.

#define PCI230P_ADCPTSC 0x18 /* ADC pre-trigger sample count (r) */

Definition at line 239 of file amplc_pci230.c.

#define PCI230P_ADCTH 0x12 /* ADC analog trigger threshold */

Definition at line 236 of file amplc_pci230.c.

#define PCI230P_ADCTRIG 0x10 /* ADC start acquisition trigger */

Definition at line 235 of file amplc_pci230.c.

#define PCI230P_EXTFUNC 0x1C /* Extended functions */

Definition at line 241 of file amplc_pci230.c.

#define PCI230P_EXTFUNC_GAT_EXTTRIG (1<<0)

Definition at line 353 of file amplc_pci230.c.

#define PCI230P_HWVER 0x1E /* Hardware version (r) */

Definition at line 242 of file amplc_pci230.c.

#define PCI_DEVICE_ID_INVALID 0xffff

Definition at line 204 of file amplc_pci230.c.

#define PCI_DEVICE_ID_PCI230 0x0000

Definition at line 202 of file amplc_pci230.c.

#define PCI_DEVICE_ID_PCI260 0x0006

Definition at line 203 of file amplc_pci230.c.

#define PCI_VENDOR_ID_AMPLICON 0x14dc

Definition at line 201 of file amplc_pci230.c.

#define THISCPU smp_processor_id()

Definition at line 435 of file amplc_pci230.c.

#define TIMEBASE_100KHZ 10000

Definition at line 375 of file amplc_pci230.c.

#define TIMEBASE_10KHZ 100000

Definition at line 376 of file amplc_pci230.c.

#define TIMEBASE_10MHZ 100

Definition at line 373 of file amplc_pci230.c.

#define TIMEBASE_1KHZ 1000000

Definition at line 377 of file amplc_pci230.c.

#define TIMEBASE_1MHZ 1000

Definition at line 374 of file amplc_pci230.c.

#define TIMEOUT 100

Enumeration Type Documentation

anonymous enum

Enumerator:

RES_Z2CT0
RES_Z2CT1
RES_Z2CT2
NUM_RESOURCES

Definition at line 414 of file amplc_pci230.c.

anonymous enum

Enumerator:

OWNER_NONE
OWNER_AICMD
OWNER_AOCMD

Definition at line 421 of file amplc_pci230.c.

Function Documentation

MODULE_AUTHOR ( "Comedi http://www.comedi.org" )

module_comedi_pci_driver	(	amplc_pci230_driver	,
		amplc_pci230_pci_driver
	)

MODULE_DESCRIPTION ( "Comedi low-level driver" )

MODULE_DEVICE_TABLE	(	pci	,
		amplc_pci230_pci_table
	)

MODULE_LICENSE ( "GPL" )

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation