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setup.c
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1 /* setup.c: FRV specific setup
2  *
3  * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
4  * Written by David Howells ([email protected])
5  * - Derived from arch/m68k/kernel/setup.c
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; either version
10  * 2 of the License, or (at your option) any later version.
11  */
12 
13 #include <generated/utsrelease.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/fs.h>
19 #include <linux/mm.h>
20 #include <linux/fb.h>
21 #include <linux/console.h>
22 #include <linux/genhd.h>
23 #include <linux/errno.h>
24 #include <linux/string.h>
25 #include <linux/major.h>
26 #include <linux/bootmem.h>
27 #include <linux/highmem.h>
28 #include <linux/seq_file.h>
29 #include <linux/serial.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial_reg.h>
32 #include <linux/serial_8250.h>
33 
34 #include <asm/setup.h>
35 #include <asm/irq.h>
36 #include <asm/sections.h>
37 #include <asm/pgalloc.h>
38 #include <asm/busctl-regs.h>
39 #include <asm/serial-regs.h>
40 #include <asm/timer-regs.h>
41 #include <asm/irc-regs.h>
42 #include <asm/spr-regs.h>
43 #include <asm/mb-regs.h>
44 #include <asm/mb93493-regs.h>
45 #include <asm/gdb-stub.h>
46 #include <asm/io.h>
47 
48 #ifdef CONFIG_BLK_DEV_INITRD
49 #include <asm/pgtable.h>
50 #endif
51 
52 #include "local.h"
53 
54 #ifdef CONFIG_MB93090_MB00
55 static void __init mb93090_display(void);
56 #endif
57 #ifdef CONFIG_MMU
58 static void __init setup_linux_memory(void);
59 #else
60 static void __init setup_uclinux_memory(void);
61 #endif
62 
63 #ifdef CONFIG_MB93090_MB00
64 static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
65 static char __initdata mb93090_version[] = UTS_RELEASE;
66 
67 int __nongprelbss mb93090_mb00_detected;
68 #endif
69 
70 const char __frv_unknown_system[] = "unknown";
71 const char __frv_mb93091_cb10[] = "mb93091-cb10";
72 const char __frv_mb93091_cb11[] = "mb93091-cb11";
73 const char __frv_mb93091_cb30[] = "mb93091-cb30";
74 const char __frv_mb93091_cb41[] = "mb93091-cb41";
75 const char __frv_mb93091_cb60[] = "mb93091-cb60";
76 const char __frv_mb93091_cb70[] = "mb93091-cb70";
77 const char __frv_mb93091_cb451[] = "mb93091-cb451";
78 const char __frv_mb93090_mb00[] = "mb93090-mb00";
79 
80 const char __frv_mb93493[] = "mb93493";
81 
82 const char __frv_mb93093[] = "mb93093";
83 
84 static const char *__nongprelbss cpu_series;
85 static const char *__nongprelbss cpu_core;
86 static const char *__nongprelbss cpu_silicon;
87 static const char *__nongprelbss cpu_mmu;
88 static const char *__nongprelbss cpu_system;
89 static const char *__nongprelbss cpu_board1;
90 static const char *__nongprelbss cpu_board2;
91 
92 static unsigned long __nongprelbss cpu_psr_all;
93 static unsigned long __nongprelbss cpu_hsr0_all;
94 
95 unsigned long __nongprelbss pdm_suspend_mode;
96 
97 unsigned long __nongprelbss rom_length;
98 unsigned long __nongprelbss memory_start;
99 unsigned long __nongprelbss memory_end;
100 
101 unsigned long __nongprelbss dma_coherent_mem_start;
102 unsigned long __nongprelbss dma_coherent_mem_end;
103 
104 unsigned long __initdata __sdram_old_base;
105 unsigned long __initdata num_mappedpages;
106 
107 struct cpuinfo_frv __nongprelbss boot_cpu_data;
108 
109 char __initdata command_line[COMMAND_LINE_SIZE];
110 char __initdata redboot_command_line[COMMAND_LINE_SIZE];
111 
112 #ifdef CONFIG_PM
113 #define __pminit
114 #define __pminitdata
115 #define __pminitconst
116 #else
117 #define __pminit __init
118 #define __pminitdata __initdata
119 #define __pminitconst __initconst
120 #endif
121 
122 struct clock_cmode {
123  uint8_t xbus, sdram, corebus, core, dsu;
124 };
125 
126 #define _frac(N,D) ((N)<<4 | (D))
127 #define _x0_16 _frac(1,6)
128 #define _x0_25 _frac(1,4)
129 #define _x0_33 _frac(1,3)
130 #define _x0_375 _frac(3,8)
131 #define _x0_5 _frac(1,2)
132 #define _x0_66 _frac(2,3)
133 #define _x0_75 _frac(3,4)
134 #define _x1 _frac(1,1)
135 #define _x1_5 _frac(3,2)
136 #define _x2 _frac(2,1)
137 #define _x3 _frac(3,1)
138 #define _x4 _frac(4,1)
139 #define _x4_5 _frac(9,2)
140 #define _x6 _frac(6,1)
141 #define _x8 _frac(8,1)
142 #define _x9 _frac(9,1)
143 
144 int __nongprelbss clock_p0_current;
145 int __nongprelbss clock_cm_current;
146 int __nongprelbss clock_cmode_current;
147 #ifdef CONFIG_PM
148 int __nongprelbss clock_cmodes_permitted;
149 unsigned long __nongprelbss clock_bits_settable;
150 #endif
151 
152 static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
153 
154 static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
155  [4] = { _x1, _x1, _x2, _x2, _x0_25 },
156  [5] = { _x1, _x2, _x4, _x4, _x0_5 },
157  [8] = { _x1, _x1, _x1, _x2, _x0_25 },
158  [9] = { _x1, _x2, _x2, _x4, _x0_5 },
159  [11] = { _x1, _x4, _x4, _x8, _x1 },
160  [12] = { _x1, _x1, _x2, _x4, _x0_5 },
161  [13] = { _x1, _x2, _x4, _x8, _x1 },
162 };
163 
164 static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
165  [0] = { _x1, _x1, _x1, _x1, _x0_5 },
166  [1] = { _x1, _x1, _x1, _x3, _x0_25 },
167  [2] = { _x1, _x1, _x2, _x6, _x0_5 },
168  [3] = { _x1, _x2, _x2, _x6, _x0_5 },
169  [4] = { _x1, _x1, _x2, _x2, _x0_16 },
170  [8] = { _x1, _x1, _x1, _x2, _x0_16 },
171  [9] = { _x1, _x2, _x2, _x4, _x0_33 },
172  [12] = { _x1, _x1, _x2, _x4, _x0_33 },
173  [14] = { _x1, _x3, _x3, _x9, _x0_75 },
174  [15] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
175 
176 #define CLOCK_CMODES_PERMITTED_FR405 0xd31f
177 };
178 
179 static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
180  [0] = { _x1, _x2, _x2, _x4, _x0_33 },
181  [1] = { _x1, _x3, _x3, _x6, _x0_5 },
182  [2] = { _x1, _x2, _x4, _x8, _x0_66 },
183  [3] = { _x1, _x1_5, _x3, _x6, _x0_5 },
184  [4] = { _x1, _x3, _x3, _x9, _x0_75 },
185  [5] = { _x1, _x2, _x2, _x6, _x0_5 },
186  [6] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
187 };
188 
189 static const struct clock_cmode __pminitconst *clock_cmodes;
190 static int __pminitdata clock_doubled;
191 
192 static struct uart_port __pminitdata __frv_uart0 = {
193  .uartclk = 0,
194  .membase = (char *) UART0_BASE,
195  .irq = IRQ_CPU_UART0,
196  .regshift = 3,
197  .iotype = UPIO_MEM,
198  .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
199 };
200 
201 static struct uart_port __pminitdata __frv_uart1 = {
202  .uartclk = 0,
203  .membase = (char *) UART1_BASE,
204  .irq = IRQ_CPU_UART1,
205  .regshift = 3,
206  .iotype = UPIO_MEM,
207  .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
208 };
209 
210 #if 0
211 static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
212 {
213  unsigned long phys, virt, cxn, size;
214 
215 #ifdef CONFIG_MMU
216  virt = amlr & 0xffffc000;
217  cxn = amlr & 0x3fff;
218 #else
219  virt = ampr & 0xffffc000;
220  cxn = 0;
221 #endif
222  phys = ampr & xAMPRx_PPFN;
223  size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
224 
225  printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
226  i_d, n,
227  virt, virt + size - 1,
228  phys,
229  ampr & xAMPRx_S ? 'S' : '-',
230  ampr & xAMPRx_C ? 'C' : '-',
231  ampr & DAMPRx_WP ? 'W' : '-',
232  ampr & xAMPRx_V ? 'V' : '-',
233  cxn
234  );
235 }
236 #endif
237 
238 /*****************************************************************************/
239 /*
240  * dump the memory map
241  */
242 static void __init dump_memory_map(void)
243 {
244 
245 #if 0
246  /* dump the protection map */
247  printk_xampr(__get_IAMPR(0), __get_IAMLR(0), 'I', 0);
248  printk_xampr(__get_IAMPR(1), __get_IAMLR(1), 'I', 1);
249  printk_xampr(__get_IAMPR(2), __get_IAMLR(2), 'I', 2);
250  printk_xampr(__get_IAMPR(3), __get_IAMLR(3), 'I', 3);
251  printk_xampr(__get_IAMPR(4), __get_IAMLR(4), 'I', 4);
252  printk_xampr(__get_IAMPR(5), __get_IAMLR(5), 'I', 5);
253  printk_xampr(__get_IAMPR(6), __get_IAMLR(6), 'I', 6);
254  printk_xampr(__get_IAMPR(7), __get_IAMLR(7), 'I', 7);
255  printk_xampr(__get_IAMPR(8), __get_IAMLR(8), 'I', 8);
256  printk_xampr(__get_IAMPR(9), __get_IAMLR(9), 'i', 9);
257  printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
258  printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
259  printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
260  printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
261  printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
262  printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
263 
264  printk_xampr(__get_DAMPR(0), __get_DAMLR(0), 'D', 0);
265  printk_xampr(__get_DAMPR(1), __get_DAMLR(1), 'D', 1);
266  printk_xampr(__get_DAMPR(2), __get_DAMLR(2), 'D', 2);
267  printk_xampr(__get_DAMPR(3), __get_DAMLR(3), 'D', 3);
268  printk_xampr(__get_DAMPR(4), __get_DAMLR(4), 'D', 4);
269  printk_xampr(__get_DAMPR(5), __get_DAMLR(5), 'D', 5);
270  printk_xampr(__get_DAMPR(6), __get_DAMLR(6), 'D', 6);
271  printk_xampr(__get_DAMPR(7), __get_DAMLR(7), 'D', 7);
272  printk_xampr(__get_DAMPR(8), __get_DAMLR(8), 'D', 8);
273  printk_xampr(__get_DAMPR(9), __get_DAMLR(9), 'D', 9);
274  printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
275  printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
276  printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
277  printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
278  printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
279  printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
280 #endif
281 
282 #if 0
283  /* dump the bus controller registers */
284  printk("LGCR: %08lx\n", __get_LGCR());
285  printk("Master: %08lx-%08lx CR=%08lx\n",
286  __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
287  __get_LMAICR());
288 
289  int loop;
290  for (loop = 1; loop <= 7; loop++) {
291  unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
292  printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
293  loop,
294  lsbr, lsbr + __get_LSAM(loop),
295  lcr & 0x80000000 ? 'r' : '-',
296  lcr & 0x40000000 ? 'w' : '-',
297  lcr & 0x08000000 ? 'b' : '-',
298  lcr & 0x04000000 ? 'B' : '-',
299  lcr & 0x02000000 ? 'C' : '-',
300  lcr & 0x01000000 ? 'D' : '-',
301  lcr & 0x00800000 ? 'W' : '-',
302  lcr & 0x00400000 ? 'R' : '-',
303  (lcr & 0x00030000) == 0x00000000 ? '4' :
304  (lcr & 0x00030000) == 0x00010000 ? '2' :
305  (lcr & 0x00030000) == 0x00020000 ? '1' :
306  '-'
307  );
308  }
309 #endif
310 
311 #if 0
312  printk("\n");
313 #endif
314 } /* end dump_memory_map() */
315 
316 /*****************************************************************************/
317 /*
318  * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
319  */
320 #ifdef CONFIG_MB93091_VDK
321 static void __init detect_mb93091(void)
322 {
323 #ifdef CONFIG_MB93090_MB00
324  /* Detect CB70 without motherboard */
325  if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
326  cpu_board1 = __frv_mb93090_mb00;
327  mb93090_mb00_detected = 1;
328  }
329 #endif
330 
331 #ifdef CONFIG_FUJITSU_MB93493
332  cpu_board2 = __frv_mb93493;
333 #endif
334 
335 } /* end detect_mb93091() */
336 #endif
337 
338 /*****************************************************************************/
339 /*
340  * determine the CPU type and set appropriate parameters
341  *
342  * Family Series CPU Core Silicon Imple Vers
343  * ----------------------------------------------------------
344  * FR-V --+-> FR400 --+-> FR401 --+-> MB93401 02 00 [1]
345  * | | |
346  * | | +-> MB93401/A 02 01
347  * | | |
348  * | | +-> MB93403 02 02
349  * | |
350  * | +-> FR405 ----> MB93405 04 00
351  * |
352  * +-> FR450 ----> FR451 ----> MB93451 05 00
353  * |
354  * +-> FR500 ----> FR501 --+-> MB93501 01 01 [2]
355  * | |
356  * | +-> MB93501/A 01 02
357  * |
358  * +-> FR550 --+-> FR551 ----> MB93555 03 01
359  *
360  * [1] The MB93401 is an obsolete CPU replaced by the MB93401A
361  * [2] The MB93501 is an obsolete CPU replaced by the MB93501A
362  *
363  * Imple is PSR(Processor Status Register)[31:28].
364  * Vers is PSR(Processor Status Register)[27:24].
365  *
366  * A "Silicon" consists of CPU core and some on-chip peripherals.
367  */
368 static void __init determine_cpu(void)
369 {
370  unsigned long hsr0 = __get_HSR(0);
371  unsigned long psr = __get_PSR();
372 
373  /* work out what selectable services the CPU supports */
374  __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
375  cpu_psr_all = __get_PSR();
376  __set_PSR(psr);
377 
378  __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
379  cpu_hsr0_all = __get_HSR(0);
380  __set_HSR(0, hsr0);
381 
382  /* derive other service specs from the CPU type */
383  cpu_series = "unknown";
384  cpu_core = "unknown";
385  cpu_silicon = "unknown";
386  cpu_mmu = "Prot";
387  cpu_system = __frv_unknown_system;
388  clock_cmodes = NULL;
389  clock_doubled = 0;
390 #ifdef CONFIG_PM
391  clock_bits_settable = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
392 #endif
393 
394  switch (PSR_IMPLE(psr)) {
395  case PSR_IMPLE_FR401:
396  cpu_series = "fr400";
397  cpu_core = "fr401";
398  pdm_suspend_mode = HSR0_PDM_PLL_RUN;
399 
400  switch (PSR_VERSION(psr)) {
401  case PSR_VERSION_FR401_MB93401:
402  cpu_silicon = "mb93401";
403  cpu_system = __frv_mb93091_cb10;
404  clock_cmodes = clock_cmodes_fr401_fr403;
405  clock_doubled = 1;
406  break;
407  case PSR_VERSION_FR401_MB93401A:
408  cpu_silicon = "mb93401/A";
409  cpu_system = __frv_mb93091_cb11;
410  clock_cmodes = clock_cmodes_fr401_fr403;
411  break;
412  case PSR_VERSION_FR401_MB93403:
413  cpu_silicon = "mb93403";
414 #ifndef CONFIG_MB93093_PDK
415  cpu_system = __frv_mb93091_cb30;
416 #else
417  cpu_system = __frv_mb93093;
418 #endif
419  clock_cmodes = clock_cmodes_fr401_fr403;
420  break;
421  default:
422  break;
423  }
424  break;
425 
426  case PSR_IMPLE_FR405:
427  cpu_series = "fr400";
428  cpu_core = "fr405";
429  pdm_suspend_mode = HSR0_PDM_PLL_STOP;
430 
431  switch (PSR_VERSION(psr)) {
432  case PSR_VERSION_FR405_MB93405:
433  cpu_silicon = "mb93405";
434  cpu_system = __frv_mb93091_cb60;
435  clock_cmodes = clock_cmodes_fr405;
436 #ifdef CONFIG_PM
437  clock_bits_settable |= CLOCK_BIT_CMODE;
438  clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
439 #endif
440 
441  /* the FPGA on the CB70 has extra registers
442  * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
443  * how we tell the difference between it and a CB60
444  */
445  if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
446  cpu_system = __frv_mb93091_cb70;
447  break;
448  default:
449  break;
450  }
451  break;
452 
453  case PSR_IMPLE_FR451:
454  cpu_series = "fr450";
455  cpu_core = "fr451";
456  pdm_suspend_mode = HSR0_PDM_PLL_STOP;
457 #ifdef CONFIG_PM
458  clock_bits_settable |= CLOCK_BIT_CMODE;
459  clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
460 #endif
461  switch (PSR_VERSION(psr)) {
462  case PSR_VERSION_FR451_MB93451:
463  cpu_silicon = "mb93451";
464  cpu_mmu = "Prot, SAT, xSAT, DAT";
465  cpu_system = __frv_mb93091_cb451;
466  clock_cmodes = clock_cmodes_fr405;
467  break;
468  default:
469  break;
470  }
471  break;
472 
473  case PSR_IMPLE_FR501:
474  cpu_series = "fr500";
475  cpu_core = "fr501";
476  pdm_suspend_mode = HSR0_PDM_PLL_STOP;
477 
478  switch (PSR_VERSION(psr)) {
479  case PSR_VERSION_FR501_MB93501: cpu_silicon = "mb93501"; break;
480  case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
481  default:
482  break;
483  }
484  break;
485 
486  case PSR_IMPLE_FR551:
487  cpu_series = "fr550";
488  cpu_core = "fr551";
489  pdm_suspend_mode = HSR0_PDM_PLL_RUN;
490 
491  switch (PSR_VERSION(psr)) {
492  case PSR_VERSION_FR551_MB93555:
493  cpu_silicon = "mb93555";
494  cpu_mmu = "Prot, SAT";
495  cpu_system = __frv_mb93091_cb41;
496  clock_cmodes = clock_cmodes_fr555;
497  clock_doubled = 1;
498  break;
499  default:
500  break;
501  }
502  break;
503 
504  default:
505  break;
506  }
507 
508  printk("- Series:%s CPU:%s Silicon:%s\n",
509  cpu_series, cpu_core, cpu_silicon);
510 
511 #ifdef CONFIG_MB93091_VDK
512  detect_mb93091();
513 #endif
514 
515 #if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
516  cpu_board2 = __frv_mb93493;
517 #endif
518 
519 } /* end determine_cpu() */
520 
521 /*****************************************************************************/
522 /*
523  * calculate the bus clock speed
524  */
525 void __pminit determine_clocks(int verbose)
526 {
527  const struct clock_cmode *mode, *tmode;
528  unsigned long clkc, psr, quot;
529 
530  clkc = __get_CLKC();
531  psr = __get_PSR();
532 
533  clock_p0_current = !!(clkc & CLKC_P0);
534  clock_cm_current = clkc & CLKC_CM;
535  clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
536 
537  if (verbose)
538  printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
539 
540  /* the CB70 has some alternative ways of setting the clock speed through switches accessed
541  * through the FPGA. */
542  if (cpu_system == __frv_mb93091_cb70) {
543  unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
544 
545  if (clkswr & 0x1000)
546  __clkin_clock_speed_HZ = 60000000UL;
547  else
548  __clkin_clock_speed_HZ =
549  ((clkswr >> 8) & 0xf) * 10000000 +
550  ((clkswr >> 4) & 0xf) * 1000000 +
551  ((clkswr ) & 0xf) * 100000;
552  }
553  /* the FR451 is currently fixed at 24MHz */
554  else if (cpu_system == __frv_mb93091_cb451) {
555  //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
556  unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
557 
558  if (clkswr & 0x1000)
559  __clkin_clock_speed_HZ = 60000000UL;
560  else
561  __clkin_clock_speed_HZ =
562  ((clkswr >> 8) & 0xf) * 10000000 +
563  ((clkswr >> 4) & 0xf) * 1000000 +
564  ((clkswr ) & 0xf) * 100000;
565  }
566  /* otherwise determine the clockspeed from VDK or other registers */
567  else {
568  __clkin_clock_speed_HZ = __get_CLKIN();
569  }
570 
571  /* look up the appropriate clock relationships table entry */
572  mode = &undef_clock_cmode;
573  if (clock_cmodes) {
574  tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
575  if (tmode->xbus)
576  mode = tmode;
577  }
578 
579 #define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
580 
581  if (clock_doubled)
582  __clkin_clock_speed_HZ <<= 1;
583 
584  __ext_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
585  __sdram_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
586  __dsu_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
587 
588  switch (clkc & CLKC_CM) {
589  case 0: /* High */
590  __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
591  __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->core);
592  break;
593  case 1: /* Medium */
594  __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
595  __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
596  break;
597  case 2: /* Low; not supported */
598  case 3: /* UNDEF */
599  printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
600  panic("Bye");
601  }
602 
603  __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
604  if (clkc & CLKC_P0)
605  __res_bus_clock_speed_HZ >>= 1;
606 
607  if (verbose) {
608  printk("CLKIN: %lu.%3.3luMHz\n",
609  __clkin_clock_speed_HZ / 1000000,
610  (__clkin_clock_speed_HZ / 1000) % 1000);
611 
612  printk("CLKS:"
613  " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
614  __ext_bus_clock_speed_HZ / 1000000,
615  __res_bus_clock_speed_HZ / 1000000,
616  __sdram_clock_speed_HZ / 1000000,
617  __core_bus_clock_speed_HZ / 1000000,
618  __core_clock_speed_HZ / 1000000,
619  __dsu_clock_speed_HZ / 1000000
620  );
621  }
622 
623  /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
624  __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
625 
626  /* set the serial prescaler */
627  __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
628  quot = 1;
629  while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
630  quot += 1;
631 
632  /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
633  * - we have to be careful - dividing too much can mean we can't get 115200 baud
634  */
635  if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
636  quot <<= 1;
637 
638  __serial_clock_speed_HZ /= quot;
639  __frv_uart0.uartclk = __serial_clock_speed_HZ;
640  __frv_uart1.uartclk = __serial_clock_speed_HZ;
641 
642  if (verbose)
643  printk(" uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
644 
645  while (!(__get_UART0_LSR() & UART_LSR_TEMT))
646  continue;
647 
648  while (!(__get_UART1_LSR() & UART_LSR_TEMT))
649  continue;
650 
651  __set_UCPVR(quot);
652  __set_UCPSR(0);
653 } /* end determine_clocks() */
654 
655 /*****************************************************************************/
656 /*
657  * reserve some DMA consistent memory
658  */
659 #ifdef CONFIG_RESERVE_DMA_COHERENT
660 static void __init reserve_dma_coherent(void)
661 {
662  unsigned long ampr;
663 
664  /* find the first non-kernel memory tile and steal it */
665 #define __steal_AMPR(r) \
666  if (__get_DAMPR(r) & xAMPRx_V) { \
667  ampr = __get_DAMPR(r); \
668  __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C); \
669  __set_IAMPR(r, 0); \
670  goto found; \
671  }
672 
673  __steal_AMPR(1);
674  __steal_AMPR(2);
675  __steal_AMPR(3);
676  __steal_AMPR(4);
677  __steal_AMPR(5);
678  __steal_AMPR(6);
679 
680  if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
681  __steal_AMPR(7);
682  __steal_AMPR(8);
683  __steal_AMPR(9);
684  __steal_AMPR(10);
685  __steal_AMPR(11);
686  __steal_AMPR(12);
687  __steal_AMPR(13);
688  __steal_AMPR(14);
689  }
690 
691  /* unable to grant any DMA consistent memory */
692  printk("No DMA consistent memory reserved\n");
693  return;
694 
695  found:
696  dma_coherent_mem_start = ampr & xAMPRx_PPFN;
697  ampr &= xAMPRx_SS;
698  ampr >>= 4;
699  ampr = 1 << (ampr - 3 + 20);
700  dma_coherent_mem_end = dma_coherent_mem_start + ampr;
701 
702  printk("DMA consistent memory reserved %lx-%lx\n",
703  dma_coherent_mem_start, dma_coherent_mem_end);
704 
705 } /* end reserve_dma_coherent() */
706 #endif
707 
708 /*****************************************************************************/
709 /*
710  * calibrate the delay loop
711  */
712 void __cpuinit calibrate_delay(void)
713 {
714  loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
715 
716  printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
717  loops_per_jiffy / (500000 / HZ),
718  (loops_per_jiffy / (5000 / HZ)) % 100);
719 
720 } /* end calibrate_delay() */
721 
722 /*****************************************************************************/
723 /*
724  * look through the command line for some things we need to know immediately
725  */
726 static void __init parse_cmdline_early(char *cmdline)
727 {
728  if (!cmdline)
729  return;
730 
731  while (*cmdline) {
732  if (*cmdline == ' ')
733  cmdline++;
734 
735  /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
736  * out from the SDRAM controller mask register
737  */
738  if (!memcmp(cmdline, "mem=", 4)) {
739  unsigned long long mem_size;
740 
741  mem_size = memparse(cmdline + 4, &cmdline);
742  memory_end = memory_start + mem_size;
743  }
744 
745  while (*cmdline && *cmdline != ' ')
746  cmdline++;
747  }
748 
749 } /* end parse_cmdline_early() */
750 
751 /*****************************************************************************/
752 /*
753  *
754  */
755 void __init setup_arch(char **cmdline_p)
756 {
757 #ifdef CONFIG_MMU
758  printk("Linux FR-V port done by Red Hat Inc <[email protected]>\n");
759 #else
760  printk("uClinux FR-V port done by Red Hat Inc <[email protected]>\n");
761 #endif
762 
763  memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
764 
765  determine_cpu();
766  determine_clocks(1);
767 
768  /* For printk-directly-beats-on-serial-hardware hack */
769  console_set_baud(115200);
770 #ifdef CONFIG_GDBSTUB
771  gdbstub_set_baud(115200);
772 #endif
773 
774 #ifdef CONFIG_RESERVE_DMA_COHERENT
775  reserve_dma_coherent();
776 #endif
777  dump_memory_map();
778 
779 #ifdef CONFIG_MB93090_MB00
780  if (mb93090_mb00_detected)
781  mb93090_display();
782 #endif
783 
784  /* register those serial ports that are available */
785 #ifdef CONFIG_FRV_ONCPU_SERIAL
786 #ifndef CONFIG_GDBSTUB_UART0
787  __reg(UART0_BASE + UART_IER * 8) = 0;
788  early_serial_setup(&__frv_uart0);
789 #endif
790 #ifndef CONFIG_GDBSTUB_UART1
791  __reg(UART1_BASE + UART_IER * 8) = 0;
792  early_serial_setup(&__frv_uart1);
793 #endif
794 #endif
795 
796  /* deal with the command line - RedBoot may have passed one to the kernel */
797  memcpy(command_line, boot_command_line, sizeof(command_line));
798  *cmdline_p = &command_line[0];
799  parse_cmdline_early(command_line);
800 
801  /* set up the memory description
802  * - by now the stack is part of the init task */
803  printk("Memory %08lx-%08lx\n", memory_start, memory_end);
804 
805  BUG_ON(memory_start == memory_end);
806 
807  init_mm.start_code = (unsigned long) &_stext;
808  init_mm.end_code = (unsigned long) &_etext;
809  init_mm.end_data = (unsigned long) &_edata;
810 #if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
811  init_mm.brk = (unsigned long) &_end;
812 #else
813  init_mm.brk = (unsigned long) 0;
814 #endif
815 
816 #ifdef DEBUG
817  printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n",
818  (int) &_stext, (int) &_etext,
819  (int) &_sdata, (int) &_edata,
820  (int) &_sbss, (int) &_ebss);
821 #endif
822 
823 #ifdef CONFIG_VT
824 #if defined(CONFIG_VGA_CONSOLE)
825  conswitchp = &vga_con;
826 #elif defined(CONFIG_DUMMY_CONSOLE)
827  conswitchp = &dummy_con;
828 #endif
829 #endif
830 
831 #ifdef CONFIG_MMU
832  setup_linux_memory();
833 #else
834  setup_uclinux_memory();
835 #endif
836 
837  /* get kmalloc into gear */
838  paging_init();
839 
840  /* init DMA */
841  frv_dma_init();
842 #ifdef DEBUG
843  printk("Done setup_arch\n");
844 #endif
845 
846  /* start the decrement timer running */
847 // asm volatile("movgs %0,timerd" :: "r"(10000000));
848 // __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
849 
850 } /* end setup_arch() */
851 
852 #if 0
853 /*****************************************************************************/
854 /*
855  *
856  */
857 static int __devinit setup_arch_serial(void)
858 {
859  /* register those serial ports that are available */
860 #ifndef CONFIG_GDBSTUB_UART0
861  early_serial_setup(&__frv_uart0);
862 #endif
863 #ifndef CONFIG_GDBSTUB_UART1
864  early_serial_setup(&__frv_uart1);
865 #endif
866 
867  return 0;
868 } /* end setup_arch_serial() */
869 
870 late_initcall(setup_arch_serial);
871 #endif
872 
873 /*****************************************************************************/
874 /*
875  * set up the memory map for normal MMU linux
876  */
877 #ifdef CONFIG_MMU
878 static void __init setup_linux_memory(void)
879 {
880  unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
881 
882  kstart = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
883  kend = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
884 
885  kstart = kstart & PAGE_MASK;
886  kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
887 
888  /* give all the memory to the bootmap allocator, tell it to put the
889  * boot mem_map immediately following the kernel image
890  */
891  bootmap_size = init_bootmem_node(NODE_DATA(0),
892  kend >> PAGE_SHIFT, /* map addr */
893  memory_start >> PAGE_SHIFT, /* start of RAM */
894  memory_end >> PAGE_SHIFT /* end of RAM */
895  );
896 
897  /* pass the memory that the kernel can immediately use over to the bootmem allocator */
898  max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT;
899  low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
900  high_mem = 0;
901 
902  if (num_physpages > low_top_pfn) {
903 #ifdef CONFIG_HIGHMEM
904  high_mem = num_physpages - low_top_pfn;
905 #else
906  max_mapnr = num_physpages = low_top_pfn;
907 #endif
908  }
909  else {
910  low_top_pfn = num_physpages;
911  }
912 
913  min_low_pfn = memory_start >> PAGE_SHIFT;
914  max_low_pfn = low_top_pfn;
915  max_pfn = memory_end >> PAGE_SHIFT;
916 
917  num_mappedpages = low_top_pfn;
918 
919  printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
920 
921  free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
922 
923 #ifdef CONFIG_HIGHMEM
924  if (high_mem)
925  printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
926 #endif
927 
928  /* take back the memory occupied by the kernel image and the bootmem alloc map */
929  reserve_bootmem(kstart, kend - kstart + bootmap_size,
930  BOOTMEM_DEFAULT);
931 
932  /* reserve the memory occupied by the initial ramdisk */
933 #ifdef CONFIG_BLK_DEV_INITRD
934  if (LOADER_TYPE && INITRD_START) {
935  if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
936  reserve_bootmem(INITRD_START, INITRD_SIZE,
937  BOOTMEM_DEFAULT);
938  initrd_start = INITRD_START + PAGE_OFFSET;
939  initrd_end = initrd_start + INITRD_SIZE;
940  }
941  else {
942  printk(KERN_ERR
943  "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
944  "disabling initrd\n",
945  INITRD_START + INITRD_SIZE,
946  low_top_pfn << PAGE_SHIFT);
947  initrd_start = 0;
948  }
949  }
950 #endif
951 
952 } /* end setup_linux_memory() */
953 #endif
954 
955 /*****************************************************************************/
956 /*
957  * set up the memory map for uClinux
958  */
959 #ifndef CONFIG_MMU
960 static void __init setup_uclinux_memory(void)
961 {
962 #ifdef CONFIG_PROTECT_KERNEL
963  unsigned long dampr;
964 #endif
965  unsigned long kend;
966  int bootmap_size;
967 
968  kend = (unsigned long) &__kernel_image_end;
969  kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
970 
971  /* give all the memory to the bootmap allocator, tell it to put the
972  * boot mem_map immediately following the kernel image
973  */
974  bootmap_size = init_bootmem_node(NODE_DATA(0),
975  kend >> PAGE_SHIFT, /* map addr */
976  memory_start >> PAGE_SHIFT, /* start of RAM */
977  memory_end >> PAGE_SHIFT /* end of RAM */
978  );
979 
980  /* free all the usable memory */
981  free_bootmem(memory_start, memory_end - memory_start);
982 
983  high_memory = (void *) (memory_end & PAGE_MASK);
984  max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
985 
986  min_low_pfn = memory_start >> PAGE_SHIFT;
987  max_low_pfn = memory_end >> PAGE_SHIFT;
988  max_pfn = max_low_pfn;
989 
990  /* now take back the bits the core kernel is occupying */
991 #ifndef CONFIG_PROTECT_KERNEL
992  reserve_bootmem(kend, bootmap_size, BOOTMEM_DEFAULT);
993  reserve_bootmem((unsigned long) &__kernel_image_start,
994  kend - (unsigned long) &__kernel_image_start,
995  BOOTMEM_DEFAULT);
996 
997 #else
998  dampr = __get_DAMPR(0);
999  dampr &= xAMPRx_SS;
1000  dampr = (dampr >> 4) + 17;
1001  dampr = 1 << dampr;
1002 
1003  reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr, BOOTMEM_DEFAULT);
1004 #endif
1005 
1006  /* reserve some memory to do uncached DMA through if requested */
1007 #ifdef CONFIG_RESERVE_DMA_COHERENT
1008  if (dma_coherent_mem_start)
1009  reserve_bootmem(dma_coherent_mem_start,
1010  dma_coherent_mem_end - dma_coherent_mem_start,
1011  BOOTMEM_DEFAULT);
1012 #endif
1013 
1014 } /* end setup_uclinux_memory() */
1015 #endif
1016 
1017 /*****************************************************************************/
1018 /*
1019  * get CPU information for use by procfs
1020  */
1021 static int show_cpuinfo(struct seq_file *m, void *v)
1022 {
1023  const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
1024 #ifdef CONFIG_PM
1025  const char *sep;
1026 #endif
1027 
1028  gr = cpu_hsr0_all & HSR0_GRHE ? "gr0-63" : "gr0-31";
1029  fr = cpu_hsr0_all & HSR0_FRHE ? "fr0-63" : "fr0-31";
1030  fm = cpu_psr_all & PSR_EM ? ", Media" : "";
1031  fp = cpu_psr_all & PSR_EF ? ", FPU" : "";
1032  cm = cpu_psr_all & PSR_CM ? ", CCCR" : "";
1033  nem = cpu_psr_all & PSR_NEM ? ", NE" : "";
1034  ble = cpu_psr_all & PSR_BE ? "BE" : "LE";
1035 
1036  seq_printf(m,
1037  "CPU-Series:\t%s\n"
1038  "CPU-Core:\t%s, %s, %s%s%s\n"
1039  "CPU:\t\t%s\n"
1040  "MMU:\t\t%s\n"
1041  "FP-Media:\t%s%s%s\n"
1042  "System:\t\t%s",
1043  cpu_series,
1044  cpu_core, gr, ble, cm, nem,
1045  cpu_silicon,
1046  cpu_mmu,
1047  fr, fm, fp,
1048  cpu_system);
1049 
1050  if (cpu_board1)
1051  seq_printf(m, ", %s", cpu_board1);
1052 
1053  if (cpu_board2)
1054  seq_printf(m, ", %s", cpu_board2);
1055 
1056  seq_printf(m, "\n");
1057 
1058 #ifdef CONFIG_PM
1059  seq_printf(m, "PM-Controls:");
1060  sep = "\t";
1061 
1062  if (clock_bits_settable & CLOCK_BIT_CMODE) {
1063  seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
1064  sep = ", ";
1065  }
1066 
1067  if (clock_bits_settable & CLOCK_BIT_CM) {
1068  seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
1069  sep = ", ";
1070  }
1071 
1072  if (clock_bits_settable & CLOCK_BIT_P0) {
1073  seq_printf(m, "%sp0=0x3", sep);
1074  sep = ", ";
1075  }
1076 
1077  seq_printf(m, "%ssuspend=0x22\n", sep);
1078 #endif
1079 
1080  seq_printf(m,
1081  "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
1082  clock_cmode_current, clock_cm_current, clock_p0_current);
1083 
1084 #define print_clk(TAG, VAR) \
1085  seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
1086 
1087  print_clk("In", __clkin_clock_speed_HZ);
1088  print_clk("Core", __core_clock_speed_HZ);
1089  print_clk("SDRAM", __sdram_clock_speed_HZ);
1090  print_clk("CBus", __core_bus_clock_speed_HZ);
1091  print_clk("Res", __res_bus_clock_speed_HZ);
1092  print_clk("Ext", __ext_bus_clock_speed_HZ);
1093  print_clk("DSU", __dsu_clock_speed_HZ);
1094 
1095  seq_printf(m,
1096  "BogoMips:\t%lu.%02lu\n",
1097  (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
1098 
1099  return 0;
1100 } /* end show_cpuinfo() */
1101 
1102 static void *c_start(struct seq_file *m, loff_t *pos)
1103 {
1104  return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
1105 }
1106 
1107 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1108 {
1109  ++*pos;
1110  return c_start(m, pos);
1111 }
1112 
1113 static void c_stop(struct seq_file *m, void *v)
1114 {
1115 }
1116 
1117 const struct seq_operations cpuinfo_op = {
1118  .start = c_start,
1119  .next = c_next,
1120  .stop = c_stop,
1121  .show = show_cpuinfo,
1122 };
1123 
1124 void arch_gettod(int *year, int *mon, int *day, int *hour,
1125  int *min, int *sec)
1126 {
1127  *year = *mon = *day = *hour = *min = *sec = 0;
1128 }
1129 
1130 /*****************************************************************************/
1131 /*
1132  *
1133  */
1134 #ifdef CONFIG_MB93090_MB00
1135 static void __init mb93090_sendlcdcmd(uint32_t cmd)
1136 {
1137  unsigned long base = __addr_LCD();
1138  int loop;
1139 
1140  /* request reading of the busy flag */
1141  __set_LCD(base, LCD_CMD_READ_BUSY);
1142  __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
1143 
1144  /* wait for the busy flag to become clear */
1145  for (loop = 10000; loop > 0; loop--)
1146  if (!(__get_LCD(base) & 0x80))
1147  break;
1148 
1149  /* send the command */
1150  __set_LCD(base, cmd);
1151  __set_LCD(base, cmd & ~LCD_E);
1152 
1153 } /* end mb93090_sendlcdcmd() */
1154 
1155 /*****************************************************************************/
1156 /*
1157  * write to the MB93090 LEDs and LCD
1158  */
1159 static void __init mb93090_display(void)
1160 {
1161  const char *p;
1162 
1163  __set_LEDS(0);
1164 
1165  /* set up the LCD */
1166  mb93090_sendlcdcmd(LCD_CMD_CLEAR);
1167  mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
1168  mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
1169  mb93090_sendlcdcmd(LCD_CMD_HOME);
1170 
1171  mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
1172  for (p = mb93090_banner; *p; p++)
1173  mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1174 
1175  mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
1176  for (p = mb93090_version; *p; p++)
1177  mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1178 
1179 } /* end mb93090_display() */
1180 
1181 #endif // CONFIG_MB93090_MB00
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