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pci.c
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1 /*
2  * Support for PCI bridges found on Power Macintoshes.
3  *
4  * Copyright (C) 2003-2005 Benjamin Herrenschmuidt ([email protected])
5  * Copyright (C) 1997 Paul Mackerras ([email protected])
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; either version
10  * 2 of the License, or (at your option) any later version.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
19 #include <linux/irq.h>
20 #include <linux/of_pci.h>
21 
22 #include <asm/sections.h>
23 #include <asm/io.h>
24 #include <asm/prom.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <asm/pmac_feature.h>
28 #include <asm/grackle.h>
29 #include <asm/ppc-pci.h>
30 
31 #undef DEBUG
32 
33 #ifdef DEBUG
34 #define DBG(x...) printk(x)
35 #else
36 #define DBG(x...)
37 #endif
38 
39 /* XXX Could be per-controller, but I don't think we risk anything by
40  * assuming we won't have both UniNorth and Bandit */
41 static int has_uninorth;
42 #ifdef CONFIG_PPC64
43 static struct pci_controller *u3_agp;
44 #else
45 static int has_second_ohare;
46 #endif /* CONFIG_PPC64 */
47 
48 extern int pcibios_assign_bus_offset;
49 
51 
52 /*
53  * Magic constants for enabling cache coherency in the bandit/PSX bridge.
54  */
55 #define BANDIT_DEVID_2 8
56 #define BANDIT_REVID 3
57 
58 #define BANDIT_DEVNUM 11
59 #define BANDIT_MAGIC 0x50
60 #define BANDIT_COHERENT 0x40
61 
62 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
63 {
64  for (; node != 0;node = node->sibling) {
65  const int * bus_range;
66  const unsigned int *class_code;
67  int len;
68 
69  /* For PCI<->PCI bridges or CardBus bridges, we go down */
70  class_code = of_get_property(node, "class-code", NULL);
71  if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
72  (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
73  continue;
74  bus_range = of_get_property(node, "bus-range", &len);
75  if (bus_range != NULL && len > 2 * sizeof(int)) {
76  if (bus_range[1] > higher)
77  higher = bus_range[1];
78  }
79  higher = fixup_one_level_bus_range(node->child, higher);
80  }
81  return higher;
82 }
83 
84 /* This routine fixes the "bus-range" property of all bridges in the
85  * system since they tend to have their "last" member wrong on macs
86  *
87  * Note that the bus numbers manipulated here are OF bus numbers, they
88  * are not Linux bus numbers.
89  */
90 static void __init fixup_bus_range(struct device_node *bridge)
91 {
92  int *bus_range, len;
93  struct property *prop;
94 
95  /* Lookup the "bus-range" property for the hose */
96  prop = of_find_property(bridge, "bus-range", &len);
97  if (prop == NULL || prop->length < 2 * sizeof(int))
98  return;
99 
100  bus_range = prop->value;
101  bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
102 }
103 
104 /*
105  * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
106  *
107  * The "Bandit" version is present in all early PCI PowerMacs,
108  * and up to the first ones using Grackle. Some machines may
109  * have 2 bandit controllers (2 PCI busses).
110  *
111  * "Chaos" is used in some "Bandit"-type machines as a bridge
112  * for the separate display bus. It is accessed the same
113  * way as bandit, but cannot be probed for devices. It therefore
114  * has its own config access functions.
115  *
116  * The "UniNorth" version is present in all Core99 machines
117  * (iBook, G4, new IMacs, and all the recent Apple machines).
118  * It contains 3 controllers in one ASIC.
119  *
120  * The U3 is the bridge used on G5 machines. It contains an
121  * AGP bus which is dealt with the old UniNorth access routines
122  * and a HyperTransport bus which uses its own set of access
123  * functions.
124  */
125 
126 #define MACRISC_CFA0(devfn, off) \
127  ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
128  | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
129  | (((unsigned int)(off)) & 0xFCUL))
130 
131 #define MACRISC_CFA1(bus, devfn, off) \
132  ((((unsigned int)(bus)) << 16) \
133  |(((unsigned int)(devfn)) << 8) \
134  |(((unsigned int)(off)) & 0xFCUL) \
135  |1UL)
136 
137 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose,
138  u8 bus, u8 dev_fn, u8 offset)
139 {
140  unsigned int caddr;
141 
142  if (bus == hose->first_busno) {
143  if (dev_fn < (11 << 3))
144  return NULL;
145  caddr = MACRISC_CFA0(dev_fn, offset);
146  } else
147  caddr = MACRISC_CFA1(bus, dev_fn, offset);
148 
149  /* Uninorth will return garbage if we don't read back the value ! */
150  do {
151  out_le32(hose->cfg_addr, caddr);
152  } while (in_le32(hose->cfg_addr) != caddr);
153 
154  offset &= has_uninorth ? 0x07 : 0x03;
155  return hose->cfg_data + offset;
156 }
157 
158 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
159  int offset, int len, u32 *val)
160 {
161  struct pci_controller *hose;
162  volatile void __iomem *addr;
163 
164  hose = pci_bus_to_host(bus);
165  if (hose == NULL)
167  if (offset >= 0x100)
169  addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
170  if (!addr)
172  /*
173  * Note: the caller has already checked that offset is
174  * suitably aligned and that len is 1, 2 or 4.
175  */
176  switch (len) {
177  case 1:
178  *val = in_8(addr);
179  break;
180  case 2:
181  *val = in_le16(addr);
182  break;
183  default:
184  *val = in_le32(addr);
185  break;
186  }
187  return PCIBIOS_SUCCESSFUL;
188 }
189 
190 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
191  int offset, int len, u32 val)
192 {
193  struct pci_controller *hose;
194  volatile void __iomem *addr;
195 
196  hose = pci_bus_to_host(bus);
197  if (hose == NULL)
199  if (offset >= 0x100)
201  addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
202  if (!addr)
204  /*
205  * Note: the caller has already checked that offset is
206  * suitably aligned and that len is 1, 2 or 4.
207  */
208  switch (len) {
209  case 1:
210  out_8(addr, val);
211  break;
212  case 2:
213  out_le16(addr, val);
214  break;
215  default:
216  out_le32(addr, val);
217  break;
218  }
219  return PCIBIOS_SUCCESSFUL;
220 }
221 
222 static struct pci_ops macrisc_pci_ops =
223 {
224  .read = macrisc_read_config,
225  .write = macrisc_write_config,
226 };
227 
228 #ifdef CONFIG_PPC32
229 /*
230  * Verify that a specific (bus, dev_fn) exists on chaos
231  */
232 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
233 {
234  struct device_node *np;
235  const u32 *vendor, *device;
236 
237  if (offset >= 0x100)
239  np = of_pci_find_child_device(bus->dev.of_node, devfn);
240  if (np == NULL)
242 
243  vendor = of_get_property(np, "vendor-id", NULL);
244  device = of_get_property(np, "device-id", NULL);
245  if (vendor == NULL || device == NULL)
247 
248  if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
249  && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
251 
252  return PCIBIOS_SUCCESSFUL;
253 }
254 
255 static int
256 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
257  int len, u32 *val)
258 {
259  int result = chaos_validate_dev(bus, devfn, offset);
260  if (result == PCIBIOS_BAD_REGISTER_NUMBER)
261  *val = ~0U;
262  if (result != PCIBIOS_SUCCESSFUL)
263  return result;
264  return macrisc_read_config(bus, devfn, offset, len, val);
265 }
266 
267 static int
268 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
269  int len, u32 val)
270 {
271  int result = chaos_validate_dev(bus, devfn, offset);
272  if (result != PCIBIOS_SUCCESSFUL)
273  return result;
274  return macrisc_write_config(bus, devfn, offset, len, val);
275 }
276 
277 static struct pci_ops chaos_pci_ops =
278 {
279  .read = chaos_read_config,
280  .write = chaos_write_config,
281 };
282 
283 static void __init setup_chaos(struct pci_controller *hose,
284  struct resource *addr)
285 {
286  /* assume a `chaos' bridge */
287  hose->ops = &chaos_pci_ops;
288  hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
289  hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
290 }
291 #endif /* CONFIG_PPC32 */
292 
293 #ifdef CONFIG_PPC64
294 /*
295  * These versions of U3 HyperTransport config space access ops do not
296  * implement self-view of the HT host yet
297  */
298 
299 /*
300  * This function deals with some "special cases" devices.
301  *
302  * 0 -> No special case
303  * 1 -> Skip the device but act as if the access was successful
304  * (return 0xff's on reads, eventually, cache config space
305  * accesses in a later version)
306  * -1 -> Hide the device (unsuccessful access)
307  */
308 static int u3_ht_skip_device(struct pci_controller *hose,
309  struct pci_bus *bus, unsigned int devfn)
310 {
311  struct device_node *busdn, *dn;
312  int i;
313 
314  /* We only allow config cycles to devices that are in OF device-tree
315  * as we are apparently having some weird things going on with some
316  * revs of K2 on recent G5s, except for the host bridge itself, which
317  * is missing from the tree but we know we can probe.
318  */
319  if (bus->self)
320  busdn = pci_device_to_OF_node(bus->self);
321  else if (devfn == 0)
322  return 0;
323  else
324  busdn = hose->dn;
325  for (dn = busdn->child; dn; dn = dn->sibling)
326  if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn)
327  break;
328  if (dn == NULL)
329  return -1;
330 
331  /*
332  * When a device in K2 is powered down, we die on config
333  * cycle accesses. Fix that here.
334  */
335  for (i=0; i<2; i++)
336  if (k2_skiplist[i] == dn)
337  return 1;
338 
339  return 0;
340 }
341 
342 #define U3_HT_CFA0(devfn, off) \
343  ((((unsigned int)devfn) << 8) | offset)
344 #define U3_HT_CFA1(bus, devfn, off) \
345  (U3_HT_CFA0(devfn, off) \
346  + (((unsigned int)bus) << 16) \
347  + 0x01000000UL)
348 
349 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus,
350  u8 devfn, u8 offset, int *swap)
351 {
352  *swap = 1;
353  if (bus == hose->first_busno) {
354  if (devfn != 0)
355  return hose->cfg_data + U3_HT_CFA0(devfn, offset);
356  *swap = 0;
357  return ((void __iomem *)hose->cfg_addr) + (offset << 2);
358  } else
359  return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
360 }
361 
362 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
363  int offset, int len, u32 *val)
364 {
365  struct pci_controller *hose;
366  void __iomem *addr;
367  int swap;
368 
369  hose = pci_bus_to_host(bus);
370  if (hose == NULL)
372  if (offset >= 0x100)
374  addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
375  if (!addr)
377 
378  switch (u3_ht_skip_device(hose, bus, devfn)) {
379  case 0:
380  break;
381  case 1:
382  switch (len) {
383  case 1:
384  *val = 0xff; break;
385  case 2:
386  *val = 0xffff; break;
387  default:
388  *val = 0xfffffffful; break;
389  }
390  return PCIBIOS_SUCCESSFUL;
391  default:
393  }
394 
395  /*
396  * Note: the caller has already checked that offset is
397  * suitably aligned and that len is 1, 2 or 4.
398  */
399  switch (len) {
400  case 1:
401  *val = in_8(addr);
402  break;
403  case 2:
404  *val = swap ? in_le16(addr) : in_be16(addr);
405  break;
406  default:
407  *val = swap ? in_le32(addr) : in_be32(addr);
408  break;
409  }
410  return PCIBIOS_SUCCESSFUL;
411 }
412 
413 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
414  int offset, int len, u32 val)
415 {
416  struct pci_controller *hose;
417  void __iomem *addr;
418  int swap;
419 
420  hose = pci_bus_to_host(bus);
421  if (hose == NULL)
423  if (offset >= 0x100)
425  addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
426  if (!addr)
428 
429  switch (u3_ht_skip_device(hose, bus, devfn)) {
430  case 0:
431  break;
432  case 1:
433  return PCIBIOS_SUCCESSFUL;
434  default:
436  }
437 
438  /*
439  * Note: the caller has already checked that offset is
440  * suitably aligned and that len is 1, 2 or 4.
441  */
442  switch (len) {
443  case 1:
444  out_8(addr, val);
445  break;
446  case 2:
447  swap ? out_le16(addr, val) : out_be16(addr, val);
448  break;
449  default:
450  swap ? out_le32(addr, val) : out_be32(addr, val);
451  break;
452  }
453  return PCIBIOS_SUCCESSFUL;
454 }
455 
456 static struct pci_ops u3_ht_pci_ops =
457 {
458  .read = u3_ht_read_config,
459  .write = u3_ht_write_config,
460 };
461 
462 #define U4_PCIE_CFA0(devfn, off) \
463  ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
464  | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
465  | ((((unsigned int)(off)) >> 8) << 28) \
466  | (((unsigned int)(off)) & 0xfcU))
467 
468 #define U4_PCIE_CFA1(bus, devfn, off) \
469  ((((unsigned int)(bus)) << 16) \
470  |(((unsigned int)(devfn)) << 8) \
471  | ((((unsigned int)(off)) >> 8) << 28) \
472  |(((unsigned int)(off)) & 0xfcU) \
473  |1UL)
474 
475 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
476  u8 bus, u8 dev_fn, int offset)
477 {
478  unsigned int caddr;
479 
480  if (bus == hose->first_busno) {
481  caddr = U4_PCIE_CFA0(dev_fn, offset);
482  } else
483  caddr = U4_PCIE_CFA1(bus, dev_fn, offset);
484 
485  /* Uninorth will return garbage if we don't read back the value ! */
486  do {
487  out_le32(hose->cfg_addr, caddr);
488  } while (in_le32(hose->cfg_addr) != caddr);
489 
490  offset &= 0x03;
491  return hose->cfg_data + offset;
492 }
493 
494 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
495  int offset, int len, u32 *val)
496 {
497  struct pci_controller *hose;
498  volatile void __iomem *addr;
499 
500  hose = pci_bus_to_host(bus);
501  if (hose == NULL)
503  if (offset >= 0x1000)
505  addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
506  if (!addr)
508  /*
509  * Note: the caller has already checked that offset is
510  * suitably aligned and that len is 1, 2 or 4.
511  */
512  switch (len) {
513  case 1:
514  *val = in_8(addr);
515  break;
516  case 2:
517  *val = in_le16(addr);
518  break;
519  default:
520  *val = in_le32(addr);
521  break;
522  }
523  return PCIBIOS_SUCCESSFUL;
524 }
525 
526 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
527  int offset, int len, u32 val)
528 {
529  struct pci_controller *hose;
530  volatile void __iomem *addr;
531 
532  hose = pci_bus_to_host(bus);
533  if (hose == NULL)
535  if (offset >= 0x1000)
537  addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
538  if (!addr)
540  /*
541  * Note: the caller has already checked that offset is
542  * suitably aligned and that len is 1, 2 or 4.
543  */
544  switch (len) {
545  case 1:
546  out_8(addr, val);
547  break;
548  case 2:
549  out_le16(addr, val);
550  break;
551  default:
552  out_le32(addr, val);
553  break;
554  }
555  return PCIBIOS_SUCCESSFUL;
556 }
557 
558 static struct pci_ops u4_pcie_pci_ops =
559 {
560  .read = u4_pcie_read_config,
561  .write = u4_pcie_write_config,
562 };
563 
564 static void __devinit pmac_pci_fixup_u4_of_node(struct pci_dev *dev)
565 {
566  /* Apple's device-tree "hides" the root complex virtual P2P bridge
567  * on U4. However, Linux sees it, causing the PCI <-> OF matching
568  * code to fail to properly match devices below it. This works around
569  * it by setting the node of the bridge to point to the PHB node,
570  * which is not entirely correct but fixes the matching code and
571  * doesn't break anything else. It's also the simplest possible fix.
572  */
573  if (dev->dev.of_node == NULL)
574  dev->dev.of_node = pcibios_get_phb_of_node(dev->bus);
575 }
576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
577 
578 #endif /* CONFIG_PPC64 */
579 
580 #ifdef CONFIG_PPC32
581 /*
582  * For a bandit bridge, turn on cache coherency if necessary.
583  * N.B. we could clean this up using the hose ops directly.
584  */
585 static void __init init_bandit(struct pci_controller *bp)
586 {
587  unsigned int vendev, magic;
588  int rev;
589 
590  /* read the word at offset 0 in config space for device 11 */
591  out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
592  udelay(2);
593  vendev = in_le32(bp->cfg_data);
594  if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
596  /* read the revision id */
597  out_le32(bp->cfg_addr,
599  udelay(2);
600  rev = in_8(bp->cfg_data);
601  if (rev != BANDIT_REVID)
603  "Unknown revision %d for bandit\n", rev);
604  } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
605  printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
606  return;
607  }
608 
609  /* read the word at offset 0x50 */
610  out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
611  udelay(2);
612  magic = in_le32(bp->cfg_data);
613  if ((magic & BANDIT_COHERENT) != 0)
614  return;
615  magic |= BANDIT_COHERENT;
616  udelay(2);
617  out_le32(bp->cfg_data, magic);
618  printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
619 }
620 
621 /*
622  * Tweak the PCI-PCI bridge chip on the blue & white G3s.
623  */
624 static void __init init_p2pbridge(void)
625 {
626  struct device_node *p2pbridge;
627  struct pci_controller* hose;
628  u8 bus, devfn;
629  u16 val;
630 
631  /* XXX it would be better here to identify the specific
632  PCI-PCI bridge chip we have. */
633  p2pbridge = of_find_node_by_name(NULL, "pci-bridge");
634  if (p2pbridge == NULL
635  || p2pbridge->parent == NULL
636  || strcmp(p2pbridge->parent->name, "pci") != 0)
637  goto done;
638  if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
639  DBG("Can't find PCI infos for PCI<->PCI bridge\n");
640  goto done;
641  }
642  /* Warning: At this point, we have not yet renumbered all busses.
643  * So we must use OF walking to find out hose
644  */
645  hose = pci_find_hose_for_OF_device(p2pbridge);
646  if (!hose) {
647  DBG("Can't find hose for PCI<->PCI bridge\n");
648  goto done;
649  }
650  if (early_read_config_word(hose, bus, devfn,
651  PCI_BRIDGE_CONTROL, &val) < 0) {
652  printk(KERN_ERR "init_p2pbridge: couldn't read bridge"
653  " control\n");
654  goto done;
655  }
657  early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
658 done:
659  of_node_put(p2pbridge);
660 }
661 
662 static void __init init_second_ohare(void)
663 {
664  struct device_node *np = of_find_node_by_name(NULL, "pci106b,7");
665  unsigned char bus, devfn;
666  unsigned short cmd;
667 
668  if (np == NULL)
669  return;
670 
671  /* This must run before we initialize the PICs since the second
672  * ohare hosts a PIC that will be accessed there.
673  */
674  if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
675  struct pci_controller* hose =
677  if (!hose) {
678  printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
679  of_node_put(np);
680  return;
681  }
682  early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
684  cmd &= ~PCI_COMMAND_IO;
685  early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
686  }
687  has_second_ohare = 1;
688  of_node_put(np);
689 }
690 
691 /*
692  * Some Apple desktop machines have a NEC PD720100A USB2 controller
693  * on the motherboard. Open Firmware, on these, will disable the
694  * EHCI part of it so it behaves like a pair of OHCI's. This fixup
695  * code re-enables it ;)
696  */
697 static void __init fixup_nec_usb2(void)
698 {
699  struct device_node *nec;
700 
701  for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
702  struct pci_controller *hose;
703  u32 data;
704  const u32 *prop;
705  u8 bus, devfn;
706 
707  prop = of_get_property(nec, "vendor-id", NULL);
708  if (prop == NULL)
709  continue;
710  if (0x1033 != *prop)
711  continue;
712  prop = of_get_property(nec, "device-id", NULL);
713  if (prop == NULL)
714  continue;
715  if (0x0035 != *prop)
716  continue;
717  prop = of_get_property(nec, "reg", NULL);
718  if (prop == NULL)
719  continue;
720  devfn = (prop[0] >> 8) & 0xff;
721  bus = (prop[0] >> 16) & 0xff;
722  if (PCI_FUNC(devfn) != 0)
723  continue;
724  hose = pci_find_hose_for_OF_device(nec);
725  if (!hose)
726  continue;
727  early_read_config_dword(hose, bus, devfn, 0xe4, &data);
728  if (data & 1UL) {
729  printk("Found NEC PD720100A USB2 chip with disabled"
730  " EHCI, fixing up...\n");
731  data &= ~1UL;
732  early_write_config_dword(hose, bus, devfn, 0xe4, data);
733  }
734  }
735 }
736 
737 static void __init setup_bandit(struct pci_controller *hose,
738  struct resource *addr)
739 {
740  hose->ops = &macrisc_pci_ops;
741  hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
742  hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
743  init_bandit(hose);
744 }
745 
746 static int __init setup_uninorth(struct pci_controller *hose,
747  struct resource *addr)
748 {
749  pci_add_flags(PCI_REASSIGN_ALL_BUS);
750  has_uninorth = 1;
751  hose->ops = &macrisc_pci_ops;
752  hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
753  hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
754  /* We "know" that the bridge at f2000000 has the PCI slots. */
755  return addr->start == 0xf2000000;
756 }
757 #endif /* CONFIG_PPC32 */
758 
759 #ifdef CONFIG_PPC64
760 static void __init setup_u3_agp(struct pci_controller* hose)
761 {
762  /* On G5, we move AGP up to high bus number so we don't need
763  * to reassign bus numbers for HT. If we ever have P2P bridges
764  * on AGP, we'll have to move pci_assign_all_busses to the
765  * pci_controller structure so we enable it for AGP and not for
766  * HT childs.
767  * We hard code the address because of the different size of
768  * the reg address cell, we shall fix that by killing struct
769  * reg_property and using some accessor functions instead
770  */
771  hose->first_busno = 0xf0;
772  hose->last_busno = 0xff;
773  has_uninorth = 1;
774  hose->ops = &macrisc_pci_ops;
775  hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
776  hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
777  u3_agp = hose;
778 }
779 
780 static void __init setup_u4_pcie(struct pci_controller* hose)
781 {
782  /* We currently only implement the "non-atomic" config space, to
783  * be optimised later.
784  */
785  hose->ops = &u4_pcie_pci_ops;
786  hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
787  hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
788 
789  /* The bus contains a bridge from root -> device, we need to
790  * make it visible on bus 0 so that we pick the right type
791  * of config cycles. If we didn't, we would have to force all
792  * config cycles to be type 1. So we override the "bus-range"
793  * property here
794  */
795  hose->first_busno = 0x00;
796  hose->last_busno = 0xff;
797 }
798 
799 static void __init parse_region_decode(struct pci_controller *hose,
800  u32 decode)
801 {
802  unsigned long base, end, next = -1;
803  int i, cur = -1;
804 
805  /* Iterate through all bits. We ignore the last bit as this region is
806  * reserved for the ROM among other niceties
807  */
808  for (i = 0; i < 31; i++) {
809  if ((decode & (0x80000000 >> i)) == 0)
810  continue;
811  if (i < 16) {
812  base = 0xf0000000 | (((u32)i) << 24);
813  end = base + 0x00ffffff;
814  } else {
815  base = ((u32)i-16) << 28;
816  end = base + 0x0fffffff;
817  }
818  if (base != next) {
819  if (++cur >= 3) {
820  printk(KERN_WARNING "PCI: Too many ranges !\n");
821  break;
822  }
823  hose->mem_resources[cur].flags = IORESOURCE_MEM;
824  hose->mem_resources[cur].name = hose->dn->full_name;
825  hose->mem_resources[cur].start = base;
826  hose->mem_resources[cur].end = end;
827  DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end);
828  } else {
829  DBG(" : -0x%08lx\n", end);
830  hose->mem_resources[cur].end = end;
831  }
832  next = end + 1;
833  }
834 }
835 
836 static void __init setup_u3_ht(struct pci_controller* hose)
837 {
838  struct device_node *np = hose->dn;
839  struct resource cfg_res, self_res;
840  u32 decode;
841 
842  hose->ops = &u3_ht_pci_ops;
843 
844  /* Get base addresses from OF tree
845  */
846  if (of_address_to_resource(np, 0, &cfg_res) ||
847  of_address_to_resource(np, 1, &self_res)) {
848  printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n");
849  return;
850  }
851 
852  /* Map external cfg space access into cfg_data and self registers
853  * into cfg_addr
854  */
855  hose->cfg_data = ioremap(cfg_res.start, 0x02000000);
856  hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res));
857 
858  /*
859  * /ht node doesn't expose a "ranges" property, we read the register
860  * that controls the decoding logic and use that for memory regions.
861  * The IO region is hard coded since it is fixed in HW as well.
862  */
863  hose->io_base_phys = 0xf4000000;
864  hose->pci_io_size = 0x00400000;
865  hose->io_resource.name = np->full_name;
866  hose->io_resource.start = 0;
867  hose->io_resource.end = 0x003fffff;
868  hose->io_resource.flags = IORESOURCE_IO;
869  hose->pci_mem_offset = 0;
870  hose->first_busno = 0;
871  hose->last_busno = 0xef;
872 
873  /* Note: fix offset when cfg_addr becomes a void * */
874  decode = in_be32(hose->cfg_addr + 0x80);
875 
876  DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode);
877 
878  /* NOTE: The decode register setup is a bit weird... region
879  * 0xf8000000 for example is marked as enabled in there while it's
880  & actually the memory controller registers.
881  * That means that we are incorrectly attributing it to HT.
882  *
883  * In a similar vein, region 0xf4000000 is actually the HT IO space but
884  * also marked as enabled in here and 0xf9000000 is used by some other
885  * internal bits of the northbridge.
886  *
887  * Unfortunately, we can't just mask out those bit as we would end
888  * up with more regions than we can cope (linux can only cope with
889  * 3 memory regions for a PHB at this stage).
890  *
891  * So for now, we just do a little hack. We happen to -know- that
892  * Apple firmware doesn't assign things below 0xfa000000 for that
893  * bridge anyway so we mask out all bits we don't want.
894  */
895  decode &= 0x003fffff;
896 
897  /* Now parse the resulting bits and build resources */
898  parse_region_decode(hose, decode);
899 }
900 #endif /* CONFIG_PPC64 */
901 
902 /*
903  * We assume that if we have a G3 powermac, we have one bridge called
904  * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
905  * if we have one or more bandit or chaos bridges, we don't have a MPC106.
906  */
907 static int __init pmac_add_bridge(struct device_node *dev)
908 {
909  int len;
910  struct pci_controller *hose;
911  struct resource rsrc;
912  char *disp_name;
913  const int *bus_range;
914  int primary = 1, has_address = 0;
915 
916  DBG("Adding PCI host bridge %s\n", dev->full_name);
917 
918  /* Fetch host bridge registers address */
919  has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
920 
921  /* Get bus range if any */
922  bus_range = of_get_property(dev, "bus-range", &len);
923  if (bus_range == NULL || len < 2 * sizeof(int)) {
924  printk(KERN_WARNING "Can't get bus-range for %s, assume"
925  " bus 0\n", dev->full_name);
926  }
927 
928  hose = pcibios_alloc_controller(dev);
929  if (!hose)
930  return -ENOMEM;
931  hose->first_busno = bus_range ? bus_range[0] : 0;
932  hose->last_busno = bus_range ? bus_range[1] : 0xff;
933 
934  disp_name = NULL;
935 
936  /* 64 bits only bridges */
937 #ifdef CONFIG_PPC64
938  if (of_device_is_compatible(dev, "u3-agp")) {
939  setup_u3_agp(hose);
940  disp_name = "U3-AGP";
941  primary = 0;
942  } else if (of_device_is_compatible(dev, "u3-ht")) {
943  setup_u3_ht(hose);
944  disp_name = "U3-HT";
945  primary = 1;
946  } else if (of_device_is_compatible(dev, "u4-pcie")) {
947  setup_u4_pcie(hose);
948  disp_name = "U4-PCIE";
949  primary = 0;
950  }
951  printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:"
952  " %d->%d\n", disp_name, hose->first_busno, hose->last_busno);
953 #endif /* CONFIG_PPC64 */
954 
955  /* 32 bits only bridges */
956 #ifdef CONFIG_PPC32
957  if (of_device_is_compatible(dev, "uni-north")) {
958  primary = setup_uninorth(hose, &rsrc);
959  disp_name = "UniNorth";
960  } else if (strcmp(dev->name, "pci") == 0) {
961  /* XXX assume this is a mpc106 (grackle) */
962  setup_grackle(hose);
963  disp_name = "Grackle (MPC106)";
964  } else if (strcmp(dev->name, "bandit") == 0) {
965  setup_bandit(hose, &rsrc);
966  disp_name = "Bandit";
967  } else if (strcmp(dev->name, "chaos") == 0) {
968  setup_chaos(hose, &rsrc);
969  disp_name = "Chaos";
970  primary = 0;
971  }
972  printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "
973  "Firmware bus number: %d->%d\n",
974  disp_name, (unsigned long long)rsrc.start, hose->first_busno,
975  hose->last_busno);
976 #endif /* CONFIG_PPC32 */
977 
978  DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
979  hose, hose->cfg_addr, hose->cfg_data);
980 
981  /* Interpret the "ranges" property */
982  /* This also maps the I/O region and sets isa_io/mem_base */
983  pci_process_bridge_OF_ranges(hose, dev, primary);
984 
985  /* Fixup "bus-range" OF property */
986  fixup_bus_range(dev);
987 
988  return 0;
989 }
990 
992 {
993 #ifdef CONFIG_PPC32
994  /* Fixup interrupt for the modem/ethernet combo controller.
995  * on machines with a second ohare chip.
996  * The number in the device tree (27) is bogus (correct for
997  * the ethernet-only board but not the combo ethernet/modem
998  * board). The real interrupt is 28 on the second controller
999  * -> 28+32 = 60.
1000  */
1001  if (has_second_ohare &&
1002  dev->vendor == PCI_VENDOR_ID_DEC &&
1004  dev->irq = irq_create_mapping(NULL, 60);
1006  }
1007 #endif /* CONFIG_PPC32 */
1008 }
1009 
1011 {
1012  struct device_node *np, *root;
1013  struct device_node *ht = NULL;
1014 
1015  pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN);
1016 
1017  root = of_find_node_by_path("/");
1018  if (root == NULL) {
1019  printk(KERN_CRIT "pmac_pci_init: can't find root "
1020  "of device tree\n");
1021  return;
1022  }
1023  for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
1024  if (np->name == NULL)
1025  continue;
1026  if (strcmp(np->name, "bandit") == 0
1027  || strcmp(np->name, "chaos") == 0
1028  || strcmp(np->name, "pci") == 0) {
1029  if (pmac_add_bridge(np) == 0)
1030  of_node_get(np);
1031  }
1032  if (strcmp(np->name, "ht") == 0) {
1033  of_node_get(np);
1034  ht = np;
1035  }
1036  }
1037  of_node_put(root);
1038 
1039 #ifdef CONFIG_PPC64
1040  /* Probe HT last as it relies on the agp resources to be already
1041  * setup
1042  */
1043  if (ht && pmac_add_bridge(ht) != 0)
1044  of_node_put(ht);
1045 
1046  /* Setup the linkage between OF nodes and PHBs */
1048 
1049  /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1050  * assume there is no P2P bridge on the AGP bus, which should be a
1051  * safe assumptions for now. We should do something better in the
1052  * future though
1053  */
1054  if (u3_agp) {
1055  struct device_node *np = u3_agp->dn;
1056  PCI_DN(np)->busno = 0xf0;
1057  for (np = np->child; np; np = np->sibling)
1058  PCI_DN(np)->busno = 0xf0;
1059  }
1060  /* pmac_check_ht_link(); */
1061 
1062 #else /* CONFIG_PPC64 */
1063  init_p2pbridge();
1064  init_second_ohare();
1065  fixup_nec_usb2();
1066 
1067  /* We are still having some issues with the Xserve G4, enabling
1068  * some offset between bus number and domains for now when we
1069  * assign all busses should help for now
1070  */
1071  if (pci_has_flag(PCI_REASSIGN_ALL_BUS))
1073 #endif
1074 }
1075 
1076 #ifdef CONFIG_PPC32
1077 int pmac_pci_enable_device_hook(struct pci_dev *dev)
1078 {
1079  struct device_node* node;
1080  int updatecfg = 0;
1081  int uninorth_child;
1082 
1083  node = pci_device_to_OF_node(dev);
1084 
1085  /* We don't want to enable USB controllers absent from the OF tree
1086  * (iBook second controller)
1087  */
1088  if (dev->vendor == PCI_VENDOR_ID_APPLE
1089  && dev->class == PCI_CLASS_SERIAL_USB_OHCI
1090  && !node) {
1091  printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1092  pci_name(dev));
1093  return -EINVAL;
1094  }
1095 
1096  if (!node)
1097  return 0;
1098 
1099  uninorth_child = node->parent &&
1100  of_device_is_compatible(node->parent, "uni-north");
1101 
1102  /* Firewire & GMAC were disabled after PCI probe, the driver is
1103  * claiming them, we must re-enable them now.
1104  */
1105  if (uninorth_child && !strcmp(node->name, "firewire") &&
1106  (of_device_is_compatible(node, "pci106b,18") ||
1107  of_device_is_compatible(node, "pci106b,30") ||
1108  of_device_is_compatible(node, "pci11c1,5811"))) {
1109  pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1110  pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1111  updatecfg = 1;
1112  }
1113  if (uninorth_child && !strcmp(node->name, "ethernet") &&
1114  of_device_is_compatible(node, "gmac")) {
1115  pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1116  updatecfg = 1;
1117  }
1118 
1119  /*
1120  * Fixup various header fields on 32 bits. We don't do that on
1121  * 64 bits as some of these have strange values behind the HT
1122  * bridge and we must not, for example, enable MWI or set the
1123  * cache line size on them.
1124  */
1125  if (updatecfg) {
1126  u16 cmd;
1127 
1128  pci_read_config_word(dev, PCI_COMMAND, &cmd);
1131  pci_write_config_word(dev, PCI_COMMAND, cmd);
1132  pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1133 
1134  pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1135  L1_CACHE_BYTES >> 2);
1136  }
1137 
1138  return 0;
1139 }
1140 
1141 void __devinit pmac_pci_fixup_ohci(struct pci_dev *dev)
1142 {
1143  struct device_node *node = pci_device_to_OF_node(dev);
1144 
1145  /* We don't want to assign resources to USB controllers
1146  * absent from the OF tree (iBook second controller)
1147  */
1148  if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node)
1149  dev->resource[0].flags = 0;
1150 }
1152 
1153 /* We power down some devices after they have been probed. They'll
1154  * be powered back on later on
1155  */
1157 {
1158  struct device_node* nd;
1159 
1160  for_each_node_by_name(nd, "firewire") {
1161  if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") ||
1162  of_device_is_compatible(nd, "pci106b,30") ||
1163  of_device_is_compatible(nd, "pci11c1,5811"))
1164  && of_device_is_compatible(nd->parent, "uni-north")) {
1165  pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1166  pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1167  }
1168  }
1169  for_each_node_by_name(nd, "ethernet") {
1170  if (nd->parent && of_device_is_compatible(nd, "gmac")
1171  && of_device_is_compatible(nd->parent, "uni-north"))
1172  pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1173  }
1174 }
1175 
1176 void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1177 {
1178  if (!machine_is(powermac))
1179  return;
1180  /*
1181  * Fix the interrupt routing on the various cardbus bridges
1182  * used on powerbooks
1183  */
1184  if (dev->vendor != PCI_VENDOR_ID_TI)
1185  return;
1186  if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1187  dev->device == PCI_DEVICE_ID_TI_1131) {
1188  u8 val;
1189  /* Enable PCI interrupt */
1190  if (pci_read_config_byte(dev, 0x91, &val) == 0)
1191  pci_write_config_byte(dev, 0x91, val | 0x30);
1192  /* Disable ISA interrupt mode */
1193  if (pci_read_config_byte(dev, 0x92, &val) == 0)
1194  pci_write_config_byte(dev, 0x92, val & ~0x06);
1195  }
1196  if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1197  dev->device == PCI_DEVICE_ID_TI_1211 ||
1198  dev->device == PCI_DEVICE_ID_TI_1410 ||
1199  dev->device == PCI_DEVICE_ID_TI_1510) {
1200  u8 val;
1201  /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1202  signal out the MFUNC0 pin */
1203  if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1204  pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1205  /* Disable ISA interrupt mode */
1206  if (pci_read_config_byte(dev, 0x92, &val) == 0)
1207  pci_write_config_byte(dev, 0x92, val & ~0x06);
1208  }
1209 }
1210 
1211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1212 
1213 void pmac_pci_fixup_pciata(struct pci_dev* dev)
1214 {
1215  u8 progif = 0;
1216 
1217  /*
1218  * On PowerMacs, we try to switch any PCI ATA controller to
1219  * fully native mode
1220  */
1221  if (!machine_is(powermac))
1222  return;
1223 
1224  /* Some controllers don't have the class IDE */
1225  if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1226  switch(dev->device) {
1239  goto good;
1240  }
1241  /* Others, check PCI class */
1242  if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1243  return;
1244  good:
1245  pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1246  if ((progif & 5) != 5) {
1247  printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n",
1248  pci_name(dev));
1249  (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1250  if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1251  (progif & 5) != 5)
1252  printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1253  else {
1254  /* Clear IO BARs, they will be reassigned */
1255  pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
1256  pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
1257  pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);
1258  pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);
1259  }
1260  }
1261 }
1262 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1263 #endif /* CONFIG_PPC32 */
1264 
1265 /*
1266  * Disable second function on K2-SATA, it's broken
1267  * and disable IO BARs on first one
1268  */
1269 static void fixup_k2_sata(struct pci_dev* dev)
1270 {
1271  int i;
1272  u16 cmd;
1273 
1274  if (PCI_FUNC(dev->devfn) > 0) {
1275  pci_read_config_word(dev, PCI_COMMAND, &cmd);
1276  cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1277  pci_write_config_word(dev, PCI_COMMAND, cmd);
1278  for (i = 0; i < 6; i++) {
1279  dev->resource[i].start = dev->resource[i].end = 0;
1280  dev->resource[i].flags = 0;
1281  pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1282  0);
1283  }
1284  } else {
1285  pci_read_config_word(dev, PCI_COMMAND, &cmd);
1286  cmd &= ~PCI_COMMAND_IO;
1287  pci_write_config_word(dev, PCI_COMMAND, cmd);
1288  for (i = 0; i < 5; i++) {
1289  dev->resource[i].start = dev->resource[i].end = 0;
1290  dev->resource[i].flags = 0;
1291  pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1292  0);
1293  }
1294  }
1295 }
1296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1297 
1298 /*
1299  * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't
1300  * configured by the firmware. The bridge itself seems to ignore them but it
1301  * causes problems with Linux which then re-assigns devices below the bridge,
1302  * thus changing addresses of those devices from what was in the device-tree,
1303  * which sucks when those are video cards using offb
1304  *
1305  * We could just mark it transparent but I prefer fixing up the resources to
1306  * properly show what's going on here, as I have some doubts about having them
1307  * badly configured potentially being an issue for DMA.
1308  *
1309  * We leave PIO alone, it seems to be fine
1310  *
1311  * Oh and there's another funny bug. The OF properties advertize the region
1312  * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's
1313  * actually not true, this region is the memory mapped config space. So we
1314  * also need to filter it out or we'll map things in the wrong place.
1315  */
1316 static void fixup_u4_pcie(struct pci_dev* dev)
1317 {
1318  struct pci_controller *host = pci_bus_to_host(dev->bus);
1319  struct resource *region = NULL;
1320  u32 reg;
1321  int i;
1322 
1323  /* Only do that on PowerMac */
1324  if (!machine_is(powermac))
1325  return;
1326 
1327  /* Find the largest MMIO region */
1328  for (i = 0; i < 3; i++) {
1329  struct resource *r = &host->mem_resources[i];
1330  if (!(r->flags & IORESOURCE_MEM))
1331  continue;
1332  /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they
1333  * are reserved by HW for other things
1334  */
1335  if (r->start >= 0xf0000000 && r->start < 0xf3000000)
1336  continue;
1337  if (!region || resource_size(r) > resource_size(region))
1338  region = r;
1339  }
1340  /* Nothing found, bail */
1341  if (region == 0)
1342  return;
1343 
1344  /* Print things out */
1345  printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region);
1346 
1347  /* Fixup bridge config space. We know it's a Mac, resource aren't
1348  * offset so let's just blast them as-is. We also know that they
1349  * fit in 32 bits
1350  */
1351  reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);
1352  pci_write_config_dword(dev, PCI_MEMORY_BASE, reg);
1353  pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);
1354  pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
1355  pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);
1356 }