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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | ATMCI_CR 0x0000 /* Control */ |
| #define | ATMCI_CR_MCIEN ( 1 << 0) /* MCI Enable */ |
| #define | ATMCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */ |
| #define | ATMCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */ |
| #define | ATMCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */ |
| #define | ATMCI_CR_SWRST ( 1 << 7) /* Software Reset */ |
| #define | ATMCI_MR 0x0004 /* Mode */ |
| #define | ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */ |
| #define | ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */ |
| #define | ATMCI_MR_RDPROOF ( 1 << 11) /* Read Proof */ |
| #define | ATMCI_MR_WRPROOF ( 1 << 12) /* Write Proof */ |
| #define | ATMCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */ |
| #define | ATMCI_MR_PDCPADV ( 1 << 14) /* Padding Value */ |
| #define | ATMCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */ |
| #define | ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */ |
| #define | ATMCI_DTOR 0x0008 /* Data Timeout */ |
| #define | ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */ |
| #define | ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */ |
| #define | ATMCI_SDCR 0x000c /* SD Card / SDIO */ |
| #define | ATMCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */ |
| #define | ATMCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */ |
| #define | ATMCI_SDCSEL_MASK ( 3 << 0) |
| #define | ATMCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */ |
| #define | ATMCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */ |
| #define | ATMCI_SDCBUS_8BIT ( 3 << 6) /* 8-bit data bus[2] */ |
| #define | ATMCI_SDCBUS_MASK ( 3 << 6) |
| #define | ATMCI_ARGR 0x0010 /* Command Argument */ |
| #define | ATMCI_CMDR 0x0014 /* Command */ |
| #define | ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */ |
| #define | ATMCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */ |
| #define | ATMCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */ |
| #define | ATMCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */ |
| #define | ATMCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */ |
| #define | ATMCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */ |
| #define | ATMCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */ |
| #define | ATMCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */ |
| #define | ATMCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */ |
| #define | ATMCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */ |
| #define | ATMCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */ |
| #define | ATMCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */ |
| #define | ATMCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */ |
| #define | ATMCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */ |
| #define | ATMCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */ |
| #define | ATMCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */ |
| #define | ATMCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */ |
| #define | ATMCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */ |
| #define | ATMCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */ |
| #define | ATMCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */ |
| #define | ATMCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */ |
| #define | ATMCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */ |
| #define | ATMCI_BLKR 0x0018 /* Block */ |
| #define | ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */ |
| #define | ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */ |
| #define | ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */ |
| #define | ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */ |
| #define | ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */ |
| #define | ATMCI_RSPR 0x0020 /* Response 0 */ |
| #define | ATMCI_RSPR1 0x0024 /* Response 1 */ |
| #define | ATMCI_RSPR2 0x0028 /* Response 2 */ |
| #define | ATMCI_RSPR3 0x002c /* Response 3 */ |
| #define | ATMCI_RDR 0x0030 /* Receive Data */ |
| #define | ATMCI_TDR 0x0034 /* Transmit Data */ |
| #define | ATMCI_SR 0x0040 /* Status */ |
| #define | ATMCI_IER 0x0044 /* Interrupt Enable */ |
| #define | ATMCI_IDR 0x0048 /* Interrupt Disable */ |
| #define | ATMCI_IMR 0x004c /* Interrupt Mask */ |
| #define | ATMCI_CMDRDY ( 1 << 0) /* Command Ready */ |
| #define | ATMCI_RXRDY ( 1 << 1) /* Receiver Ready */ |
| #define | ATMCI_TXRDY ( 1 << 2) /* Transmitter Ready */ |
| #define | ATMCI_BLKE ( 1 << 3) /* Data Block Ended */ |
| #define | ATMCI_DTIP ( 1 << 4) /* Data Transfer In Progress */ |
| #define | ATMCI_NOTBUSY ( 1 << 5) /* Data Not Busy */ |
| #define | ATMCI_ENDRX ( 1 << 6) /* End of RX Buffer */ |
| #define | ATMCI_ENDTX ( 1 << 7) /* End of TX Buffer */ |
| #define | ATMCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */ |
| #define | ATMCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */ |
| #define | ATMCI_SDIOWAIT ( 1 << 12) /* SDIO Read Wait Operation Status */ |
| #define | ATMCI_CSRCV ( 1 << 13) /* CE-ATA Completion Signal Received */ |
| #define | ATMCI_RXBUFF ( 1 << 14) /* RX Buffer Full */ |
| #define | ATMCI_TXBUFE ( 1 << 15) /* TX Buffer Empty */ |
| #define | ATMCI_RINDE ( 1 << 16) /* Response Index Error */ |
| #define | ATMCI_RDIRE ( 1 << 17) /* Response Direction Error */ |
| #define | ATMCI_RCRCE ( 1 << 18) /* Response CRC Error */ |
| #define | ATMCI_RENDE ( 1 << 19) /* Response End Bit Error */ |
| #define | ATMCI_RTOE ( 1 << 20) /* Response Time-Out Error */ |
| #define | ATMCI_DCRCE ( 1 << 21) /* Data CRC Error */ |
| #define | ATMCI_DTOE ( 1 << 22) /* Data Time-Out Error */ |
| #define | ATMCI_CSTOE ( 1 << 23) /* Completion Signal Time-out Error */ |
| #define | ATMCI_BLKOVRE ( 1 << 24) /* DMA Block Overrun Error */ |
| #define | ATMCI_DMADONE ( 1 << 25) /* DMA Transfer Done */ |
| #define | ATMCI_FIFOEMPTY ( 1 << 26) /* FIFO Empty Flag */ |
| #define | ATMCI_XFRDONE ( 1 << 27) /* Transfer Done Flag */ |
| #define | ATMCI_ACKRCV ( 1 << 28) /* Boot Operation Acknowledge Received */ |
| #define | ATMCI_ACKRCVE ( 1 << 29) /* Boot Operation Acknowledge Error */ |
| #define | ATMCI_OVRE ( 1 << 30) /* RX Overrun Error */ |
| #define | ATMCI_UNRE ( 1 << 31) /* TX Underrun Error */ |
| #define | ATMCI_DMA 0x0050 /* DMA Configuration[2] */ |
| #define | ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */ |
| #define | ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */ |
| #define | ATMCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */ |
| #define | ATMCI_CFG 0x0054 /* Configuration[2] */ |
| #define | ATMCI_CFG_FIFOMODE_1DATA ( 1 << 0) /* MCI Internal FIFO control mode */ |
| #define | ATMCI_CFG_FERRCTRL_COR ( 1 << 4) /* Flow Error flag reset control mode */ |
| #define | ATMCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */ |
| #define | ATMCI_CFG_LSYNC ( 1 << 12) /* Synchronize on the last block */ |
| #define | ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */ |
| #define | ATMCI_WP_EN ( 1 << 0) /* WP Enable */ |
| #define | ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */ |
| #define | ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */ |
| #define | ATMCI_GET_WP_VS(x) ((x) & 0x0f) |
| #define | ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff) |
| #define | ATMCI_VERSION 0x00FC /* Version */ |
| #define | ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */ |
| #define | ATMCI_REGS_SIZE 0x100 |
| #define | atmci_readl(port, reg) __raw_readl((port)->regs + reg) |
| #define | atmci_writel(port, reg, value) __raw_writel((value), (port)->regs + reg) |
| #define | ATMCI_PDC_CONNECTED 1 |
| #define ATMCI_ACKRCV ( 1 << 28) /* Boot Operation Acknowledge Received */ |
Definition at line 112 of file atmel-mci-regs.h.
| #define ATMCI_ACKRCVE ( 1 << 29) /* Boot Operation Acknowledge Error */ |
Definition at line 113 of file atmel-mci-regs.h.
| #define ATMCI_ARGR 0x0010 /* Command Argument */ |
Definition at line 46 of file atmel-mci-regs.h.
Definition at line 71 of file atmel-mci-regs.h.
| #define ATMCI_BLKE ( 1 << 3) /* Data Block Ended */ |
Definition at line 89 of file atmel-mci-regs.h.
Definition at line 72 of file atmel-mci-regs.h.
Definition at line 108 of file atmel-mci-regs.h.
| #define ATMCI_BLKR 0x0018 /* Block */ |
Definition at line 70 of file atmel-mci-regs.h.
| #define ATMCI_CFG 0x0054 /* Configuration[2] */ |
Definition at line 120 of file atmel-mci-regs.h.
Definition at line 122 of file atmel-mci-regs.h.
Definition at line 121 of file atmel-mci-regs.h.
| #define ATMCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */ |
Definition at line 123 of file atmel-mci-regs.h.
Definition at line 124 of file atmel-mci-regs.h.
| #define ATMCI_CMDR 0x0014 /* Command */ |
Definition at line 47 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */ |
Definition at line 63 of file atmel-mci-regs.h.
Definition at line 48 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */ |
Definition at line 57 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */ |
Definition at line 58 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */ |
Definition at line 64 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */ |
Definition at line 56 of file atmel-mci-regs.h.
Definition at line 51 of file atmel-mci-regs.h.
Definition at line 50 of file atmel-mci-regs.h.
Definition at line 49 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */ |
Definition at line 67 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */ |
Definition at line 66 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */ |
Definition at line 69 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */ |
Definition at line 68 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */ |
Definition at line 52 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */ |
Definition at line 54 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */ |
Definition at line 55 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */ |
Definition at line 53 of file atmel-mci-regs.h.
Definition at line 59 of file atmel-mci-regs.h.
| #define ATMCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */ |
Definition at line 60 of file atmel-mci-regs.h.
Definition at line 65 of file atmel-mci-regs.h.
Definition at line 62 of file atmel-mci-regs.h.
Definition at line 61 of file atmel-mci-regs.h.
Definition at line 86 of file atmel-mci-regs.h.
| #define ATMCI_CR 0x0000 /* Control */ |
Definition at line 20 of file atmel-mci-regs.h.
| #define ATMCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */ |
Definition at line 22 of file atmel-mci-regs.h.
| #define ATMCI_CR_MCIEN ( 1 << 0) /* MCI Enable */ |
Definition at line 21 of file atmel-mci-regs.h.
| #define ATMCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */ |
Definition at line 24 of file atmel-mci-regs.h.
| #define ATMCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */ |
Definition at line 23 of file atmel-mci-regs.h.
| #define ATMCI_CR_SWRST ( 1 << 7) /* Software Reset */ |
Definition at line 25 of file atmel-mci-regs.h.
Definition at line 97 of file atmel-mci-regs.h.
Definition at line 74 of file atmel-mci-regs.h.
Definition at line 107 of file atmel-mci-regs.h.
Definition at line 75 of file atmel-mci-regs.h.
| #define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */ |
Definition at line 73 of file atmel-mci-regs.h.
Definition at line 105 of file atmel-mci-regs.h.
| #define ATMCI_DMA 0x0050 /* DMA Configuration[2] */ |
Definition at line 116 of file atmel-mci-regs.h.
Definition at line 118 of file atmel-mci-regs.h.
Definition at line 117 of file atmel-mci-regs.h.
| #define ATMCI_DMADONE ( 1 << 25) /* DMA Transfer Done */ |
Definition at line 109 of file atmel-mci-regs.h.
| #define ATMCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */ |
Definition at line 119 of file atmel-mci-regs.h.
| #define ATMCI_DTIP ( 1 << 4) /* Data Transfer In Progress */ |
Definition at line 90 of file atmel-mci-regs.h.
Definition at line 36 of file atmel-mci-regs.h.
Definition at line 106 of file atmel-mci-regs.h.
Definition at line 37 of file atmel-mci-regs.h.
| #define ATMCI_DTOR 0x0008 /* Data Timeout */ |
Definition at line 35 of file atmel-mci-regs.h.
| #define ATMCI_ENDRX ( 1 << 6) /* End of RX Buffer */ |
Definition at line 92 of file atmel-mci-regs.h.
| #define ATMCI_ENDTX ( 1 << 7) /* End of TX Buffer */ |
Definition at line 93 of file atmel-mci-regs.h.
| #define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */ |
Definition at line 132 of file atmel-mci-regs.h.
| #define ATMCI_FIFOEMPTY ( 1 << 26) /* FIFO Empty Flag */ |
Definition at line 110 of file atmel-mci-regs.h.
Definition at line 129 of file atmel-mci-regs.h.
Definition at line 130 of file atmel-mci-regs.h.
| #define ATMCI_IDR 0x0048 /* Interrupt Disable */ |
Definition at line 84 of file atmel-mci-regs.h.
| #define ATMCI_IER 0x0044 /* Interrupt Enable */ |
Definition at line 83 of file atmel-mci-regs.h.
| #define ATMCI_IMR 0x004c /* Interrupt Mask */ |
Definition at line 85 of file atmel-mci-regs.h.
| #define ATMCI_MR 0x0004 /* Mode */ |
Definition at line 26 of file atmel-mci-regs.h.
Definition at line 27 of file atmel-mci-regs.h.
Definition at line 34 of file atmel-mci-regs.h.
| #define ATMCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */ |
Definition at line 31 of file atmel-mci-regs.h.
| #define ATMCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */ |
Definition at line 33 of file atmel-mci-regs.h.
| #define ATMCI_MR_PDCPADV ( 1 << 14) /* Padding Value */ |
Definition at line 32 of file atmel-mci-regs.h.
Definition at line 28 of file atmel-mci-regs.h.
| #define ATMCI_MR_RDPROOF ( 1 << 11) /* Read Proof */ |
Definition at line 29 of file atmel-mci-regs.h.
| #define ATMCI_MR_WRPROOF ( 1 << 12) /* Write Proof */ |
Definition at line 30 of file atmel-mci-regs.h.
| #define ATMCI_NOTBUSY ( 1 << 5) /* Data Not Busy */ |
Definition at line 91 of file atmel-mci-regs.h.
Definition at line 114 of file atmel-mci-regs.h.
| #define ATMCI_PDC_CONNECTED 1 |
Definition at line 147 of file atmel-mci-regs.h.
Definition at line 102 of file atmel-mci-regs.h.
| #define ATMCI_RDIRE ( 1 << 17) /* Response Direction Error */ |
Definition at line 101 of file atmel-mci-regs.h.
| #define ATMCI_RDR 0x0030 /* Receive Data */ |
Definition at line 80 of file atmel-mci-regs.h.
Definition at line 138 of file atmel-mci-regs.h.
| #define ATMCI_REGS_SIZE 0x100 |
Definition at line 135 of file atmel-mci-regs.h.
Definition at line 103 of file atmel-mci-regs.h.
| #define ATMCI_RINDE ( 1 << 16) /* Response Index Error */ |
Definition at line 100 of file atmel-mci-regs.h.
| #define ATMCI_RSPR 0x0020 /* Response 0 */ |
Definition at line 76 of file atmel-mci-regs.h.
| #define ATMCI_RSPR1 0x0024 /* Response 1 */ |
Definition at line 77 of file atmel-mci-regs.h.
| #define ATMCI_RSPR2 0x0028 /* Response 2 */ |
Definition at line 78 of file atmel-mci-regs.h.
| #define ATMCI_RSPR3 0x002c /* Response 3 */ |
Definition at line 79 of file atmel-mci-regs.h.
Definition at line 104 of file atmel-mci-regs.h.
| #define ATMCI_RXBUFF ( 1 << 14) /* RX Buffer Full */ |
Definition at line 98 of file atmel-mci-regs.h.
| #define ATMCI_RXRDY ( 1 << 1) /* Receiver Ready */ |
Definition at line 87 of file atmel-mci-regs.h.
Definition at line 42 of file atmel-mci-regs.h.
Definition at line 43 of file atmel-mci-regs.h.
Definition at line 44 of file atmel-mci-regs.h.
| #define ATMCI_SDCBUS_MASK ( 3 << 6) |
Definition at line 45 of file atmel-mci-regs.h.
| #define ATMCI_SDCR 0x000c /* SD Card / SDIO */ |
Definition at line 38 of file atmel-mci-regs.h.
| #define ATMCI_SDCSEL_MASK ( 3 << 0) |
Definition at line 41 of file atmel-mci-regs.h.
Definition at line 39 of file atmel-mci-regs.h.
Definition at line 40 of file atmel-mci-regs.h.
Definition at line 94 of file atmel-mci-regs.h.
Definition at line 95 of file atmel-mci-regs.h.
Definition at line 96 of file atmel-mci-regs.h.
| #define ATMCI_SR 0x0040 /* Status */ |
Definition at line 82 of file atmel-mci-regs.h.
| #define ATMCI_TDR 0x0034 /* Transmit Data */ |
Definition at line 81 of file atmel-mci-regs.h.
| #define ATMCI_TXBUFE ( 1 << 15) /* TX Buffer Empty */ |
Definition at line 99 of file atmel-mci-regs.h.
| #define ATMCI_TXRDY ( 1 << 2) /* Transmitter Ready */ |
Definition at line 88 of file atmel-mci-regs.h.
Definition at line 115 of file atmel-mci-regs.h.
| #define ATMCI_VERSION 0x00FC /* Version */ |
Definition at line 131 of file atmel-mci-regs.h.
| #define ATMCI_WP_EN ( 1 << 0) /* WP Enable */ |
Definition at line 126 of file atmel-mci-regs.h.
| #define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */ |
Definition at line 127 of file atmel-mci-regs.h.
| #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */ |
Definition at line 125 of file atmel-mci-regs.h.
| #define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */ |
Definition at line 128 of file atmel-mci-regs.h.
Definition at line 140 of file atmel-mci-regs.h.
| #define ATMCI_XFRDONE ( 1 << 27) /* Transfer Done Flag */ |
Definition at line 111 of file atmel-mci-regs.h.
1.8.2