26 #include <linux/pci.h>
27 #include <linux/slab.h>
28 #include <linux/gameport.h>
29 #include <linux/module.h>
63 #define CS4281_BA0_SIZE 0x1000
64 #define CS4281_BA1_SIZE 0x10000
69 #define BA0_HISR 0x0000
70 #define BA0_HISR_INTENA (1<<31)
71 #define BA0_HISR_MIDI (1<<22)
72 #define BA0_HISR_FIFOI (1<<20)
73 #define BA0_HISR_DMAI (1<<18)
74 #define BA0_HISR_FIFO(c) (1<<(12+(c)))
75 #define BA0_HISR_DMA(c) (1<<(8+(c)))
76 #define BA0_HISR_GPPI (1<<5)
77 #define BA0_HISR_GPSI (1<<4)
78 #define BA0_HISR_GP3I (1<<3)
79 #define BA0_HISR_GP1I (1<<2)
80 #define BA0_HISR_VUPI (1<<1)
81 #define BA0_HISR_VDNI (1<<0)
83 #define BA0_HICR 0x0008
84 #define BA0_HICR_CHGM (1<<1)
85 #define BA0_HICR_IEV (1<<0)
86 #define BA0_HICR_EOI (3<<0)
88 #define BA0_HIMR 0x000c
91 #define BA0_IIER 0x0010
93 #define BA0_HDSR0 0x00f0
94 #define BA0_HDSR1 0x00f4
95 #define BA0_HDSR2 0x00f8
96 #define BA0_HDSR3 0x00fc
98 #define BA0_HDSR_CH1P (1<<25)
99 #define BA0_HDSR_CH2P (1<<24)
100 #define BA0_HDSR_DHTC (1<<17)
101 #define BA0_HDSR_DTC (1<<16)
102 #define BA0_HDSR_DRUN (1<<15)
103 #define BA0_HDSR_RQ (1<<7)
105 #define BA0_DCA0 0x0110
106 #define BA0_DCC0 0x0114
107 #define BA0_DBA0 0x0118
108 #define BA0_DBC0 0x011c
109 #define BA0_DCA1 0x0120
110 #define BA0_DCC1 0x0124
111 #define BA0_DBA1 0x0128
112 #define BA0_DBC1 0x012c
113 #define BA0_DCA2 0x0130
114 #define BA0_DCC2 0x0134
115 #define BA0_DBA2 0x0138
116 #define BA0_DBC2 0x013c
117 #define BA0_DCA3 0x0140
118 #define BA0_DCC3 0x0144
119 #define BA0_DBA3 0x0148
120 #define BA0_DBC3 0x014c
121 #define BA0_DMR0 0x0150
122 #define BA0_DCR0 0x0154
123 #define BA0_DMR1 0x0158
124 #define BA0_DCR1 0x015c
125 #define BA0_DMR2 0x0160
126 #define BA0_DCR2 0x0164
127 #define BA0_DMR3 0x0168
128 #define BA0_DCR3 0x016c
130 #define BA0_DMR_DMA (1<<29)
131 #define BA0_DMR_POLL (1<<28)
132 #define BA0_DMR_TBC (1<<25)
133 #define BA0_DMR_CBC (1<<24)
134 #define BA0_DMR_SWAPC (1<<22)
135 #define BA0_DMR_SIZE20 (1<<20)
136 #define BA0_DMR_USIGN (1<<19)
137 #define BA0_DMR_BEND (1<<18)
138 #define BA0_DMR_MONO (1<<17)
139 #define BA0_DMR_SIZE8 (1<<16)
140 #define BA0_DMR_TYPE_DEMAND (0<<6)
141 #define BA0_DMR_TYPE_SINGLE (1<<6)
142 #define BA0_DMR_TYPE_BLOCK (2<<6)
143 #define BA0_DMR_TYPE_CASCADE (3<<6)
144 #define BA0_DMR_DEC (1<<5)
145 #define BA0_DMR_AUTO (1<<4)
146 #define BA0_DMR_TR_VERIFY (0<<2)
147 #define BA0_DMR_TR_WRITE (1<<2)
148 #define BA0_DMR_TR_READ (2<<2)
150 #define BA0_DCR_HTCIE (1<<17)
151 #define BA0_DCR_TCIE (1<<16)
152 #define BA0_DCR_MSK (1<<0)
154 #define BA0_FCR0 0x0180
155 #define BA0_FCR1 0x0184
156 #define BA0_FCR2 0x0188
157 #define BA0_FCR3 0x018c
159 #define BA0_FCR_FEN (1<<31)
160 #define BA0_FCR_DACZ (1<<30)
161 #define BA0_FCR_PSH (1<<29)
162 #define BA0_FCR_RS(x) (((x)&0x1f)<<24)
163 #define BA0_FCR_LS(x) (((x)&0x1f)<<16)
164 #define BA0_FCR_SZ(x) (((x)&0x7f)<<8)
165 #define BA0_FCR_OF(x) (((x)&0x7f)<<0)
167 #define BA0_FPDR0 0x0190
168 #define BA0_FPDR1 0x0194
169 #define BA0_FPDR2 0x0198
170 #define BA0_FPDR3 0x019c
172 #define BA0_FCHS 0x020c
173 #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3)))
174 #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3)))
175 #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3)))
176 #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3)))
177 #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3)))
178 #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3)))
179 #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3)))
180 #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3)))
182 #define BA0_FSIC0 0x0210
183 #define BA0_FSIC1 0x0214
184 #define BA0_FSIC2 0x0218
185 #define BA0_FSIC3 0x021c
187 #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24)
188 #define BA0_FSIC_FORIE (1<<23)
189 #define BA0_FSIC_FURIE (1<<22)
190 #define BA0_FSIC_FSCIE (1<<16)
191 #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8)
192 #define BA0_FSIC_FOR (1<<7)
193 #define BA0_FSIC_FUR (1<<6)
194 #define BA0_FSIC_FSCR (1<<0)
196 #define BA0_PMCS 0x0344
197 #define BA0_CWPR 0x03e0
199 #define BA0_EPPMC 0x03e4
200 #define BA0_EPPMC_FPDN (1<<14)
202 #define BA0_GPIOR 0x03e8
204 #define BA0_SPMC 0x03ec
205 #define BA0_SPMC_GIPPEN (1<<15)
206 #define BA0_SPMC_GISPEN (1<<14)
207 #define BA0_SPMC_EESPD (1<<9)
208 #define BA0_SPMC_ASDI2E (1<<8)
209 #define BA0_SPMC_ASDO (1<<7)
210 #define BA0_SPMC_WUP2 (1<<3)
211 #define BA0_SPMC_WUP1 (1<<2)
212 #define BA0_SPMC_ASYNC (1<<1)
213 #define BA0_SPMC_RSTN (1<<0)
215 #define BA0_CFLR 0x03f0
216 #define BA0_CFLR_DEFAULT 0x00000001
217 #define BA0_IISR 0x03f4
218 #define BA0_TMS 0x03f8
219 #define BA0_SSVID 0x03fc
221 #define BA0_CLKCR1 0x0400
222 #define BA0_CLKCR1_CLKON (1<<25)
223 #define BA0_CLKCR1_DLLRDY (1<<24)
224 #define BA0_CLKCR1_DLLOS (1<<6)
225 #define BA0_CLKCR1_SWCE (1<<5)
226 #define BA0_CLKCR1_DLLP (1<<4)
227 #define BA0_CLKCR1_DLLSS (((x)&3)<<3)
229 #define BA0_FRR 0x0410
230 #define BA0_SLT12O 0x041c
232 #define BA0_SERMC 0x0420
233 #define BA0_SERMC_FCRN (1<<27)
234 #define BA0_SERMC_ODSEN2 (1<<25)
235 #define BA0_SERMC_ODSEN1 (1<<24)
236 #define BA0_SERMC_SXLB (1<<21)
237 #define BA0_SERMC_SLB (1<<20)
238 #define BA0_SERMC_LOVF (1<<19)
239 #define BA0_SERMC_TCID(x) (((x)&3)<<16)
240 #define BA0_SERMC_PXLB (5<<1)
241 #define BA0_SERMC_PLB (4<<1)
242 #define BA0_SERMC_PTC (7<<1)
243 #define BA0_SERMC_PTC_AC97 (1<<1)
244 #define BA0_SERMC_MSPE (1<<0)
246 #define BA0_SERC1 0x0428
247 #define BA0_SERC1_SO1F(x) (((x)&7)>>1)
248 #define BA0_SERC1_AC97 (1<<1)
249 #define BA0_SERC1_SO1EN (1<<0)
251 #define BA0_SERC2 0x042c
252 #define BA0_SERC2_SI1F(x) (((x)&7)>>1)
253 #define BA0_SERC2_AC97 (1<<1)
254 #define BA0_SERC2_SI1EN (1<<0)
256 #define BA0_SLT12M 0x045c
258 #define BA0_ACCTL 0x0460
259 #define BA0_ACCTL_TC (1<<6)
260 #define BA0_ACCTL_CRW (1<<4)
261 #define BA0_ACCTL_DCV (1<<3)
262 #define BA0_ACCTL_VFRM (1<<2)
263 #define BA0_ACCTL_ESYN (1<<1)
265 #define BA0_ACSTS 0x0464
266 #define BA0_ACSTS_VSTS (1<<1)
267 #define BA0_ACSTS_CRDY (1<<0)
269 #define BA0_ACOSV 0x0468
270 #define BA0_ACOSV_SLV(x) (1<<((x)-3))
272 #define BA0_ACCAD 0x046c
273 #define BA0_ACCDA 0x0470
275 #define BA0_ACISV 0x0474
276 #define BA0_ACISV_SLV(x) (1<<((x)-3))
278 #define BA0_ACSAD 0x0478
279 #define BA0_ACSDA 0x047c
280 #define BA0_JSPT 0x0480
281 #define BA0_JSCTL 0x0484
282 #define BA0_JSC1 0x0488
283 #define BA0_JSC2 0x048c
284 #define BA0_JSIO 0x04a0
286 #define BA0_MIDCR 0x0490
287 #define BA0_MIDCR_MRST (1<<5)
288 #define BA0_MIDCR_MLB (1<<4)
289 #define BA0_MIDCR_TIE (1<<3)
290 #define BA0_MIDCR_RIE (1<<2)
291 #define BA0_MIDCR_RXE (1<<1)
292 #define BA0_MIDCR_TXE (1<<0)
294 #define BA0_MIDCMD 0x0494
296 #define BA0_MIDSR 0x0494
297 #define BA0_MIDSR_RDA (1<<15)
298 #define BA0_MIDSR_TBE (1<<14)
299 #define BA0_MIDSR_RBE (1<<7)
300 #define BA0_MIDSR_TBF (1<<6)
302 #define BA0_MIDWP 0x0498
303 #define BA0_MIDRP 0x049c
305 #define BA0_AODSD1 0x04a8
306 #define BA0_AODSD1_NDS(x) (1<<((x)-3))
308 #define BA0_AODSD2 0x04ac
309 #define BA0_AODSD2_NDS(x) (1<<((x)-3))
311 #define BA0_CFGI 0x04b0
312 #define BA0_SLT12M2 0x04dc
313 #define BA0_ACSTS2 0x04e4
314 #define BA0_ACISV2 0x04f4
315 #define BA0_ACSAD2 0x04f8
316 #define BA0_ACSDA2 0x04fc
317 #define BA0_FMSR 0x0730
318 #define BA0_B0AP 0x0730
319 #define BA0_FMDP 0x0734
320 #define BA0_B1AP 0x0738
321 #define BA0_B1DP 0x073c
323 #define BA0_SSPM 0x0740
324 #define BA0_SSPM_MIXEN (1<<6)
325 #define BA0_SSPM_CSRCEN (1<<5)
326 #define BA0_SSPM_PSRCEN (1<<4)
327 #define BA0_SSPM_JSEN (1<<3)
328 #define BA0_SSPM_ACLEN (1<<2)
329 #define BA0_SSPM_FMEN (1<<1)
331 #define BA0_DACSR 0x0744
332 #define BA0_ADCSR 0x0748
334 #define BA0_SSCR 0x074c
335 #define BA0_SSCR_HVS1 (1<<23)
336 #define BA0_SSCR_MVCS (1<<19)
337 #define BA0_SSCR_MVLD (1<<18)
338 #define BA0_SSCR_MVAD (1<<17)
339 #define BA0_SSCR_MVMD (1<<16)
340 #define BA0_SSCR_XLPSRC (1<<8)
341 #define BA0_SSCR_LPSRC (1<<7)
342 #define BA0_SSCR_CDTX (1<<5)
343 #define BA0_SSCR_HVC (1<<3)
345 #define BA0_FMLVC 0x0754
346 #define BA0_FMRVC 0x0758
347 #define BA0_SRCSA 0x075c
348 #define BA0_PPLVC 0x0760
349 #define BA0_PPRVC 0x0764
350 #define BA0_PASR 0x0768
351 #define BA0_CASR 0x076C
354 #define SRCSLOT_LEFT_PCM_PLAYBACK 0
355 #define SRCSLOT_RIGHT_PCM_PLAYBACK 1
356 #define SRCSLOT_PHONE_LINE_1_DAC 2
357 #define SRCSLOT_CENTER_PCM_PLAYBACK 3
358 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
359 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
360 #define SRCSLOT_LFE_PCM_PLAYBACK 6
361 #define SRCSLOT_PHONE_LINE_2_DAC 7
362 #define SRCSLOT_HEADSET_DAC 8
363 #define SRCSLOT_LEFT_WT 29
364 #define SRCSLOT_RIGHT_WT 30
367 #define SRCSLOT_LEFT_PCM_RECORD 10
368 #define SRCSLOT_RIGHT_PCM_RECORD 11
369 #define SRCSLOT_PHONE_LINE_1_ADC 12
370 #define SRCSLOT_MIC_ADC 13
371 #define SRCSLOT_PHONE_LINE_2_ADC 17
372 #define SRCSLOT_HEADSET_ADC 18
373 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
374 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
375 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
376 #define SRCSLOT_SECONDARY_MIC_ADC 23
377 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
378 #define SRCSLOT_SECONDARY_HEADSET_ADC 28
381 #define SRCSLOT_POWER_DOWN 31
384 #define CS4281_MODE_OUTPUT (1<<0)
385 #define CS4281_MODE_INPUT (1<<1)
389 #define JSPT_CAX 0x00000001
390 #define JSPT_CAY 0x00000002
391 #define JSPT_CBX 0x00000004
392 #define JSPT_CBY 0x00000008
393 #define JSPT_BA1 0x00000010
394 #define JSPT_BA2 0x00000020
395 #define JSPT_BB1 0x00000040
396 #define JSPT_BB2 0x00000080
399 #define JSCTL_SP_MASK 0x00000003
400 #define JSCTL_SP_SLOW 0x00000000
401 #define JSCTL_SP_MEDIUM_SLOW 0x00000001
402 #define JSCTL_SP_MEDIUM_FAST 0x00000002
403 #define JSCTL_SP_FAST 0x00000003
404 #define JSCTL_ARE 0x00000004
407 #define JSC1_Y1V_MASK 0x0000FFFF
408 #define JSC1_X1V_MASK 0xFFFF0000
409 #define JSC1_Y1V_SHIFT 0
410 #define JSC1_X1V_SHIFT 16
411 #define JSC2_Y2V_MASK 0x0000FFFF
412 #define JSC2_X2V_MASK 0xFFFF0000
413 #define JSC2_Y2V_SHIFT 0
414 #define JSC2_X2V_SHIFT 16
417 #define JSIO_DAX 0x00000001
418 #define JSIO_DAY 0x00000002
419 #define JSIO_DBX 0x00000004
420 #define JSIO_DBY 0x00000008
421 #define JSIO_AXOE 0x00000010
422 #define JSIO_AYOE 0x00000020
423 #define JSIO_BXOE 0x00000040
424 #define JSIO_BYOE 0x00000080
450 #define SUSPEND_REGISTERS 20
489 #ifdef CONFIG_PM_SLEEP
508 #define CS4281_FIFO_SIZE 32
514 static inline void snd_cs4281_pokeBA0(
struct cs4281 *
chip,
unsigned long offset,
520 static inline unsigned int snd_cs4281_peekBA0(
struct cs4281 *
chip,
unsigned long offset)
525 static void snd_cs4281_ac97_write(
struct snd_ac97 *ac97,
526 unsigned short reg,
unsigned short val)
550 snd_cs4281_pokeBA0(chip,
BA0_ACCAD, reg);
551 snd_cs4281_pokeBA0(chip,
BA0_ACCDA, val);
554 for (count = 0; count < 2000; count++) {
570 static unsigned short snd_cs4281_ac97_read(
struct snd_ac97 *ac97,
578 volatile int ac97_num = ((
volatile struct snd_ac97 *)ac97)->num;
604 snd_cs4281_pokeBA0(chip,
BA0_ACCAD, reg);
614 for (count = 0; count < 500; count++) {
635 for (count = 0; count < 100; count++) {
707 static unsigned int snd_cs4281_rate(
unsigned int rate,
unsigned int *real_rate)
709 unsigned int val = ~0;
716 case 11025:
return 4;
717 case 16000:
return 3;
718 case 22050:
return 2;
719 case 44100:
return 1;
720 case 48000:
return 0;
725 val = 1536000 /
rate;
727 *real_rate = 1536000 /
val;
733 int capture,
int src)
768 unsigned int val = snd_cs4281_rate(runtime->
rate,
NULL);
770 snd_cs4281_pokeBA0(chip,
BA0_DACSR, val);
774 unsigned int val = snd_cs4281_rate(runtime->
rate,
NULL);
776 snd_cs4281_pokeBA0(chip,
BA0_ADCSR, val);
793 snd_cs4281_pokeBA0(chip, dma->
regFSIC, 0);
814 snd_cs4281_mode(chip, dma, runtime, 0, 1);
826 snd_cs4281_mode(chip, dma, runtime, 1, 1);
843 snd_cs4281_peekBA0(chip, dma->
regDCC) - 1;
863 .buffer_bytes_max = (512*1024),
888 .buffer_bytes_max = (512*1024),
907 runtime->
hw = snd_cs4281_playback;
926 runtime->
hw = snd_cs4281_capture;
950 static struct snd_pcm_ops snd_cs4281_playback_ops = {
951 .open = snd_cs4281_playback_open,
952 .close = snd_cs4281_playback_close,
954 .hw_params = snd_cs4281_hw_params,
955 .hw_free = snd_cs4281_hw_free,
956 .prepare = snd_cs4281_playback_prepare,
957 .trigger = snd_cs4281_trigger,
958 .pointer = snd_cs4281_pointer,
961 static struct snd_pcm_ops snd_cs4281_capture_ops = {
962 .open = snd_cs4281_capture_open,
963 .close = snd_cs4281_capture_close,
965 .hw_params = snd_cs4281_hw_params,
966 .hw_free = snd_cs4281_hw_free,
967 .prepare = snd_cs4281_capture_prepare,
968 .trigger = snd_cs4281_trigger,
969 .pointer = snd_cs4281_pointer,
1004 #define CS_VOL_MASK 0x1f
1006 static int snd_cs4281_info_volume(
struct snd_kcontrol *kcontrol,
1016 static int snd_cs4281_get_volume(
struct snd_kcontrol *kcontrol,
1027 ucontrol->
value.integer.value[0] = volL;
1028 ucontrol->
value.integer.value[1] = volR;
1032 static int snd_cs4281_put_volume(
struct snd_kcontrol *kcontrol,
1044 if (ucontrol->
value.integer.value[0] != volL) {
1046 snd_cs4281_pokeBA0(chip, regL, volL);
1049 if (ucontrol->
value.integer.value[1] != volR) {
1051 snd_cs4281_pokeBA0(chip, regR, volR);
1062 .name =
"Synth Playback Volume",
1063 .info = snd_cs4281_info_volume,
1064 .get = snd_cs4281_get_volume,
1065 .put = snd_cs4281_put_volume,
1067 .tlv = { .p = db_scale_dsp },
1073 .name =
"PCM Stream Playback Volume",
1074 .info = snd_cs4281_info_volume,
1075 .get = snd_cs4281_get_volume,
1076 .put = snd_cs4281_put_volume,
1078 .tlv = { .p = db_scale_dsp },
1087 static void snd_cs4281_mixer_free_ac97(
struct snd_ac97 *ac97)
1102 .write = snd_cs4281_ac97_write,
1103 .read = snd_cs4281_ac97_read,
1108 chip->
ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1110 memset(&ac97, 0,
sizeof(ac97));
1137 snd_iprintf(buffer,
"Cirrus Logic CS4281\n\n");
1143 void *file_private_data,
1145 size_t count, loff_t
pos)
1155 void *file_private_data,
1156 struct file *file,
char __user *buf,
1157 size_t count, loff_t pos)
1167 .read = snd_cs4281_BA0_read,
1171 .read = snd_cs4281_BA1_read,
1178 if (! snd_card_proc_new(chip->
card,
"cs4281", &entry))
1179 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read);
1180 if (! snd_card_proc_new(chip->
card,
"cs4281_BA0", &entry)) {
1183 entry->
c.
ops = &snd_cs4281_proc_ops_BA0;
1186 if (! snd_card_proc_new(chip->
card,
"cs4281_BA1", &entry)) {
1189 entry->
c.
ops = &snd_cs4281_proc_ops_BA1;
1198 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1202 struct cs4281 *chip = gameport_get_port_data(gameport);
1206 snd_cs4281_pokeBA0(chip,
BA0_JSPT, 0xff);
1209 static unsigned char snd_cs4281_gameport_read(
struct gameport *gameport)
1211 struct cs4281 *chip = gameport_get_port_data(gameport);
1215 return snd_cs4281_peekBA0(chip,
BA0_JSPT);
1219 static int snd_cs4281_gameport_cooked_read(
struct gameport *gameport,
1222 struct cs4281 *chip = gameport_get_port_data(gameport);
1223 unsigned js1, js2, jst;
1228 js1 = snd_cs4281_peekBA0(chip,
BA0_JSC1);
1229 js2 = snd_cs4281_peekBA0(chip,
BA0_JSC2);
1230 jst = snd_cs4281_peekBA0(chip,
BA0_JSPT);
1232 *buttons = (~jst >> 4) & 0x0F;
1239 for (jst = 0; jst < 4; ++jst)
1240 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1244 #define snd_cs4281_gameport_cooked_read NULL
1247 static int snd_cs4281_gameport_open(
struct gameport *gameport,
int mode)
1264 struct gameport *
gp;
1266 chip->
gameport = gp = gameport_allocate_port();
1268 printk(
KERN_ERR "cs4281: cannot allocate memory for gameport\n");
1272 gameport_set_name(gp,
"CS4281 Gameport");
1274 gameport_set_dev_parent(gp, &chip->
pci->dev);
1275 gp->
open = snd_cs4281_gameport_open;
1276 gp->
read = snd_cs4281_gameport_read;
1277 gp->
trigger = snd_cs4281_gameport_trigger;
1278 gp->
cooked_read = snd_cs4281_gameport_cooked_read;
1279 gameport_set_port_data(gp, chip);
1281 snd_cs4281_pokeBA0(chip,
BA0_JSIO, 0xFF);
1284 gameport_register_port(gp);
1289 static void snd_cs4281_free_gameport(
struct cs4281 *chip)
1297 static inline int snd_cs4281_create_gameport(
struct cs4281 *chip) {
return -
ENOSYS; }
1298 static inline void snd_cs4281_free_gameport(
struct cs4281 *chip) { }
1301 static int snd_cs4281_free(
struct cs4281 *chip)
1303 snd_cs4281_free_gameport(chip);
1309 snd_cs4281_pokeBA0(chip,
BA0_HIMR, 0x7fffffff);
1313 snd_cs4281_pokeBA0(chip,
BA0_SSPM, 0);
1330 static int snd_cs4281_dev_free(
struct snd_device *device)
1333 return snd_cs4281_free(chip);
1336 static int snd_cs4281_chip_init(
struct cs4281 *chip);
1347 .dev_free = snd_cs4281_dev_free,
1363 if (dual_codec < 0 || dual_codec > 3) {
1379 if (!chip->
ba0 || !chip->
ba1) {
1380 snd_cs4281_free(chip);
1385 KBUILD_MODNAME, chip)) {
1387 snd_cs4281_free(chip);
1392 tmp = snd_cs4281_chip_init(chip);
1394 snd_cs4281_free(chip);
1399 snd_cs4281_free(chip);
1403 snd_cs4281_proc_init(chip);
1411 static int snd_cs4281_chip_init(
struct cs4281 *chip)
1414 unsigned long end_time;
1418 tmp = snd_cs4281_peekBA0(chip,
BA0_EPPMC);
1420 snd_cs4281_pokeBA0(chip,
BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1423 tmp = snd_cs4281_peekBA0(chip,
BA0_CFLR);
1426 tmp = snd_cs4281_peekBA0(chip,
BA0_CFLR);
1436 snd_cs4281_pokeBA0(chip,
BA0_CWPR, 0x4281);
1469 snd_cs4281_pokeBA0(chip,
BA0_SPMC, 0);
1570 if (--retry_count > 0)
1586 for (tmp = 0; tmp < 4; tmp++) {
1598 snd_cs4281_pokeBA0(chip, dma->
regFCR,
1615 snd_cs4281_pokeBA0(chip, chip->
dma[0].regFCR, chip->
dma[0].valFCR);
1628 snd_cs4281_pokeBA0(chip,
BA0_HIMR, 0x7fffffff & ~(
1644 static void snd_cs4281_midi_reset(
struct cs4281 *chip)
1653 struct cs4281 *chip = substream->
rmidi->private_data;
1659 snd_cs4281_midi_reset(chip);
1669 struct cs4281 *chip = substream->
rmidi->private_data;
1675 snd_cs4281_midi_reset(chip);
1686 struct cs4281 *chip = substream->
rmidi->private_data;
1693 snd_cs4281_midi_reset(chip);
1703 struct cs4281 *chip = substream->
rmidi->private_data;
1709 snd_cs4281_midi_reset(chip);
1720 unsigned long flags;
1721 struct cs4281 *chip = substream->
rmidi->private_data;
1735 spin_unlock_irqrestore(&chip->
reg_lock, flags);
1740 unsigned long flags;
1741 struct cs4281 *chip = substream->
rmidi->private_data;
1754 snd_cs4281_pokeBA0(chip,
BA0_MIDWP, byte);
1765 spin_unlock_irqrestore(&chip->
reg_lock, flags);
1770 .open = snd_cs4281_midi_output_open,
1771 .close = snd_cs4281_midi_output_close,
1772 .trigger = snd_cs4281_midi_output_trigger,
1777 .open = snd_cs4281_midi_input_open,
1778 .close = snd_cs4281_midi_input_close,
1779 .trigger = snd_cs4281_midi_input_trigger,
1782 static int __devinit snd_cs4281_midi(
struct cs4281 * chip,
int device,
1797 chip->
rmidi = rmidi;
1815 status = snd_cs4281_peekBA0(chip,
BA0_HISR);
1816 if ((status & 0x7fffffff) == 0) {
1822 for (dma = 0; dma < 4; dma++)
1827 val = snd_cs4281_peekBA0(chip, cdma->
regHDSR);
1853 c = snd_cs4281_peekBA0(chip,
BA0_MIDRP);
1858 while ((snd_cs4281_peekBA0(chip,
BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1881 static void snd_cs4281_opl3_command(
struct snd_opl3 *opl3,
unsigned short cmd,
1884 unsigned long flags;
1895 writel((
unsigned int)cmd, port);
1898 writel((
unsigned int)val, port + 4);
1901 spin_unlock_irqrestore(&opl3->
reg_lock, flags);
1924 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1930 if ((err = snd_cs4281_mixer(chip)) < 0) {
1934 if ((err = snd_cs4281_pcm(chip, 0,
NULL)) < 0) {
1938 if ((err = snd_cs4281_midi(chip, 0,
NULL)) < 0) {
1947 opl3->
command = snd_cs4281_opl3_command;
1953 snd_cs4281_create_gameport(chip);
1966 pci_set_drvdata(pci, card);
1974 pci_set_drvdata(pci,
NULL);
1980 #ifdef CONFIG_PM_SLEEP
1998 #define CLKCR1_CKRA 0x00010000L
2000 static int cs4281_suspend(
struct device *dev)
2009 snd_pcm_suspend_all(chip->
pcm);
2011 snd_ac97_suspend(chip->
ac97);
2014 ulCLK = snd_cs4281_peekBA0(chip,
BA0_CLKCR1);
2015 ulCLK |= CLKCR1_CKRA;
2024 chip->suspend_regs[
i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2030 snd_cs4281_pokeBA0(chip,
BA0_SSPM, 0);
2036 snd_cs4281_pokeBA0(chip,
BA0_SPMC, 0);
2038 ulCLK = snd_cs4281_peekBA0(chip,
BA0_CLKCR1);
2039 ulCLK &= ~CLKCR1_CKRA;
2048 static int cs4281_resume(
struct device *dev)
2060 "disabling device\n");
2066 ulCLK = snd_cs4281_peekBA0(chip,
BA0_CLKCR1);
2067 ulCLK |= CLKCR1_CKRA;
2070 snd_cs4281_chip_init(chip);
2075 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2077 snd_ac97_resume(chip->
ac97);
2080 ulCLK = snd_cs4281_peekBA0(chip,
BA0_CLKCR1);
2081 ulCLK &= ~CLKCR1_CKRA;
2089 #define CS4281_PM_OPS &cs4281_pm
2091 #define CS4281_PM_OPS NULL
2095 .name = KBUILD_MODNAME,
2096 .id_table = snd_cs4281_ids,
2097 .probe = snd_cs4281_probe,