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cx231xx-417.c
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1 /*
2  *
3  * Support for a cx23417 mpeg encoder via cx231xx host port.
4  *
5  * (c) 2004 Jelle Foks <[email protected]>
6  * (c) 2004 Gerd Knorr <[email protected]>
7  * (c) 2008 Steven Toth <[email protected]>
8  * - CX23885/7/8 support
9  *
10  * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25  */
26 
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/fs.h>
31 #include <linux/delay.h>
32 #include <linux/device.h>
33 #include <linux/firmware.h>
34 #include <linux/vmalloc.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/cx2341x.h>
38 #include <linux/usb.h>
39 
40 #include "cx231xx.h"
41 /*#include "cx23885-ioctl.h"*/
42 
43 #define CX231xx_FIRM_IMAGE_SIZE 376836
44 #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
45 
46 /* for polaris ITVC */
47 #define ITVC_WRITE_DIR 0x03FDFC00
48 #define ITVC_READ_DIR 0x0001FC00
49 
50 #define MCI_MEMORY_DATA_BYTE0 0x00
51 #define MCI_MEMORY_DATA_BYTE1 0x08
52 #define MCI_MEMORY_DATA_BYTE2 0x10
53 #define MCI_MEMORY_DATA_BYTE3 0x18
54 
55 #define MCI_MEMORY_ADDRESS_BYTE2 0x20
56 #define MCI_MEMORY_ADDRESS_BYTE1 0x28
57 #define MCI_MEMORY_ADDRESS_BYTE0 0x30
58 
59 #define MCI_REGISTER_DATA_BYTE0 0x40
60 #define MCI_REGISTER_DATA_BYTE1 0x48
61 #define MCI_REGISTER_DATA_BYTE2 0x50
62 #define MCI_REGISTER_DATA_BYTE3 0x58
63 
64 #define MCI_REGISTER_ADDRESS_BYTE0 0x60
65 #define MCI_REGISTER_ADDRESS_BYTE1 0x68
66 
67 #define MCI_REGISTER_MODE 0x70
68 
69 /* Read and write modes for polaris ITVC */
70 #define MCI_MODE_REGISTER_READ 0x000
71 #define MCI_MODE_REGISTER_WRITE 0x100
72 #define MCI_MODE_MEMORY_READ 0x000
73 #define MCI_MODE_MEMORY_WRITE 0x4000
74 
75 static unsigned int mpegbufs = 8;
76 module_param(mpegbufs, int, 0644);
77 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
78 static unsigned int mpeglines = 128;
79 module_param(mpeglines, int, 0644);
80 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
81 static unsigned int mpeglinesize = 512;
82 module_param(mpeglinesize, int, 0644);
83 MODULE_PARM_DESC(mpeglinesize,
84  "number of bytes in each line of an MPEG buffer, range 512-1024");
85 
86 static unsigned int v4l_debug = 1;
87 module_param(v4l_debug, int, 0644);
88 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
90 #define dprintk(level, fmt, arg...)\
91  do { if (v4l_debug >= level) \
92  printk(KERN_INFO "%s: " fmt, \
93  (dev) ? dev->name : "cx231xx[?]", ## arg); \
94  } while (0)
95 
96 static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
97  {
98  .name = "NTSC-M",
99  .id = V4L2_STD_NTSC_M,
100  }, {
101  .name = "NTSC-JP",
102  .id = V4L2_STD_NTSC_M_JP,
103  }, {
104  .name = "PAL-BG",
105  .id = V4L2_STD_PAL_BG,
106  }, {
107  .name = "PAL-DK",
108  .id = V4L2_STD_PAL_DK,
109  }, {
110  .name = "PAL-I",
111  .id = V4L2_STD_PAL_I,
112  }, {
113  .name = "PAL-M",
114  .id = V4L2_STD_PAL_M,
115  }, {
116  .name = "PAL-N",
117  .id = V4L2_STD_PAL_N,
118  }, {
119  .name = "PAL-Nc",
120  .id = V4L2_STD_PAL_Nc,
121  }, {
122  .name = "PAL-60",
123  .id = V4L2_STD_PAL_60,
124  }, {
125  .name = "SECAM-L",
126  .id = V4L2_STD_SECAM_L,
127  }, {
128  .name = "SECAM-DK",
129  .id = V4L2_STD_SECAM_DK,
130  }
131 };
132 
133 /* ------------------------------------------------------------------ */
138 };
146 };
148  CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
149  CX231xx_END_NOW, /* stop immediately, no irq */
150 };
152  CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
153  CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */
154 };
159 };
163 };
169 };
173 };
180 };
184 };
189 };
193 };
197 };
200 };
204 };
207 };
209  CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
210  CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
211  CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
212 };
214  CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
215  CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
216  CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
217 };
221 };
225 };
230 };
235 };
236 
237 /* defines below are from ivtv-driver.h */
238 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
239 
240 /* Firmware API commands */
241 #define IVTV_API_STD_TIMEOUT 500
242 
243 /* Registers */
244 /* IVTV_REG_OFFSET */
245 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
246 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
247 #define IVTV_REG_SPU (0x9050)
248 #define IVTV_REG_HW_BLOCKS (0x9054)
249 #define IVTV_REG_VPU (0x9058)
250 #define IVTV_REG_APU (0xA064)
251 
252 /*
253  * Bit definitions for MC417_RWD and MC417_OEN registers
254  *
255  * bits 31-16
256  *+-----------+
257  *| Reserved |
258  *|+-----------+
259  *| bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
260  *|+-------+-------+-------+-------+-------+-------+-------+-------+
261  *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
262  *|+-------+-------+-------+-------+-------+-------+-------+-------+
263  *| bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
264  *|+-------+-------+-------+-------+-------+-------+-------+-------+
265  *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
266  *|+-------+-------+-------+-------+-------+-------+-------+-------+
267  */
268 #define MC417_MIWR 0x8000
269 #define MC417_MIRD 0x4000
270 #define MC417_MICS 0x2000
271 #define MC417_MIRDY 0x1000
272 #define MC417_MIADDR 0x0F00
273 #define MC417_MIDATA 0x00FF
274 
275 
276 /* Bit definitions for MC417_CTL register ****
277  *bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
278  *+--------+-------------+--------+--------------+------------+
279  *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
280  *+--------+-------------+--------+--------------+------------+
281  */
282 #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
283 #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
284 #define MC417_UART_GPIO_EN 0x00000001
285 
286 /* Values for speed control */
287 #define MC417_SPD_CTL_SLOW 0x1
288 #define MC417_SPD_CTL_MEDIUM 0x0
289 #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
290 
291 /* Values for GPIO select */
292 #define MC417_GPIO_SEL_GPIO3 0x3
293 #define MC417_GPIO_SEL_GPIO2 0x2
294 #define MC417_GPIO_SEL_GPIO1 0x1
295 #define MC417_GPIO_SEL_GPIO0 0x0
296 
297 
298 #define CX23417_GPIO_MASK 0xFC0003FF
299 static int setITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 value)
300 {
301  int status = 0;
302  u32 _gpio_direction = 0;
303 
304  _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
305  _gpio_direction = _gpio_direction|gpio_direction;
306  status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
307  (u8 *)&value, 4, 0, 0);
308  return status;
309 }
310 static int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue)
311 {
312  int status = 0;
313  u32 _gpio_direction = 0;
314 
315  _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
316  _gpio_direction = _gpio_direction|gpio_direction;
317 
318  status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
319  (u8 *)pValue, 4, 0, 1);
320  return status;
321 }
322 
323 static int waitForMciComplete(struct cx231xx *dev)
324 {
325  u32 gpio;
326  u32 gpio_driection = 0;
327  u8 count = 0;
328  getITVCReg(dev, gpio_driection, &gpio);
329 
330  while (!(gpio&0x020000)) {
331  msleep(10);
332 
333  getITVCReg(dev, gpio_driection, &gpio);
334 
335  if (count++ > 100) {
336  dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
337  return -1;
338  }
339  }
340  return 0;
341 }
342 
343 static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
344 {
345  u32 temp;
346  int status = 0;
347 
348  temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8);
349  temp = temp<<10;
350  status = setITVCReg(dev, ITVC_WRITE_DIR, temp);
351  if (status < 0)
352  return status;
353  temp = temp|((0x05)<<10);
354  setITVCReg(dev, ITVC_WRITE_DIR, temp);
355 
356  /*write data byte 1;*/
357  temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00);
358  temp = temp<<10;
359  setITVCReg(dev, ITVC_WRITE_DIR, temp);
360  temp = temp|((0x05)<<10);
361  setITVCReg(dev, ITVC_WRITE_DIR, temp);
362 
363  /*write data byte 2;*/
364  temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8);
365  temp = temp<<10;
366  setITVCReg(dev, ITVC_WRITE_DIR, temp);
367  temp = temp|((0x05)<<10);
368  setITVCReg(dev, ITVC_WRITE_DIR, temp);
369 
370  /*write data byte 3;*/
371  temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16);
372  temp = temp<<10;
373  setITVCReg(dev, ITVC_WRITE_DIR, temp);
374  temp = temp|((0x05)<<10);
375  setITVCReg(dev, ITVC_WRITE_DIR, temp);
376 
377  /*write address byte 0;*/
378  temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8);
379  temp = temp<<10;
380  setITVCReg(dev, ITVC_WRITE_DIR, temp);
381  temp = temp|((0x05)<<10);
382  setITVCReg(dev, ITVC_WRITE_DIR, temp);
383 
384  /*write address byte 1;*/
385  temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00);
386  temp = temp<<10;
387  setITVCReg(dev, ITVC_WRITE_DIR, temp);
388  temp = temp|((0x05)<<10);
389  setITVCReg(dev, ITVC_WRITE_DIR, temp);
390 
391  /*Write that the mode is write.*/
393  temp = temp<<10;
394  setITVCReg(dev, ITVC_WRITE_DIR, temp);
395  temp = temp|((0x05)<<10);
396  setITVCReg(dev, ITVC_WRITE_DIR, temp);
397 
398  return waitForMciComplete(dev);
399 }
400 
401 static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
402 {
403  /*write address byte 0;*/
404  u32 temp;
405  u32 return_value = 0;
406  int ret = 0;
407 
408  temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
409  temp = temp << 10;
410  setITVCReg(dev, ITVC_WRITE_DIR, temp);
411  temp = temp | ((0x05) << 10);
412  setITVCReg(dev, ITVC_WRITE_DIR, temp);
413 
414  /*write address byte 1;*/
415  temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
416  temp = temp << 10;
417  setITVCReg(dev, ITVC_WRITE_DIR, temp);
418  temp = temp | ((0x05) << 10);
419  setITVCReg(dev, ITVC_WRITE_DIR, temp);
420 
421  /*write that the mode is read;*/
423  temp = temp << 10;
424  setITVCReg(dev, ITVC_WRITE_DIR, temp);
425  temp = temp | ((0x05) << 10);
426  setITVCReg(dev, ITVC_WRITE_DIR, temp);
427 
428  /*wait for the MIRDY line to be asserted ,
429  signalling that the read is done;*/
430  ret = waitForMciComplete(dev);
431 
432  /*switch the DATA- GPIO to input mode;*/
433 
434  /*Read data byte 0;*/
435  temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
436  setITVCReg(dev, ITVC_READ_DIR, temp);
437  temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
438  setITVCReg(dev, ITVC_READ_DIR, temp);
439  getITVCReg(dev, ITVC_READ_DIR, &temp);
440  return_value |= ((temp & 0x03FC0000) >> 18);
441  setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
442 
443  /* Read data byte 1;*/
444  temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
445  setITVCReg(dev, ITVC_READ_DIR, temp);
446  temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
447  setITVCReg(dev, ITVC_READ_DIR, temp);
448  getITVCReg(dev, ITVC_READ_DIR, &temp);
449 
450  return_value |= ((temp & 0x03FC0000) >> 10);
451  setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
452 
453  /*Read data byte 2;*/
454  temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
455  setITVCReg(dev, ITVC_READ_DIR, temp);
456  temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
457  setITVCReg(dev, ITVC_READ_DIR, temp);
458  getITVCReg(dev, ITVC_READ_DIR, &temp);
459  return_value |= ((temp & 0x03FC0000) >> 2);
460  setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
461 
462  /*Read data byte 3;*/
463  temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
464  setITVCReg(dev, ITVC_READ_DIR, temp);
465  temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
466  setITVCReg(dev, ITVC_READ_DIR, temp);
467  getITVCReg(dev, ITVC_READ_DIR, &temp);
468  return_value |= ((temp & 0x03FC0000) << 6);
469  setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10));
470 
471  *value = return_value;
472 
473 
474  return ret;
475 }
476 
477 static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
478 {
479  /*write data byte 0;*/
480 
481  u32 temp;
482  int ret = 0;
483 
484  temp = 0x82 | MCI_MEMORY_DATA_BYTE0|((value & 0x000000FF) << 8);
485  temp = temp << 10;
486  ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
487  if (ret < 0)
488  return ret;
489  temp = temp | ((0x05) << 10);
490  setITVCReg(dev, ITVC_WRITE_DIR, temp);
491 
492  /*write data byte 1;*/
493  temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
494  temp = temp << 10;
495  setITVCReg(dev, ITVC_WRITE_DIR, temp);
496  temp = temp | ((0x05) << 10);
497  setITVCReg(dev, ITVC_WRITE_DIR, temp);
498 
499  /*write data byte 2;*/
500  temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
501  temp = temp<<10;
502  setITVCReg(dev, ITVC_WRITE_DIR, temp);
503  temp = temp|((0x05)<<10);
504  setITVCReg(dev, ITVC_WRITE_DIR, temp);
505 
506  /*write data byte 3;*/
507  temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
508  temp = temp<<10;
509  setITVCReg(dev, ITVC_WRITE_DIR, temp);
510  temp = temp|((0x05)<<10);
511  setITVCReg(dev, ITVC_WRITE_DIR, temp);
512 
513  /* write address byte 2;*/
515  ((address & 0x003F0000)>>8);
516  temp = temp<<10;
517  setITVCReg(dev, ITVC_WRITE_DIR, temp);
518  temp = temp|((0x05)<<10);
519  setITVCReg(dev, ITVC_WRITE_DIR, temp);
520 
521  /* write address byte 1;*/
522  temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
523  temp = temp<<10;
524  setITVCReg(dev, ITVC_WRITE_DIR, temp);
525  temp = temp|((0x05)<<10);
526  setITVCReg(dev, ITVC_WRITE_DIR, temp);
527 
528  /* write address byte 0;*/
529  temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
530  temp = temp<<10;
531  setITVCReg(dev, ITVC_WRITE_DIR, temp);
532  temp = temp|((0x05)<<10);
533  setITVCReg(dev, ITVC_WRITE_DIR, temp);
534 
535  /*wait for MIRDY line;*/
536  waitForMciComplete(dev);
537 
538  return 0;
539 }
540 
541 static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
542 {
543  u32 temp = 0;
544  u32 return_value = 0;
545  int ret = 0;
546 
547  /*write address byte 2;*/
549  ((address & 0x003F0000)>>8);
550  temp = temp<<10;
551  ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
552  if (ret < 0)
553  return ret;
554  temp = temp|((0x05)<<10);
555  setITVCReg(dev, ITVC_WRITE_DIR, temp);
556 
557  /*write address byte 1*/
558  temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
559  temp = temp<<10;
560  setITVCReg(dev, ITVC_WRITE_DIR, temp);
561  temp = temp|((0x05)<<10);
562  setITVCReg(dev, ITVC_WRITE_DIR, temp);
563 
564  /*write address byte 0*/
565  temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8);
566  temp = temp<<10;
567  setITVCReg(dev, ITVC_WRITE_DIR, temp);
568  temp = temp|((0x05)<<10);
569  setITVCReg(dev, ITVC_WRITE_DIR, temp);
570 
571  /*Wait for MIRDY line*/
572  ret = waitForMciComplete(dev);
573 
574 
575  /*Read data byte 3;*/
576  temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10;
577  setITVCReg(dev, ITVC_READ_DIR, temp);
578  temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10);
579  setITVCReg(dev, ITVC_READ_DIR, temp);
580  getITVCReg(dev, ITVC_READ_DIR, &temp);
581  return_value |= ((temp&0x03FC0000)<<6);
582  setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
583 
584  /*Read data byte 2;*/
585  temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10;
586  setITVCReg(dev, ITVC_READ_DIR, temp);
587  temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10);
588  setITVCReg(dev, ITVC_READ_DIR, temp);
589  getITVCReg(dev, ITVC_READ_DIR, &temp);
590  return_value |= ((temp&0x03FC0000)>>2);
591  setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
592 
593  /* Read data byte 1;*/
594  temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10;
595  setITVCReg(dev, ITVC_READ_DIR, temp);
596  temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10);
597  setITVCReg(dev, ITVC_READ_DIR, temp);
598  getITVCReg(dev, ITVC_READ_DIR, &temp);
599  return_value |= ((temp&0x03FC0000)>>10);
600  setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
601 
602  /*Read data byte 0;*/
603  temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10;
604  setITVCReg(dev, ITVC_READ_DIR, temp);
605  temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10);
606  setITVCReg(dev, ITVC_READ_DIR, temp);
607  getITVCReg(dev, ITVC_READ_DIR, &temp);
608  return_value |= ((temp&0x03FC0000)>>18);
609  setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
610 
611  *value = return_value;
612  return ret;
613 }
614 
615 /* ------------------------------------------------------------------ */
616 
617 /* MPEG encoder API */
618 static char *cmd_to_str(int cmd)
619 {
620  switch (cmd) {
621  case CX2341X_ENC_PING_FW:
622  return "PING_FW";
624  return "START_CAPTURE";
626  return "STOP_CAPTURE";
628  return "SET_AUDIO_ID";
630  return "SET_VIDEO_ID";
632  return "SET_PCR_PID";
634  return "SET_FRAME_RATE";
636  return "SET_FRAME_SIZE";
638  return "SET_BIT_RATE";
640  return "SET_GOP_PROPERTIES";
642  return "SET_ASPECT_RATIO";
644  return "SET_DNR_FILTER_PROPS";
646  return "SET_DNR_FILTER_PROPS";
648  return "SET_CORING_LEVELS";
650  return "SET_SPATIAL_FILTER_TYPE";
652  return "SET_VBI_LINE";
654  return "SET_STREAM_TYPE";
656  return "SET_OUTPUT_PORT";
658  return "SET_AUDIO_PROPERTIES";
659  case CX2341X_ENC_HALT_FW:
660  return "HALT_FW";
662  return "GET_VERSION";
664  return "SET_GOP_CLOSURE";
666  return "GET_SEQ_END";
668  return "SET_PGM_INDEX_INFO";
670  return "SET_VBI_CONFIG";
672  return "SET_DMA_BLOCK_SIZE";
674  return "GET_PREV_DMA_INFO_MB_10";
676  return "GET_PREV_DMA_INFO_MB_9";
678  return "SCHED_DMA_TO_HOST";
680  return "INITIALIZE_INPUT";
682  return "SET_FRAME_DROP_RATE";
684  return "PAUSE_ENCODER";
686  return "REFRESH_INPUT";
688  return "SET_COPYRIGHT";
690  return "SET_EVENT_NOTIFICATION";
692  return "SET_NUM_VSYNC_LINES";
694  return "SET_PLACEHOLDER";
696  return "MUTE_VIDEO";
698  return "MUTE_AUDIO";
699  case CX2341X_ENC_MISC:
700  return "MISC";
701  default:
702  return "UNKNOWN";
703  }
704 }
705 
706 static int cx231xx_mbox_func(void *priv,
707  u32 command,
708  int in,
709  int out,
711 {
712  struct cx231xx *dev = priv;
713  unsigned long timeout;
714  u32 value, flag, retval = 0;
715  int i;
716 
717  dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
718  cmd_to_str(command));
719 
720  /* this may not be 100% safe if we can't read any memory location
721  without side effects */
722  mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
723  if (value != 0x12345678) {
724  dprintk(3,
725  "Firmware and/or mailbox pointer not initialized "
726  "or corrupted, signature = 0x%x, cmd = %s\n", value,
727  cmd_to_str(command));
728  return -1;
729  }
730 
731  /* This read looks at 32 bits, but flag is only 8 bits.
732  * Seems we also bail if CMD or TIMEOUT bytes are set???
733  */
734  mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
735  if (flag) {
736  dprintk(3, "ERROR: Mailbox appears to be in use "
737  "(%x), cmd = %s\n", flag, cmd_to_str(command));
738  return -1;
739  }
740 
741  flag |= 1; /* tell 'em we're working on it */
742  mc417_memory_write(dev, dev->cx23417_mailbox, flag);
743 
744  /* write command + args + fill remaining with zeros */
745  /* command code */
746  mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
747  mc417_memory_write(dev, dev->cx23417_mailbox + 3,
748  IVTV_API_STD_TIMEOUT); /* timeout */
749  for (i = 0; i < in; i++) {
750  mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
751  dprintk(3, "API Input %d = %d\n", i, data[i]);
752  }
753  for (; i < CX2341X_MBOX_MAX_DATA; i++)
754  mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
755 
756  flag |= 3; /* tell 'em we're done writing */
757  mc417_memory_write(dev, dev->cx23417_mailbox, flag);
758 
759  /* wait for firmware to handle the API command */
760  timeout = jiffies + msecs_to_jiffies(10);
761  for (;;) {
762  mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
763  if (0 != (flag & 4))
764  break;
765  if (time_after(jiffies, timeout)) {
766  dprintk(3, "ERROR: API Mailbox timeout\n");
767  return -1;
768  }
769  udelay(10);
770  }
771 
772  /* read output values */
773  for (i = 0; i < out; i++) {
774  mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
775  dprintk(3, "API Output %d = %d\n", i, data[i]);
776  }
777 
778  mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
779  dprintk(3, "API result = %d\n", retval);
780 
781  flag = 0;
782  mc417_memory_write(dev, dev->cx23417_mailbox, flag);
783 
784  return retval;
785 }
786 
787 /* We don't need to call the API often, so using just one
788  * mailbox will probably suffice
789  */
790 static int cx231xx_api_cmd(struct cx231xx *dev,
791  u32 command,
792  u32 inputcnt,
793  u32 outputcnt,
794  ...)
795 {
797  va_list vargs;
798  int i, err;
799 
800  dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
801 
802  va_start(vargs, outputcnt);
803  for (i = 0; i < inputcnt; i++)
804  data[i] = va_arg(vargs, int);
805 
806  err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
807  for (i = 0; i < outputcnt; i++) {
808  int *vptr = va_arg(vargs, int *);
809  *vptr = data[i];
810  }
811  va_end(vargs);
812 
813  return err;
814 }
815 
816 static int cx231xx_find_mailbox(struct cx231xx *dev)
817 {
818  u32 signature[4] = {
819  0x12345678, 0x34567812, 0x56781234, 0x78123456
820  };
821  int signaturecnt = 0;
822  u32 value;
823  int i;
824  int ret = 0;
825 
826  dprintk(2, "%s()\n", __func__);
827 
828  for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
829  ret = mc417_memory_read(dev, i, &value);
830  if (ret < 0)
831  return ret;
832  if (value == signature[signaturecnt])
833  signaturecnt++;
834  else
835  signaturecnt = 0;
836  if (4 == signaturecnt) {
837  dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
838  return i+1;
839  }
840  }
841  dprintk(3, "Mailbox signature values not found!\n");
842  return -1;
843 }
844 
845 static void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value,
846  u32 *p_fw_image)
847 {
848 
849  u32 temp = 0;
850  int i = 0;
851 
852  temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
853  temp = temp<<10;
854  *p_fw_image = temp;
855  p_fw_image++;
856  temp = temp|((0x05)<<10);
857  *p_fw_image = temp;
858  p_fw_image++;
859 
860  /*write data byte 1;*/
861  temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
862  temp = temp<<10;
863  *p_fw_image = temp;
864  p_fw_image++;
865  temp = temp|((0x05)<<10);
866  *p_fw_image = temp;
867  p_fw_image++;
868 
869  /*write data byte 2;*/
870  temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
871  temp = temp<<10;
872  *p_fw_image = temp;
873  p_fw_image++;
874  temp = temp|((0x05)<<10);
875  *p_fw_image = temp;
876  p_fw_image++;
877 
878  /*write data byte 3;*/
879  temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
880  temp = temp<<10;
881  *p_fw_image = temp;
882  p_fw_image++;
883  temp = temp|((0x05)<<10);
884  *p_fw_image = temp;
885  p_fw_image++;
886 
887  /* write address byte 2;*/
889  ((address & 0x003F0000)>>8);
890  temp = temp<<10;
891  *p_fw_image = temp;
892  p_fw_image++;
893  temp = temp|((0x05)<<10);
894  *p_fw_image = temp;
895  p_fw_image++;
896 
897  /* write address byte 1;*/
898  temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
899  temp = temp<<10;
900  *p_fw_image = temp;
901  p_fw_image++;
902  temp = temp|((0x05)<<10);
903  *p_fw_image = temp;
904  p_fw_image++;
905 
906  /* write address byte 0;*/
907  temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
908  temp = temp<<10;
909  *p_fw_image = temp;
910  p_fw_image++;
911  temp = temp|((0x05)<<10);
912  *p_fw_image = temp;
913  p_fw_image++;
914 
915  for (i = 0; i < 6; i++) {
916  *p_fw_image = 0xFFFFFFFF;
917  p_fw_image++;
918  }
919 }
920 
921 
922 static int cx231xx_load_firmware(struct cx231xx *dev)
923 {
924  static const unsigned char magic[8] = {
925  0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
926  };
927  const struct firmware *firmware;
928  int i, retval = 0;
929  u32 value = 0;
930  u32 gpio_output = 0;
931  /*u32 checksum = 0;*/
932  /*u32 *dataptr;*/
933  u32 transfer_size = 0;
934  u32 fw_data = 0;
935  u32 address = 0;
936  /*u32 current_fw[800];*/
937  u32 *p_current_fw, *p_fw;
938  u32 *p_fw_data;
939  int frame = 0;
940  u16 _buffer_size = 4096;
941  u8 *p_buffer;
942 
943  p_current_fw = vmalloc(1884180 * 4);
944  p_fw = p_current_fw;
945  if (p_current_fw == NULL) {
946  dprintk(2, "FAIL!!!\n");
947  return -1;
948  }
949 
950  p_buffer = vmalloc(4096);
951  if (p_buffer == NULL) {
952  dprintk(2, "FAIL!!!\n");
953  return -1;
954  }
955 
956  dprintk(2, "%s()\n", __func__);
957 
958  /* Save GPIO settings before reset of APU */
959  retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
960  retval |= mc417_memory_read(dev, 0x900C, &value);
961 
962  retval = mc417_register_write(dev,
963  IVTV_REG_VPU, 0xFFFFFFED);
964  retval |= mc417_register_write(dev,
966  retval |= mc417_register_write(dev,
967  IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
968  retval |= mc417_register_write(dev,
970  retval |= mc417_register_write(dev,
971  IVTV_REG_APU, 0);
972 
973  if (retval != 0) {
974  printk(KERN_ERR "%s: Error with mc417_register_write\n",
975  __func__);
976  return -1;
977  }
978 
979  retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
980  &dev->udev->dev);
981 
982  if (retval != 0) {
984  "ERROR: Hotplug firmware request failed (%s).\n",
986  printk(KERN_ERR "Please fix your hotplug setup, the board will "
987  "not work without firmware loaded!\n");
988  return -1;
989  }
990 
991  if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
992  printk(KERN_ERR "ERROR: Firmware size mismatch "
993  "(have %zd, expected %d)\n",
994  firmware->size, CX231xx_FIRM_IMAGE_SIZE);
995  release_firmware(firmware);
996  return -1;
997  }
998 
999  if (0 != memcmp(firmware->data, magic, 8)) {
1001  "ERROR: Firmware magic mismatch, wrong file?\n");
1002  release_firmware(firmware);
1003  return -1;
1004  }
1005 
1006  initGPIO(dev);
1007 
1008  /* transfer to the chip */
1009  dprintk(2, "Loading firmware to GPIO...\n");
1010  p_fw_data = (u32 *)firmware->data;
1011  dprintk(2, "firmware->size=%zd\n", firmware->size);
1012  for (transfer_size = 0; transfer_size < firmware->size;
1013  transfer_size += 4) {
1014  fw_data = *p_fw_data;
1015 
1016  mciWriteMemoryToGPIO(dev, address, fw_data, p_current_fw);
1017  address = address + 1;
1018  p_current_fw += 20;
1019  p_fw_data += 1;
1020  }
1021 
1022  /*download the firmware by ep5-out*/
1023 
1024  for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1025  frame++) {
1026  for (i = 0; i < _buffer_size; i++) {
1027  *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF);
1028  i++;
1029  *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8);
1030  i++;
1031  *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16);
1032  i++;
1033  *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24);
1034  }
1035  cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1036  }
1037 
1038  p_current_fw = p_fw;
1039  vfree(p_current_fw);
1040  p_current_fw = NULL;
1041  uninitGPIO(dev);
1042  release_firmware(firmware);
1043  dprintk(1, "Firmware upload successful.\n");
1044 
1047  if (retval < 0) {
1048  printk(KERN_ERR "%s: Error with mc417_register_write\n",
1049  __func__);
1050  return retval;
1051  }
1052  /* F/W power up disturbs the GPIOs, restore state */
1053  retval |= mc417_register_write(dev, 0x9020, gpio_output);
1054  retval |= mc417_register_write(dev, 0x900C, value);
1055 
1056  retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1057  retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1058 
1059  if (retval < 0) {
1060  printk(KERN_ERR "%s: Error with mc417_register_write\n",
1061  __func__);
1062  return retval;
1063  }
1064  return 0;
1065 }
1066 
1067 static void cx231xx_417_check_encoder(struct cx231xx *dev)
1068 {
1069  u32 status, seq;
1070 
1071  status = 0;
1072  seq = 0;
1073  cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1074  dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1075 }
1076 
1077 static void cx231xx_codec_settings(struct cx231xx *dev)
1078 {
1079  dprintk(1, "%s()\n", __func__);
1080 
1081  /* assign frame size */
1082  cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1083  dev->ts1.height, dev->ts1.width);
1084 
1085  dev->mpeg_params.width = dev->ts1.width;
1086  dev->mpeg_params.height = dev->ts1.height;
1087 
1088  cx2341x_update(dev, cx231xx_mbox_func, NULL, &dev->mpeg_params);
1089 
1090  cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1091  cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1092 }
1093 
1094 static int cx231xx_initialize_codec(struct cx231xx *dev)
1095 {
1096  int version;
1097  int retval;
1098  u32 i;
1099  u32 val = 0;
1100 
1101  dprintk(1, "%s()\n", __func__);
1102  cx231xx_disable656(dev);
1103  retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1104  if (retval < 0) {
1105  dprintk(2, "%s() PING OK\n", __func__);
1106  retval = cx231xx_load_firmware(dev);
1107  if (retval < 0) {
1108  printk(KERN_ERR "%s() f/w load failed\n", __func__);
1109  return retval;
1110  }
1111  retval = cx231xx_find_mailbox(dev);
1112  if (retval < 0) {
1113  printk(KERN_ERR "%s() mailbox < 0, error\n",
1114  __func__);
1115  return -1;
1116  }
1117  dev->cx23417_mailbox = retval;
1118  retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1119  if (retval < 0) {
1121  "ERROR: cx23417 firmware ping failed!\n");
1122  return -1;
1123  }
1124  retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1125  &version);
1126  if (retval < 0) {
1127  printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1128  "version failed!\n");
1129  return -1;
1130  }
1131  dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1132  msleep(200);
1133  }
1134 
1135  for (i = 0; i < 1; i++) {
1136  retval = mc417_register_read(dev, 0x20f8, &val);
1137  dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n",
1138  val);
1139  if (retval < 0)
1140  return retval;
1141  }
1142 
1143  cx231xx_enable656(dev);
1144  /* stop mpeg capture */
1145  cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE,
1146  3, 0, 1, 3, 4);
1147 
1148  cx231xx_codec_settings(dev);
1149  msleep(60);
1150 
1151 /* cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1152  CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1153  cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1154  CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1155  0, 0);
1156 */
1157 
1158 #if 0
1159  /* TODO */
1160  u32 data[7];
1161 
1162  /* Setup to capture VBI */
1163  data[0] = 0x0001BD00;
1164  data[1] = 1; /* frames per interrupt */
1165  data[2] = 4; /* total bufs */
1166  data[3] = 0x91559155; /* start codes */
1167  data[4] = 0x206080C0; /* stop codes */
1168  data[5] = 6; /* lines */
1169  data[6] = 64; /* BPL */
1170 
1171  cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1172  data[2], data[3], data[4], data[5], data[6]);
1173 
1174  for (i = 2; i <= 24; i++) {
1175  int valid;
1176 
1177  valid = ((i >= 19) && (i <= 21));
1178  cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1179  valid, 0 , 0, 0);
1180  cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1181  i | 0x80000000, valid, 0, 0, 0);
1182  }
1183 #endif
1184 /* cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1185  msleep(60);
1186 */
1187  /* initialize the video input */
1188  retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1189  if (retval < 0)
1190  return retval;
1191  msleep(60);
1192 
1193  /* Enable VIP style pixel invalidation so we work with scaled mode */
1194  mc417_memory_write(dev, 2120, 0x00000080);
1195 
1196  /* start capturing to the host interface */
1197  retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1199  if (retval < 0)
1200  return retval;
1201  msleep(10);
1202 
1203  for (i = 0; i < 1; i++) {
1204  mc417_register_read(dev, 0x20f8, &val);
1205  dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1206  }
1207 
1208  return 0;
1209 }
1210 
1211 /* ------------------------------------------------------------------ */
1212 
1213 static int bb_buf_setup(struct videobuf_queue *q,
1214  unsigned int *count, unsigned int *size)
1215 {
1216  struct cx231xx_fh *fh = q->priv_data;
1217 
1218  fh->dev->ts1.ts_packet_size = mpeglinesize;
1219  fh->dev->ts1.ts_packet_count = mpeglines;
1220 
1221  *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1222  *count = mpegbufs;
1223 
1224  return 0;
1225 }
1226 static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1227 {
1228  struct cx231xx_fh *fh = vq->priv_data;
1229  struct cx231xx *dev = fh->dev;
1230  unsigned long flags = 0;
1231 
1232  if (in_interrupt())
1233  BUG();
1234 
1235  spin_lock_irqsave(&dev->video_mode.slock, flags);
1236  if (dev->USE_ISO) {
1237  if (dev->video_mode.isoc_ctl.buf == buf)
1238  dev->video_mode.isoc_ctl.buf = NULL;
1239  } else {
1240  if (dev->video_mode.bulk_ctl.buf == buf)
1241  dev->video_mode.bulk_ctl.buf = NULL;
1242  }
1243  spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1244  videobuf_waiton(vq, &buf->vb, 0, 0);
1245  videobuf_vmalloc_free(&buf->vb);
1246  buf->vb.state = VIDEOBUF_NEEDS_INIT;
1247 }
1248 
1249 static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1250  struct cx231xx_dmaqueue *dma_q)
1251 {
1252  void *vbuf;
1253  struct cx231xx_buffer *buf;
1254  u32 tail_data = 0;
1255  char *p_data;
1256 
1257  if (dma_q->mpeg_buffer_done == 0) {
1258  if (list_empty(&dma_q->active))
1259  return;
1260 
1261  buf = list_entry(dma_q->active.next,
1262  struct cx231xx_buffer, vb.queue);
1263  dev->video_mode.isoc_ctl.buf = buf;
1264  dma_q->mpeg_buffer_done = 1;
1265  }
1266  /* Fill buffer */
1267  buf = dev->video_mode.isoc_ctl.buf;
1268  vbuf = videobuf_to_vmalloc(&buf->vb);
1269 
1270  if ((dma_q->mpeg_buffer_completed+len) <
1271  mpeglines*mpeglinesize) {
1272  if (dma_q->add_ps_package_head ==
1274  memcpy(vbuf+dma_q->mpeg_buffer_completed,
1275  dma_q->ps_head, 3);
1276  dma_q->mpeg_buffer_completed =
1277  dma_q->mpeg_buffer_completed + 3;
1278  dma_q->add_ps_package_head =
1280  }
1281  memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1282  dma_q->mpeg_buffer_completed =
1283  dma_q->mpeg_buffer_completed + len;
1284  } else {
1285  dma_q->mpeg_buffer_done = 0;
1286 
1287  tail_data =
1288  mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1289  memcpy(vbuf+dma_q->mpeg_buffer_completed,
1290  data, tail_data);
1291 
1292  buf->vb.state = VIDEOBUF_DONE;
1293  buf->vb.field_count++;
1294  do_gettimeofday(&buf->vb.ts);
1295  list_del(&buf->vb.queue);
1296  wake_up(&buf->vb.done);
1297  dma_q->mpeg_buffer_completed = 0;
1298 
1299  if (len - tail_data > 0) {
1300  p_data = data + tail_data;
1301  dma_q->left_data_count = len - tail_data;
1302  memcpy(dma_q->p_left_data,
1303  p_data, len - tail_data);
1304  }
1305 
1306  }
1307 
1308  return;
1309 }
1310 
1311 static void buffer_filled(char *data, int len, struct urb *urb,
1312  struct cx231xx_dmaqueue *dma_q)
1313 {
1314  void *vbuf;
1315  struct cx231xx_buffer *buf;
1316 
1317  if (list_empty(&dma_q->active))
1318  return;
1319 
1320 
1321  buf = list_entry(dma_q->active.next,
1322  struct cx231xx_buffer, vb.queue);
1323 
1324 
1325  /* Fill buffer */
1326  vbuf = videobuf_to_vmalloc(&buf->vb);
1327  memcpy(vbuf, data, len);
1328  buf->vb.state = VIDEOBUF_DONE;
1329  buf->vb.field_count++;
1330  do_gettimeofday(&buf->vb.ts);
1331  list_del(&buf->vb.queue);
1332  wake_up(&buf->vb.done);
1333 
1334  return;
1335 }
1336 static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1337 {
1338  struct cx231xx_dmaqueue *dma_q = urb->context;
1339  unsigned char *p_buffer;
1340  u32 buffer_size = 0;
1341  u32 i = 0;
1342 
1343  for (i = 0; i < urb->number_of_packets; i++) {
1344  if (dma_q->left_data_count > 0) {
1345  buffer_copy(dev, dma_q->p_left_data,
1346  dma_q->left_data_count, urb, dma_q);
1347  dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1348  dma_q->left_data_count = 0;
1349  }
1350 
1351  p_buffer = urb->transfer_buffer +
1352  urb->iso_frame_desc[i].offset;
1353  buffer_size = urb->iso_frame_desc[i].actual_length;
1354 
1355  if (buffer_size > 0)
1356  buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1357  }
1358 
1359  return 0;
1360 }
1361 static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1362 {
1363 
1364  /*char *outp;*/
1365  /*struct cx231xx_buffer *buf;*/
1366  struct cx231xx_dmaqueue *dma_q = urb->context;
1367  unsigned char *p_buffer, *buffer;
1368  u32 buffer_size = 0;
1369 
1370  p_buffer = urb->transfer_buffer;
1371  buffer_size = urb->actual_length;
1372 
1373  buffer = kmalloc(buffer_size, GFP_ATOMIC);
1374 
1375  memcpy(buffer, dma_q->ps_head, 3);
1376  memcpy(buffer+3, p_buffer, buffer_size-3);
1377  memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1378 
1379  p_buffer = buffer;
1380  buffer_filled(p_buffer, buffer_size, urb, dma_q);
1381 
1382  kfree(buffer);
1383  return 0;
1384 }
1385 
1386 static int bb_buf_prepare(struct videobuf_queue *q,
1387  struct videobuf_buffer *vb, enum v4l2_field field)
1388 {
1389  struct cx231xx_fh *fh = q->priv_data;
1390  struct cx231xx_buffer *buf =
1391  container_of(vb, struct cx231xx_buffer, vb);
1392  struct cx231xx *dev = fh->dev;
1393  int rc = 0, urb_init = 0;
1394  int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1395 
1396  dma_qq = &dev->video_mode.vidq;
1397 
1398  if (0 != buf->vb.baddr && buf->vb.bsize < size)
1399  return -EINVAL;
1400  buf->vb.width = fh->dev->ts1.ts_packet_size;
1401  buf->vb.height = fh->dev->ts1.ts_packet_count;
1402  buf->vb.size = size;
1403  buf->vb.field = field;
1404 
1405  if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1406  rc = videobuf_iolock(q, &buf->vb, NULL);
1407  if (rc < 0)
1408  goto fail;
1409  }
1410 
1411  if (dev->USE_ISO) {
1412  if (!dev->video_mode.isoc_ctl.num_bufs)
1413  urb_init = 1;
1414  } else {
1415  if (!dev->video_mode.bulk_ctl.num_bufs)
1416  urb_init = 1;
1417  }
1418  /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1419  urb_init, dev->video_mode.max_pkt_size);*/
1420  dev->mode_tv = 1;
1421 
1422  if (urb_init) {
1424  rc = cx231xx_unmute_audio(dev);
1425  if (dev->USE_ISO) {
1427  rc = cx231xx_init_isoc(dev, mpeglines,
1428  mpegbufs,
1429  dev->ts1_mode.max_pkt_size,
1430  cx231xx_isoc_copy);
1431  } else {
1433  rc = cx231xx_init_bulk(dev, mpeglines,
1434  mpegbufs,
1435  dev->ts1_mode.max_pkt_size,
1436  cx231xx_bulk_copy);
1437  }
1438  if (rc < 0)
1439  goto fail;
1440  }
1441 
1442  buf->vb.state = VIDEOBUF_PREPARED;
1443  return 0;
1444 
1445 fail:
1446  free_buffer(q, buf);
1447  return rc;
1448 }
1449 
1450 static void bb_buf_queue(struct videobuf_queue *q,
1451  struct videobuf_buffer *vb)
1452 {
1453  struct cx231xx_fh *fh = q->priv_data;
1454 
1455  struct cx231xx_buffer *buf =
1456  container_of(vb, struct cx231xx_buffer, vb);
1457  struct cx231xx *dev = fh->dev;
1458  struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1459 
1460  buf->vb.state = VIDEOBUF_QUEUED;
1461  list_add_tail(&buf->vb.queue, &vidq->active);
1462 
1463 }
1464 
1465 static void bb_buf_release(struct videobuf_queue *q,
1466  struct videobuf_buffer *vb)
1467 {
1468  struct cx231xx_buffer *buf =
1469  container_of(vb, struct cx231xx_buffer, vb);
1470  /*struct cx231xx_fh *fh = q->priv_data;*/
1471  /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1472 
1473  free_buffer(q, buf);
1474 }
1475 
1476 static struct videobuf_queue_ops cx231xx_qops = {
1477  .buf_setup = bb_buf_setup,
1478  .buf_prepare = bb_buf_prepare,
1479  .buf_queue = bb_buf_queue,
1480  .buf_release = bb_buf_release,
1481 };
1482 
1483 /* ------------------------------------------------------------------ */
1484 
1485 static const u32 *ctrl_classes[] = {
1487  NULL
1488 };
1489 
1490 static int cx231xx_queryctrl(struct cx231xx *dev,
1491  struct v4l2_queryctrl *qctrl)
1492 {
1493  qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1494  if (qctrl->id == 0)
1495  return -EINVAL;
1496 
1497  /* MPEG V4L2 controls */
1498  if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1499  qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1500 
1501  return 0;
1502 }
1503 
1504 static int cx231xx_querymenu(struct cx231xx *dev,
1505  struct v4l2_querymenu *qmenu)
1506 {
1507  struct v4l2_queryctrl qctrl;
1508 
1509  qctrl.id = qmenu->id;
1510  cx231xx_queryctrl(dev, &qctrl);
1511  return v4l2_ctrl_query_menu(qmenu, &qctrl,
1512  cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
1513 }
1514 
1515 static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1516 {
1517  struct cx231xx_fh *fh = file->private_data;
1518  struct cx231xx *dev = fh->dev;
1519 
1520  *norm = dev->encodernorm.id;
1521  return 0;
1522 }
1523 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
1524 {
1525  struct cx231xx_fh *fh = file->private_data;
1526  struct cx231xx *dev = fh->dev;
1527  unsigned int i;
1528 
1529  for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1530  if (*id & cx231xx_tvnorms[i].id)
1531  break;
1532  if (i == ARRAY_SIZE(cx231xx_tvnorms))
1533  return -EINVAL;
1534  dev->encodernorm = cx231xx_tvnorms[i];
1535 
1536  if (dev->encodernorm.id & 0xb000) {
1537  dprintk(3, "encodernorm set to NTSC\n");
1538  dev->norm = V4L2_STD_NTSC;
1539  dev->ts1.height = 480;
1540  dev->mpeg_params.is_50hz = 0;
1541  } else {
1542  dprintk(3, "encodernorm set to PAL\n");
1543  dev->norm = V4L2_STD_PAL_B;
1544  dev->ts1.height = 576;
1545  dev->mpeg_params.is_50hz = 1;
1546  }
1547  call_all(dev, core, s_std, dev->norm);
1548  /* do mode control overrides */
1550 
1551  dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1552  return 0;
1553 }
1554 static int vidioc_g_audio(struct file *file, void *fh,
1555  struct v4l2_audio *a)
1556 {
1557  struct v4l2_audio *vin = a;
1558 
1559  int ret = -EINVAL;
1560  if (vin->index > 0)
1561  return ret;
1562  strncpy(vin->name, "VideoGrabber Audio", 14);
1564 return 0;
1565 }
1566 static int vidioc_enumaudio(struct file *file, void *fh,
1567  struct v4l2_audio *a)
1568 {
1569  struct v4l2_audio *vin = a;
1570 
1571  int ret = -EINVAL;
1572 
1573  if (vin->index > 0)
1574  return ret;
1575  strncpy(vin->name, "VideoGrabber Audio", 14);
1577 
1578 
1579 return 0;
1580 }
1581 static const char *iname[] = {
1582  [CX231XX_VMUX_COMPOSITE1] = "Composite1",
1583  [CX231XX_VMUX_SVIDEO] = "S-Video",
1584  [CX231XX_VMUX_TELEVISION] = "Television",
1585  [CX231XX_VMUX_CABLE] = "Cable TV",
1586  [CX231XX_VMUX_DVB] = "DVB",
1587  [CX231XX_VMUX_DEBUG] = "for debug only",
1588 };
1589 static int vidioc_enum_input(struct file *file, void *priv,
1590  struct v4l2_input *i)
1591 {
1592  struct cx231xx_fh *fh = file->private_data;
1593  struct cx231xx *dev = fh->dev;
1594  struct cx231xx_input *input;
1595  int n;
1596  dprintk(3, "enter vidioc_enum_input()i->index=%d\n", i->index);
1597 
1598  if (i->index >= 4)
1599  return -EINVAL;
1600 
1601 
1602  input = &cx231xx_boards[dev->model].input[i->index];
1603 
1604  if (input->type == 0)
1605  return -EINVAL;
1606 
1607  /* FIXME
1608  * strcpy(i->name, input->name); */
1609 
1610  n = i->index;
1611  strcpy(i->name, iname[INPUT(n)->type]);
1612 
1613  if (input->type == CX231XX_VMUX_TELEVISION ||
1614  input->type == CX231XX_VMUX_CABLE)
1616  else
1618 
1619 
1620  return 0;
1621 }
1622 
1623 static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1624 {
1625  *i = 0;
1626  return 0;
1627 }
1628 
1629 static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1630 {
1631  struct cx231xx_fh *fh = file->private_data;
1632  struct cx231xx *dev = fh->dev;
1633 
1634  dprintk(3, "enter vidioc_s_input() i=%d\n", i);
1635 
1636  mutex_lock(&dev->lock);
1637 
1638  video_mux(dev, i);
1639 
1640  mutex_unlock(&dev->lock);
1641 
1642  if (i >= 4)
1643  return -EINVAL;
1644  dev->input = i;
1645  dprintk(3, "exit vidioc_s_input()\n");
1646  return 0;
1647 }
1648 
1649 static int vidioc_g_tuner(struct file *file, void *priv,
1650  struct v4l2_tuner *t)
1651 {
1652  return 0;
1653 }
1654 
1655 static int vidioc_s_tuner(struct file *file, void *priv,
1656  struct v4l2_tuner *t)
1657 {
1658  return 0;
1659 }
1660 
1661 static int vidioc_g_frequency(struct file *file, void *priv,
1662  struct v4l2_frequency *f)
1663 {
1664  return 0;
1665 }
1666 
1667 static int vidioc_s_frequency(struct file *file, void *priv,
1668  struct v4l2_frequency *f)
1669 {
1670 
1671 
1672  return 0;
1673 }
1674 
1675 static int vidioc_s_ctrl(struct file *file, void *priv,
1676  struct v4l2_control *ctl)
1677 {
1678  struct cx231xx_fh *fh = file->private_data;
1679  struct cx231xx *dev = fh->dev;
1680  dprintk(3, "enter vidioc_s_ctrl()\n");
1681  /* Update the A/V core */
1682  call_all(dev, core, s_ctrl, ctl);
1683  dprintk(3, "exit vidioc_s_ctrl()\n");
1684  return 0;
1685 }
1686 static struct v4l2_capability pvr_capability = {
1687  .driver = "cx231xx",
1688  .card = "VideoGrabber",
1689  .bus_info = "usb",
1690  .version = 1,
1691  .capabilities = (V4L2_CAP_VIDEO_CAPTURE |
1694 };
1695 static int vidioc_querycap(struct file *file, void *priv,
1696  struct v4l2_capability *cap)
1697 {
1698 
1699 
1700 
1701  memcpy(cap, &pvr_capability, sizeof(struct v4l2_capability));
1702  return 0;
1703 }
1704 
1705 static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1706  struct v4l2_fmtdesc *f)
1707 {
1708 
1709  if (f->index != 0)
1710  return -EINVAL;
1711 
1712  strlcpy(f->description, "MPEG", sizeof(f->description));
1714 
1715  return 0;
1716 }
1717 
1718 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1719  struct v4l2_format *f)
1720 {
1721  struct cx231xx_fh *fh = file->private_data;
1722  struct cx231xx *dev = fh->dev;
1723  dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1724  f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1725  f->fmt.pix.bytesperline = 0;
1726  f->fmt.pix.sizeimage =
1727  dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1728  f->fmt.pix.colorspace = 0;
1729  f->fmt.pix.width = dev->ts1.width;
1730  f->fmt.pix.height = dev->ts1.height;
1731  f->fmt.pix.field = fh->vidq.field;
1732  dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1733  dev->ts1.width, dev->ts1.height, fh->vidq.field);
1734  dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1735  return 0;
1736 }
1737 
1738 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1739  struct v4l2_format *f)
1740 {
1741  struct cx231xx_fh *fh = file->private_data;
1742  struct cx231xx *dev = fh->dev;
1743  dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1744  f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1745  f->fmt.pix.bytesperline = 0;
1746  f->fmt.pix.sizeimage =
1747  dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1748  f->fmt.pix.colorspace = 0;
1749  dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1750  dev->ts1.width, dev->ts1.height, fh->vidq.field);
1751  dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1752  return 0;
1753 }
1754 
1755 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1756  struct v4l2_format *f)
1757 {
1758 
1759  return 0;
1760 }
1761 
1762 static int vidioc_reqbufs(struct file *file, void *priv,
1763  struct v4l2_requestbuffers *p)
1764 {
1765  struct cx231xx_fh *fh = file->private_data;
1766 
1767  return videobuf_reqbufs(&fh->vidq, p);
1768 }
1769 
1770 static int vidioc_querybuf(struct file *file, void *priv,
1771  struct v4l2_buffer *p)
1772 {
1773  struct cx231xx_fh *fh = file->private_data;
1774 
1775  return videobuf_querybuf(&fh->vidq, p);
1776 }
1777 
1778 static int vidioc_qbuf(struct file *file, void *priv,
1779  struct v4l2_buffer *p)
1780 {
1781  struct cx231xx_fh *fh = file->private_data;
1782 
1783  return videobuf_qbuf(&fh->vidq, p);
1784 }
1785 
1786 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1787 {
1788  struct cx231xx_fh *fh = priv;
1789 
1790  return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1791 }
1792 
1793 
1794 static int vidioc_streamon(struct file *file, void *priv,
1795  enum v4l2_buf_type i)
1796 {
1797  struct cx231xx_fh *fh = file->private_data;
1798 
1799  struct cx231xx *dev = fh->dev;
1800  dprintk(3, "enter vidioc_streamon()\n");
1803  if (dev->USE_ISO)
1806  dev->video_mode.max_pkt_size,
1807  cx231xx_isoc_copy);
1808  else {
1809  cx231xx_init_bulk(dev, 320,
1810  5,
1811  dev->ts1_mode.max_pkt_size,
1812  cx231xx_bulk_copy);
1813  }
1814  dprintk(3, "exit vidioc_streamon()\n");
1815  return videobuf_streamon(&fh->vidq);
1816 }
1817 
1818 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1819 {
1820  struct cx231xx_fh *fh = file->private_data;
1821 
1822  return videobuf_streamoff(&fh->vidq);
1823 }
1824 
1825 static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1826  struct v4l2_ext_controls *f)
1827 {
1828  struct cx231xx_fh *fh = priv;
1829  struct cx231xx *dev = fh->dev;
1830  dprintk(3, "enter vidioc_g_ext_ctrls()\n");
1831  if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1832  return -EINVAL;
1833  dprintk(3, "exit vidioc_g_ext_ctrls()\n");
1834  return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1835 }
1836 
1837 static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1838  struct v4l2_ext_controls *f)
1839 {
1840  struct cx231xx_fh *fh = priv;
1841  struct cx231xx *dev = fh->dev;
1842  struct cx2341x_mpeg_params p;
1843  int err;
1844  dprintk(3, "enter vidioc_s_ext_ctrls()\n");
1845  if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1846  return -EINVAL;
1847 
1848  p = dev->mpeg_params;
1849  err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1850  if (err == 0) {
1851  err = cx2341x_update(dev, cx231xx_mbox_func,
1852  &dev->mpeg_params, &p);
1853  dev->mpeg_params = p;
1854  }
1855 
1856  return err;
1857 
1858 
1859 return 0;
1860 }
1861 
1862 static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1863  struct v4l2_ext_controls *f)
1864 {
1865  struct cx231xx_fh *fh = priv;
1866  struct cx231xx *dev = fh->dev;
1867  struct cx2341x_mpeg_params p;
1868  int err;
1869  dprintk(3, "enter vidioc_try_ext_ctrls()\n");
1870  if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1871  return -EINVAL;
1872 
1873  p = dev->mpeg_params;
1874  err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1875  dprintk(3, "exit vidioc_try_ext_ctrls() err=%d\n", err);
1876  return err;
1877 }
1878 
1879 static int vidioc_log_status(struct file *file, void *priv)
1880 {
1881  struct cx231xx_fh *fh = priv;
1882  struct cx231xx *dev = fh->dev;
1883  char name[32 + 2];
1884 
1885  snprintf(name, sizeof(name), "%s/2", dev->name);
1886  dprintk(3,
1887  "%s/2: ============ START LOG STATUS ============\n",
1888  dev->name);
1889  call_all(dev, core, log_status);
1890  cx2341x_log_status(&dev->mpeg_params, name);
1891  dprintk(3,
1892  "%s/2: ============= END LOG STATUS =============\n",
1893  dev->name);
1894  return 0;
1895 }
1896 
1897 static int vidioc_querymenu(struct file *file, void *priv,
1898  struct v4l2_querymenu *a)
1899 {
1900  struct cx231xx_fh *fh = priv;
1901  struct cx231xx *dev = fh->dev;
1902  dprintk(3, "enter vidioc_querymenu()\n");
1903  dprintk(3, "exit vidioc_querymenu()\n");
1904  return cx231xx_querymenu(dev, a);
1905 }
1906 
1907 static int vidioc_queryctrl(struct file *file, void *priv,
1908  struct v4l2_queryctrl *c)
1909 {
1910  struct cx231xx_fh *fh = priv;
1911  struct cx231xx *dev = fh->dev;
1912  dprintk(3, "enter vidioc_queryctrl()\n");
1913  dprintk(3, "exit vidioc_queryctrl()\n");
1914  return cx231xx_queryctrl(dev, c);
1915 }
1916 
1917 static int mpeg_open(struct file *file)
1918 {
1919  int minor = video_devdata(file)->minor;
1920  struct cx231xx *h, *dev = NULL;
1921  /*struct list_head *list;*/
1922  struct cx231xx_fh *fh;
1923  /*u32 value = 0;*/
1924 
1925  dprintk(2, "%s()\n", __func__);
1926 
1927  list_for_each_entry(h, &cx231xx_devlist, devlist) {
1928  if (h->v4l_device->minor == minor)
1929  dev = h;
1930  }
1931 
1932  if (dev == NULL)
1933  return -ENODEV;
1934 
1935  mutex_lock(&dev->lock);
1936 
1937  /* allocate + initialize per filehandle data */
1938  fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1939  if (NULL == fh) {
1940  mutex_unlock(&dev->lock);
1941  return -ENOMEM;
1942  }
1943 
1944  file->private_data = fh;
1945  fh->dev = dev;
1946 
1947 
1948  videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1949  NULL, &dev->video_mode.slock,
1951  sizeof(struct cx231xx_buffer), fh, NULL);
1952 /*
1953  videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1954  &dev->udev->dev, &dev->ts1.slock,
1955  V4L2_BUF_TYPE_VIDEO_CAPTURE,
1956  V4L2_FIELD_INTERLACED,
1957  sizeof(struct cx231xx_buffer),
1958  fh, NULL);
1959 */
1960 
1961 
1963  cx231xx_set_gpio_value(dev, 2, 0);
1964 
1965  cx231xx_initialize_codec(dev);
1966 
1967  mutex_unlock(&dev->lock);
1968  cx231xx_start_TS1(dev);
1969 
1970  return 0;
1971 }
1972 
1973 static int mpeg_release(struct file *file)
1974 {
1975  struct cx231xx_fh *fh = file->private_data;
1976  struct cx231xx *dev = fh->dev;
1977 
1978  dprintk(3, "mpeg_release()! dev=0x%p\n", dev);
1979 
1980  if (!dev) {
1981  dprintk(3, "abort!!!\n");
1982  return 0;
1983  }
1984 
1985  mutex_lock(&dev->lock);
1986 
1987  cx231xx_stop_TS1(dev);
1988 
1989  /* do this before setting alternate! */
1990  if (dev->USE_ISO)
1991  cx231xx_uninit_isoc(dev);
1992  else
1993  cx231xx_uninit_bulk(dev);
1995 
1996  cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1999 
2000  /* FIXME: Review this crap */
2001  /* Shut device down on last close */
2002  if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
2003  if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
2004  /* stop mpeg capture */
2005 
2006  msleep(500);
2007  cx231xx_417_check_encoder(dev);
2008 
2009  }
2010  }
2011 
2012  if (fh->vidq.streaming)
2013  videobuf_streamoff(&fh->vidq);
2014  if (fh->vidq.reading)
2015  videobuf_read_stop(&fh->vidq);
2016 
2017  videobuf_mmap_free(&fh->vidq);
2018  file->private_data = NULL;
2019  kfree(fh);
2020  mutex_unlock(&dev->lock);
2021  return 0;
2022 }
2023 
2024 static ssize_t mpeg_read(struct file *file, char __user *data,
2025  size_t count, loff_t *ppos)
2026 {
2027  struct cx231xx_fh *fh = file->private_data;
2028  struct cx231xx *dev = fh->dev;
2029 
2030 
2031  /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
2032  /* Start mpeg encoder on first read. */
2033  if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
2034  if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
2035  if (cx231xx_initialize_codec(dev) < 0)
2036  return -EINVAL;
2037  }
2038  }
2039 
2040  return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
2041  file->f_flags & O_NONBLOCK);
2042 }
2043 
2044 static unsigned int mpeg_poll(struct file *file,
2045  struct poll_table_struct *wait)
2046 {
2047  struct cx231xx_fh *fh = file->private_data;
2048  /*struct cx231xx *dev = fh->dev;*/
2049 
2050  /*dprintk(2, "%s\n", __func__);*/
2051 
2052  return videobuf_poll_stream(file, &fh->vidq, wait);
2053 }
2054 
2055 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
2056 {
2057  struct cx231xx_fh *fh = file->private_data;
2058  struct cx231xx *dev = fh->dev;
2059 
2060  dprintk(2, "%s()\n", __func__);
2061 
2062  return videobuf_mmap_mapper(&fh->vidq, vma);
2063 }
2064 
2065 static struct v4l2_file_operations mpeg_fops = {
2066  .owner = THIS_MODULE,
2067  .open = mpeg_open,
2068  .release = mpeg_release,
2069  .read = mpeg_read,
2070  .poll = mpeg_poll,
2071  .mmap = mpeg_mmap,
2072  .ioctl = video_ioctl2,
2073 };
2074 
2075 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
2076  .vidioc_s_std = vidioc_s_std,
2077  .vidioc_g_std = vidioc_g_std,
2078  .vidioc_enum_input = vidioc_enum_input,
2079  .vidioc_enumaudio = vidioc_enumaudio,
2080  .vidioc_g_audio = vidioc_g_audio,
2081  .vidioc_g_input = vidioc_g_input,
2082  .vidioc_s_input = vidioc_s_input,
2083  .vidioc_g_tuner = vidioc_g_tuner,
2084  .vidioc_s_tuner = vidioc_s_tuner,
2085  .vidioc_g_frequency = vidioc_g_frequency,
2086  .vidioc_s_frequency = vidioc_s_frequency,
2087  .vidioc_s_ctrl = vidioc_s_ctrl,
2088  .vidioc_querycap = vidioc_querycap,
2089  .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
2090  .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
2091  .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
2092  .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
2093  .vidioc_reqbufs = vidioc_reqbufs,
2094  .vidioc_querybuf = vidioc_querybuf,
2095  .vidioc_qbuf = vidioc_qbuf,
2096  .vidioc_dqbuf = vidioc_dqbuf,
2097  .vidioc_streamon = vidioc_streamon,
2098  .vidioc_streamoff = vidioc_streamoff,
2099  .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
2100  .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
2101  .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
2102  .vidioc_log_status = vidioc_log_status,
2103  .vidioc_querymenu = vidioc_querymenu,
2104  .vidioc_queryctrl = vidioc_queryctrl,
2105 /* .vidioc_g_chip_ident = cx231xx_g_chip_ident,*/
2106 #ifdef CONFIG_VIDEO_ADV_DEBUG
2107 /* .vidioc_g_register = cx231xx_g_register,*/
2108 /* .vidioc_s_register = cx231xx_s_register,*/
2109 #endif
2110 };
2111 
2112 static struct video_device cx231xx_mpeg_template = {
2113  .name = "cx231xx",
2114  .fops = &mpeg_fops,
2115  .ioctl_ops = &mpeg_ioctl_ops,
2116  .minor = -1,
2117  .tvnorms = CX231xx_NORMS,
2118  .current_norm = V4L2_STD_NTSC_M,
2119 };
2120 
2122 {
2123  dprintk(1, "%s()\n", __func__);
2124  dprintk(3, "%s()\n", __func__);
2125 
2126  if (dev->v4l_device) {
2127  if (-1 != dev->v4l_device->minor)
2129  else
2131  dev->v4l_device = NULL;
2132  }
2133 }
2134 
2135 static struct video_device *cx231xx_video_dev_alloc(
2136  struct cx231xx *dev,
2137  struct usb_device *usbdev,
2138  struct video_device *template,
2139  char *type)
2140 {
2141  struct video_device *vfd;
2142 
2143  dprintk(1, "%s()\n", __func__);
2144  vfd = video_device_alloc();
2145  if (NULL == vfd)
2146  return NULL;
2147  *vfd = *template;
2148  vfd->minor = -1;
2149  snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
2150  type, cx231xx_boards[dev->model].name);
2151 
2152  vfd->v4l2_dev = &dev->v4l2_dev;
2154 
2155  return vfd;
2156 
2157 }
2158 
2160 {
2161  /* FIXME: Port1 hardcoded here */
2162  int err = -ENODEV;
2163  struct cx231xx_tsport *tsport = &dev->ts1;
2164 
2165  dprintk(1, "%s()\n", __func__);
2166 
2167  /* Set default TV standard */
2168  dev->encodernorm = cx231xx_tvnorms[0];
2169 
2170  if (dev->encodernorm.id & V4L2_STD_525_60)
2171  tsport->height = 480;
2172  else
2173  tsport->height = 576;
2174 
2175  tsport->width = 720;
2177  dev->norm = V4L2_STD_NTSC;
2178 
2179  dev->mpeg_params.port = CX2341X_PORT_SERIAL;
2180 
2181  /* Allocate and initialize V4L video device */
2182  dev->v4l_device = cx231xx_video_dev_alloc(dev,
2183  dev->udev, &cx231xx_mpeg_template, "mpeg");
2184  err = video_register_device(dev->v4l_device,
2185  VFL_TYPE_GRABBER, -1);
2186  if (err < 0) {
2187  dprintk(3, "%s: can't register mpeg device\n", dev->name);
2188  return err;
2189  }
2190 
2191  dprintk(3, "%s: registered device video%d [mpeg]\n",
2192  dev->name, dev->v4l_device->num);
2193 
2194  return 0;
2195 }
2196