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Data Structures | Macros | Enumerations | Variables
d11.h File Reference
#include <linux/ieee80211.h>
#include <defs.h>
#include "pub.h"
#include "dma.h"

Go to the source code of this file.

Data Structures

struct  intctrlregs
 
struct  pio2regs
 
struct  pio2regp
 
struct  pio4regs
 
struct  pio4regp
 
union  pmqreg
 
struct  fifo64
 
struct  d11regs
 
struct  ofdm_phy_hdr
 
struct  cck_phy_hdr
 
struct  d11txh
 
struct  tx_status
 
struct  shm_acparams
 
struct  d11rxhdr_le
 
struct  d11rxhdr
 
struct  macstat
 
struct  d11cnt
 

Macros

#define RX_FIFO   0 /* data and ctl frames */
 
#define RX_TXSTATUS_FIFO   3 /* RX fifo for tx status packages */
 
#define TX_AC_BK_FIFO   0 /* Background TX FIFO */
 
#define TX_AC_BE_FIFO   1 /* Best-Effort TX FIFO */
 
#define TX_AC_VI_FIFO   2 /* Video TX FIFO */
 
#define TX_AC_VO_FIFO   3 /* Voice TX FIFO */
 
#define TX_BCMC_FIFO   4 /* Broadcast/Multicast TX FIFO */
 
#define TX_ATIM_FIFO   5 /* TX fifo for ATIM window info */
 
#define M_AC_TXLMT_BASE_ADDR   (0x180 * 2)
 
#define M_AC_TXLMT_ADDR(_ac)   (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
 
#define TX_DATA_FIFO   TX_AC_BE_FIFO
 
#define TX_CTL_FIFO   TX_AC_VO_FIFO
 
#define WL_RSSI_ANT_MAX   4 /* max possible rx antennas */
 
#define D11REGOFFS(field)   offsetof(struct d11regs, field)
 
#define PIHR_BASE   0x0400 /* byte address of packed IHR region */
 
#define BT_DONE   (1U << 31) /* bist done */
 
#define BT_B2S   (1 << 30) /* bist2 ram summary bit */
 
#define I_PC   (1 << 10) /* pci descriptor error */
 
#define I_PD   (1 << 11) /* pci data error */
 
#define I_DE   (1 << 12) /* descriptor protocol error */
 
#define I_RU   (1 << 13) /* receive descriptor underflow */
 
#define I_RO   (1 << 14) /* receive fifo overflow */
 
#define I_XU   (1 << 15) /* transmit fifo underflow */
 
#define I_RI   (1 << 16) /* receive interrupt */
 
#define I_XI   (1 << 24) /* transmit interrupt */
 
#define IRL_TO_MASK   0x00ffffff /* timeout */
 
#define IRL_FC_MASK   0xff000000 /* frame count */
 
#define IRL_FC_SHIFT   24 /* frame count */
 
#define MCTL_GMODE   (1U << 31)
 
#define MCTL_DISCARD_PMQ   (1 << 30)
 
#define MCTL_WAKE   (1 << 26)
 
#define MCTL_HPS   (1 << 25)
 
#define MCTL_PROMISC   (1 << 24)
 
#define MCTL_KEEPBADFCS   (1 << 23)
 
#define MCTL_KEEPCONTROL   (1 << 22)
 
#define MCTL_PHYLOCK   (1 << 21)
 
#define MCTL_BCNS_PROMISC   (1 << 20)
 
#define MCTL_LOCK_RADIO   (1 << 19)
 
#define MCTL_AP   (1 << 18)
 
#define MCTL_INFRA   (1 << 17)
 
#define MCTL_BIGEND   (1 << 16)
 
#define MCTL_GPOUT_SEL_MASK   (3 << 14)
 
#define MCTL_GPOUT_SEL_SHIFT   14
 
#define MCTL_EN_PSMDBG   (1 << 13)
 
#define MCTL_IHR_EN   (1 << 10)
 
#define MCTL_SHM_UPPER   (1 << 9)
 
#define MCTL_SHM_EN   (1 << 8)
 
#define MCTL_PSM_JMP_0   (1 << 2)
 
#define MCTL_PSM_RUN   (1 << 1)
 
#define MCTL_EN_MAC   (1 << 0)
 
#define MCMD_BCN0VLD   (1 << 0)
 
#define MCMD_BCN1VLD   (1 << 1)
 
#define MCMD_DIRFRMQVAL   (1 << 2)
 
#define MCMD_CCA   (1 << 3)
 
#define MCMD_BG_NOISE   (1 << 4)
 
#define MCMD_SKIP_SHMINIT   (1 << 5) /* only used for simulation */
 
#define MCMD_SAMPLECOLL   MCMD_SKIP_SHMINIT /* reuse for sample collect */
 
#define MI_MACSSPNDD   (1 << 0)
 
#define MI_BCNTPL   (1 << 1)
 
#define MI_TBTT   (1 << 2)
 
#define MI_BCNSUCCESS   (1 << 3)
 
#define MI_BCNCANCLD   (1 << 4)
 
#define MI_ATIMWINEND   (1 << 5)
 
#define MI_PMQ   (1 << 6)
 
#define MI_NSPECGEN_0   (1 << 7)
 
#define MI_NSPECGEN_1   (1 << 8)
 
#define MI_MACTXERR   (1 << 9)
 
#define MI_NSPECGEN_3   (1 << 10)
 
#define MI_PHYTXERR   (1 << 11)
 
#define MI_PME   (1 << 12)
 
#define MI_GP0   (1 << 13)
 
#define MI_GP1   (1 << 14)
 
#define MI_DMAINT   (1 << 15)
 
#define MI_TXSTOP   (1 << 16)
 
#define MI_CCA   (1 << 17)
 
#define MI_BG_NOISE   (1 << 18)
 
#define MI_DTIM_TBTT   (1 << 19)
 
#define MI_PRQ   (1 << 20)
 
#define MI_PWRUP   (1 << 21)
 
#define MI_RESERVED3   (1 << 22)
 
#define MI_RESERVED2   (1 << 23)
 
#define MI_RESERVED1   (1 << 25)
 
#define MI_RFDISABLE   (1 << 28)
 
#define MI_TFS   (1 << 29)
 
#define MI_PHYCHANGED   (1 << 30)
 
#define MI_TO   (1U << 31)
 
#define MCAP_TKIPMIC   0x80000000 /* TKIP MIC hardware present */
 
#define PMQH_DATA_MASK   0xffff0000
 
#define PMQH_BSSCFG   0x00100000
 
#define PMQH_PMOFF   0x00010000
 
#define PMQH_PMON   0x00020000
 
#define PMQH_DASAT   0x00040000
 
#define PMQH_ATIMFAIL   0x00080000
 
#define PMQH_DEL_ENTRY   0x00000001
 
#define PMQH_DEL_MULT   0x00000002
 
#define PMQH_OFLO   0x00000004
 
#define PMQH_NOT_EMPTY   0x00000008
 
#define PDBG_CRS   (1 << 0)
 
#define PDBG_TXA   (1 << 1)
 
#define PDBG_TXF   (1 << 2)
 
#define PDBG_TXE   (1 << 3)
 
#define PDBG_RXF   (1 << 4)
 
#define PDBG_RXS   (1 << 5)
 
#define PDBG_RXFRG   (1 << 6)
 
#define PDBG_RXV   (1 << 7)
 
#define PDBG_RFD   (1 << 16)
 
#define OBJADDR_SEL_MASK   0x000F0000
 
#define OBJADDR_UCM_SEL   0x00000000
 
#define OBJADDR_SHM_SEL   0x00010000
 
#define OBJADDR_SCR_SEL   0x00020000
 
#define OBJADDR_IHR_SEL   0x00030000
 
#define OBJADDR_RCMTA_SEL   0x00040000
 
#define OBJADDR_SRCHM_SEL   0x00060000
 
#define OBJADDR_WINC   0x01000000
 
#define OBJADDR_RINC   0x02000000
 
#define OBJADDR_AUTO_INC   0x03000000
 
#define WEP_PCMADDR   0x07d4
 
#define WEP_PCMDATA   0x07d6
 
#define TXS_V   (1 << 0) /* valid bit */
 
#define TXS_STATUS_MASK   0xffff
 
#define TXS_FID_MASK   0xffff0000
 
#define TXS_FID_SHIFT   16
 
#define TXS_SEQ_MASK   0xffff
 
#define TXS_PTX_MASK   0xff0000
 
#define TXS_PTX_SHIFT   16
 
#define TXS_MU_MASK   0x01000000
 
#define TXS_MU_SHIFT   24
 
#define CCS_ERSRC_REQ_D11PLL   0x00000100 /* d11 core pll request */
 
#define CCS_ERSRC_REQ_PHYPLL   0x00000200 /* PHY pll request */
 
#define CCS_ERSRC_AVAIL_D11PLL   0x01000000 /* d11 core pll available */
 
#define CCS_ERSRC_AVAIL_PHYPLL   0x02000000 /* PHY pll available */
 
#define CCS_ERSRC_REQ_HT   0x00000010 /* HT avail request */
 
#define CCS_ERSRC_AVAIL_HT   0x00020000 /* HT clock available */
 
#define CFPREP_CBI_MASK   0xffffffc0
 
#define CFPREP_CBI_SHIFT   6
 
#define CFPREP_CFPP   0x00000001
 
#define TXFIFOCMD_RESET_MASK   (1 << 15) /* reset */
 
#define TXFIFOCMD_FIFOSEL_SHIFT   8 /* fifo */
 
#define TXFIFO_FIFOTOP_SHIFT   8 /* fifo start */
 
#define TXFIFO_START_BLK16   65 /* Base address + 32 * 512 B/P */
 
#define TXFIFO_START_BLK   6 /* Base address + 6 * 256 B */
 
#define TXFIFO_SIZE_UNIT   256 /* one unit corresponds to 256 bytes */
 
#define MBSS16_TEMPLMEM_MINBLKS   65 /* one unit corresponds to 256 bytes */
 
#define PV_AV_MASK   0xf000
 
#define PV_AV_SHIFT   12
 
#define PV_PT_MASK   0x0f00
 
#define PV_PT_SHIFT   8
 
#define PV_PV_MASK   0x000f
 
#define PHY_TYPE(v)   ((v & PV_PT_MASK) >> PV_PT_SHIFT)
 
#define PHY_TYPE_N   4 /* N-Phy value */
 
#define PHY_TYPE_SSN   6 /* SSLPN-Phy value */
 
#define PHY_TYPE_LCN   8 /* LCN-Phy value */
 
#define PHY_TYPE_LCNXN   9 /* LCNXN-Phy value */
 
#define PHY_TYPE_NULL   0xf /* Invalid Phy value */
 
#define ANA_11N_013   5
 
#define D11A_PHY_HDR_GRATE(phdr)   ((phdr)->rlpt[0] & 0x0f)
 
#define D11A_PHY_HDR_GRES(phdr)   (((phdr)->rlpt[0] >> 4) & 0x01)
 
#define D11A_PHY_HDR_GLENGTH(phdr)   (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
 
#define D11A_PHY_HDR_GPARITY(phdr)   (((phdr)->rlpt[3] >> 1) & 0x01)
 
#define D11A_PHY_HDR_GTAIL(phdr)   (((phdr)->rlpt[3] >> 2) & 0x3f)
 
#define D11A_PHY_HDR_SRATE(phdr, rate)   ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
 
#define D11A_PHY_HDR_SRES(phdr)   ((phdr)->rlpt[0] &= 0xef)
 
#define D11A_PHY_HDR_SLENGTH(phdr, length)
 
#define D11A_PHY_HDR_STAIL(phdr)   ((phdr)->rlpt[3] &= 0x03)
 
#define D11A_PHY_HDR_LEN_L   3 /* low-rate part of PLCP header */
 
#define D11A_PHY_HDR_LEN_R   2 /* high-rate part of PLCP header */
 
#define D11A_PHY_TX_DELAY   (2) /* 2.1 usec */
 
#define D11A_PHY_HDR_TIME   (4) /* low-rate part of PLCP header */
 
#define D11A_PHY_PRE_TIME   (16)
 
#define D11A_PHY_PREHDR_TIME   (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
 
#define D11B_PHY_HDR_LEN   6
 
#define D11B_PHY_TX_DELAY   (3) /* 3.4 usec */
 
#define D11B_PHY_LHDR_TIME   (D11B_PHY_HDR_LEN << 3)
 
#define D11B_PHY_LPRE_TIME   (144)
 
#define D11B_PHY_LPREHDR_TIME   (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
 
#define D11B_PHY_SHDR_TIME   (D11B_PHY_LHDR_TIME >> 1)
 
#define D11B_PHY_SPRE_TIME   (D11B_PHY_LPRE_TIME >> 1)
 
#define D11B_PHY_SPREHDR_TIME   (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
 
#define D11B_PLCP_SIGNAL_LOCKED   (1 << 2)
 
#define D11B_PLCP_SIGNAL_LE   (1 << 7)
 
#define MIMO_PLCP_MCS_MASK   0x7f /* mcs index */
 
#define MIMO_PLCP_40MHZ   0x80 /* 40 Hz frame */
 
#define MIMO_PLCP_AMPDU   0x08 /* ampdu */
 
#define BRCMS_GET_CCK_PLCP_LEN(plcp)   (plcp[4] + (plcp[5] << 8))
 
#define BRCMS_GET_MIMO_PLCP_LEN(plcp)   (plcp[1] + (plcp[2] << 8))
 
#define BRCMS_SET_MIMO_PLCP_LEN(plcp, len)
 
#define BRCMS_SET_MIMO_PLCP_AMPDU(plcp)   (plcp[3] |= MIMO_PLCP_AMPDU)
 
#define BRCMS_CLR_MIMO_PLCP_AMPDU(plcp)   (plcp[3] &= ~MIMO_PLCP_AMPDU)
 
#define BRCMS_IS_MIMO_PLCP_AMPDU(plcp)   (plcp[3] & MIMO_PLCP_AMPDU)
 
#define D11_PHY_HDR_LEN   6
 
#define D11_TXH_LEN   112 /* bytes */
 
#define FT_CCK   0
 
#define FT_OFDM   1
 
#define FT_HT   2
 
#define FT_N   3
 
#define TXC_AMPDU_SHIFT   9 /* shift for ampdu settings */
 
#define TXC_AMPDU_NONE   0 /* Regular MPDU, not an A-MPDU */
 
#define TXC_AMPDU_FIRST   1 /* first MPDU of an A-MPDU */
 
#define TXC_AMPDU_MIDDLE   2 /* intermediate MPDU of an A-MPDU */
 
#define TXC_AMPDU_LAST   3 /* last (or single) MPDU of an A-MPDU */
 
#define TXC_AMIC   0x8000
 
#define TXC_SENDCTS   0x0800
 
#define TXC_AMPDU_MASK   0x0600
 
#define TXC_BW_40   0x0100
 
#define TXC_FREQBAND_5G   0x0080
 
#define TXC_DFCS   0x0040
 
#define TXC_IGNOREPMQ   0x0020
 
#define TXC_HWSEQ   0x0010
 
#define TXC_STARTMSDU   0x0008
 
#define TXC_SENDRTS   0x0004
 
#define TXC_LONGFRAME   0x0002
 
#define TXC_IMMEDACK   0x0001
 
#define TXC_PREAMBLE_RTS_FB_SHORT   0x8000
 
#define TXC_PREAMBLE_RTS_MAIN_SHORT   0x4000
 
#define TXC_PREAMBLE_DATA_FB_SHORT   0x2000
 
#define TXC_AMPDU_FBR   0x1000
 
#define TXC_SECKEY_MASK   0x0FF0
 
#define TXC_SECKEY_SHIFT   4
 
#define TXC_ALT_TXPWR   0x0008
 
#define TXC_SECTYPE_MASK   0x0007
 
#define TXC_SECTYPE_SHIFT   0
 
#define AMPDU_FBR_NULL_DELIM   5 /* Location of Null delimiter count for AMPDU */
 
#define PHY_TXC_PWR_MASK   0xFC00
 
#define PHY_TXC_PWR_SHIFT   10
 
#define PHY_TXC_ANT_MASK   0x03C0 /* bit 6, 7, 8, 9 */
 
#define PHY_TXC_ANT_SHIFT   6
 
#define PHY_TXC_ANT_0_1   0x00C0 /* auto, last rx */
 
#define PHY_TXC_LCNPHY_ANT_LAST   0x0000
 
#define PHY_TXC_ANT_3   0x0200 /* virtual antenna 3 */
 
#define PHY_TXC_ANT_2   0x0100 /* virtual antenna 2 */
 
#define PHY_TXC_ANT_1   0x0080 /* virtual antenna 1 */
 
#define PHY_TXC_ANT_0   0x0040 /* virtual antenna 0 */
 
#define PHY_TXC_SHORT_HDR   0x0010
 
#define PHY_TXC_OLD_ANT_0   0x0000
 
#define PHY_TXC_OLD_ANT_1   0x0100
 
#define PHY_TXC_OLD_ANT_LAST   0x0300
 
#define PHY_TXC1_BW_MASK   0x0007
 
#define PHY_TXC1_BW_10MHZ   0
 
#define PHY_TXC1_BW_10MHZ_UP   1
 
#define PHY_TXC1_BW_20MHZ   2
 
#define PHY_TXC1_BW_20MHZ_UP   3
 
#define PHY_TXC1_BW_40MHZ   4
 
#define PHY_TXC1_BW_40MHZ_DUP   5
 
#define PHY_TXC1_MODE_SHIFT   3
 
#define PHY_TXC1_MODE_MASK   0x0038
 
#define PHY_TXC1_MODE_SISO   0
 
#define PHY_TXC1_MODE_CDD   1
 
#define PHY_TXC1_MODE_STBC   2
 
#define PHY_TXC1_MODE_SDM   3
 
#define PHY_TXC_HTANT_MASK   0x3fC0 /* bits 6-13 */
 
#define XFTS_RTS_FT_SHIFT   2
 
#define XFTS_FBRRTS_FT_SHIFT   4
 
#define XFTS_CHANNEL_SHIFT   8
 
#define PHY_AWS_ANTDIV   0x2000
 
#define IFS_USEEDCF   (1 << 2)
 
#define IFS_CTL1_EDCRS   (1 << 3)
 
#define IFS_CTL1_EDCRS_20L   (1 << 4)
 
#define IFS_CTL1_EDCRS_40   (1 << 5)
 
#define ABI_MAS_ADDR_BMP_IDX_MASK   0x0f00
 
#define ABI_MAS_ADDR_BMP_IDX_SHIFT   8
 
#define ABI_MAS_FBR_ANT_PTN_MASK   0x00f0
 
#define ABI_MAS_FBR_ANT_PTN_SHIFT   4
 
#define ABI_MAS_MRT_ANT_PTN_MASK   0x000f
 
#define TXSTATUS_LEN   16
 
#define TX_STATUS_FRM_RTX_MASK   0xF000
 
#define TX_STATUS_FRM_RTX_SHIFT   12
 
#define TX_STATUS_RTS_RTX_MASK   0x0F00
 
#define TX_STATUS_RTS_RTX_SHIFT   8
 
#define TX_STATUS_MASK   0x00FE
 
#define TX_STATUS_PMINDCTD   (1 << 7) /* PM mode indicated to AP */
 
#define TX_STATUS_INTERMEDIATE   (1 << 6) /* intermediate or 1st ampdu pkg */
 
#define TX_STATUS_AMPDU   (1 << 5) /* AMPDU status */
 
#define TX_STATUS_SUPR_MASK   0x1C /* suppress status bits (4:2) */
 
#define TX_STATUS_SUPR_SHIFT   2
 
#define TX_STATUS_ACK_RCV   (1 << 1) /* ACK received */
 
#define TX_STATUS_VALID   (1 << 0) /* Tx status valid */
 
#define TX_STATUS_NO_ACK   0
 
#define TX_STATUS_SUPR_PMQ   (1 << 2) /* PMQ entry */
 
#define TX_STATUS_SUPR_FLUSH   (2 << 2) /* flush request */
 
#define TX_STATUS_SUPR_FRAG   (3 << 2) /* previous frag failure */
 
#define TX_STATUS_SUPR_TBTT   (3 << 2) /* SHARED: Probe resp supr for TBTT */
 
#define TX_STATUS_SUPR_BADCH   (4 << 2) /* channel mismatch */
 
#define TX_STATUS_SUPR_EXPTIME   (5 << 2) /* lifetime expiry */
 
#define TX_STATUS_SUPR_UF   (6 << 2) /* underflow */
 
#define TX_STATUS_UNEXP(status)
 
#define TX_STATUS_UNEXP_AMPDU(status)
 
#define TX_STATUS_BA_BMAP03_MASK   0xF000 /* ba bitmap 0:3 in 1st pkg */
 
#define TX_STATUS_BA_BMAP03_SHIFT   12 /* ba bitmap 0:3 in 1st pkg */
 
#define TX_STATUS_BA_BMAP47_MASK   0x001E /* ba bitmap 4:7 in 2nd pkg */
 
#define TX_STATUS_BA_BMAP47_SHIFT   3 /* ba bitmap 4:7 in 2nd pkg */
 
#define RCM_INC_MASK_H   0x0080
 
#define RCM_INC_MASK_L   0x0040
 
#define RCM_INC_DATA   0x0020
 
#define RCM_INDEX_MASK   0x001F
 
#define RCM_SIZE   15
 
#define RCM_MAC_OFFSET   0 /* current MAC address */
 
#define RCM_BSSID_OFFSET   3 /* current BSSID address */
 
#define RCM_F_BSSID_0_OFFSET   6 /* foreign BSS CFP tracking */
 
#define RCM_F_BSSID_1_OFFSET   9 /* foreign BSS CFP tracking */
 
#define RCM_F_BSSID_2_OFFSET   12 /* foreign BSS CFP tracking */
 
#define RCM_WEP_TA0_OFFSET   16
 
#define RCM_WEP_TA1_OFFSET   19
 
#define RCM_WEP_TA2_OFFSET   22
 
#define RCM_WEP_TA3_OFFSET   25
 
#define MAC_PHY_RESET   1
 
#define MAC_PHY_CLOCK_EN   2
 
#define MAC_PHY_FORCE_CLK   4
 
#define WKEY_START   (1 << 8)
 
#define WKEY_SEL_MASK   0x1F
 
#define RCMTA_SIZE   50
 
#define M_ADDR_BMP_BLK   (0x37e * 2)
 
#define M_ADDR_BMP_BLK_SZ   12
 
#define ADDR_BMP_RA   (1 << 0) /* Receiver Address (RA) */
 
#define ADDR_BMP_TA   (1 << 1) /* Transmitter Address (TA) */
 
#define ADDR_BMP_BSSID   (1 << 2) /* BSSID */
 
#define ADDR_BMP_AP   (1 << 3) /* Infra-BSS Access Point */
 
#define ADDR_BMP_STA   (1 << 4) /* Infra-BSS Station */
 
#define ADDR_BMP_RESERVED1   (1 << 5)
 
#define ADDR_BMP_RESERVED2   (1 << 6)
 
#define ADDR_BMP_RESERVED3   (1 << 7)
 
#define ADDR_BMP_BSS_IDX_MASK   (3 << 8) /* BSS control block index */
 
#define ADDR_BMP_BSS_IDX_SHIFT   8
 
#define WSEC_MAX_RCMTA_KEYS   54
 
#define WSEC_MAX_TKMIC_ENGINE_KEYS   12 /* 8 + 4 default */
 
#define WSEC_MAX_RXE_KEYS   4
 
#define SKL_ALGO_MASK   0x0007
 
#define SKL_ALGO_SHIFT   0
 
#define SKL_KEYID_MASK   0x0008
 
#define SKL_KEYID_SHIFT   3
 
#define SKL_INDEX_MASK   0x03F0
 
#define SKL_INDEX_SHIFT   4
 
#define SKL_GRP_ALGO_MASK   0x1c00
 
#define SKL_GRP_ALGO_SHIFT   10
 
#define SKL_IBSS_INDEX_MASK   0x01F0
 
#define SKL_IBSS_INDEX_SHIFT   4
 
#define SKL_IBSS_KEYID1_MASK   0x0600
 
#define SKL_IBSS_KEYID1_SHIFT   9
 
#define SKL_IBSS_KEYID2_MASK   0x1800
 
#define SKL_IBSS_KEYID2_SHIFT   11
 
#define SKL_IBSS_KEYALGO_MASK   0xE000
 
#define SKL_IBSS_KEYALGO_SHIFT   13
 
#define WSEC_MODE_OFF   0
 
#define WSEC_MODE_HW   1
 
#define WSEC_MODE_SW   2
 
#define WSEC_ALGO_OFF   0
 
#define WSEC_ALGO_WEP1   1
 
#define WSEC_ALGO_TKIP   2
 
#define WSEC_ALGO_AES   3
 
#define WSEC_ALGO_WEP128   4
 
#define WSEC_ALGO_AES_LEGACY   5
 
#define WSEC_ALGO_NALG   6
 
#define AES_MODE_NONE   0
 
#define AES_MODE_CCM   1
 
#define WECR0_KEYREG_SHIFT   0
 
#define WECR0_KEYREG_MASK   0x7
 
#define WECR0_DECRYPT   (1 << 3)
 
#define WECR0_IVINLINE   (1 << 4)
 
#define WECR0_WEPALG_SHIFT   5
 
#define WECR0_WEPALG_MASK   (0x7 << 5)
 
#define WECR0_WKEYSEL_SHIFT   8
 
#define WECR0_WKEYSEL_MASK   (0x7 << 8)
 
#define WECR0_WKEYSTART   (1 << 11)
 
#define WECR0_WEPINIT   (1 << 14)
 
#define WECR0_ICVERR   (1 << 15)
 
#define T_ACTS_TPL_BASE   (0)
 
#define T_NULL_TPL_BASE   (0xc * 2)
 
#define T_QNULL_TPL_BASE   (0x1c * 2)
 
#define T_RR_TPL_BASE   (0x2c * 2)
 
#define T_BCN0_TPL_BASE   (0x34 * 2)
 
#define T_PRS_TPL_BASE   (0x134 * 2)
 
#define T_BCN1_TPL_BASE   (0x234 * 2)
 
#define T_TX_FIFO_TXRAM_BASE
 
#define T_BA_TPL_BASE   T_QNULL_TPL_BASE /* template area for BA */
 
#define T_RAM_ACCESS_SZ   4 /* template ram is 4 byte access only */
 
#define M_MACHW_VER   (0x00b * 2)
 
#define M_MACHW_CAP_L   (0x060 * 2)
 
#define M_MACHW_CAP_H   (0x061 * 2)
 
#define M_EDCF_STATUS_OFF   (0x007 * 2)
 
#define M_TXF_CUR_INDEX   (0x018 * 2)
 
#define M_EDCF_QINFO   (0x120 * 2)
 
#define M_DOT11_SLOT   (0x008 * 2)
 
#define M_DOT11_DTIMPERIOD   (0x009 * 2)
 
#define M_NOSLPZNATDTIM   (0x026 * 2)
 
#define M_BCN0_FRM_BYTESZ   (0x00c * 2) /* Bcn 0 template length */
 
#define M_BCN1_FRM_BYTESZ   (0x00d * 2) /* Bcn 1 template length */
 
#define M_BCN_TXTSF_OFFSET   (0x00e * 2)
 
#define M_TIMBPOS_INBEACON   (0x00f * 2)
 
#define M_SFRMTXCNTFBRTHSD   (0x022 * 2)
 
#define M_LFRMTXCNTFBRTHSD   (0x023 * 2)
 
#define M_BCN_PCTLWD   (0x02a * 2)
 
#define M_BCN_LI   (0x05b * 2) /* beacon listen interval */
 
#define M_MAXRXFRM_LEN   (0x010 * 2)
 
#define M_RSP_PCTLWD   (0x011 * 2)
 
#define M_TXPWR_N   (0x012 * 2)
 
#define M_TXPWR_TARGET   (0x013 * 2)
 
#define M_TXPWR_MAX   (0x014 * 2)
 
#define M_TXPWR_CUR   (0x019 * 2)
 
#define M_RX_PAD_DATA_OFFSET   (0x01a * 2)
 
#define M_SEC_DEFIVLOC   (0x01e * 2)
 
#define M_SEC_VALNUMSOFTMCHTA   (0x01f * 2)
 
#define M_PHYVER   (0x028 * 2)
 
#define M_PHYTYPE   (0x029 * 2)
 
#define M_SECRXKEYS_PTR   (0x02b * 2)
 
#define M_TKMICKEYS_PTR   (0x059 * 2)
 
#define M_SECKINDXALGO_BLK   (0x2ea * 2)
 
#define M_SECKINDXALGO_BLK_SZ   54
 
#define M_SECPSMRXTAMCH_BLK   (0x2fa * 2)
 
#define M_TKIP_TSC_TTAK   (0x18c * 2)
 
#define D11_MAX_KEY_SIZE   16
 
#define M_MAX_ANTCNT   (0x02e * 2) /* antenna swap threshold */
 
#define M_SSIDLEN   (0x024 * 2)
 
#define M_PRB_RESP_FRM_LEN   (0x025 * 2)
 
#define M_PRS_MAXTIME   (0x03a * 2)
 
#define M_SSID   (0xb0 * 2)
 
#define M_CTXPRS_BLK   (0xc0 * 2)
 
#define C_CTX_PCTLWD_POS   (0x4 * 2)
 
#define M_OFDM_OFFSET   (0x027 * 2)
 
#define M_B_TSSI_0   (0x02c * 2)
 
#define M_B_TSSI_1   (0x02d * 2)
 
#define M_HOST_FLAGS1   (0x02f * 2)
 
#define M_HOST_FLAGS2   (0x030 * 2)
 
#define M_HOST_FLAGS3   (0x031 * 2)
 
#define M_HOST_FLAGS4   (0x03c * 2)
 
#define M_HOST_FLAGS5   (0x06a * 2)
 
#define M_HOST_FLAGS_SZ   16
 
#define M_RADAR_REG   (0x033 * 2)
 
#define M_A_TSSI_0   (0x034 * 2)
 
#define M_A_TSSI_1   (0x035 * 2)
 
#define M_NOISE_IF_COUNT   (0x034 * 2)
 
#define M_NOISE_IF_TIMEOUT   (0x035 * 2)
 
#define M_RF_RX_SP_REG1   (0x036 * 2)
 
#define M_G_TSSI_0   (0x038 * 2)
 
#define M_G_TSSI_1   (0x039 * 2)
 
#define M_JSSI_0   (0x44 * 2)
 
#define M_JSSI_1   (0x45 * 2)
 
#define M_JSSI_AUX   (0x46 * 2)
 
#define M_CUR_2050_RADIOCODE   (0x47 * 2)
 
#define M_FIFOSIZE0   (0x4c * 2)
 
#define M_FIFOSIZE1   (0x4d * 2)
 
#define M_FIFOSIZE2   (0x4e * 2)
 
#define M_FIFOSIZE3   (0x4f * 2)
 
#define D11_MAX_TX_FRMS   32 /* max frames allowed in tx fifo */
 
#define M_CURCHANNEL   (0x50 * 2)
 
#define D11_CURCHANNEL_5G   0x0100;
 
#define D11_CURCHANNEL_40   0x0200;
 
#define D11_CURCHANNEL_MAX   0x00FF;
 
#define M_BCMC_FID   (0x54 * 2)
 
#define INVALIDFID   0xffff
 
#define M_BCN_PCTL1WD   (0x058 * 2)
 
#define M_TX_IDLE_BUSY_RATIO_X_16_CCK   (0x52 * 2)
 
#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM   (0x5A * 2)
 
#define M_LCN_RSSI_0   0x1332
 
#define M_LCN_RSSI_1   0x1338
 
#define M_LCN_RSSI_2   0x133e
 
#define M_LCN_RSSI_3   0x1344
 
#define M_LCN_SNR_A_0   0x1334
 
#define M_LCN_SNR_B_0   0x1336
 
#define M_LCN_SNR_A_1   0x133a
 
#define M_LCN_SNR_B_1   0x133c
 
#define M_LCN_SNR_A_2   0x1340
 
#define M_LCN_SNR_B_2   0x1342
 
#define M_LCN_SNR_A_3   0x1346
 
#define M_LCN_SNR_B_3   0x1348
 
#define M_LCN_LAST_RESET   (81*2)
 
#define M_LCN_LAST_LOC   (63*2)
 
#define M_LCNPHY_RESET_STATUS   (4902)
 
#define M_LCNPHY_DSC_TIME   (0x98d*2)
 
#define M_LCNPHY_RESET_CNT_DSC   (0x98b*2)
 
#define M_LCNPHY_RESET_CNT   (0x98c*2)
 
#define M_RT_DIRMAP_A   (0xe0 * 2)
 
#define M_RT_BBRSMAP_A   (0xf0 * 2)
 
#define M_RT_DIRMAP_B   (0x100 * 2)
 
#define M_RT_BBRSMAP_B   (0x110 * 2)
 
#define M_RT_PRS_PLCP_POS   10
 
#define M_RT_PRS_DUR_POS   16
 
#define M_RT_OFDM_PCTL1_POS   18
 
#define M_20IN40_IQ   (0x380 * 2)
 
#define M_CURR_IDX1   (0x384 * 2)
 
#define M_CURR_IDX2   (0x387 * 2)
 
#define M_BSCALE_ANT0   (0x5e * 2)
 
#define M_BSCALE_ANT1   (0x5f * 2)
 
#define M_MIMO_ANTSEL_RXDFLT   (0x63 * 2)
 
#define M_ANTSEL_CLKDIV   (0x61 * 2)
 
#define M_MIMO_ANTSEL_TXDFLT   (0x64 * 2)
 
#define M_MIMO_MAXSYM   (0x5d * 2)
 
#define MIMO_MAXSYM_DEF   0x8000 /* 32k */
 
#define MIMO_MAXSYM_MAX   0xffff /* 64k */
 
#define M_WATCHDOG_8TU   (0x1e * 2)
 
#define WATCHDOG_8TU_DEF   5
 
#define WATCHDOG_8TU_MAX   10
 
#define M_PKTENG_CTRL   (0x6c * 2)
 
#define M_PKTENG_IFS   (0x6d * 2)
 
#define M_PKTENG_FRMCNT_LO   (0x6e * 2)
 
#define M_PKTENG_FRMCNT_HI   (0x6f * 2)
 
#define M_LCN_PWR_IDX_MAX   (0x67 * 2) /* highest index read by ucode */
 
#define M_LCN_PWR_IDX_MIN   (0x66 * 2) /* lowest index read by ucode */
 
#define M_PKTENG_MODE_TX   0x0001
 
#define M_PKTENG_MODE_TX_RIFS   0x0004
 
#define M_PKTENG_MODE_TX_CTS   0x0008
 
#define M_PKTENG_MODE_RX   0x0002
 
#define M_PKTENG_MODE_RX_WITH_ACK   0x0402
 
#define M_PKTENG_MODE_MASK   0x0003
 
#define M_PKTENG_FRMCNT_VLD   0x0100
 
#define M_SMPL_COL_BMP   (0x37d * 2)
 
#define M_SMPL_COL_CTL   (0x3b2 * 2)
 
#define ANTSEL_CLKDIV_4MHZ   6
 
#define MIMO_ANTSEL_BUSY   0x4000 /* bit 14 (busy) */
 
#define MIMO_ANTSEL_SEL   0x8000 /* bit 15 write the value */
 
#define MIMO_ANTSEL_WAIT   50 /* 50us wait */
 
#define MIMO_ANTSEL_OVERRIDE   0x8000 /* flag */
 
#define M_EDCF_QLEN   (16 * 2)
 
#define WME_STATUS_NEWAC   (1 << 8)
 
#define MHFMAX   5 /* Number of valid hostflag half-word (u16) */
 
#define MHF1   0 /* Hostflag 1 index */
 
#define MHF2   1 /* Hostflag 2 index */
 
#define MHF3   2 /* Hostflag 3 index */
 
#define MHF4   3 /* Hostflag 4 index */
 
#define MHF5   4 /* Hostflag 5 index */
 
#define MHF1_ANTDIV   0x0001
 
#define MHF1_EDCF   0x0100
 
#define MHF1_IQSWAP_WAR   0x0200
 
#define MHF1_FORCEFASTCLK   0x0400
 
#define MHF2_TXBCMC_NOW   0x0040
 
#define MHF2_HWPWRCTL   0x0080
 
#define MHF2_NPHY40MHZ_WAR   0x0800
 
#define MHF3_ANTSEL_EN   0x0001
 
#define MHF3_ANTSEL_MODE   0x0002
 
#define MHF3_RESERVED1   0x0004
 
#define MHF3_RESERVED2   0x0008
 
#define MHF3_NPHY_MLADV_WAR   0x0010
 
#define MHF4_BPHY_TXCORE0   0x0080
 
#define MHF4_EXTPA_ENABLE   0x4000
 
#define MHF5_4313_GPIOCTRL   0x0001
 
#define MHF5_RESERVED1   0x0002
 
#define MHF5_RESERVED2   0x0004
 
#define M_RADIO_PWR   (0x32 * 2)
 
#define M_PHY_NOISE   (0x037 * 2)
 
#define PHY_NOISE_MASK   0x00ff
 
#define PRXS0_FT_MASK   0x0003
 
#define PRXS0_CLIP_MASK   0x000C
 
#define PRXS0_CLIP_SHIFT   2
 
#define PRXS0_UNSRATE   0x0010
 
#define PRXS0_RXANT_UPSUBBAND   0x0020
 
#define PRXS0_LCRS   0x0040
 
#define PRXS0_SHORTH   0x0080
 
#define PRXS0_PLCPFV   0x0100
 
#define PRXS0_PLCPHCF   0x0200
 
#define PRXS0_GAIN_CTL   0x4000
 
#define PRXS0_ANTSEL_MASK   0xF000
 
#define PRXS0_ANTSEL_SHIFT   0x12
 
#define PRXS0_CCK   0x0000
 
#define PRXS0_OFDM   0x0001
 
#define PRXS0_PREN   0x0002
 
#define PRXS0_STDN   0x0003
 
#define PRXS0_ANTSEL_0   0x0 /* antenna 0 is used */
 
#define PRXS0_ANTSEL_1   0x2 /* antenna 1 is used */
 
#define PRXS0_ANTSEL_2   0x4 /* antenna 2 is used */
 
#define PRXS0_ANTSEL_3   0x8 /* antenna 3 is used */
 
#define PRXS1_JSSI_MASK   0x00FF
 
#define PRXS1_JSSI_SHIFT   0
 
#define PRXS1_SQ_MASK   0xFF00
 
#define PRXS1_SQ_SHIFT   8
 
#define PRXS1_nphy_PWR0_MASK   0x00FF
 
#define PRXS1_nphy_PWR1_MASK   0xFF00
 
#define PRXS0_BAND   0x0400 /* 0 = 2.4G, 1 = 5G */
 
#define PRXS0_RSVD   0x0800 /* reserved; set to 0 */
 
#define PRXS0_UNUSED   0xF000 /* unused and not defined; set to 0 */
 
#define PRXS1_HTPHY_CORE_MASK   0x000F
 
#define PRXS1_HTPHY_ANTCFG_MASK   0x00F0
 
#define PRXS1_HTPHY_MMPLCPLenL_MASK   0xFF00
 
#define PRXS2_HTPHY_MMPLCPLenH_MASK   0x000F
 
#define PRXS2_HTPHY_MMPLCH_RATE_MASK   0x00F0
 
#define PRXS2_HTPHY_RXPWR_ANT0   0xFF00
 
#define PRXS3_HTPHY_RXPWR_ANT1   0x00FF
 
#define PRXS3_HTPHY_RXPWR_ANT2   0xFF00
 
#define PRXS4_HTPHY_RXPWR_ANT3   0x00FF
 
#define PRXS4_HTPHY_CFO   0xFF00
 
#define PRXS5_HTPHY_FFO   0x00FF
 
#define PRXS5_HTPHY_AR   0xFF00
 
#define HTPHY_MMPLCPLen(rxs)
 
#define HTPHY_RXPWR_ANT0(rxs)   ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
 
#define HTPHY_RXPWR_ANT1(rxs)   (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
 
#define HTPHY_RXPWR_ANT2(rxs)   ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
 
#define RXS_BCNSENT   0x8000
 
#define RXS_SECKINDX_MASK   0x07e0
 
#define RXS_SECKINDX_SHIFT   5
 
#define RXS_DECERR   (1 << 4)
 
#define RXS_DECATMPT   (1 << 3)
 
#define RXS_PBPRES   (1 << 2)
 
#define RXS_RESPFRAMETX   (1 << 1)
 
#define RXS_FCSERR   (1 << 0)
 
#define RXS_AMSDU_MASK   1
 
#define RXS_AGGTYPE_MASK   0x6
 
#define RXS_AGGTYPE_SHIFT   1
 
#define RXS_PHYRXST_VALID   (1 << 8)
 
#define RXS_RXANT_MASK   0x3
 
#define RXS_RXANT_SHIFT   12
 
#define RXS_CHAN_40   0x1000
 
#define RXS_CHAN_5G   0x0800
 
#define RXS_CHAN_ID_MASK   0x07f8
 
#define RXS_CHAN_ID_SHIFT   3
 
#define RXS_CHAN_PHYTYPE_MASK   0x0007
 
#define RXS_CHAN_PHYTYPE_SHIFT   0
 
#define M_PWRIND_BLKS   (0x184 * 2)
 
#define M_PWRIND_MAP0   (M_PWRIND_BLKS + 0x0)
 
#define M_PWRIND_MAP1   (M_PWRIND_BLKS + 0x2)
 
#define M_PWRIND_MAP2   (M_PWRIND_BLKS + 0x4)
 
#define M_PWRIND_MAP3   (M_PWRIND_BLKS + 0x6)
 
#define M_PWRIND_MAP(core)   (M_PWRIND_BLKS + ((core)<<1))
 
#define M_PSM_SOFT_REGS   0x0
 
#define M_BOM_REV_MAJOR   (M_PSM_SOFT_REGS + 0x0)
 
#define M_BOM_REV_MINOR   (M_PSM_SOFT_REGS + 0x2)
 
#define M_UCODE_DBGST   (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
 
#define M_UCODE_MACSTAT   (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
 
#define M_AGING_THRSH   (0x3e * 2) /* max time waiting for medium before tx */
 
#define M_MBURST_SIZE   (0x40 * 2) /* max frames in a frameburst */
 
#define M_MBURST_TXOP   (0x41 * 2) /* max frameburst TXOP in unit of us */
 
#define M_SYNTHPU_DLY   (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
 
#define M_PRETBTT   (0x4b * 2)
 
#define M_ALT_TXPWR_IDX   (M_PSM_SOFT_REGS + (0x3b * 2))
 
#define M_PHY_TX_FLT_PTR   (M_PSM_SOFT_REGS + (0x3d * 2))
 
#define M_CTS_DURATION   (M_PSM_SOFT_REGS + (0x5c * 2))
 
#define M_LP_RCCAL_OVR   (M_PSM_SOFT_REGS + (0x6b * 2))
 
#define M_RXSTATS_BLK_PTR   (M_PSM_SOFT_REGS + (0x65 * 2))
 
#define DBGST_INACTIVE   0
 
#define DBGST_INIT   1
 
#define DBGST_ACTIVE   2
 
#define DBGST_SUSPENDED   3
 
#define DBGST_ASLEEP   4
 
#define S_BEACON_INDX   S_OLD_BREM
 
#define S_PRS_INDX   S_OLD_CWWIN
 
#define S_PHYTYPE   S_SSRC
 
#define S_PHYVER   S_SLRC
 
#define SLOW_CTRL_PDE   (1 << 0)
 
#define SLOW_CTRL_FD   (1 << 8)
 
#define SICF_PCLKE   0x0004 /* PHY clock enable */
 
#define SICF_PRST   0x0008 /* PHY reset */
 
#define SICF_MPCLKE   0x0010 /* MAC PHY clockcontrol enable */
 
#define SICF_FREF   0x0020 /* PLL FreqRefSelect */
 
#define SICF_BWMASK   0x00c0 /* phy clock mask (b6 & b7) */
 
#define SICF_BW40   0x0080 /* 40MHz BW (160MHz phyclk) */
 
#define SICF_BW20   0x0040 /* 20MHz BW (80MHz phyclk) */
 
#define SICF_BW10   0x0000 /* 10MHz BW (40MHz phyclk) */
 
#define SICF_GMODE   0x2000 /* gmode enable */
 
#define SISF_2G_PHY   0x0001 /* 2.4G capable phy */
 
#define SISF_5G_PHY   0x0002 /* 5G capable phy */
 
#define SISF_FCLKA   0x0004 /* FastClkAvailable */
 
#define SISF_DB_PHY   0x0008 /* Dualband phy */
 
#define BPHY_REG_OFT_BASE   0x0
 
#define BPHY_BB_CONFIG   0x01
 
#define BPHY_ADCBIAS   0x02
 
#define BPHY_ANACORE   0x03
 
#define BPHY_PHYCRSTH   0x06
 
#define BPHY_TEST   0x0a
 
#define BPHY_PA_TX_TO   0x10
 
#define BPHY_SYNTH_DC_TO   0x11
 
#define BPHY_PA_TX_TIME_UP   0x12
 
#define BPHY_RX_FLTR_TIME_UP   0x13
 
#define BPHY_TX_POWER_OVERRIDE   0x14
 
#define BPHY_RF_OVERRIDE   0x15
 
#define BPHY_RF_TR_LOOKUP1   0x16
 
#define BPHY_RF_TR_LOOKUP2   0x17
 
#define BPHY_COEFFS   0x18
 
#define BPHY_PLL_OUT   0x19
 
#define BPHY_REFRESH_MAIN   0x1a
 
#define BPHY_REFRESH_TO0   0x1b
 
#define BPHY_REFRESH_TO1   0x1c
 
#define BPHY_RSSI_TRESH   0x20
 
#define BPHY_IQ_TRESH_HH   0x21
 
#define BPHY_IQ_TRESH_H   0x22
 
#define BPHY_IQ_TRESH_L   0x23
 
#define BPHY_IQ_TRESH_LL   0x24
 
#define BPHY_GAIN   0x25
 
#define BPHY_LNA_GAIN_RANGE   0x26
 
#define BPHY_JSSI   0x27
 
#define BPHY_TSSI_CTL   0x28
 
#define BPHY_TSSI   0x29
 
#define BPHY_TR_LOSS_CTL   0x2a
 
#define BPHY_LO_LEAKAGE   0x2b
 
#define BPHY_LO_RSSI_ACC   0x2c
 
#define BPHY_LO_IQMAG_ACC   0x2d
 
#define BPHY_TX_DC_OFF1   0x2e
 
#define BPHY_TX_DC_OFF2   0x2f
 
#define BPHY_PEAK_CNT_THRESH   0x30
 
#define BPHY_FREQ_OFFSET   0x31
 
#define BPHY_DIVERSITY_CTL   0x32
 
#define BPHY_PEAK_ENERGY_LO   0x33
 
#define BPHY_PEAK_ENERGY_HI   0x34
 
#define BPHY_SYNC_CTL   0x35
 
#define BPHY_TX_PWR_CTRL   0x36
 
#define BPHY_TX_EST_PWR   0x37
 
#define BPHY_STEP   0x38
 
#define BPHY_WARMUP   0x39
 
#define BPHY_LMS_CFF_READ   0x3a
 
#define BPHY_LMS_COEFF_I   0x3b
 
#define BPHY_LMS_COEFF_Q   0x3c
 
#define BPHY_SIG_POW   0x3d
 
#define BPHY_RFDC_CANCEL_CTL   0x3e
 
#define BPHY_HDR_TYPE   0x40
 
#define BPHY_SFD_TO   0x41
 
#define BPHY_SFD_CTL   0x42
 
#define BPHY_DEBUG   0x43
 
#define BPHY_RX_DELAY_COMP   0x44
 
#define BPHY_CRS_DROP_TO   0x45
 
#define BPHY_SHORT_SFD_NZEROS   0x46
 
#define BPHY_DSSS_COEFF1   0x48
 
#define BPHY_DSSS_COEFF2   0x49
 
#define BPHY_CCK_COEFF1   0x4a
 
#define BPHY_CCK_COEFF2   0x4b
 
#define BPHY_TR_CORR   0x4c
 
#define BPHY_ANGLE_SCALE   0x4d
 
#define BPHY_TX_PWR_BASE_IDX   0x4e
 
#define BPHY_OPTIONAL_MODES2   0x4f
 
#define BPHY_CCK_LMS_STEP   0x50
 
#define BPHY_BYPASS   0x51
 
#define BPHY_CCK_DELAY_LONG   0x52
 
#define BPHY_CCK_DELAY_SHORT   0x53
 
#define BPHY_PPROC_CHAN_DELAY   0x54
 
#define BPHY_DDFS_ENABLE   0x58
 
#define BPHY_PHASE_SCALE   0x59
 
#define BPHY_FREQ_CONTROL   0x5a
 
#define BPHY_LNA_GAIN_RANGE_10   0x5b
 
#define BPHY_LNA_GAIN_RANGE_32   0x5c
 
#define BPHY_OPTIONAL_MODES   0x5d
 
#define BPHY_RX_STATUS2   0x5e
 
#define BPHY_RX_STATUS3   0x5f
 
#define BPHY_DAC_CONTROL   0x60
 
#define BPHY_ANA11G_FILT_CTRL   0x62
 
#define BPHY_REFRESH_CTRL   0x64
 
#define BPHY_RF_OVERRIDE2   0x65
 
#define BPHY_SPUR_CANCEL_CTRL   0x66
 
#define BPHY_FINE_DIGIGAIN_CTRL   0x67
 
#define BPHY_RSSI_LUT   0x88
 
#define BPHY_RSSI_LUT_END   0xa7
 
#define BPHY_TSSI_LUT   0xa8
 
#define BPHY_TSSI_LUT_END   0xc7
 
#define BPHY_TSSI2PWR_LUT   0x380
 
#define BPHY_TSSI2PWR_LUT_END   0x39f
 
#define BPHY_LOCOMP_LUT   0x3a0
 
#define BPHY_LOCOMP_LUT_END   0x3bf
 
#define BPHY_TXGAIN_LUT   0x3c0
 
#define BPHY_TXGAIN_LUT_END   0x3ff
 
#define PHY_BBC_ANT_MASK   0x0180
 
#define PHY_BBC_ANT_SHIFT   7
 
#define BB_DARWIN   0x1000
 
#define BBCFG_RESETCCA   0x4000
 
#define BBCFG_RESETRX   0x8000
 
#define TST_DDFS   0x2000
 
#define TST_TXFILT1   0x0800
 
#define TST_UNSCRAM   0x0400
 
#define TST_CARR_SUPP   0x0200
 
#define TST_DC_COMP_LOOP   0x0100
 
#define TST_LOOPBACK   0x0080
 
#define TST_TXFILT0   0x0040
 
#define TST_TXTEST_ENABLE   0x0020
 
#define TST_TXTEST_RATE   0x0018
 
#define TST_TXTEST_PHASE   0x0007
 
#define TST_TXTEST_RATE_1MBPS   0
 
#define TST_TXTEST_RATE_2MBPS   1
 
#define TST_TXTEST_RATE_5_5MBPS   2
 
#define TST_TXTEST_RATE_11MBPS   3
 
#define TST_TXTEST_RATE_SHIFT   3
 
#define SHM_BYT_CNT   0x2 /* IHR location */
 
#define MAX_BYT_CNT   0x600 /* Maximum frame len */
 

Enumerations

enum  _ePsmScratchPadRegDefinitions {
  S_RSV0 = 0, S_RSV1, S_RSV2, S_DOT11_CWMIN,
  S_DOT11_CWMAX, S_DOT11_CWCUR, S_DOT11_SRC_LMT, S_DOT11_LRC_LMT,
  S_DOT11_DTIMCOUNT, S_SEQ_NUM, S_SEQ_NUM_FRAG, S_FRMRETX_CNT,
  S_SSRC, S_SLRC, S_EXP_RSP, S_OLD_BREM,
  S_OLD_CWWIN, S_TXECTL, S_CTXTST, S_RXTST,
  S_STREG, S_TXPWR_SUM, S_TXPWR_ITER, S_RX_FRMTYPE,
  S_THIS_AGG, S_KEYINDX, S_RXFRMLEN, S_RXTSFTMRVAL_WD3,
  S_RXTSFTMRVAL_WD2, S_RXTSFTMRVAL_WD1, S_RXTSFTMRVAL_WD0, S_RXSSN,
  S_RXQOSFLD, S_TMP0, S_TMP1, S_TMP2,
  S_TMP3, S_TMP4, S_TMP5, S_PRQPENALTY_CTR,
  S_ANTCNT, S_SYMBOL, S_RXTP, S_STREG2,
  S_STREG3, S_STREG4, S_STREG5, S_ADJPWR_IDX,
  S_CUR_PTR, S_REVID4, S_INDX, S_ADDR0,
  S_ADDR1, S_ADDR2, S_ADDR3, S_ADDR4,
  S_ADDR5, S_TMP6, S_KEYINDX_BU, S_MFGTEST_TMP0,
  S_RXESN, S_STREG6
}
 

Variables

struct ofdm_phy_hdr __packed
 

Macro Definition Documentation

#define ABI_MAS_ADDR_BMP_IDX_MASK   0x0f00

Definition at line 896 of file d11.h.

#define ABI_MAS_ADDR_BMP_IDX_SHIFT   8

Definition at line 897 of file d11.h.

#define ABI_MAS_FBR_ANT_PTN_MASK   0x00f0

Definition at line 898 of file d11.h.

#define ABI_MAS_FBR_ANT_PTN_SHIFT   4

Definition at line 899 of file d11.h.

#define ABI_MAS_MRT_ANT_PTN_MASK   0x000f

Definition at line 900 of file d11.h.

#define ADDR_BMP_AP   (1 << 3) /* Infra-BSS Access Point */

Definition at line 999 of file d11.h.

#define ADDR_BMP_BSS_IDX_MASK   (3 << 8) /* BSS control block index */

Definition at line 1004 of file d11.h.

#define ADDR_BMP_BSS_IDX_SHIFT   8

Definition at line 1005 of file d11.h.

#define ADDR_BMP_BSSID   (1 << 2) /* BSSID */

Definition at line 998 of file d11.h.

#define ADDR_BMP_RA   (1 << 0) /* Receiver Address (RA) */

Definition at line 996 of file d11.h.

#define ADDR_BMP_RESERVED1   (1 << 5)

Definition at line 1001 of file d11.h.

#define ADDR_BMP_RESERVED2   (1 << 6)

Definition at line 1002 of file d11.h.

#define ADDR_BMP_RESERVED3   (1 << 7)

Definition at line 1003 of file d11.h.

#define ADDR_BMP_STA   (1 << 4) /* Infra-BSS Station */

Definition at line 1000 of file d11.h.

#define ADDR_BMP_TA   (1 << 1) /* Transmitter Address (TA) */

Definition at line 997 of file d11.h.

#define AES_MODE_CCM   1

Definition at line 1049 of file d11.h.

#define AES_MODE_NONE   0

Definition at line 1048 of file d11.h.

#define AMPDU_FBR_NULL_DELIM   5 /* Location of Null delimiter count for AMPDU */

Definition at line 842 of file d11.h.

#define ANA_11N_013   5

Definition at line 667 of file d11.h.

#define ANTSEL_CLKDIV_4MHZ   6

Definition at line 1297 of file d11.h.

#define BB_DARWIN   0x1000

Definition at line 1858 of file d11.h.

#define BBCFG_RESETCCA   0x4000

Definition at line 1859 of file d11.h.

#define BBCFG_RESETRX   0x8000

Definition at line 1860 of file d11.h.

#define BPHY_ADCBIAS   0x02

Definition at line 1762 of file d11.h.

#define BPHY_ANA11G_FILT_CTRL   0x62

Definition at line 1839 of file d11.h.

#define BPHY_ANACORE   0x03

Definition at line 1763 of file d11.h.

#define BPHY_ANGLE_SCALE   0x4d

Definition at line 1822 of file d11.h.

#define BPHY_BB_CONFIG   0x01

Definition at line 1761 of file d11.h.

#define BPHY_BYPASS   0x51

Definition at line 1826 of file d11.h.

#define BPHY_CCK_COEFF1   0x4a

Definition at line 1819 of file d11.h.

#define BPHY_CCK_COEFF2   0x4b

Definition at line 1820 of file d11.h.

#define BPHY_CCK_DELAY_LONG   0x52

Definition at line 1827 of file d11.h.

#define BPHY_CCK_DELAY_SHORT   0x53

Definition at line 1828 of file d11.h.

#define BPHY_CCK_LMS_STEP   0x50

Definition at line 1825 of file d11.h.

#define BPHY_COEFFS   0x18

Definition at line 1774 of file d11.h.

#define BPHY_CRS_DROP_TO   0x45

Definition at line 1815 of file d11.h.

#define BPHY_DAC_CONTROL   0x60

Definition at line 1838 of file d11.h.

#define BPHY_DDFS_ENABLE   0x58

Definition at line 1830 of file d11.h.

#define BPHY_DEBUG   0x43

Definition at line 1813 of file d11.h.

#define BPHY_DIVERSITY_CTL   0x32

Definition at line 1797 of file d11.h.

#define BPHY_DSSS_COEFF1   0x48

Definition at line 1817 of file d11.h.

#define BPHY_DSSS_COEFF2   0x49

Definition at line 1818 of file d11.h.

#define BPHY_FINE_DIGIGAIN_CTRL   0x67

Definition at line 1843 of file d11.h.

#define BPHY_FREQ_CONTROL   0x5a

Definition at line 1832 of file d11.h.

#define BPHY_FREQ_OFFSET   0x31

Definition at line 1796 of file d11.h.

#define BPHY_GAIN   0x25

Definition at line 1784 of file d11.h.

#define BPHY_HDR_TYPE   0x40

Definition at line 1810 of file d11.h.

#define BPHY_IQ_TRESH_H   0x22

Definition at line 1781 of file d11.h.

#define BPHY_IQ_TRESH_HH   0x21

Definition at line 1780 of file d11.h.

#define BPHY_IQ_TRESH_L   0x23

Definition at line 1782 of file d11.h.

#define BPHY_IQ_TRESH_LL   0x24

Definition at line 1783 of file d11.h.

#define BPHY_JSSI   0x27

Definition at line 1786 of file d11.h.

#define BPHY_LMS_CFF_READ   0x3a

Definition at line 1805 of file d11.h.

#define BPHY_LMS_COEFF_I   0x3b

Definition at line 1806 of file d11.h.

#define BPHY_LMS_COEFF_Q   0x3c

Definition at line 1807 of file d11.h.

#define BPHY_LNA_GAIN_RANGE   0x26

Definition at line 1785 of file d11.h.

#define BPHY_LNA_GAIN_RANGE_10   0x5b

Definition at line 1833 of file d11.h.

#define BPHY_LNA_GAIN_RANGE_32   0x5c

Definition at line 1834 of file d11.h.

#define BPHY_LO_IQMAG_ACC   0x2d

Definition at line 1792 of file d11.h.

#define BPHY_LO_LEAKAGE   0x2b

Definition at line 1790 of file d11.h.

#define BPHY_LO_RSSI_ACC   0x2c

Definition at line 1791 of file d11.h.

#define BPHY_LOCOMP_LUT   0x3a0

Definition at line 1850 of file d11.h.

#define BPHY_LOCOMP_LUT_END   0x3bf

Definition at line 1851 of file d11.h.

#define BPHY_OPTIONAL_MODES   0x5d

Definition at line 1835 of file d11.h.

#define BPHY_OPTIONAL_MODES2   0x4f

Definition at line 1824 of file d11.h.

#define BPHY_PA_TX_TIME_UP   0x12

Definition at line 1768 of file d11.h.

#define BPHY_PA_TX_TO   0x10

Definition at line 1766 of file d11.h.

#define BPHY_PEAK_CNT_THRESH   0x30

Definition at line 1795 of file d11.h.

#define BPHY_PEAK_ENERGY_HI   0x34

Definition at line 1799 of file d11.h.

#define BPHY_PEAK_ENERGY_LO   0x33

Definition at line 1798 of file d11.h.

#define BPHY_PHASE_SCALE   0x59

Definition at line 1831 of file d11.h.

#define BPHY_PHYCRSTH   0x06

Definition at line 1764 of file d11.h.

#define BPHY_PLL_OUT   0x19

Definition at line 1775 of file d11.h.

#define BPHY_PPROC_CHAN_DELAY   0x54

Definition at line 1829 of file d11.h.

#define BPHY_REFRESH_CTRL   0x64

Definition at line 1840 of file d11.h.

#define BPHY_REFRESH_MAIN   0x1a

Definition at line 1776 of file d11.h.

#define BPHY_REFRESH_TO0   0x1b

Definition at line 1777 of file d11.h.

#define BPHY_REFRESH_TO1   0x1c

Definition at line 1778 of file d11.h.

#define BPHY_REG_OFT_BASE   0x0

Definition at line 1759 of file d11.h.

#define BPHY_RF_OVERRIDE   0x15

Definition at line 1771 of file d11.h.

#define BPHY_RF_OVERRIDE2   0x65

Definition at line 1841 of file d11.h.

#define BPHY_RF_TR_LOOKUP1   0x16

Definition at line 1772 of file d11.h.

#define BPHY_RF_TR_LOOKUP2   0x17

Definition at line 1773 of file d11.h.

#define BPHY_RFDC_CANCEL_CTL   0x3e

Definition at line 1809 of file d11.h.

#define BPHY_RSSI_LUT   0x88

Definition at line 1844 of file d11.h.

#define BPHY_RSSI_LUT_END   0xa7

Definition at line 1845 of file d11.h.

#define BPHY_RSSI_TRESH   0x20

Definition at line 1779 of file d11.h.

#define BPHY_RX_DELAY_COMP   0x44

Definition at line 1814 of file d11.h.

#define BPHY_RX_FLTR_TIME_UP   0x13

Definition at line 1769 of file d11.h.

#define BPHY_RX_STATUS2   0x5e

Definition at line 1836 of file d11.h.

#define BPHY_RX_STATUS3   0x5f

Definition at line 1837 of file d11.h.

#define BPHY_SFD_CTL   0x42

Definition at line 1812 of file d11.h.

#define BPHY_SFD_TO   0x41

Definition at line 1811 of file d11.h.

#define BPHY_SHORT_SFD_NZEROS   0x46

Definition at line 1816 of file d11.h.

#define BPHY_SIG_POW   0x3d

Definition at line 1808 of file d11.h.

#define BPHY_SPUR_CANCEL_CTRL   0x66

Definition at line 1842 of file d11.h.

#define BPHY_STEP   0x38

Definition at line 1803 of file d11.h.

#define BPHY_SYNC_CTL   0x35

Definition at line 1800 of file d11.h.

#define BPHY_SYNTH_DC_TO   0x11

Definition at line 1767 of file d11.h.

#define BPHY_TEST   0x0a

Definition at line 1765 of file d11.h.

#define BPHY_TR_CORR   0x4c

Definition at line 1821 of file d11.h.

#define BPHY_TR_LOSS_CTL   0x2a

Definition at line 1789 of file d11.h.

#define BPHY_TSSI   0x29

Definition at line 1788 of file d11.h.

#define BPHY_TSSI2PWR_LUT   0x380

Definition at line 1848 of file d11.h.

#define BPHY_TSSI2PWR_LUT_END   0x39f

Definition at line 1849 of file d11.h.

#define BPHY_TSSI_CTL   0x28

Definition at line 1787 of file d11.h.

#define BPHY_TSSI_LUT   0xa8

Definition at line 1846 of file d11.h.

#define BPHY_TSSI_LUT_END   0xc7

Definition at line 1847 of file d11.h.

#define BPHY_TX_DC_OFF1   0x2e

Definition at line 1793 of file d11.h.

#define BPHY_TX_DC_OFF2   0x2f

Definition at line 1794 of file d11.h.

#define BPHY_TX_EST_PWR   0x37

Definition at line 1802 of file d11.h.

#define BPHY_TX_POWER_OVERRIDE   0x14

Definition at line 1770 of file d11.h.

#define BPHY_TX_PWR_BASE_IDX   0x4e

Definition at line 1823 of file d11.h.

#define BPHY_TX_PWR_CTRL   0x36

Definition at line 1801 of file d11.h.

#define BPHY_TXGAIN_LUT   0x3c0

Definition at line 1852 of file d11.h.

#define BPHY_TXGAIN_LUT_END   0x3ff

Definition at line 1853 of file d11.h.

#define BPHY_WARMUP   0x39

Definition at line 1804 of file d11.h.

#define BRCMS_CLR_MIMO_PLCP_AMPDU (   plcp)    (plcp[3] &= ~MIMO_PLCP_AMPDU)

Definition at line 739 of file d11.h.

#define BRCMS_GET_CCK_PLCP_LEN (   plcp)    (plcp[4] + (plcp[5] << 8))

Definition at line 730 of file d11.h.

#define BRCMS_GET_MIMO_PLCP_LEN (   plcp)    (plcp[1] + (plcp[2] << 8))

Definition at line 731 of file d11.h.

#define BRCMS_IS_MIMO_PLCP_AMPDU (   plcp)    (plcp[3] & MIMO_PLCP_AMPDU)

Definition at line 740 of file d11.h.

#define BRCMS_SET_MIMO_PLCP_AMPDU (   plcp)    (plcp[3] |= MIMO_PLCP_AMPDU)

Definition at line 738 of file d11.h.

#define BRCMS_SET_MIMO_PLCP_LEN (   plcp,
  len 
)
Value:
do { \
plcp[1] = len & 0xff; \
plcp[2] = ((len >> 8) & 0xff); \
} while (0)

Definition at line 732 of file d11.h.

#define BT_B2S   (1 << 30) /* bist2 ram summary bit */

Definition at line 440 of file d11.h.

#define BT_DONE   (1U << 31) /* bist done */

Definition at line 439 of file d11.h.

#define C_CTX_PCTLWD_POS   (0x4 * 2)

Definition at line 1144 of file d11.h.

#define CCS_ERSRC_AVAIL_D11PLL   0x01000000 /* d11 core pll available */

Definition at line 624 of file d11.h.

#define CCS_ERSRC_AVAIL_HT   0x00020000 /* HT clock available */

Definition at line 629 of file d11.h.

#define CCS_ERSRC_AVAIL_PHYPLL   0x02000000 /* PHY pll available */

Definition at line 625 of file d11.h.

#define CCS_ERSRC_REQ_D11PLL   0x00000100 /* d11 core pll request */

Definition at line 622 of file d11.h.

#define CCS_ERSRC_REQ_HT   0x00000010 /* HT avail request */

Definition at line 628 of file d11.h.

#define CCS_ERSRC_REQ_PHYPLL   0x00000200 /* PHY pll request */

Definition at line 623 of file d11.h.

#define CFPREP_CBI_MASK   0xffffffc0

Definition at line 632 of file d11.h.

#define CFPREP_CBI_SHIFT   6

Definition at line 633 of file d11.h.

#define CFPREP_CFPP   0x00000001

Definition at line 634 of file d11.h.

#define D11_CURCHANNEL_40   0x0200;

Definition at line 1194 of file d11.h.

#define D11_CURCHANNEL_5G   0x0100;

Definition at line 1193 of file d11.h.

#define D11_CURCHANNEL_MAX   0x00FF;

Definition at line 1195 of file d11.h.

#define D11_MAX_KEY_SIZE   16

Definition at line 1134 of file d11.h.

#define D11_MAX_TX_FRMS   32 /* max frames allowed in tx fifo */

Definition at line 1189 of file d11.h.

#define D11_PHY_HDR_LEN   6

Definition at line 747 of file d11.h.

#define D11_TXH_LEN   112 /* bytes */

Definition at line 787 of file d11.h.

#define D11A_PHY_HDR_GLENGTH (   phdr)    (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)

Definition at line 678 of file d11.h.

#define D11A_PHY_HDR_GPARITY (   phdr)    (((phdr)->rlpt[3] >> 1) & 0x01)

Definition at line 679 of file d11.h.

#define D11A_PHY_HDR_GRATE (   phdr)    ((phdr)->rlpt[0] & 0x0f)

Definition at line 676 of file d11.h.

#define D11A_PHY_HDR_GRES (   phdr)    (((phdr)->rlpt[0] >> 4) & 0x01)

Definition at line 677 of file d11.h.

#define D11A_PHY_HDR_GTAIL (   phdr)    (((phdr)->rlpt[3] >> 2) & 0x3f)

Definition at line 680 of file d11.h.

#define D11A_PHY_HDR_LEN_L   3 /* low-rate part of PLCP header */

Definition at line 694 of file d11.h.

#define D11A_PHY_HDR_LEN_R   2 /* high-rate part of PLCP header */

Definition at line 695 of file d11.h.

#define D11A_PHY_HDR_SLENGTH (   phdr,
  length 
)
Value:
(*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
(((length) & 0x0fff) << 5))

Definition at line 688 of file d11.h.

#define D11A_PHY_HDR_SRATE (   phdr,
  rate 
)    ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))

Definition at line 683 of file d11.h.

#define D11A_PHY_HDR_SRES (   phdr)    ((phdr)->rlpt[0] &= 0xef)

Definition at line 686 of file d11.h.

#define D11A_PHY_HDR_STAIL (   phdr)    ((phdr)->rlpt[3] &= 0x03)

Definition at line 692 of file d11.h.

#define D11A_PHY_HDR_TIME   (4) /* low-rate part of PLCP header */

Definition at line 699 of file d11.h.

#define D11A_PHY_PRE_TIME   (16)

Definition at line 700 of file d11.h.

#define D11A_PHY_PREHDR_TIME   (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)

Definition at line 701 of file d11.h.

#define D11A_PHY_TX_DELAY   (2) /* 2.1 usec */

Definition at line 697 of file d11.h.

#define D11B_PHY_HDR_LEN   6

Definition at line 711 of file d11.h.

#define D11B_PHY_LHDR_TIME   (D11B_PHY_HDR_LEN << 3)

Definition at line 715 of file d11.h.

#define D11B_PHY_LPRE_TIME   (144)

Definition at line 716 of file d11.h.

#define D11B_PHY_LPREHDR_TIME   (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)

Definition at line 717 of file d11.h.

#define D11B_PHY_SHDR_TIME   (D11B_PHY_LHDR_TIME >> 1)

Definition at line 719 of file d11.h.

#define D11B_PHY_SPRE_TIME   (D11B_PHY_LPRE_TIME >> 1)

Definition at line 720 of file d11.h.

#define D11B_PHY_SPREHDR_TIME   (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)

Definition at line 721 of file d11.h.

#define D11B_PHY_TX_DELAY   (3) /* 3.4 usec */

Definition at line 713 of file d11.h.

#define D11B_PLCP_SIGNAL_LE   (1 << 7)

Definition at line 724 of file d11.h.

#define D11B_PLCP_SIGNAL_LOCKED   (1 << 2)

Definition at line 723 of file d11.h.

#define D11REGOFFS (   field)    offsetof(struct d11regs, field)

Definition at line 434 of file d11.h.

#define DBGST_ACTIVE   2

Definition at line 1579 of file d11.h.

#define DBGST_ASLEEP   4

Definition at line 1583 of file d11.h.

#define DBGST_INACTIVE   0

Definition at line 1575 of file d11.h.

#define DBGST_INIT   1

Definition at line 1577 of file d11.h.

#define DBGST_SUSPENDED   3

Definition at line 1581 of file d11.h.

#define FT_CCK   0

Definition at line 790 of file d11.h.

#define FT_HT   2

Definition at line 792 of file d11.h.

#define FT_N   3

Definition at line 793 of file d11.h.

#define FT_OFDM   1

Definition at line 791 of file d11.h.

#define HTPHY_MMPLCPLen (   rxs)
Value:
((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
(((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))

Definition at line 1502 of file d11.h.

#define HTPHY_RXPWR_ANT0 (   rxs)    ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)

Definition at line 1506 of file d11.h.

#define HTPHY_RXPWR_ANT1 (   rxs)    (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)

Definition at line 1509 of file d11.h.

#define HTPHY_RXPWR_ANT2 (   rxs)    ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)

Definition at line 1512 of file d11.h.

#define I_DE   (1 << 12) /* descriptor protocol error */

Definition at line 445 of file d11.h.

#define I_PC   (1 << 10) /* pci descriptor error */

Definition at line 443 of file d11.h.

#define I_PD   (1 << 11) /* pci data error */

Definition at line 444 of file d11.h.

#define I_RI   (1 << 16) /* receive interrupt */

Definition at line 449 of file d11.h.

#define I_RO   (1 << 14) /* receive fifo overflow */

Definition at line 447 of file d11.h.

#define I_RU   (1 << 13) /* receive descriptor underflow */

Definition at line 446 of file d11.h.

#define I_XI   (1 << 24) /* transmit interrupt */

Definition at line 450 of file d11.h.

#define I_XU   (1 << 15) /* transmit fifo underflow */

Definition at line 448 of file d11.h.

#define IFS_CTL1_EDCRS   (1 << 3)

Definition at line 891 of file d11.h.

#define IFS_CTL1_EDCRS_20L   (1 << 4)

Definition at line 892 of file d11.h.

#define IFS_CTL1_EDCRS_40   (1 << 5)

Definition at line 893 of file d11.h.

#define IFS_USEEDCF   (1 << 2)

Definition at line 888 of file d11.h.

#define INVALIDFID   0xffff

Definition at line 1199 of file d11.h.

#define IRL_FC_MASK   0xff000000 /* frame count */

Definition at line 454 of file d11.h.

#define IRL_FC_SHIFT   24 /* frame count */

Definition at line 455 of file d11.h.

#define IRL_TO_MASK   0x00ffffff /* timeout */

Definition at line 453 of file d11.h.

#define M_20IN40_IQ   (0x380 * 2)

Definition at line 1245 of file d11.h.

#define M_A_TSSI_0   (0x034 * 2)

Definition at line 1164 of file d11.h.

#define M_A_TSSI_1   (0x035 * 2)

Definition at line 1165 of file d11.h.

#define M_AC_TXLMT_ADDR (   _ac)    (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))

Definition at line 42 of file d11.h.

#define M_AC_TXLMT_BASE_ADDR   (0x180 * 2)

Definition at line 41 of file d11.h.

#define M_ADDR_BMP_BLK   (0x37e * 2)

Definition at line 993 of file d11.h.

#define M_ADDR_BMP_BLK_SZ   12

Definition at line 994 of file d11.h.

#define M_AGING_THRSH   (0x3e * 2) /* max time waiting for medium before tx */

Definition at line 1558 of file d11.h.

#define M_ALT_TXPWR_IDX   (M_PSM_SOFT_REGS + (0x3b * 2))

Definition at line 1565 of file d11.h.

#define M_ANTSEL_CLKDIV   (0x61 * 2)

Definition at line 1256 of file d11.h.

#define M_B_TSSI_0   (0x02c * 2)

Definition at line 1150 of file d11.h.

#define M_B_TSSI_1   (0x02d * 2)

Definition at line 1151 of file d11.h.

#define M_BCMC_FID   (0x54 * 2)

Definition at line 1198 of file d11.h.

#define M_BCN0_FRM_BYTESZ   (0x00c * 2) /* Bcn 0 template length */

Definition at line 1099 of file d11.h.

#define M_BCN1_FRM_BYTESZ   (0x00d * 2) /* Bcn 1 template length */

Definition at line 1100 of file d11.h.

#define M_BCN_LI   (0x05b * 2) /* beacon listen interval */

Definition at line 1106 of file d11.h.

#define M_BCN_PCTL1WD   (0x058 * 2)

Definition at line 1202 of file d11.h.

#define M_BCN_PCTLWD   (0x02a * 2)

Definition at line 1105 of file d11.h.

#define M_BCN_TXTSF_OFFSET   (0x00e * 2)

Definition at line 1101 of file d11.h.

#define M_BOM_REV_MAJOR   (M_PSM_SOFT_REGS + 0x0)

Definition at line 1553 of file d11.h.

#define M_BOM_REV_MINOR   (M_PSM_SOFT_REGS + 0x2)

Definition at line 1554 of file d11.h.

#define M_BSCALE_ANT0   (0x5e * 2)

Definition at line 1251 of file d11.h.

#define M_BSCALE_ANT1   (0x5f * 2)

Definition at line 1252 of file d11.h.

#define M_CTS_DURATION   (M_PSM_SOFT_REGS + (0x5c * 2))

Definition at line 1567 of file d11.h.

#define M_CTXPRS_BLK   (0xc0 * 2)

Definition at line 1143 of file d11.h.

#define M_CUR_2050_RADIOCODE   (0x47 * 2)

Definition at line 1182 of file d11.h.

#define M_CURCHANNEL   (0x50 * 2)

Definition at line 1192 of file d11.h.

#define M_CURR_IDX1   (0x384 * 2)

Definition at line 1248 of file d11.h.

#define M_CURR_IDX2   (0x387 * 2)

Definition at line 1249 of file d11.h.

#define M_DOT11_DTIMPERIOD   (0x009 * 2)

Definition at line 1095 of file d11.h.

#define M_DOT11_SLOT   (0x008 * 2)

Definition at line 1094 of file d11.h.

#define M_EDCF_QINFO   (0x120 * 2)

Definition at line 1091 of file d11.h.

#define M_EDCF_QLEN   (16 * 2)

Definition at line 1314 of file d11.h.

#define M_EDCF_STATUS_OFF   (0x007 * 2)

Definition at line 1089 of file d11.h.

#define M_FIFOSIZE0   (0x4c * 2)

Definition at line 1185 of file d11.h.

#define M_FIFOSIZE1   (0x4d * 2)

Definition at line 1186 of file d11.h.

#define M_FIFOSIZE2   (0x4e * 2)

Definition at line 1187 of file d11.h.

#define M_FIFOSIZE3   (0x4f * 2)

Definition at line 1188 of file d11.h.

#define M_G_TSSI_0   (0x038 * 2)

Definition at line 1174 of file d11.h.

#define M_G_TSSI_1   (0x039 * 2)

Definition at line 1175 of file d11.h.

#define M_HOST_FLAGS1   (0x02f * 2)

Definition at line 1154 of file d11.h.

#define M_HOST_FLAGS2   (0x030 * 2)

Definition at line 1155 of file d11.h.

#define M_HOST_FLAGS3   (0x031 * 2)

Definition at line 1156 of file d11.h.

#define M_HOST_FLAGS4   (0x03c * 2)

Definition at line 1157 of file d11.h.

#define M_HOST_FLAGS5   (0x06a * 2)

Definition at line 1158 of file d11.h.

#define M_HOST_FLAGS_SZ   16

Definition at line 1159 of file d11.h.

#define M_JSSI_0   (0x44 * 2)

Definition at line 1178 of file d11.h.

#define M_JSSI_1   (0x45 * 2)

Definition at line 1179 of file d11.h.

#define M_JSSI_AUX   (0x46 * 2)

Definition at line 1180 of file d11.h.

#define M_LCN_LAST_LOC   (63*2)

Definition at line 1228 of file d11.h.

#define M_LCN_LAST_RESET   (81*2)

Definition at line 1227 of file d11.h.

#define M_LCN_PWR_IDX_MAX   (0x67 * 2) /* highest index read by ucode */

Definition at line 1278 of file d11.h.

#define M_LCN_PWR_IDX_MIN   (0x66 * 2) /* lowest index read by ucode */

Definition at line 1279 of file d11.h.

#define M_LCN_RSSI_0   0x1332

Definition at line 1209 of file d11.h.

#define M_LCN_RSSI_1   0x1338

Definition at line 1210 of file d11.h.

#define M_LCN_RSSI_2   0x133e

Definition at line 1211 of file d11.h.

#define M_LCN_RSSI_3   0x1344

Definition at line 1212 of file d11.h.

#define M_LCN_SNR_A_0   0x1334

Definition at line 1215 of file d11.h.

#define M_LCN_SNR_A_1   0x133a

Definition at line 1218 of file d11.h.

#define M_LCN_SNR_A_2   0x1340

Definition at line 1221 of file d11.h.

#define M_LCN_SNR_A_3   0x1346

Definition at line 1224 of file d11.h.

#define M_LCN_SNR_B_0   0x1336

Definition at line 1216 of file d11.h.

#define M_LCN_SNR_B_1   0x133c

Definition at line 1219 of file d11.h.

#define M_LCN_SNR_B_2   0x1342

Definition at line 1222 of file d11.h.

#define M_LCN_SNR_B_3   0x1348

Definition at line 1225 of file d11.h.

#define M_LCNPHY_DSC_TIME   (0x98d*2)

Definition at line 1230 of file d11.h.

#define M_LCNPHY_RESET_CNT   (0x98c*2)

Definition at line 1232 of file d11.h.

#define M_LCNPHY_RESET_CNT_DSC   (0x98b*2)

Definition at line 1231 of file d11.h.

#define M_LCNPHY_RESET_STATUS   (4902)

Definition at line 1229 of file d11.h.

#define M_LFRMTXCNTFBRTHSD   (0x023 * 2)

Definition at line 1104 of file d11.h.

#define M_LP_RCCAL_OVR   (M_PSM_SOFT_REGS + (0x6b * 2))

Definition at line 1568 of file d11.h.

#define M_MACHW_CAP_H   (0x061 * 2)

Definition at line 1086 of file d11.h.

#define M_MACHW_CAP_L   (0x060 * 2)

Definition at line 1085 of file d11.h.

#define M_MACHW_VER   (0x00b * 2)

Definition at line 1082 of file d11.h.

#define M_MAX_ANTCNT   (0x02e * 2) /* antenna swap threshold */

Definition at line 1136 of file d11.h.

#define M_MAXRXFRM_LEN   (0x010 * 2)

Definition at line 1109 of file d11.h.

#define M_MBURST_SIZE   (0x40 * 2) /* max frames in a frameburst */

Definition at line 1559 of file d11.h.

#define M_MBURST_TXOP   (0x41 * 2) /* max frameburst TXOP in unit of us */

Definition at line 1560 of file d11.h.

#define M_MIMO_ANTSEL_RXDFLT   (0x63 * 2)

Definition at line 1255 of file d11.h.

#define M_MIMO_ANTSEL_TXDFLT   (0x64 * 2)

Definition at line 1257 of file d11.h.

#define M_MIMO_MAXSYM   (0x5d * 2)

Definition at line 1259 of file d11.h.

#define M_NOISE_IF_COUNT   (0x034 * 2)

Definition at line 1168 of file d11.h.

#define M_NOISE_IF_TIMEOUT   (0x035 * 2)

Definition at line 1169 of file d11.h.

#define M_NOSLPZNATDTIM   (0x026 * 2)

Definition at line 1096 of file d11.h.

#define M_OFDM_OFFSET   (0x027 * 2)

Definition at line 1147 of file d11.h.

#define M_PHY_NOISE   (0x037 * 2)

Definition at line 1366 of file d11.h.

#define M_PHY_TX_FLT_PTR   (M_PSM_SOFT_REGS + (0x3d * 2))

Definition at line 1566 of file d11.h.

#define M_PHYTYPE   (0x029 * 2)

Definition at line 1127 of file d11.h.

#define M_PHYVER   (0x028 * 2)

Definition at line 1126 of file d11.h.

#define M_PKTENG_CTRL   (0x6c * 2)

Definition at line 1269 of file d11.h.

#define M_PKTENG_FRMCNT_HI   (0x6f * 2)

Definition at line 1275 of file d11.h.

#define M_PKTENG_FRMCNT_LO   (0x6e * 2)

Definition at line 1273 of file d11.h.

#define M_PKTENG_FRMCNT_VLD   0x0100

Definition at line 1289 of file d11.h.

#define M_PKTENG_IFS   (0x6d * 2)

Definition at line 1271 of file d11.h.

#define M_PKTENG_MODE_MASK   0x0003

Definition at line 1287 of file d11.h.

#define M_PKTENG_MODE_RX   0x0002

Definition at line 1285 of file d11.h.

#define M_PKTENG_MODE_RX_WITH_ACK   0x0402

Definition at line 1286 of file d11.h.

#define M_PKTENG_MODE_TX   0x0001

Definition at line 1282 of file d11.h.

#define M_PKTENG_MODE_TX_CTS   0x0008

Definition at line 1284 of file d11.h.

#define M_PKTENG_MODE_TX_RIFS   0x0004

Definition at line 1283 of file d11.h.

#define M_PRB_RESP_FRM_LEN   (0x025 * 2)

Definition at line 1140 of file d11.h.

#define M_PRETBTT   (0x4b * 2)

Definition at line 1562 of file d11.h.

#define M_PRS_MAXTIME   (0x03a * 2)

Definition at line 1141 of file d11.h.

#define M_PSM_SOFT_REGS   0x0

Definition at line 1552 of file d11.h.

#define M_PWRIND_BLKS   (0x184 * 2)

Definition at line 1543 of file d11.h.

#define M_PWRIND_MAP (   core)    (M_PWRIND_BLKS + ((core)<<1))

Definition at line 1549 of file d11.h.

#define M_PWRIND_MAP0   (M_PWRIND_BLKS + 0x0)

Definition at line 1544 of file d11.h.

#define M_PWRIND_MAP1   (M_PWRIND_BLKS + 0x2)

Definition at line 1545 of file d11.h.

#define M_PWRIND_MAP2   (M_PWRIND_BLKS + 0x4)

Definition at line 1546 of file d11.h.

#define M_PWRIND_MAP3   (M_PWRIND_BLKS + 0x6)

Definition at line 1547 of file d11.h.

#define M_RADAR_REG   (0x033 * 2)

Definition at line 1161 of file d11.h.

#define M_RADIO_PWR   (0x32 * 2)

Definition at line 1363 of file d11.h.

#define M_RF_RX_SP_REG1   (0x036 * 2)

Definition at line 1171 of file d11.h.

#define M_RSP_PCTLWD   (0x011 * 2)

Definition at line 1112 of file d11.h.

#define M_RT_BBRSMAP_A   (0xf0 * 2)

Definition at line 1236 of file d11.h.

#define M_RT_BBRSMAP_B   (0x110 * 2)

Definition at line 1238 of file d11.h.

#define M_RT_DIRMAP_A   (0xe0 * 2)

Definition at line 1235 of file d11.h.

#define M_RT_DIRMAP_B   (0x100 * 2)

Definition at line 1237 of file d11.h.

#define M_RT_OFDM_PCTL1_POS   18

Definition at line 1243 of file d11.h.

#define M_RT_PRS_DUR_POS   16

Definition at line 1242 of file d11.h.

#define M_RT_PRS_PLCP_POS   10

Definition at line 1241 of file d11.h.

#define M_RX_PAD_DATA_OFFSET   (0x01a * 2)

Definition at line 1121 of file d11.h.

#define M_RXSTATS_BLK_PTR   (M_PSM_SOFT_REGS + (0x65 * 2))

Definition at line 1571 of file d11.h.

#define M_SEC_DEFIVLOC   (0x01e * 2)

Definition at line 1124 of file d11.h.

#define M_SEC_VALNUMSOFTMCHTA   (0x01f * 2)

Definition at line 1125 of file d11.h.

#define M_SECKINDXALGO_BLK   (0x2ea * 2)

Definition at line 1130 of file d11.h.

#define M_SECKINDXALGO_BLK_SZ   54

Definition at line 1131 of file d11.h.

#define M_SECPSMRXTAMCH_BLK   (0x2fa * 2)

Definition at line 1132 of file d11.h.

#define M_SECRXKEYS_PTR   (0x02b * 2)

Definition at line 1128 of file d11.h.

#define M_SFRMTXCNTFBRTHSD   (0x022 * 2)

Definition at line 1103 of file d11.h.

#define M_SMPL_COL_BMP   (0x37d * 2)

Definition at line 1293 of file d11.h.

#define M_SMPL_COL_CTL   (0x3b2 * 2)

Definition at line 1295 of file d11.h.

#define M_SSID   (0xb0 * 2)

Definition at line 1142 of file d11.h.

#define M_SSIDLEN   (0x024 * 2)

Definition at line 1139 of file d11.h.

#define M_SYNTHPU_DLY   (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */

Definition at line 1561 of file d11.h.

#define M_TIMBPOS_INBEACON   (0x00f * 2)

Definition at line 1102 of file d11.h.

#define M_TKIP_TSC_TTAK   (0x18c * 2)

Definition at line 1133 of file d11.h.

#define M_TKMICKEYS_PTR   (0x059 * 2)

Definition at line 1129 of file d11.h.

#define M_TX_IDLE_BUSY_RATIO_X_16_CCK   (0x52 * 2)

Definition at line 1205 of file d11.h.

#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM   (0x5A * 2)

Definition at line 1206 of file d11.h.

#define M_TXF_CUR_INDEX   (0x018 * 2)

Definition at line 1090 of file d11.h.

#define M_TXPWR_CUR   (0x019 * 2)

Definition at line 1118 of file d11.h.

#define M_TXPWR_MAX   (0x014 * 2)

Definition at line 1117 of file d11.h.

#define M_TXPWR_N   (0x012 * 2)

Definition at line 1115 of file d11.h.

#define M_TXPWR_TARGET   (0x013 * 2)

Definition at line 1116 of file d11.h.

#define M_UCODE_DBGST   (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */

Definition at line 1555 of file d11.h.

#define M_UCODE_MACSTAT   (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */

Definition at line 1556 of file d11.h.

#define M_WATCHDOG_8TU   (0x1e * 2)

Definition at line 1263 of file d11.h.

#define MAC_PHY_CLOCK_EN   2

Definition at line 979 of file d11.h.

#define MAC_PHY_FORCE_CLK   4

Definition at line 980 of file d11.h.

#define MAC_PHY_RESET   1

Definition at line 978 of file d11.h.

#define MAX_BYT_CNT   0x600 /* Maximum frame len */

Definition at line 1882 of file d11.h.

#define MBSS16_TEMPLMEM_MINBLKS   65 /* one unit corresponds to 256 bytes */

Definition at line 644 of file d11.h.

#define MCAP_TKIPMIC   0x80000000 /* TKIP MIC hardware present */

Definition at line 549 of file d11.h.

#define MCMD_BCN0VLD   (1 << 0)

Definition at line 482 of file d11.h.

#define MCMD_BCN1VLD   (1 << 1)

Definition at line 483 of file d11.h.

#define MCMD_BG_NOISE   (1 << 4)

Definition at line 486 of file d11.h.

#define MCMD_CCA   (1 << 3)

Definition at line 485 of file d11.h.

#define MCMD_DIRFRMQVAL   (1 << 2)

Definition at line 484 of file d11.h.

#define MCMD_SAMPLECOLL   MCMD_SKIP_SHMINIT /* reuse for sample collect */

Definition at line 488 of file d11.h.

#define MCMD_SKIP_SHMINIT   (1 << 5) /* only used for simulation */

Definition at line 487 of file d11.h.

#define MCTL_AP   (1 << 18)

Definition at line 468 of file d11.h.

#define MCTL_BCNS_PROMISC   (1 << 20)

Definition at line 466 of file d11.h.

#define MCTL_BIGEND   (1 << 16)

Definition at line 470 of file d11.h.

#define MCTL_DISCARD_PMQ   (1 << 30)

Definition at line 459 of file d11.h.

#define MCTL_EN_MAC   (1 << 0)

Definition at line 479 of file d11.h.

#define MCTL_EN_PSMDBG   (1 << 13)

Definition at line 473 of file d11.h.

#define MCTL_GMODE   (1U << 31)

Definition at line 458 of file d11.h.

#define MCTL_GPOUT_SEL_MASK   (3 << 14)

Definition at line 471 of file d11.h.

#define MCTL_GPOUT_SEL_SHIFT   14

Definition at line 472 of file d11.h.

#define MCTL_HPS   (1 << 25)

Definition at line 461 of file d11.h.

#define MCTL_IHR_EN   (1 << 10)

Definition at line 474 of file d11.h.

#define MCTL_INFRA   (1 << 17)

Definition at line 469 of file d11.h.

#define MCTL_KEEPBADFCS   (1 << 23)

Definition at line 463 of file d11.h.

#define MCTL_KEEPCONTROL   (1 << 22)

Definition at line 464 of file d11.h.

#define MCTL_LOCK_RADIO   (1 << 19)

Definition at line 467 of file d11.h.

#define MCTL_PHYLOCK   (1 << 21)

Definition at line 465 of file d11.h.

#define MCTL_PROMISC   (1 << 24)

Definition at line 462 of file d11.h.

#define MCTL_PSM_JMP_0   (1 << 2)

Definition at line 477 of file d11.h.

#define MCTL_PSM_RUN   (1 << 1)

Definition at line 478 of file d11.h.

#define MCTL_SHM_EN   (1 << 8)

Definition at line 476 of file d11.h.

#define MCTL_SHM_UPPER   (1 << 9)

Definition at line 475 of file d11.h.

#define MCTL_WAKE   (1 << 26)

Definition at line 460 of file d11.h.

#define MHF1   0 /* Hostflag 1 index */

Definition at line 1320 of file d11.h.

#define MHF1_ANTDIV   0x0001

Definition at line 1328 of file d11.h.

#define MHF1_EDCF   0x0100

Definition at line 1330 of file d11.h.

#define MHF1_FORCEFASTCLK   0x0400

Definition at line 1333 of file d11.h.

#define MHF1_IQSWAP_WAR   0x0200

Definition at line 1331 of file d11.h.

#define MHF2   1 /* Hostflag 2 index */

Definition at line 1321 of file d11.h.

#define MHF2_HWPWRCTL   0x0080

Definition at line 1340 of file d11.h.

#define MHF2_NPHY40MHZ_WAR   0x0800

Definition at line 1341 of file d11.h.

#define MHF2_TXBCMC_NOW   0x0040

Definition at line 1338 of file d11.h.

#define MHF3   2 /* Hostflag 3 index */

Definition at line 1322 of file d11.h.

#define MHF3_ANTSEL_EN   0x0001

Definition at line 1345 of file d11.h.

#define MHF3_ANTSEL_MODE   0x0002

Definition at line 1347 of file d11.h.

#define MHF3_NPHY_MLADV_WAR   0x0010

Definition at line 1350 of file d11.h.

#define MHF3_RESERVED1   0x0004

Definition at line 1348 of file d11.h.

#define MHF3_RESERVED2   0x0008

Definition at line 1349 of file d11.h.

#define MHF4   3 /* Hostflag 4 index */

Definition at line 1323 of file d11.h.

#define MHF4_BPHY_TXCORE0   0x0080

Definition at line 1354 of file d11.h.

#define MHF4_EXTPA_ENABLE   0x4000

Definition at line 1356 of file d11.h.

#define MHF5   4 /* Hostflag 5 index */

Definition at line 1324 of file d11.h.

#define MHF5_4313_GPIOCTRL   0x0001

Definition at line 1359 of file d11.h.

#define MHF5_RESERVED1   0x0002

Definition at line 1360 of file d11.h.

#define MHF5_RESERVED2   0x0004

Definition at line 1361 of file d11.h.

#define MHFMAX   5 /* Number of valid hostflag half-word (u16) */

Definition at line 1319 of file d11.h.

#define MI_ATIMWINEND   (1 << 5)

Definition at line 502 of file d11.h.

#define MI_BCNCANCLD   (1 << 4)

Definition at line 500 of file d11.h.

#define MI_BCNSUCCESS   (1 << 3)

Definition at line 498 of file d11.h.

#define MI_BCNTPL   (1 << 1)

Definition at line 494 of file d11.h.

#define MI_BG_NOISE   (1 << 18)

Definition at line 528 of file d11.h.

#define MI_CCA   (1 << 17)

Definition at line 526 of file d11.h.

#define MI_DMAINT   (1 << 15)

Definition at line 522 of file d11.h.

#define MI_DTIM_TBTT   (1 << 19)

Definition at line 530 of file d11.h.

#define MI_GP0   (1 << 13)

Definition at line 518 of file d11.h.

#define MI_GP1   (1 << 14)

Definition at line 520 of file d11.h.

#define MI_MACSSPNDD   (1 << 0)

Definition at line 492 of file d11.h.

#define MI_MACTXERR   (1 << 9)

Definition at line 510 of file d11.h.

#define MI_NSPECGEN_0   (1 << 7)

Definition at line 506 of file d11.h.

#define MI_NSPECGEN_1   (1 << 8)

Definition at line 508 of file d11.h.

#define MI_NSPECGEN_3   (1 << 10)

Definition at line 512 of file d11.h.

#define MI_PHYCHANGED   (1 << 30)

Definition at line 543 of file d11.h.

#define MI_PHYTXERR   (1 << 11)

Definition at line 514 of file d11.h.

#define MI_PME   (1 << 12)

Definition at line 516 of file d11.h.

#define MI_PMQ   (1 << 6)

Definition at line 504 of file d11.h.

#define MI_PRQ   (1 << 20)

Definition at line 532 of file d11.h.

#define MI_PWRUP   (1 << 21)

Definition at line 534 of file d11.h.

#define MI_RESERVED1   (1 << 25)

Definition at line 537 of file d11.h.

#define MI_RESERVED2   (1 << 23)

Definition at line 536 of file d11.h.

#define MI_RESERVED3   (1 << 22)

Definition at line 535 of file d11.h.

#define MI_RFDISABLE   (1 << 28)

Definition at line 539 of file d11.h.

#define MI_TBTT   (1 << 2)

Definition at line 496 of file d11.h.

#define MI_TFS   (1 << 29)

Definition at line 541 of file d11.h.

#define MI_TO   (1U << 31)

Definition at line 545 of file d11.h.

#define MI_TXSTOP   (1 << 16)

Definition at line 524 of file d11.h.

#define MIMO_ANTSEL_BUSY   0x4000 /* bit 14 (busy) */

Definition at line 1298 of file d11.h.

#define MIMO_ANTSEL_OVERRIDE   0x8000 /* flag */

Definition at line 1301 of file d11.h.

#define MIMO_ANTSEL_SEL   0x8000 /* bit 15 write the value */

Definition at line 1299 of file d11.h.

#define MIMO_ANTSEL_WAIT   50 /* 50us wait */

Definition at line 1300 of file d11.h.

#define MIMO_MAXSYM_DEF   0x8000 /* 32k */

Definition at line 1260 of file d11.h.

#define MIMO_MAXSYM_MAX   0xffff /* 64k */

Definition at line 1261 of file d11.h.

#define MIMO_PLCP_40MHZ   0x80 /* 40 Hz frame */

Definition at line 727 of file d11.h.

#define MIMO_PLCP_AMPDU   0x08 /* ampdu */

Definition at line 728 of file d11.h.

#define MIMO_PLCP_MCS_MASK   0x7f /* mcs index */

Definition at line 726 of file d11.h.

#define OBJADDR_AUTO_INC   0x03000000

Definition at line 603 of file d11.h.

#define OBJADDR_IHR_SEL   0x00030000

Definition at line 598 of file d11.h.

#define OBJADDR_RCMTA_SEL   0x00040000

Definition at line 599 of file d11.h.

#define OBJADDR_RINC   0x02000000

Definition at line 602 of file d11.h.

#define OBJADDR_SCR_SEL   0x00020000

Definition at line 597 of file d11.h.

#define OBJADDR_SEL_MASK   0x000F0000

Definition at line 594 of file d11.h.

#define OBJADDR_SHM_SEL   0x00010000

Definition at line 596 of file d11.h.

#define OBJADDR_SRCHM_SEL   0x00060000

Definition at line 600 of file d11.h.

#define OBJADDR_UCM_SEL   0x00000000

Definition at line 595 of file d11.h.

#define OBJADDR_WINC   0x01000000

Definition at line 601 of file d11.h.

#define PDBG_CRS   (1 << 0)

Definition at line 575 of file d11.h.

#define PDBG_RFD   (1 << 16)

Definition at line 591 of file d11.h.

#define PDBG_RXF   (1 << 4)

Definition at line 583 of file d11.h.

#define PDBG_RXFRG   (1 << 6)

Definition at line 587 of file d11.h.

#define PDBG_RXS   (1 << 5)

Definition at line 585 of file d11.h.

#define PDBG_RXV   (1 << 7)

Definition at line 589 of file d11.h.

#define PDBG_TXA   (1 << 1)

Definition at line 577 of file d11.h.

#define PDBG_TXE   (1 << 3)

Definition at line 581 of file d11.h.

#define PDBG_TXF   (1 << 2)

Definition at line 579 of file d11.h.

#define PHY_AWS_ANTDIV   0x2000

Definition at line 885 of file d11.h.

#define PHY_BBC_ANT_MASK   0x0180

Definition at line 1856 of file d11.h.

#define PHY_BBC_ANT_SHIFT   7

Definition at line 1857 of file d11.h.

#define PHY_NOISE_MASK   0x00ff

Definition at line 1367 of file d11.h.

#define PHY_TXC1_BW_10MHZ   0

Definition at line 863 of file d11.h.

#define PHY_TXC1_BW_10MHZ_UP   1

Definition at line 864 of file d11.h.

#define PHY_TXC1_BW_20MHZ   2

Definition at line 865 of file d11.h.

#define PHY_TXC1_BW_20MHZ_UP   3

Definition at line 866 of file d11.h.

#define PHY_TXC1_BW_40MHZ   4

Definition at line 867 of file d11.h.

#define PHY_TXC1_BW_40MHZ_DUP   5

Definition at line 868 of file d11.h.

#define PHY_TXC1_BW_MASK   0x0007

Definition at line 862 of file d11.h.

#define PHY_TXC1_MODE_CDD   1

Definition at line 872 of file d11.h.

#define PHY_TXC1_MODE_MASK   0x0038

Definition at line 870 of file d11.h.

#define PHY_TXC1_MODE_SDM   3

Definition at line 874 of file d11.h.

#define PHY_TXC1_MODE_SHIFT   3

Definition at line 869 of file d11.h.

#define PHY_TXC1_MODE_SISO   0

Definition at line 871 of file d11.h.

#define PHY_TXC1_MODE_STBC   2

Definition at line 873 of file d11.h.

#define PHY_TXC_ANT_0   0x0040 /* virtual antenna 0 */

Definition at line 854 of file d11.h.

#define PHY_TXC_ANT_0_1   0x00C0 /* auto, last rx */

Definition at line 849 of file d11.h.

#define PHY_TXC_ANT_1   0x0080 /* virtual antenna 1 */

Definition at line 853 of file d11.h.

#define PHY_TXC_ANT_2   0x0100 /* virtual antenna 2 */

Definition at line 852 of file d11.h.

#define PHY_TXC_ANT_3   0x0200 /* virtual antenna 3 */

Definition at line 851 of file d11.h.

#define PHY_TXC_ANT_MASK   0x03C0 /* bit 6, 7, 8, 9 */

Definition at line 847 of file d11.h.

#define PHY_TXC_ANT_SHIFT   6

Definition at line 848 of file d11.h.

#define PHY_TXC_HTANT_MASK   0x3fC0 /* bits 6-13 */

Definition at line 877 of file d11.h.

#define PHY_TXC_LCNPHY_ANT_LAST   0x0000

Definition at line 850 of file d11.h.

#define PHY_TXC_OLD_ANT_0   0x0000

Definition at line 857 of file d11.h.

#define PHY_TXC_OLD_ANT_1   0x0100

Definition at line 858 of file d11.h.

#define PHY_TXC_OLD_ANT_LAST   0x0300

Definition at line 859 of file d11.h.

#define PHY_TXC_PWR_MASK   0xFC00

Definition at line 845 of file d11.h.

#define PHY_TXC_PWR_SHIFT   10

Definition at line 846 of file d11.h.

#define PHY_TXC_SHORT_HDR   0x0010

Definition at line 855 of file d11.h.

#define PHY_TYPE (   v)    ((v & PV_PT_MASK) >> PV_PT_SHIFT)

Definition at line 657 of file d11.h.

#define PHY_TYPE_LCN   8 /* LCN-Phy value */

Definition at line 662 of file d11.h.

#define PHY_TYPE_LCNXN   9 /* LCNXN-Phy value */

Definition at line 663 of file d11.h.

#define PHY_TYPE_N   4 /* N-Phy value */

Definition at line 660 of file d11.h.

#define PHY_TYPE_NULL   0xf /* Invalid Phy value */

Definition at line 664 of file d11.h.

#define PHY_TYPE_SSN   6 /* SSLPN-Phy value */

Definition at line 661 of file d11.h.

#define PIHR_BASE   0x0400 /* byte address of packed IHR region */

Definition at line 436 of file d11.h.

#define PMQH_ATIMFAIL   0x00080000

Definition at line 563 of file d11.h.

#define PMQH_BSSCFG   0x00100000

Definition at line 555 of file d11.h.

#define PMQH_DASAT   0x00040000

Definition at line 561 of file d11.h.

#define PMQH_DATA_MASK   0xffff0000

Definition at line 553 of file d11.h.

#define PMQH_DEL_ENTRY   0x00000001

Definition at line 565 of file d11.h.

#define PMQH_DEL_MULT   0x00000002

Definition at line 567 of file d11.h.

#define PMQH_NOT_EMPTY   0x00000008

Definition at line 571 of file d11.h.

#define PMQH_OFLO   0x00000004

Definition at line 569 of file d11.h.

#define PMQH_PMOFF   0x00010000

Definition at line 557 of file d11.h.

#define PMQH_PMON   0x00020000

Definition at line 559 of file d11.h.

#define PRXS0_ANTSEL_0   0x0 /* antenna 0 is used */

Definition at line 1447 of file d11.h.

#define PRXS0_ANTSEL_1   0x2 /* antenna 1 is used */

Definition at line 1448 of file d11.h.

#define PRXS0_ANTSEL_2   0x4 /* antenna 2 is used */

Definition at line 1449 of file d11.h.

#define PRXS0_ANTSEL_3   0x8 /* antenna 3 is used */

Definition at line 1450 of file d11.h.

#define PRXS0_ANTSEL_MASK   0xF000

Definition at line 1436 of file d11.h.

#define PRXS0_ANTSEL_SHIFT   0x12

Definition at line 1437 of file d11.h.

#define PRXS0_BAND   0x0400 /* 0 = 2.4G, 1 = 5G */

Definition at line 1464 of file d11.h.

#define PRXS0_CCK   0x0000

Definition at line 1440 of file d11.h.

#define PRXS0_CLIP_MASK   0x000C

Definition at line 1419 of file d11.h.

#define PRXS0_CLIP_SHIFT   2

Definition at line 1420 of file d11.h.

#define PRXS0_FT_MASK   0x0003

Definition at line 1417 of file d11.h.

#define PRXS0_GAIN_CTL   0x4000

Definition at line 1434 of file d11.h.

#define PRXS0_LCRS   0x0040

Definition at line 1426 of file d11.h.

#define PRXS0_OFDM   0x0001

Definition at line 1442 of file d11.h.

#define PRXS0_PLCPFV   0x0100

Definition at line 1430 of file d11.h.

#define PRXS0_PLCPHCF   0x0200

Definition at line 1432 of file d11.h.

#define PRXS0_PREN   0x0002

Definition at line 1443 of file d11.h.

#define PRXS0_RSVD   0x0800 /* reserved; set to 0 */

Definition at line 1465 of file d11.h.

#define PRXS0_RXANT_UPSUBBAND   0x0020

Definition at line 1424 of file d11.h.

#define PRXS0_SHORTH   0x0080

Definition at line 1428 of file d11.h.

#define PRXS0_STDN   0x0003

Definition at line 1444 of file d11.h.

#define PRXS0_UNSRATE   0x0010

Definition at line 1422 of file d11.h.

#define PRXS0_UNUSED   0xF000 /* unused and not defined; set to 0 */

Definition at line 1466 of file d11.h.

#define PRXS1_HTPHY_ANTCFG_MASK   0x00F0

Definition at line 1472 of file d11.h.

#define PRXS1_HTPHY_CORE_MASK   0x000F

Definition at line 1470 of file d11.h.

#define PRXS1_HTPHY_MMPLCPLenL_MASK   0xFF00

Definition at line 1474 of file d11.h.

#define PRXS1_JSSI_MASK   0x00FF

Definition at line 1453 of file d11.h.

#define PRXS1_JSSI_SHIFT   0

Definition at line 1454 of file d11.h.

#define PRXS1_nphy_PWR0_MASK   0x00FF

Definition at line 1459 of file d11.h.

#define PRXS1_nphy_PWR1_MASK   0xFF00

Definition at line 1460 of file d11.h.

#define PRXS1_SQ_MASK   0xFF00

Definition at line 1455 of file d11.h.

#define PRXS1_SQ_SHIFT   8

Definition at line 1456 of file d11.h.

#define PRXS2_HTPHY_MMPLCH_RATE_MASK   0x00F0

Definition at line 1480 of file d11.h.

#define PRXS2_HTPHY_MMPLCPLenH_MASK   0x000F

Definition at line 1478 of file d11.h.

#define PRXS2_HTPHY_RXPWR_ANT0   0xFF00

Definition at line 1482 of file d11.h.

#define PRXS3_HTPHY_RXPWR_ANT1   0x00FF

Definition at line 1486 of file d11.h.

#define PRXS3_HTPHY_RXPWR_ANT2   0xFF00

Definition at line 1488 of file d11.h.

#define PRXS4_HTPHY_CFO   0xFF00

Definition at line 1494 of file d11.h.

#define PRXS4_HTPHY_RXPWR_ANT3   0x00FF

Definition at line 1492 of file d11.h.

#define PRXS5_HTPHY_AR   0xFF00

Definition at line 1500 of file d11.h.

#define PRXS5_HTPHY_FFO   0x00FF

Definition at line 1498 of file d11.h.

#define PV_AV_MASK   0xf000

Definition at line 648 of file d11.h.

#define PV_AV_SHIFT   12

Definition at line 650 of file d11.h.

#define PV_PT_MASK   0x0f00

Definition at line 652 of file d11.h.

#define PV_PT_SHIFT   8

Definition at line 654 of file d11.h.

#define PV_PV_MASK   0x000f

Definition at line 656 of file d11.h.

#define RCM_BSSID_OFFSET   3 /* current BSSID address */

Definition at line 965 of file d11.h.

#define RCM_F_BSSID_0_OFFSET   6 /* foreign BSS CFP tracking */

Definition at line 966 of file d11.h.

#define RCM_F_BSSID_1_OFFSET   9 /* foreign BSS CFP tracking */

Definition at line 967 of file d11.h.

#define RCM_F_BSSID_2_OFFSET   12 /* foreign BSS CFP tracking */

Definition at line 968 of file d11.h.

#define RCM_INC_DATA   0x0020

Definition at line 960 of file d11.h.

#define RCM_INC_MASK_H   0x0080

Definition at line 958 of file d11.h.

#define RCM_INC_MASK_L   0x0040

Definition at line 959 of file d11.h.

#define RCM_INDEX_MASK   0x001F

Definition at line 961 of file d11.h.

#define RCM_MAC_OFFSET   0 /* current MAC address */

Definition at line 964 of file d11.h.

#define RCM_SIZE   15

Definition at line 962 of file d11.h.

#define RCM_WEP_TA0_OFFSET   16

Definition at line 970 of file d11.h.

#define RCM_WEP_TA1_OFFSET   19

Definition at line 971 of file d11.h.

#define RCM_WEP_TA2_OFFSET   22

Definition at line 972 of file d11.h.

#define RCM_WEP_TA3_OFFSET   25

Definition at line 973 of file d11.h.

#define RCMTA_SIZE   50

Definition at line 991 of file d11.h.

#define RX_FIFO   0 /* data and ctl frames */

Definition at line 27 of file d11.h.

#define RX_TXSTATUS_FIFO   3 /* RX fifo for tx status packages */

Definition at line 28 of file d11.h.

#define RXS_AGGTYPE_MASK   0x6

Definition at line 1528 of file d11.h.

#define RXS_AGGTYPE_SHIFT   1

Definition at line 1529 of file d11.h.

#define RXS_AMSDU_MASK   1

Definition at line 1527 of file d11.h.

#define RXS_BCNSENT   0x8000

Definition at line 1516 of file d11.h.

#define RXS_CHAN_40   0x1000

Definition at line 1535 of file d11.h.

#define RXS_CHAN_5G   0x0800

Definition at line 1536 of file d11.h.

#define RXS_CHAN_ID_MASK   0x07f8

Definition at line 1537 of file d11.h.

#define RXS_CHAN_ID_SHIFT   3

Definition at line 1538 of file d11.h.

#define RXS_CHAN_PHYTYPE_MASK   0x0007

Definition at line 1539 of file d11.h.

#define RXS_CHAN_PHYTYPE_SHIFT   0

Definition at line 1540 of file d11.h.

#define RXS_DECATMPT   (1 << 3)

Definition at line 1520 of file d11.h.

#define RXS_DECERR   (1 << 4)

Definition at line 1519 of file d11.h.

#define RXS_FCSERR   (1 << 0)

Definition at line 1524 of file d11.h.

#define RXS_PBPRES   (1 << 2)

Definition at line 1522 of file d11.h.

#define RXS_PHYRXST_VALID   (1 << 8)

Definition at line 1530 of file d11.h.

#define RXS_RESPFRAMETX   (1 << 1)

Definition at line 1523 of file d11.h.

#define RXS_RXANT_MASK   0x3

Definition at line 1531 of file d11.h.

#define RXS_RXANT_SHIFT   12

Definition at line 1532 of file d11.h.

#define RXS_SECKINDX_MASK   0x07e0

Definition at line 1517 of file d11.h.

#define RXS_SECKINDX_SHIFT   5

Definition at line 1518 of file d11.h.

#define S_BEACON_INDX   S_OLD_BREM

Definition at line 1666 of file d11.h.

#define S_PHYTYPE   S_SSRC

Definition at line 1668 of file d11.h.

#define S_PHYVER   S_SLRC

Definition at line 1669 of file d11.h.

#define S_PRS_INDX   S_OLD_CWWIN

Definition at line 1667 of file d11.h.

#define SHM_BYT_CNT   0x2 /* IHR location */

Definition at line 1881 of file d11.h.

#define SICF_BW10   0x0000 /* 10MHz BW (40MHz phyclk) */

Definition at line 1747 of file d11.h.

#define SICF_BW20   0x0040 /* 20MHz BW (80MHz phyclk) */

Definition at line 1746 of file d11.h.

#define SICF_BW40   0x0080 /* 40MHz BW (160MHz phyclk) */

Definition at line 1745 of file d11.h.

#define SICF_BWMASK   0x00c0 /* phy clock mask (b6 & b7) */

Definition at line 1744 of file d11.h.

#define SICF_FREF   0x0020 /* PLL FreqRefSelect */

Definition at line 1740 of file d11.h.

#define SICF_GMODE   0x2000 /* gmode enable */

Definition at line 1748 of file d11.h.

#define SICF_MPCLKE   0x0010 /* MAC PHY clockcontrol enable */

Definition at line 1739 of file d11.h.

#define SICF_PCLKE   0x0004 /* PHY clock enable */

Definition at line 1737 of file d11.h.

#define SICF_PRST   0x0008 /* PHY reset */

Definition at line 1738 of file d11.h.

#define SISF_2G_PHY   0x0001 /* 2.4G capable phy */

Definition at line 1751 of file d11.h.

#define SISF_5G_PHY   0x0002 /* 5G capable phy */

Definition at line 1752 of file d11.h.

#define SISF_DB_PHY   0x0008 /* Dualband phy */

Definition at line 1754 of file d11.h.

#define SISF_FCLKA   0x0004 /* FastClkAvailable */

Definition at line 1753 of file d11.h.

#define SKL_ALGO_MASK   0x0007

Definition at line 1017 of file d11.h.

#define SKL_ALGO_SHIFT   0

Definition at line 1018 of file d11.h.

#define SKL_GRP_ALGO_MASK   0x1c00

Definition at line 1023 of file d11.h.

#define SKL_GRP_ALGO_SHIFT   10

Definition at line 1024 of file d11.h.

#define SKL_IBSS_INDEX_MASK   0x01F0

Definition at line 1027 of file d11.h.

#define SKL_IBSS_INDEX_SHIFT   4

Definition at line 1028 of file d11.h.

#define SKL_IBSS_KEYALGO_MASK   0xE000

Definition at line 1033 of file d11.h.

#define SKL_IBSS_KEYALGO_SHIFT   13

Definition at line 1034 of file d11.h.

#define SKL_IBSS_KEYID1_MASK   0x0600

Definition at line 1029 of file d11.h.

#define SKL_IBSS_KEYID1_SHIFT   9

Definition at line 1030 of file d11.h.

#define SKL_IBSS_KEYID2_MASK   0x1800

Definition at line 1031 of file d11.h.

#define SKL_IBSS_KEYID2_SHIFT   11

Definition at line 1032 of file d11.h.

#define SKL_INDEX_MASK   0x03F0

Definition at line 1021 of file d11.h.

#define SKL_INDEX_SHIFT   4

Definition at line 1022 of file d11.h.

#define SKL_KEYID_MASK   0x0008

Definition at line 1019 of file d11.h.

#define SKL_KEYID_SHIFT   3

Definition at line 1020 of file d11.h.

#define SLOW_CTRL_FD   (1 << 8)

Definition at line 1673 of file d11.h.

#define SLOW_CTRL_PDE   (1 << 0)

Definition at line 1672 of file d11.h.

#define T_ACTS_TPL_BASE   (0)

Definition at line 1065 of file d11.h.

#define T_BA_TPL_BASE   T_QNULL_TPL_BASE /* template area for BA */

Definition at line 1075 of file d11.h.

#define T_BCN0_TPL_BASE   (0x34 * 2)

Definition at line 1069 of file d11.h.

#define T_BCN1_TPL_BASE   (0x234 * 2)

Definition at line 1071 of file d11.h.

#define T_NULL_TPL_BASE   (0xc * 2)

Definition at line 1066 of file d11.h.

#define T_PRS_TPL_BASE   (0x134 * 2)

Definition at line 1070 of file d11.h.

#define T_QNULL_TPL_BASE   (0x1c * 2)

Definition at line 1067 of file d11.h.

#define T_RAM_ACCESS_SZ   4 /* template ram is 4 byte access only */

Definition at line 1077 of file d11.h.

#define T_RR_TPL_BASE   (0x2c * 2)

Definition at line 1068 of file d11.h.

#define T_TX_FIFO_TXRAM_BASE
Value:
(T_ACTS_TPL_BASE + \
(TXFIFO_START_BLK * TXFIFO_SIZE_UNIT))

Definition at line 1072 of file d11.h.

#define TST_CARR_SUPP   0x0200

Definition at line 1866 of file d11.h.

#define TST_DC_COMP_LOOP   0x0100

Definition at line 1867 of file d11.h.

#define TST_DDFS   0x2000

Definition at line 1863 of file d11.h.

#define TST_LOOPBACK   0x0080

Definition at line 1868 of file d11.h.

#define TST_TXFILT0   0x0040

Definition at line 1869 of file d11.h.

#define TST_TXFILT1   0x0800

Definition at line 1864 of file d11.h.

#define TST_TXTEST_ENABLE   0x0020

Definition at line 1870 of file d11.h.

#define TST_TXTEST_PHASE   0x0007

Definition at line 1872 of file d11.h.

#define TST_TXTEST_RATE   0x0018

Definition at line 1871 of file d11.h.

#define TST_TXTEST_RATE_11MBPS   3

Definition at line 1878 of file d11.h.

#define TST_TXTEST_RATE_1MBPS   0

Definition at line 1875 of file d11.h.

#define TST_TXTEST_RATE_2MBPS   1

Definition at line 1876 of file d11.h.

#define TST_TXTEST_RATE_5_5MBPS   2

Definition at line 1877 of file d11.h.

#define TST_TXTEST_RATE_SHIFT   3

Definition at line 1879 of file d11.h.

#define TST_UNSCRAM   0x0400

Definition at line 1865 of file d11.h.

#define TX_AC_BE_FIFO   1 /* Best-Effort TX FIFO */

Definition at line 32 of file d11.h.

#define TX_AC_BK_FIFO   0 /* Background TX FIFO */

Definition at line 31 of file d11.h.

#define TX_AC_VI_FIFO   2 /* Video TX FIFO */

Definition at line 33 of file d11.h.

#define TX_AC_VO_FIFO   3 /* Voice TX FIFO */

Definition at line 34 of file d11.h.

#define TX_ATIM_FIFO   5 /* TX fifo for ATIM window info */

Definition at line 36 of file d11.h.

#define TX_BCMC_FIFO   4 /* Broadcast/Multicast TX FIFO */

Definition at line 35 of file d11.h.

#define TX_CTL_FIFO   TX_AC_VO_FIFO

Definition at line 46 of file d11.h.

#define TX_DATA_FIFO   TX_AC_BE_FIFO

Definition at line 45 of file d11.h.

#define TX_STATUS_ACK_RCV   (1 << 1) /* ACK received */

Definition at line 927 of file d11.h.

#define TX_STATUS_AMPDU   (1 << 5) /* AMPDU status */

Definition at line 924 of file d11.h.

#define TX_STATUS_BA_BMAP03_MASK   0xF000 /* ba bitmap 0:3 in 1st pkg */

Definition at line 950 of file d11.h.

#define TX_STATUS_BA_BMAP03_SHIFT   12 /* ba bitmap 0:3 in 1st pkg */

Definition at line 951 of file d11.h.

#define TX_STATUS_BA_BMAP47_MASK   0x001E /* ba bitmap 4:7 in 2nd pkg */

Definition at line 952 of file d11.h.

#define TX_STATUS_BA_BMAP47_SHIFT   3 /* ba bitmap 4:7 in 2nd pkg */

Definition at line 953 of file d11.h.

#define TX_STATUS_FRM_RTX_MASK   0xF000

Definition at line 917 of file d11.h.

#define TX_STATUS_FRM_RTX_SHIFT   12

Definition at line 918 of file d11.h.

#define TX_STATUS_INTERMEDIATE   (1 << 6) /* intermediate or 1st ampdu pkg */

Definition at line 923 of file d11.h.

#define TX_STATUS_MASK   0x00FE

Definition at line 921 of file d11.h.

#define TX_STATUS_NO_ACK   0

Definition at line 929 of file d11.h.

#define TX_STATUS_PMINDCTD   (1 << 7) /* PM mode indicated to AP */

Definition at line 922 of file d11.h.

#define TX_STATUS_RTS_RTX_MASK   0x0F00

Definition at line 919 of file d11.h.

#define TX_STATUS_RTS_RTX_SHIFT   8

Definition at line 920 of file d11.h.

#define TX_STATUS_SUPR_BADCH   (4 << 2) /* channel mismatch */

Definition at line 936 of file d11.h.

#define TX_STATUS_SUPR_EXPTIME   (5 << 2) /* lifetime expiry */

Definition at line 937 of file d11.h.

#define TX_STATUS_SUPR_FLUSH   (2 << 2) /* flush request */

Definition at line 933 of file d11.h.

#define TX_STATUS_SUPR_FRAG   (3 << 2) /* previous frag failure */

Definition at line 934 of file d11.h.

#define TX_STATUS_SUPR_MASK   0x1C /* suppress status bits (4:2) */

Definition at line 925 of file d11.h.

#define TX_STATUS_SUPR_PMQ   (1 << 2) /* PMQ entry */

Definition at line 932 of file d11.h.

#define TX_STATUS_SUPR_SHIFT   2

Definition at line 926 of file d11.h.

#define TX_STATUS_SUPR_TBTT   (3 << 2) /* SHARED: Probe resp supr for TBTT */

Definition at line 935 of file d11.h.

#define TX_STATUS_SUPR_UF   (6 << 2) /* underflow */

Definition at line 938 of file d11.h.

#define TX_STATUS_UNEXP (   status)
Value:
((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
TX_STATUS_UNEXP_AMPDU(status))

Definition at line 941 of file d11.h.

#define TX_STATUS_UNEXP_AMPDU (   status)
Value:
((((status) & TX_STATUS_SUPR_MASK) != 0) && \
(((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME))

Definition at line 946 of file d11.h.

#define TX_STATUS_VALID   (1 << 0) /* Tx status valid */

Definition at line 928 of file d11.h.

#define TXC_ALT_TXPWR   0x0008

Definition at line 837 of file d11.h.

#define TXC_AMIC   0x8000

Definition at line 806 of file d11.h.

#define TXC_AMPDU_FBR   0x1000

Definition at line 833 of file d11.h.

#define TXC_AMPDU_FIRST   1 /* first MPDU of an A-MPDU */

Definition at line 801 of file d11.h.

#define TXC_AMPDU_LAST   3 /* last (or single) MPDU of an A-MPDU */

Definition at line 803 of file d11.h.

#define TXC_AMPDU_MASK   0x0600

Definition at line 808 of file d11.h.

#define TXC_AMPDU_MIDDLE   2 /* intermediate MPDU of an A-MPDU */

Definition at line 802 of file d11.h.

#define TXC_AMPDU_NONE   0 /* Regular MPDU, not an A-MPDU */

Definition at line 800 of file d11.h.

#define TXC_AMPDU_SHIFT   9 /* shift for ampdu settings */

Definition at line 799 of file d11.h.

#define TXC_BW_40   0x0100

Definition at line 809 of file d11.h.

#define TXC_DFCS   0x0040

Definition at line 811 of file d11.h.

#define TXC_FREQBAND_5G   0x0080

Definition at line 810 of file d11.h.

#define TXC_HWSEQ   0x0010

Definition at line 813 of file d11.h.

#define TXC_IGNOREPMQ   0x0020

Definition at line 812 of file d11.h.

#define TXC_IMMEDACK   0x0001

Definition at line 817 of file d11.h.

#define TXC_LONGFRAME   0x0002

Definition at line 816 of file d11.h.

#define TXC_PREAMBLE_DATA_FB_SHORT   0x2000

Definition at line 829 of file d11.h.

#define TXC_PREAMBLE_RTS_FB_SHORT   0x8000

Definition at line 821 of file d11.h.

#define TXC_PREAMBLE_RTS_MAIN_SHORT   0x4000

Definition at line 823 of file d11.h.

#define TXC_SECKEY_MASK   0x0FF0

Definition at line 834 of file d11.h.

#define TXC_SECKEY_SHIFT   4

Definition at line 835 of file d11.h.

#define TXC_SECTYPE_MASK   0x0007

Definition at line 838 of file d11.h.

#define TXC_SECTYPE_SHIFT   0

Definition at line 839 of file d11.h.

#define TXC_SENDCTS   0x0800

Definition at line 807 of file d11.h.

#define TXC_SENDRTS   0x0004

Definition at line 815 of file d11.h.

#define TXC_STARTMSDU   0x0008

Definition at line 814 of file d11.h.

#define TXFIFO_FIFOTOP_SHIFT   8 /* fifo start */

Definition at line 639 of file d11.h.

#define TXFIFO_SIZE_UNIT   256 /* one unit corresponds to 256 bytes */

Definition at line 643 of file d11.h.

#define TXFIFO_START_BLK   6 /* Base address + 6 * 256 B */

Definition at line 642 of file d11.h.

#define TXFIFO_START_BLK16   65 /* Base address + 32 * 512 B/P */

Definition at line 641 of file d11.h.

#define TXFIFOCMD_FIFOSEL_SHIFT   8 /* fifo */

Definition at line 638 of file d11.h.

#define TXFIFOCMD_RESET_MASK   (1 << 15) /* reset */

Definition at line 637 of file d11.h.

#define TXS_FID_MASK   0xffff0000

Definition at line 611 of file d11.h.

#define TXS_FID_SHIFT   16

Definition at line 612 of file d11.h.

#define TXS_MU_MASK   0x01000000

Definition at line 618 of file d11.h.

#define TXS_MU_SHIFT   24

Definition at line 619 of file d11.h.

#define TXS_PTX_MASK   0xff0000

Definition at line 616 of file d11.h.

#define TXS_PTX_SHIFT   16

Definition at line 617 of file d11.h.

#define TXS_SEQ_MASK   0xffff

Definition at line 615 of file d11.h.

#define TXS_STATUS_MASK   0xffff

Definition at line 610 of file d11.h.

#define TXS_V   (1 << 0) /* valid bit */

Definition at line 609 of file d11.h.

#define TXSTATUS_LEN   16

Definition at line 914 of file d11.h.

#define WATCHDOG_8TU_DEF   5

Definition at line 1264 of file d11.h.

#define WATCHDOG_8TU_MAX   10

Definition at line 1265 of file d11.h.

#define WECR0_DECRYPT   (1 << 3)

Definition at line 1054 of file d11.h.

#define WECR0_ICVERR   (1 << 15)

Definition at line 1062 of file d11.h.

#define WECR0_IVINLINE   (1 << 4)

Definition at line 1055 of file d11.h.

#define WECR0_KEYREG_MASK   0x7

Definition at line 1053 of file d11.h.

#define WECR0_KEYREG_SHIFT   0

Definition at line 1052 of file d11.h.

#define WECR0_WEPALG_MASK   (0x7 << 5)

Definition at line 1057 of file d11.h.

#define WECR0_WEPALG_SHIFT   5

Definition at line 1056 of file d11.h.

#define WECR0_WEPINIT   (1 << 14)

Definition at line 1061 of file d11.h.

#define WECR0_WKEYSEL_MASK   (0x7 << 8)

Definition at line 1059 of file d11.h.

#define WECR0_WKEYSEL_SHIFT   8

Definition at line 1058 of file d11.h.

#define WECR0_WKEYSTART   (1 << 11)

Definition at line 1060 of file d11.h.

#define WEP_PCMADDR   0x07d4

Definition at line 605 of file d11.h.

#define WEP_PCMDATA   0x07d6

Definition at line 606 of file d11.h.

#define WKEY_SEL_MASK   0x1F

Definition at line 986 of file d11.h.

#define WKEY_START   (1 << 8)

Definition at line 985 of file d11.h.

#define WL_RSSI_ANT_MAX   4 /* max possible rx antennas */

Definition at line 48 of file d11.h.

#define WME_STATUS_NEWAC   (1 << 8)

Definition at line 1316 of file d11.h.

#define WSEC_ALGO_AES   3

Definition at line 1043 of file d11.h.

#define WSEC_ALGO_AES_LEGACY   5

Definition at line 1045 of file d11.h.

#define WSEC_ALGO_NALG   6

Definition at line 1046 of file d11.h.

#define WSEC_ALGO_OFF   0

Definition at line 1040 of file d11.h.

#define WSEC_ALGO_TKIP   2

Definition at line 1042 of file d11.h.

#define WSEC_ALGO_WEP1   1

Definition at line 1041 of file d11.h.

#define WSEC_ALGO_WEP128   4

Definition at line 1044 of file d11.h.

#define WSEC_MAX_RCMTA_KEYS   54

Definition at line 1007 of file d11.h.

#define WSEC_MAX_RXE_KEYS   4

Definition at line 1013 of file d11.h.

#define WSEC_MAX_TKMIC_ENGINE_KEYS   12 /* 8 + 4 default */

Definition at line 1010 of file d11.h.

#define WSEC_MODE_HW   1

Definition at line 1037 of file d11.h.

#define WSEC_MODE_OFF   0

Definition at line 1036 of file d11.h.

#define WSEC_MODE_SW   2

Definition at line 1038 of file d11.h.

#define XFTS_CHANNEL_SHIFT   8

Definition at line 882 of file d11.h.

#define XFTS_FBRRTS_FT_SHIFT   4

Definition at line 881 of file d11.h.

#define XFTS_RTS_FT_SHIFT   2

Definition at line 880 of file d11.h.

Enumeration Type Documentation

enum _ePsmScratchPadRegDefinitions
Enumerator:
S_RSV0 
S_RSV1 
S_RSV2 
S_DOT11_CWMIN 
S_DOT11_CWMAX 
S_DOT11_CWCUR 
S_DOT11_SRC_LMT 
S_DOT11_LRC_LMT 
S_DOT11_DTIMCOUNT 
S_SEQ_NUM 
S_SEQ_NUM_FRAG 
S_FRMRETX_CNT 
S_SSRC 
S_SLRC 
S_EXP_RSP 
S_OLD_BREM 
S_OLD_CWWIN 
S_TXECTL 
S_CTXTST 
S_RXTST 
S_STREG 
S_TXPWR_SUM 
S_TXPWR_ITER 
S_RX_FRMTYPE 
S_THIS_AGG 
S_KEYINDX 
S_RXFRMLEN 
S_RXTSFTMRVAL_WD3 
S_RXTSFTMRVAL_WD2 
S_RXTSFTMRVAL_WD1 
S_RXTSFTMRVAL_WD0 
S_RXSSN 
S_RXQOSFLD 
S_TMP0 
S_TMP1 
S_TMP2 
S_TMP3 
S_TMP4 
S_TMP5 
S_PRQPENALTY_CTR 
S_ANTCNT 
S_SYMBOL 
S_RXTP 
S_STREG2 
S_STREG3 
S_STREG4 
S_STREG5 
S_ADJPWR_IDX 
S_CUR_PTR 
S_REVID4 
S_INDX 
S_ADDR0 
S_ADDR1 
S_ADDR2 
S_ADDR3 
S_ADDR4 
S_ADDR5 
S_TMP6 
S_KEYINDX_BU 
S_MFGTEST_TMP0 
S_RXESN 
S_STREG6 

Definition at line 1586 of file d11.h.

Variable Documentation

struct d11rxhdr __packed
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