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#define | SMC_DYNAMIC_BUS_CONFIG |
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#define | SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2) |
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#define | SMC911X_IO_EXTENT 0x100 |
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#define | SMC911X_EEPROM_LEN 7 |
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#define | RX_DATA_FIFO (0x00) |
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#define | TX_DATA_FIFO (0x20) |
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#define | TX_CMD_A_INT_ON_COMP_ (0x80000000) |
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#define | TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000) |
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#define | TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000) |
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#define | TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000) |
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#define | TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000) |
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#define | TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000) |
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#define | TX_CMD_A_INT_FIRST_SEG_ (0x00002000) |
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#define | TX_CMD_A_INT_LAST_SEG_ (0x00001000) |
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#define | TX_CMD_A_BUF_SIZE_ (0x000007FF) |
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#define | TX_CMD_B_PKT_TAG_ (0xFFFF0000) |
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#define | TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000) |
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#define | TX_CMD_B_DISABLE_PADDING_ (0x00001000) |
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#define | TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF) |
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#define | RX_STATUS_FIFO (0x40) |
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#define | RX_STS_PKT_LEN_ (0x3FFF0000) |
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#define | RX_STS_ES_ (0x00008000) |
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#define | RX_STS_BCST_ (0x00002000) |
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#define | RX_STS_LEN_ERR_ (0x00001000) |
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#define | RX_STS_RUNT_ERR_ (0x00000800) |
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#define | RX_STS_MCAST_ (0x00000400) |
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#define | RX_STS_TOO_LONG_ (0x00000080) |
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#define | RX_STS_COLL_ (0x00000040) |
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#define | RX_STS_ETH_TYPE_ (0x00000020) |
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#define | RX_STS_WDOG_TMT_ (0x00000010) |
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#define | RX_STS_MII_ERR_ (0x00000008) |
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#define | RX_STS_DRIBBLING_ (0x00000004) |
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#define | RX_STS_CRC_ERR_ (0x00000002) |
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#define | RX_STATUS_FIFO_PEEK (0x44) |
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#define | TX_STATUS_FIFO (0x48) |
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#define | TX_STS_TAG_ (0xFFFF0000) |
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#define | TX_STS_ES_ (0x00008000) |
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#define | TX_STS_LOC_ (0x00000800) |
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#define | TX_STS_NO_CARR_ (0x00000400) |
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#define | TX_STS_LATE_COLL_ (0x00000200) |
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#define | TX_STS_MANY_COLL_ (0x00000100) |
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#define | TX_STS_COLL_CNT_ (0x00000078) |
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#define | TX_STS_MANY_DEFER_ (0x00000004) |
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#define | TX_STS_UNDERRUN_ (0x00000002) |
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#define | TX_STS_DEFERRED_ (0x00000001) |
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#define | TX_STATUS_FIFO_PEEK (0x4C) |
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#define | ID_REV (0x50) |
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#define | ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */ |
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#define | ID_REV_REV_ID_ (0x0000FFFF) /* RO */ |
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#define | INT_CFG (0x54) |
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#define | INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */ |
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#define | INT_CFG_INT_DEAS_CLR_ (0x00004000) |
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#define | INT_CFG_INT_DEAS_STS_ (0x00002000) |
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#define | INT_CFG_IRQ_INT_ (0x00001000) /* RO */ |
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#define | INT_CFG_IRQ_EN_ (0x00000100) /* R/W */ |
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#define | INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */ |
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#define | INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */ |
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#define | INT_STS (0x58) |
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#define | INT_STS_SW_INT_ (0x80000000) /* R/WC */ |
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#define | INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */ |
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#define | INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */ |
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#define | INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */ |
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#define | INT_STS_RXDF_INT_ (0x00400000) /* R/WC */ |
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#define | INT_STS_TX_IOC_ (0x00200000) /* R/WC */ |
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#define | INT_STS_RXD_INT_ (0x00100000) /* R/WC */ |
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#define | INT_STS_GPT_INT_ (0x00080000) /* R/WC */ |
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#define | INT_STS_PHY_INT_ (0x00040000) /* RO */ |
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#define | INT_STS_PME_INT_ (0x00020000) /* R/WC */ |
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#define | INT_STS_TXSO_ (0x00010000) /* R/WC */ |
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#define | INT_STS_RWT_ (0x00008000) /* R/WC */ |
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#define | INT_STS_RXE_ (0x00004000) /* R/WC */ |
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#define | INT_STS_TXE_ (0x00002000) /* R/WC */ |
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#define | INT_STS_TDFU_ (0x00000800) /* R/WC */ |
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#define | INT_STS_TDFO_ (0x00000400) /* R/WC */ |
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#define | INT_STS_TDFA_ (0x00000200) /* R/WC */ |
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#define | INT_STS_TSFF_ (0x00000100) /* R/WC */ |
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#define | INT_STS_TSFL_ (0x00000080) /* R/WC */ |
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#define | INT_STS_RDFO_ (0x00000040) /* R/WC */ |
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#define | INT_STS_RDFL_ (0x00000020) /* R/WC */ |
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#define | INT_STS_RSFF_ (0x00000010) /* R/WC */ |
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#define | INT_STS_RSFL_ (0x00000008) /* R/WC */ |
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#define | INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */ |
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#define | INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */ |
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#define | INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */ |
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#define | INT_EN (0x5C) |
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#define | INT_EN_SW_INT_EN_ (0x80000000) /* R/W */ |
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#define | INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */ |
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#define | INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */ |
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#define | INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */ |
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#define | INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */ |
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#define | INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */ |
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#define | INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */ |
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#define | INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */ |
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#define | INT_EN_PME_INT_EN_ (0x00020000) /* R/W */ |
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#define | INT_EN_TXSO_EN_ (0x00010000) /* R/W */ |
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#define | INT_EN_RWT_EN_ (0x00008000) /* R/W */ |
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#define | INT_EN_RXE_EN_ (0x00004000) /* R/W */ |
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#define | INT_EN_TXE_EN_ (0x00002000) /* R/W */ |
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#define | INT_EN_TDFU_EN_ (0x00000800) /* R/W */ |
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#define | INT_EN_TDFO_EN_ (0x00000400) /* R/W */ |
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#define | INT_EN_TDFA_EN_ (0x00000200) /* R/W */ |
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#define | INT_EN_TSFF_EN_ (0x00000100) /* R/W */ |
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#define | INT_EN_TSFL_EN_ (0x00000080) /* R/W */ |
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#define | INT_EN_RDFO_EN_ (0x00000040) /* R/W */ |
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#define | INT_EN_RDFL_EN_ (0x00000020) /* R/W */ |
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#define | INT_EN_RSFF_EN_ (0x00000010) /* R/W */ |
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#define | INT_EN_RSFL_EN_ (0x00000008) /* R/W */ |
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#define | INT_EN_GPIO2_INT_ (0x00000004) /* R/W */ |
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#define | INT_EN_GPIO1_INT_ (0x00000002) /* R/W */ |
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#define | INT_EN_GPIO0_INT_ (0x00000001) /* R/W */ |
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#define | BYTE_TEST (0x64) |
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#define | FIFO_INT (0x68) |
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#define | FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */ |
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#define | FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */ |
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#define | FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */ |
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#define | FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */ |
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#define | RX_CFG (0x6C) |
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#define | RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */ |
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#define | RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */ |
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#define | RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */ |
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#define | RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */ |
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#define | RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */ |
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#define | RX_CFG_RX_DUMP_ (0x00008000) /* R/W */ |
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#define | RX_CFG_RXDOFF_ (0x00001F00) /* R/W */ |
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#define | TX_CFG (0x70) |
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#define | TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */ |
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#define | TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */ |
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#define | TX_CFG_TXSAO_ (0x00000004) /* R/W */ |
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#define | TX_CFG_TX_ON_ (0x00000002) /* R/W */ |
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#define | TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */ |
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#define | HW_CFG (0x74) |
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#define | HW_CFG_TTM_ (0x00200000) /* R/W */ |
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#define | HW_CFG_SF_ (0x00100000) /* R/W */ |
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#define | HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */ |
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#define | HW_CFG_TR_ (0x00003000) /* R/W */ |
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#define | HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */ |
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#define | HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */ |
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#define | HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */ |
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#define | HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */ |
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#define | HW_CFG_SMI_SEL_ (0x00000010) /* R/W */ |
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#define | HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */ |
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#define | HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */ |
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#define | HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */ |
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#define | HW_CFG_SRST_TO_ (0x00000002) /* RO */ |
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#define | HW_CFG_SRST_ (0x00000001) /* Self Clearing */ |
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#define | RX_DP_CTRL (0x78) |
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#define | RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */ |
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#define | RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */ |
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#define | RX_FIFO_INF (0x7C) |
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#define | RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */ |
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#define | RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */ |
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#define | TX_FIFO_INF (0x80) |
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#define | TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */ |
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#define | TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */ |
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#define | PMT_CTRL (0x84) |
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#define | PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */ |
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#define | PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */ |
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#define | PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */ |
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#define | PMT_CTRL_ED_EN_ (0x00000100) /* R/W */ |
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#define | PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */ |
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#define | PMT_CTRL_WUPS_ (0x00000030) /* R/WC */ |
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#define | PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */ |
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#define | PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */ |
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#define | PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */ |
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#define | PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */ |
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#define | PMT_CTRL_PME_IND_ (0x00000008) /* R/W */ |
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#define | PMT_CTRL_PME_POL_ (0x00000004) /* R/W */ |
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#define | PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */ |
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#define | PMT_CTRL_READY_ (0x00000001) /* RO */ |
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#define | GPIO_CFG (0x88) |
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#define | GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */ |
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#define | GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */ |
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#define | GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */ |
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#define | GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */ |
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#define | GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */ |
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#define | GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */ |
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#define | GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */ |
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#define | GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */ |
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#define | GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */ |
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#define | GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */ |
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#define | GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */ |
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#define | GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */ |
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#define | GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */ |
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#define | GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */ |
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#define | GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */ |
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#define | GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */ |
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#define | GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */ |
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#define | GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */ |
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#define | GPT_CFG (0x8C) |
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#define | GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */ |
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#define | GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */ |
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#define | GPT_CNT (0x90) |
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#define | GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */ |
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#define | ENDIAN (0x98) |
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#define | FREE_RUN (0x9C) |
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#define | RX_DROP (0xA0) |
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#define | MAC_CSR_CMD (0xA4) |
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#define | MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */ |
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#define | MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */ |
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#define | MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */ |
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#define | MAC_CSR_DATA (0xA8) |
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#define | AFC_CFG (0xAC) |
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#define | AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */ |
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#define | AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */ |
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#define | AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */ |
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#define | AFC_CFG_FCMULT_ (0x00000008) /* R/W */ |
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#define | AFC_CFG_FCBRD_ (0x00000004) /* R/W */ |
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#define | AFC_CFG_FCADD_ (0x00000002) /* R/W */ |
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#define | AFC_CFG_FCANY_ (0x00000001) /* R/W */ |
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#define | E2P_CMD (0xB0) |
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#define | E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */ |
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#define | E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */ |
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#define | E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */ |
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#define | E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */ |
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#define | E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */ |
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#define | E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */ |
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#define | E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */ |
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#define | E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */ |
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#define | E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */ |
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#define | E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */ |
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#define | E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */ |
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#define | E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */ |
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#define | E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */ |
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#define | E2P_DATA (0xB4) |
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#define | E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */ |
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#define | MAC_CR (0x01) /* R/W */ |
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#define | MAC_CR_RXALL_ (0x80000000) |
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#define | MAC_CR_HBDIS_ (0x10000000) |
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#define | MAC_CR_RCVOWN_ (0x00800000) |
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#define | MAC_CR_LOOPBK_ (0x00200000) |
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#define | MAC_CR_FDPX_ (0x00100000) |
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#define | MAC_CR_MCPAS_ (0x00080000) |
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#define | MAC_CR_PRMS_ (0x00040000) |
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#define | MAC_CR_INVFILT_ (0x00020000) |
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#define | MAC_CR_PASSBAD_ (0x00010000) |
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#define | MAC_CR_HFILT_ (0x00008000) |
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#define | MAC_CR_HPFILT_ (0x00002000) |
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#define | MAC_CR_LCOLL_ (0x00001000) |
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#define | MAC_CR_BCAST_ (0x00000800) |
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#define | MAC_CR_DISRTY_ (0x00000400) |
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#define | MAC_CR_PADSTR_ (0x00000100) |
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#define | MAC_CR_BOLMT_MASK_ (0x000000C0) |
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#define | MAC_CR_DFCHK_ (0x00000020) |
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#define | MAC_CR_TXEN_ (0x00000008) |
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#define | MAC_CR_RXEN_ (0x00000004) |
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#define | ADDRH (0x02) /* R/W mask 0x0000FFFFUL */ |
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#define | ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */ |
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#define | HASHH (0x04) /* R/W */ |
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#define | HASHL (0x05) /* R/W */ |
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#define | MII_ACC (0x06) /* R/W */ |
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#define | MII_ACC_PHY_ADDR_ (0x0000F800) |
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#define | MII_ACC_MIIRINDA_ (0x000007C0) |
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#define | MII_ACC_MII_WRITE_ (0x00000002) |
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#define | MII_ACC_MII_BUSY_ (0x00000001) |
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#define | MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */ |
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#define | FLOW (0x08) /* R/W */ |
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#define | FLOW_FCPT_ (0xFFFF0000) |
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#define | FLOW_FCPASS_ (0x00000004) |
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#define | FLOW_FCEN_ (0x00000002) |
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#define | FLOW_FCBSY_ (0x00000001) |
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#define | VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */ |
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#define | VLAN1_VTI1_ (0x0000ffff) |
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#define | VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */ |
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#define | VLAN2_VTI2_ (0x0000ffff) |
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#define | WUFF (0x0B) /* WO */ |
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#define | WUCSR (0x0C) /* R/W */ |
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#define | WUCSR_GUE_ (0x00000200) |
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#define | WUCSR_WUFR_ (0x00000040) |
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#define | WUCSR_MPR_ (0x00000020) |
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#define | WUCSR_WAKE_EN_ (0x00000004) |
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#define | WUCSR_MPEN_ (0x00000002) |
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#define | PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */ |
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#define | MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000) |
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#define | MODE_CTRL_STS_ENERGYON_ ((u16)0x0002) |
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#define | PHY_INT_SRC ((u32)29) |
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#define | PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080) |
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#define | PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040) |
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#define | PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020) |
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#define | PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010) |
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#define | PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008) |
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#define | PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004) |
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#define | PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002) |
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#define | PHY_INT_MASK ((u32)30) |
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#define | PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080) |
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#define | PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) |
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#define | PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020) |
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#define | PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) |
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#define | PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008) |
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#define | PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004) |
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#define | PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002) |
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#define | PHY_SPECIAL ((u32)31) |
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#define | PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000) |
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#define | PHY_SPECIAL_RES_ ((u16)0x0040) |
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#define | PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1) |
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#define | PHY_SPECIAL_SPD_ ((u16)0x001C) |
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#define | PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004) |
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#define | PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014) |
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#define | PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008) |
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#define | PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018) |
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#define | LAN911X_INTERNAL_PHY_ID (0x0007C000) |
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#define | CHIP_9115 0x0115 |
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#define | CHIP_9116 0x0116 |
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#define | CHIP_9117 0x0117 |
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#define | CHIP_9118 0x0118 |
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#define | CHIP_9211 0x9211 |
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#define | CHIP_9215 0x115A |
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#define | CHIP_9217 0x117A |
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#define | CHIP_9218 0x118A |
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#define | IS_REV_A(x) ((x & 0xFFFF)==0) |
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#define | SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 ) |
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#define | SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 ) |
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#define | SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO ) |
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#define | SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO ) |
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#define | SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO ) |
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#define | SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO ) |
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#define | SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK ) |
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#define | SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16) |
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#define | SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF) |
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#define | SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG ) |
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#define | SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG ) |
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#define | SMC_GET_INT(lp) SMC_inl( lp, INT_STS ) |
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#define | SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS ) |
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#define | SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN ) |
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#define | SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN ) |
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#define | SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST ) |
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#define | SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST ) |
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#define | SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT ) |
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#define | SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT ) |
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#define | SMC_SET_FIFO_TDA(lp, x) |
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#define | SMC_SET_FIFO_TSL(lp, x) |
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#define | SMC_SET_FIFO_RSA(lp, x) |
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#define | SMC_SET_FIFO_RSL(lp, x) |
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#define | SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG ) |
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#define | SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG ) |
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#define | SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG ) |
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#define | SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG ) |
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#define | SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG ) |
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#define | SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG ) |
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#define | SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL ) |
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#define | SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL ) |
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#define | SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL ) |
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#define | SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL ) |
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#define | SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG ) |
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#define | SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG ) |
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#define | SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF ) |
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#define | SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF ) |
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#define | SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF ) |
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#define | SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF ) |
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#define | SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG ) |
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#define | SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG ) |
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#define | SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP ) |
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#define | SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP ) |
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#define | SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD ) |
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#define | SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD ) |
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#define | SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA ) |
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#define | SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA ) |
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#define | SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG ) |
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#define | SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG ) |
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#define | SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD ) |
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#define | SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD ) |
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#define | SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA ) |
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#define | SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA ) |
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#define | SMC_GET_MAC_CSR(lp, a, v) |
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#define | SMC_SET_MAC_CSR(lp, a, v) |
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#define | SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x ) |
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#define | SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x ) |
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#define | SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x ) |
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#define | SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x ) |
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#define | SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x ) |
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#define | SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x ) |
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#define | SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x ) |
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#define | SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x ) |
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#define | SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x ) |
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#define | SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x ) |
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#define | SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x ) |
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#define | SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x ) |
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#define | SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x ) |
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#define | SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x ) |
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#define | SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x ) |
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#define | SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x ) |
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#define | SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x ) |
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#define | SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x ) |
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#define | SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x ) |
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#define | SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x ) |
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#define | SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x ) |
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#define | SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x ) |
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#define | SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x ) |
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#define | SMC_GET_MII(lp, a, phy, v) |
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#define | SMC_SET_MII(lp, a, phy, v) |
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#define | SMC_GET_PHY_BMCR(lp, phy, x) SMC_GET_MII( (lp), MII_BMCR, phy, x ) |
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#define | SMC_SET_PHY_BMCR(lp, phy, x) SMC_SET_MII( (lp), MII_BMCR, phy, x ) |
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#define | SMC_GET_PHY_BMSR(lp, phy, x) SMC_GET_MII( (lp), MII_BMSR, phy, x ) |
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#define | SMC_GET_PHY_ID1(lp, phy, x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x ) |
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#define | SMC_GET_PHY_ID2(lp, phy, x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x ) |
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#define | SMC_GET_PHY_MII_ADV(lp, phy, x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x ) |
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#define | SMC_SET_PHY_MII_ADV(lp, phy, x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x ) |
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#define | SMC_GET_PHY_MII_LPA(lp, phy, x) SMC_GET_MII( (lp), MII_LPA, phy, x ) |
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#define | SMC_SET_PHY_MII_LPA(lp, phy, x) SMC_SET_MII( (lp), MII_LPA, phy, x ) |
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#define | SMC_GET_PHY_CTRL_STS(lp, phy, x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x ) |
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#define | SMC_SET_PHY_CTRL_STS(lp, phy, x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x ) |
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#define | SMC_GET_PHY_INT_SRC(lp, phy, x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x ) |
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#define | SMC_SET_PHY_INT_SRC(lp, phy, x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x ) |
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#define | SMC_GET_PHY_INT_MASK(lp, phy, x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x ) |
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#define | SMC_SET_PHY_INT_MASK(lp, phy, x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x ) |
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#define | SMC_GET_PHY_SPECIAL(lp, phy, x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x ) |
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#define | SMC_GET_MAC_ADDR(lp, addr) |
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#define | SMC_SET_MAC_ADDR(lp, addr) |
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#define | SMC_WRITE_EEPROM_CMD(lp, cmd, addr) |
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