Linux Kernel  3.7.1
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main.c
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1 /*
2  * This file is part of wl18xx
3  *
4  * Copyright (C) 2011 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18  * 02110-1301 USA
19  *
20  */
21 
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/ip.h>
25 #include <linux/firmware.h>
26 
27 #include "../wlcore/wlcore.h"
28 #include "../wlcore/debug.h"
29 #include "../wlcore/io.h"
30 #include "../wlcore/acx.h"
31 #include "../wlcore/tx.h"
32 #include "../wlcore/rx.h"
33 #include "../wlcore/boot.h"
34 
35 #include "reg.h"
36 #include "conf.h"
37 #include "acx.h"
38 #include "tx.h"
39 #include "wl18xx.h"
40 #include "io.h"
41 #include "debugfs.h"
42 
43 #define WL18XX_RX_CHECKSUM_MASK 0x40
44 
45 static char *ht_mode_param = NULL;
46 static char *board_type_param = NULL;
47 static bool checksum_param = false;
48 static int num_rx_desc_param = -1;
49 
50 /* phy paramters */
51 static int dc2dc_param = -1;
52 static int n_antennas_2_param = -1;
53 static int n_antennas_5_param = -1;
54 static int low_band_component_param = -1;
55 static int low_band_component_type_param = -1;
56 static int high_band_component_param = -1;
57 static int high_band_component_type_param = -1;
58 static int pwr_limit_reference_11_abg_param = -1;
59 
60 static const u8 wl18xx_rate_to_idx_2ghz[] = {
61  /* MCS rates are used only with 11n */
62  15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
63  14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
64  13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
65  12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
66  11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
67  10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
68  9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
69  8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
70  7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
71  6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
72  5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
73  4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
74  3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
75  2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
76  1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
77  0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
78 
79  11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
80  10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
81  9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
82  8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
83 
84  /* TI-specific rate */
85  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
86 
87  7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
88  6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
89  3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
90  5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
91  4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
92  2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
93  1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
94  0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
95 };
96 
97 static const u8 wl18xx_rate_to_idx_5ghz[] = {
98  /* MCS rates are used only with 11n */
99  15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
100  14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
101  13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
102  12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
103  11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
104  10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
105  9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
106  8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
107  7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
108  6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
109  5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
110  4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
111  3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
112  2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
113  1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
114  0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
115 
116  7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
117  6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
118  5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
119  4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
120 
121  /* TI-specific rate */
122  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
123 
124  3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
125  2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
126  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
127  1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
128  0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
129  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
130  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
131  CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
132 };
133 
134 static const u8 *wl18xx_band_rate_to_idx[] = {
135  [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
136  [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
137 };
138 
139 enum wl18xx_hw_rates {
140  WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
141  WL18XX_CONF_HW_RXTX_RATE_MCS14,
142  WL18XX_CONF_HW_RXTX_RATE_MCS13,
143  WL18XX_CONF_HW_RXTX_RATE_MCS12,
144  WL18XX_CONF_HW_RXTX_RATE_MCS11,
145  WL18XX_CONF_HW_RXTX_RATE_MCS10,
146  WL18XX_CONF_HW_RXTX_RATE_MCS9,
147  WL18XX_CONF_HW_RXTX_RATE_MCS8,
148  WL18XX_CONF_HW_RXTX_RATE_MCS7,
149  WL18XX_CONF_HW_RXTX_RATE_MCS6,
150  WL18XX_CONF_HW_RXTX_RATE_MCS5,
151  WL18XX_CONF_HW_RXTX_RATE_MCS4,
152  WL18XX_CONF_HW_RXTX_RATE_MCS3,
153  WL18XX_CONF_HW_RXTX_RATE_MCS2,
154  WL18XX_CONF_HW_RXTX_RATE_MCS1,
155  WL18XX_CONF_HW_RXTX_RATE_MCS0,
156  WL18XX_CONF_HW_RXTX_RATE_54,
157  WL18XX_CONF_HW_RXTX_RATE_48,
158  WL18XX_CONF_HW_RXTX_RATE_36,
159  WL18XX_CONF_HW_RXTX_RATE_24,
160  WL18XX_CONF_HW_RXTX_RATE_22,
161  WL18XX_CONF_HW_RXTX_RATE_18,
162  WL18XX_CONF_HW_RXTX_RATE_12,
163  WL18XX_CONF_HW_RXTX_RATE_11,
164  WL18XX_CONF_HW_RXTX_RATE_9,
165  WL18XX_CONF_HW_RXTX_RATE_6,
166  WL18XX_CONF_HW_RXTX_RATE_5_5,
167  WL18XX_CONF_HW_RXTX_RATE_2,
168  WL18XX_CONF_HW_RXTX_RATE_1,
169  WL18XX_CONF_HW_RXTX_RATE_MAX,
170 };
171 
172 static struct wlcore_conf wl18xx_conf = {
173  .sg = {
174  .params = {
175  [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
176  [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
177  [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
178  [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
179  [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
180  [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
181  [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
182  [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
183  [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
184  [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
185  [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
186  [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
187  [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
188  [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
189  [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
190  [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
191  [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
192  [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
193  [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
194  [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
195  [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
196  [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
197  [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
198  [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
199  [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
200  [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
201  /* active scan params */
202  [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
203  [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
204  [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
205  /* passive scan params */
206  [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
207  [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
208  [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
209  /* passive scan in dual antenna params */
210  [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
211  [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
212  [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
213  /* general params */
214  [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
215  [CONF_SG_ANTENNA_CONFIGURATION] = 0,
216  [CONF_SG_BEACON_MISS_PERCENT] = 60,
217  [CONF_SG_DHCP_TIME] = 5000,
218  [CONF_SG_RXT] = 1200,
219  [CONF_SG_TXT] = 1000,
220  [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
221  [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
222  [CONF_SG_HV3_MAX_SERVED] = 6,
223  [CONF_SG_PS_POLL_TIMEOUT] = 10,
224  [CONF_SG_UPSD_TIMEOUT] = 10,
225  [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
226  [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
227  [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
228  /* AP params */
229  [CONF_AP_BEACON_MISS_TX] = 3,
230  [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
231  [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
232  [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
233  [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
234  [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
235  /* CTS Diluting params */
236  [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
237  [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
238  },
239  .state = CONF_SG_PROTECTIVE,
240  },
241  .rx = {
242  .rx_msdu_life_time = 512000,
243  .packet_detection_threshold = 0,
244  .ps_poll_timeout = 15,
245  .upsd_timeout = 15,
246  .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
247  .rx_cca_threshold = 0,
248  .irq_blk_threshold = 0xFFFF,
249  .irq_pkt_threshold = 0,
250  .irq_timeout = 600,
251  .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
252  },
253  .tx = {
254  .tx_energy_detection = 0,
255  .sta_rc_conf = {
256  .enabled_rates = 0,
257  .short_retry_limit = 10,
258  .long_retry_limit = 10,
259  .aflags = 0,
260  },
261  .ac_conf_count = 4,
262  .ac_conf = {
263  [CONF_TX_AC_BE] = {
264  .ac = CONF_TX_AC_BE,
265  .cw_min = 15,
266  .cw_max = 63,
267  .aifsn = 3,
268  .tx_op_limit = 0,
269  },
270  [CONF_TX_AC_BK] = {
271  .ac = CONF_TX_AC_BK,
272  .cw_min = 15,
273  .cw_max = 63,
274  .aifsn = 7,
275  .tx_op_limit = 0,
276  },
277  [CONF_TX_AC_VI] = {
278  .ac = CONF_TX_AC_VI,
279  .cw_min = 15,
280  .cw_max = 63,
281  .aifsn = CONF_TX_AIFS_PIFS,
282  .tx_op_limit = 3008,
283  },
284  [CONF_TX_AC_VO] = {
285  .ac = CONF_TX_AC_VO,
286  .cw_min = 15,
287  .cw_max = 63,
288  .aifsn = CONF_TX_AIFS_PIFS,
289  .tx_op_limit = 1504,
290  },
291  },
292  .max_tx_retries = 100,
293  .ap_aging_period = 300,
294  .tid_conf_count = 4,
295  .tid_conf = {
296  [CONF_TX_AC_BE] = {
297  .queue_id = CONF_TX_AC_BE,
298  .channel_type = CONF_CHANNEL_TYPE_EDCF,
299  .tsid = CONF_TX_AC_BE,
300  .ps_scheme = CONF_PS_SCHEME_LEGACY,
301  .ack_policy = CONF_ACK_POLICY_LEGACY,
302  .apsd_conf = {0, 0},
303  },
304  [CONF_TX_AC_BK] = {
305  .queue_id = CONF_TX_AC_BK,
306  .channel_type = CONF_CHANNEL_TYPE_EDCF,
307  .tsid = CONF_TX_AC_BK,
308  .ps_scheme = CONF_PS_SCHEME_LEGACY,
309  .ack_policy = CONF_ACK_POLICY_LEGACY,
310  .apsd_conf = {0, 0},
311  },
312  [CONF_TX_AC_VI] = {
313  .queue_id = CONF_TX_AC_VI,
314  .channel_type = CONF_CHANNEL_TYPE_EDCF,
315  .tsid = CONF_TX_AC_VI,
316  .ps_scheme = CONF_PS_SCHEME_LEGACY,
317  .ack_policy = CONF_ACK_POLICY_LEGACY,
318  .apsd_conf = {0, 0},
319  },
320  [CONF_TX_AC_VO] = {
321  .queue_id = CONF_TX_AC_VO,
322  .channel_type = CONF_CHANNEL_TYPE_EDCF,
323  .tsid = CONF_TX_AC_VO,
324  .ps_scheme = CONF_PS_SCHEME_LEGACY,
325  .ack_policy = CONF_ACK_POLICY_LEGACY,
326  .apsd_conf = {0, 0},
327  },
328  },
329  .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
330  .tx_compl_timeout = 350,
331  .tx_compl_threshold = 10,
332  .basic_rate = CONF_HW_BIT_RATE_1MBPS,
333  .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
334  .tmpl_short_retry_limit = 10,
335  .tmpl_long_retry_limit = 10,
336  .tx_watchdog_timeout = 5000,
337  },
338  .conn = {
339  .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
340  .listen_interval = 1,
341  .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
342  .suspend_listen_interval = 3,
343  .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
344  .bcn_filt_ie_count = 3,
345  .bcn_filt_ie = {
346  [0] = {
347  .ie = WLAN_EID_CHANNEL_SWITCH,
348  .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
349  },
350  [1] = {
351  .ie = WLAN_EID_HT_OPERATION,
352  .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
353  },
354  [2] = {
355  .ie = WLAN_EID_ERP_INFO,
356  .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
357  },
358  },
359  .synch_fail_thold = 12,
360  .bss_lose_timeout = 400,
361  .beacon_rx_timeout = 10000,
362  .broadcast_timeout = 20000,
363  .rx_broadcast_in_ps = 1,
364  .ps_poll_threshold = 10,
365  .bet_enable = CONF_BET_MODE_ENABLE,
366  .bet_max_consecutive = 50,
367  .psm_entry_retries = 8,
368  .psm_exit_retries = 16,
369  .psm_entry_nullfunc_retries = 3,
370  .dynamic_ps_timeout = 1500,
371  .forced_ps = false,
372  .keep_alive_interval = 55000,
373  .max_listen_interval = 20,
374  .sta_sleep_auth = WL1271_PSM_ILLEGAL,
375  },
376  .itrim = {
377  .enable = false,
378  .timeout = 50000,
379  },
380  .pm_config = {
381  .host_clk_settling_time = 5000,
382  .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
383  },
384  .roam_trigger = {
385  .trigger_pacing = 1,
386  .avg_weight_rssi_beacon = 20,
387  .avg_weight_rssi_data = 10,
388  .avg_weight_snr_beacon = 20,
389  .avg_weight_snr_data = 10,
390  },
391  .scan = {
392  .min_dwell_time_active = 7500,
393  .max_dwell_time_active = 30000,
394  .min_dwell_time_passive = 100000,
395  .max_dwell_time_passive = 100000,
396  .num_probe_reqs = 2,
397  .split_scan_timeout = 50000,
398  },
399  .sched_scan = {
400  /*
401  * Values are in TU/1000 but since sched scan FW command
402  * params are in TUs rounding up may occur.
403  */
404  .base_dwell_time = 7500,
405  .max_dwell_time_delta = 22500,
406  /* based on 250bits per probe @1Mbps */
407  .dwell_time_delta_per_probe = 2000,
408  /* based on 250bits per probe @6Mbps (plus a bit more) */
409  .dwell_time_delta_per_probe_5 = 350,
410  .dwell_time_passive = 100000,
411  .dwell_time_dfs = 150000,
412  .num_probe_reqs = 2,
413  .rssi_threshold = -90,
414  .snr_threshold = 0,
415  },
416  .ht = {
417  .rx_ba_win_size = 32,
418  .tx_ba_win_size = 64,
419  .inactivity_timeout = 10000,
420  .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
421  },
422  .mem = {
423  .num_stations = 1,
424  .ssid_profiles = 1,
425  .rx_block_num = 40,
426  .tx_min_block_num = 40,
427  .dynamic_memory = 1,
428  .min_req_tx_blocks = 45,
429  .min_req_rx_blocks = 22,
430  .tx_min = 27,
431  },
432  .fm_coex = {
433  .enable = true,
434  .swallow_period = 5,
435  .n_divider_fref_set_1 = 0xff, /* default */
436  .n_divider_fref_set_2 = 12,
437  .m_divider_fref_set_1 = 0xffff,
438  .m_divider_fref_set_2 = 148, /* default */
439  .coex_pll_stabilization_time = 0xffffffff, /* default */
440  .ldo_stabilization_time = 0xffff, /* default */
441  .fm_disturbed_band_margin = 0xff, /* default */
442  .swallow_clk_diff = 0xff, /* default */
443  },
444  .rx_streaming = {
445  .duration = 150,
446  .queues = 0x1,
447  .interval = 20,
448  .always = 0,
449  },
450  .fwlog = {
451  .mode = WL12XX_FWLOG_ON_DEMAND,
452  .mem_blocks = 2,
453  .severity = 0,
454  .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
455  .output = WL12XX_FWLOG_OUTPUT_HOST,
456  .threshold = 0,
457  },
458  .rate = {
459  .rate_retry_score = 32000,
460  .per_add = 8192,
461  .per_th1 = 2048,
462  .per_th2 = 4096,
463  .max_per = 8100,
464  .inverse_curiosity_factor = 5,
465  .tx_fail_low_th = 4,
466  .tx_fail_high_th = 10,
467  .per_alpha_shift = 4,
468  .per_add_shift = 13,
469  .per_beta1_shift = 10,
470  .per_beta2_shift = 8,
471  .rate_check_up = 2,
472  .rate_check_down = 12,
473  .rate_retry_policy = {
474  0x00, 0x00, 0x00, 0x00, 0x00,
475  0x00, 0x00, 0x00, 0x00, 0x00,
476  0x00, 0x00, 0x00,
477  },
478  },
479  .hangover = {
480  .recover_time = 0,
481  .hangover_period = 20,
482  .dynamic_mode = 1,
483  .early_termination_mode = 1,
484  .max_period = 20,
485  .min_period = 1,
486  .increase_delta = 1,
487  .decrease_delta = 2,
488  .quiet_time = 4,
489  .increase_time = 1,
490  .window_size = 16,
491  },
492 };
493 
494 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
495  .ht = {
496  .mode = HT_MODE_DEFAULT,
497  },
498  .phy = {
499  .phy_standalone = 0x00,
500  .primary_clock_setting_time = 0x05,
501  .clock_valid_on_wake_up = 0x00,
502  .secondary_clock_setting_time = 0x05,
503  .board_type = BOARD_TYPE_HDK_18XX,
504  .rdl = 0x01,
505  .auto_detect = 0x00,
506  .dedicated_fem = FEM_NONE,
507  .low_band_component = COMPONENT_3_WAY_SWITCH,
508  .low_band_component_type = 0x04,
509  .high_band_component = COMPONENT_2_WAY_SWITCH,
510  .high_band_component_type = 0x09,
511  .tcxo_ldo_voltage = 0x00,
512  .xtal_itrim_val = 0x04,
513  .srf_state = 0x00,
514  .io_configuration = 0x01,
515  .sdio_configuration = 0x00,
516  .settings = 0x00,
517  .enable_clpc = 0x00,
518  .enable_tx_low_pwr_on_siso_rdl = 0x00,
519  .rx_profile = 0x00,
520  .pwr_limit_reference_11_abg = 0xc8,
521  .psat = 0,
522  .low_power_val = 0x00,
523  .med_power_val = 0x0a,
524  .high_power_val = 0x1e,
525  .external_pa_dc2dc = 0,
526  .number_of_assembled_ant2_4 = 1,
527  .number_of_assembled_ant5 = 1,
528  },
529 };
530 
531 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
532  [PART_TOP_PRCM_ELP_SOC] = {
533  .mem = { .start = 0x00A02000, .size = 0x00010000 },
534  .reg = { .start = 0x00807000, .size = 0x00005000 },
535  .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
536  .mem3 = { .start = 0x00000000, .size = 0x00000000 },
537  },
538  [PART_DOWN] = {
539  .mem = { .start = 0x00000000, .size = 0x00014000 },
540  .reg = { .start = 0x00810000, .size = 0x0000BFFF },
541  .mem2 = { .start = 0x00000000, .size = 0x00000000 },
542  .mem3 = { .start = 0x00000000, .size = 0x00000000 },
543  },
544  [PART_BOOT] = {
545  .mem = { .start = 0x00700000, .size = 0x0000030c },
546  .reg = { .start = 0x00802000, .size = 0x00014578 },
547  .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
548  .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
549  },
550  [PART_WORK] = {
551  .mem = { .start = 0x00800000, .size = 0x000050FC },
552  .reg = { .start = 0x00B00404, .size = 0x00001000 },
553  .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
554  .mem3 = { .start = 0x00000000, .size = 0x00000000 },
555  },
556  [PART_PHY_INIT] = {
557  .mem = { .start = 0x80926000,
558  .size = sizeof(struct wl18xx_mac_and_phy_params) },
559  .reg = { .start = 0x00000000, .size = 0x00000000 },
560  .mem2 = { .start = 0x00000000, .size = 0x00000000 },
561  .mem3 = { .start = 0x00000000, .size = 0x00000000 },
562  },
563 };
564 
565 static const int wl18xx_rtable[REG_TABLE_LEN] = {
566  [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
567  [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
568  [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
569  [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
570  [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
571  [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
572  [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
573  [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
574  [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
575  [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
576 
577  /* data access memory addresses, used with partition translation */
578  [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
579  [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
580 
581  /* raw data access memory addresses */
582  [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
583 };
584 
585 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
586  [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
587  [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
588  [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
589  [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
590  [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
591  [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
592  [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
593  [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
594  [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
595 };
596 
597 /* TODO: maybe move to a new header file? */
598 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
599 
600 static int wl18xx_identify_chip(struct wl1271 *wl)
601 {
602  int ret = 0;
603 
604  switch (wl->chip.id) {
605  case CHIP_ID_185x_PG20:
606  wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
607  wl->chip.id);
608  wl->sr_fw_name = WL18XX_FW_NAME;
609  /* wl18xx uses the same firmware for PLT */
610  wl->plt_fw_name = WL18XX_FW_NAME;
611  wl->quirks |= WLCORE_QUIRK_NO_ELP |
612  WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
613  WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
614  WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN |
615  WLCORE_QUIRK_TX_PAD_LAST_FRAME;
616 
617  wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER, WL18XX_IFTYPE_VER,
618  WL18XX_MAJOR_VER, WL18XX_SUBTYPE_VER,
619  WL18XX_MINOR_VER);
620  break;
621  case CHIP_ID_185x_PG10:
622  wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
623  wl->chip.id);
624  ret = -ENODEV;
625  goto out;
626 
627  default:
628  wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
629  ret = -ENODEV;
630  goto out;
631  }
632 
633 out:
634  return ret;
635 }
636 
637 static int wl18xx_set_clk(struct wl1271 *wl)
638 {
639  u16 clk_freq;
640  int ret;
641 
642  ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
643  if (ret < 0)
644  goto out;
645 
646  /* TODO: PG2: apparently we need to read the clk type */
647 
648  ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
649  if (ret < 0)
650  goto out;
651 
652  wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
653  wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
654  wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
655  wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
656 
657  ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
658  wl18xx_clk_table[clk_freq].n);
659  if (ret < 0)
660  goto out;
661 
662  ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
663  wl18xx_clk_table[clk_freq].m);
664  if (ret < 0)
665  goto out;
666 
667  if (wl18xx_clk_table[clk_freq].swallow) {
668  /* first the 16 lower bits */
669  ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
670  wl18xx_clk_table[clk_freq].q &
671  PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
672  if (ret < 0)
673  goto out;
674 
675  /* then the 16 higher bits, masked out */
676  ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
677  (wl18xx_clk_table[clk_freq].q >> 16) &
678  PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
679  if (ret < 0)
680  goto out;
681 
682  /* first the 16 lower bits */
683  ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
684  wl18xx_clk_table[clk_freq].p &
685  PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
686  if (ret < 0)
687  goto out;
688 
689  /* then the 16 higher bits, masked out */
690  ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
691  (wl18xx_clk_table[clk_freq].p >> 16) &
692  PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
693  } else {
694  ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
695  PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
696  }
697 
698 out:
699  return ret;
700 }
701 
702 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
703 {
704  int ret;
705 
706  /* disable Rx/Tx */
707  ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
708  if (ret < 0)
709  goto out;
710 
711  /* disable auto calibration on start*/
712  ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
713 
714 out:
715  return ret;
716 }
717 
718 static int wl18xx_pre_boot(struct wl1271 *wl)
719 {
720  int ret;
721 
722  ret = wl18xx_set_clk(wl);
723  if (ret < 0)
724  goto out;
725 
726  /* Continue the ELP wake up sequence */
727  ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
728  if (ret < 0)
729  goto out;
730 
731  udelay(500);
732 
733  ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
734  if (ret < 0)
735  goto out;
736 
737  /* Disable interrupts */
738  ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
739  if (ret < 0)
740  goto out;
741 
742  ret = wl18xx_boot_soft_reset(wl);
743 
744 out:
745  return ret;
746 }
747 
748 static int wl18xx_pre_upload(struct wl1271 *wl)
749 {
750  u32 tmp;
751  int ret;
752 
753  ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
754  if (ret < 0)
755  goto out;
756 
757  /* TODO: check if this is all needed */
758  ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
759  if (ret < 0)
760  goto out;
761 
762  ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
763  if (ret < 0)
764  goto out;
765 
766  wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
767 
768  ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
769 
770 out:
771  return ret;
772 }
773 
774 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
775 {
776  struct wl18xx_priv *priv = wl->priv;
777  struct wl18xx_mac_and_phy_params *params;
778  int ret;
779 
780  params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL);
781  if (!params) {
782  ret = -ENOMEM;
783  goto out;
784  }
785 
786  ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
787  if (ret < 0)
788  goto out;
789 
790  ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
791  sizeof(*params), false);
792 
793 out:
794  kfree(params);
795  return ret;
796 }
797 
798 static int wl18xx_enable_interrupts(struct wl1271 *wl)
799 {
800  u32 event_mask, intr_mask;
801  int ret;
802 
803  event_mask = WL18XX_ACX_EVENTS_VECTOR;
804  intr_mask = WL18XX_INTR_MASK;
805 
806  ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
807  if (ret < 0)
808  goto out;
809 
810  wlcore_enable_interrupts(wl);
811 
812  ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
813  WL1271_ACX_INTR_ALL & ~intr_mask);
814  if (ret < 0)
815  goto disable_interrupts;
816 
817  return ret;
818 
819 disable_interrupts:
820  wlcore_disable_interrupts(wl);
821 
822 out:
823  return ret;
824 }
825 
826 static int wl18xx_boot(struct wl1271 *wl)
827 {
828  int ret;
829 
830  ret = wl18xx_pre_boot(wl);
831  if (ret < 0)
832  goto out;
833 
834  ret = wl18xx_pre_upload(wl);
835  if (ret < 0)
836  goto out;
837 
838  ret = wlcore_boot_upload_firmware(wl);
839  if (ret < 0)
840  goto out;
841 
842  ret = wl18xx_set_mac_and_phy(wl);
843  if (ret < 0)
844  goto out;
845 
846  ret = wlcore_boot_run_firmware(wl);
847  if (ret < 0)
848  goto out;
849 
850  ret = wl18xx_enable_interrupts(wl);
851 
852 out:
853  return ret;
854 }
855 
856 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
857  void *buf, size_t len)
858 {
859  struct wl18xx_priv *priv = wl->priv;
860 
861  memcpy(priv->cmd_buf, buf, len);
862  memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
863 
864  return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
865  WL18XX_CMD_MAX_SIZE, false);
866 }
867 
868 static int wl18xx_ack_event(struct wl1271 *wl)
869 {
870  return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
871  WL18XX_INTR_TRIG_EVENT_ACK);
872 }
873 
874 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
875 {
876  u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
877  return (len + blk_size - 1) / blk_size + spare_blks;
878 }
879 
880 static void
881 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
882  u32 blks, u32 spare_blks)
883 {
884  desc->wl18xx_mem.total_mem_blocks = blks;
885 }
886 
887 static void
888 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
889  struct sk_buff *skb)
890 {
891  desc->length = cpu_to_le16(skb->len);
892 
893  /* if only the last frame is to be padded, we unset this bit on Tx */
894  if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
895  desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
896  else
897  desc->wl18xx_mem.ctrl = 0;
898 
899  wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
900  "len: %d life: %d mem: %d", desc->hlid,
901  le16_to_cpu(desc->length),
902  le16_to_cpu(desc->life_time),
903  desc->wl18xx_mem.total_mem_blocks);
904 }
905 
906 static enum wl_rx_buf_align
907 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
908 {
909  if (rx_desc & RX_BUF_PADDED_PAYLOAD)
910  return WLCORE_RX_BUF_PADDED;
911 
912  return WLCORE_RX_BUF_ALIGNED;
913 }
914 
915 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
916  u32 data_len)
917 {
918  struct wl1271_rx_descriptor *desc = rx_data;
919 
920  /* invalid packet */
921  if (data_len < sizeof(*desc))
922  return 0;
923 
924  return data_len - sizeof(*desc);
925 }
926 
927 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
928 {
929  wl18xx_tx_immediate_complete(wl);
930 }
931 
932 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
933 {
934  int ret;
935  u32 sdio_align_size = 0;
936  u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
937  HOST_IF_CFG_ADD_RX_ALIGNMENT;
938 
939  /* Enable Tx SDIO padding */
940  if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
941  host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
942  sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
943  }
944 
945  /* Enable Rx SDIO padding */
946  if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
947  host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
948  sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
949  }
950 
951  ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
952  sdio_align_size, extra_mem_blk,
953  WL18XX_HOST_IF_LEN_SIZE_FIELD);
954  if (ret < 0)
955  return ret;
956 
957  return 0;
958 }
959 
960 static int wl18xx_hw_init(struct wl1271 *wl)
961 {
962  int ret;
963  struct wl18xx_priv *priv = wl->priv;
964 
965  /* (re)init private structures. Relevant on recovery as well. */
966  priv->last_fw_rls_idx = 0;
967  priv->extra_spare_vif_count = 0;
968 
969  /* set the default amount of spare blocks in the bitmap */
970  ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
971  if (ret < 0)
972  return ret;
973 
974  if (checksum_param) {
975  ret = wl18xx_acx_set_checksum_state(wl);
976  if (ret != 0)
977  return ret;
978  }
979 
980  return ret;
981 }
982 
983 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
984  struct wl1271_tx_hw_descr *desc,
985  struct sk_buff *skb)
986 {
987  u32 ip_hdr_offset;
988  struct iphdr *ip_hdr;
989 
990  if (!checksum_param) {
991  desc->wl18xx_checksum_data = 0;
992  return;
993  }
994 
995  if (skb->ip_summed != CHECKSUM_PARTIAL) {
996  desc->wl18xx_checksum_data = 0;
997  return;
998  }
999 
1000  ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1001  if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1002  desc->wl18xx_checksum_data = 0;
1003  return;
1004  }
1005 
1006  desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1007 
1008  /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
1009  ip_hdr = (void *)skb_network_header(skb);
1010  desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1011 }
1012 
1013 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1014  struct wl1271_rx_descriptor *desc,
1015  struct sk_buff *skb)
1016 {
1017  if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1018  skb->ip_summed = CHECKSUM_UNNECESSARY;
1019 }
1020 
1021 static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1022 {
1023  struct wl18xx_priv *priv = wl->priv;
1024 
1025  return priv->conf.phy.number_of_assembled_ant2_4 >= 2;
1026 }
1027 
1028 /*
1029  * TODO: instead of having these two functions to get the rate mask,
1030  * we should modify the wlvif->rate_set instead
1031  */
1032 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1033  struct wl12xx_vif *wlvif)
1034 {
1035  u32 hw_rate_set = wlvif->rate_set;
1036 
1037  if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1038  wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1039  wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1040  hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1041 
1042  /* we don't support MIMO in wide-channel mode */
1043  hw_rate_set &= ~CONF_TX_MIMO_RATES;
1044  } else if (wl18xx_is_mimo_supported(wl)) {
1045  wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask");
1046  hw_rate_set |= CONF_TX_MIMO_RATES;
1047  }
1048 
1049  return hw_rate_set;
1050 }
1051 
1052 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1053  struct wl12xx_vif *wlvif)
1054 {
1055  if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1056  wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1057  wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1058 
1059  /* sanity check - we don't support this */
1060  if (WARN_ON(wlvif->band != IEEE80211_BAND_5GHZ))
1061  return 0;
1062 
1063  return CONF_TX_RATE_USE_WIDE_CHAN;
1064  } else if (wl18xx_is_mimo_supported(wl) &&
1065  wlvif->band == IEEE80211_BAND_2GHZ) {
1066  wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1067  /*
1068  * we don't care about HT channel here - if a peer doesn't
1069  * support MIMO, we won't enable it in its rates
1070  */
1071  return CONF_TX_MIMO_RATES;
1072  } else {
1073  return 0;
1074  }
1075 }
1076 
1077 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1078 {
1079  u32 fuse;
1080  int ret;
1081 
1082  ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1083  if (ret < 0)
1084  goto out;
1085 
1086  ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1087  if (ret < 0)
1088  goto out;
1089 
1090  if (ver)
1091  *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1092 
1093  ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1094 
1095 out:
1096  return ret;
1097 }
1098 
1099 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
1100 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1101 {
1102  struct wl18xx_priv *priv = wl->priv;
1103  struct wlcore_conf_file *conf_file;
1104  const struct firmware *fw;
1105  int ret;
1106 
1107  ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1108  if (ret < 0) {
1109  wl1271_error("could not get configuration binary %s: %d",
1110  WL18XX_CONF_FILE_NAME, ret);
1111  goto out_fallback;
1112  }
1113 
1114  if (fw->size != WL18XX_CONF_SIZE) {
1115  wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1116  WL18XX_CONF_SIZE, fw->size);
1117  ret = -EINVAL;
1118  goto out;
1119  }
1120 
1121  conf_file = (struct wlcore_conf_file *) fw->data;
1122 
1123  if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1124  wl1271_error("configuration binary file magic number mismatch, "
1125  "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1126  conf_file->header.magic);
1127  ret = -EINVAL;
1128  goto out;
1129  }
1130 
1131  if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1132  wl1271_error("configuration binary file version not supported, "
1133  "expected 0x%08x got 0x%08x",
1134  WL18XX_CONF_VERSION, conf_file->header.version);
1135  ret = -EINVAL;
1136  goto out;
1137  }
1138 
1139  memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf));
1140  memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf));
1141 
1142  goto out;
1143 
1144 out_fallback:
1145  wl1271_warning("falling back to default config");
1146 
1147  /* apply driver default configuration */
1148  memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
1149  /* apply default private configuration */
1150  memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
1151 
1152  /* For now we just fallback */
1153  return 0;
1154 
1155 out:
1156  release_firmware(fw);
1157  return ret;
1158 }
1159 
1160 static int wl18xx_plt_init(struct wl1271 *wl)
1161 {
1162  int ret;
1163 
1164  /* calibrator based auto/fem detect not supported for 18xx */
1165  if (wl->plt_mode == PLT_FEM_DETECT) {
1166  wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported");
1167  return -EINVAL;
1168  }
1169 
1170  ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1171  if (ret < 0)
1172  return ret;
1173 
1174  return wl->ops->boot(wl);
1175 }
1176 
1177 static int wl18xx_get_mac(struct wl1271 *wl)
1178 {
1179  u32 mac1, mac2;
1180  int ret;
1181 
1182  ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1183  if (ret < 0)
1184  goto out;
1185 
1186  ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1187  if (ret < 0)
1188  goto out;
1189 
1190  ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1191  if (ret < 0)
1192  goto out;
1193 
1194  /* these are the two parts of the BD_ADDR */
1195  wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1196  ((mac1 & 0xff000000) >> 24);
1197  wl->fuse_nic_addr = (mac1 & 0xffffff);
1198 
1199  ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1200 
1201 out:
1202  return ret;
1203 }
1204 
1205 static int wl18xx_handle_static_data(struct wl1271 *wl,
1206  struct wl1271_static_data *static_data)
1207 {
1208  struct wl18xx_static_data_priv *static_data_priv =
1209  (struct wl18xx_static_data_priv *) static_data->priv;
1210 
1211  strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1212  sizeof(wl->chip.phy_fw_ver_str));
1213 
1214  /* make sure the string is NULL-terminated */
1215  wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0';
1216 
1217  wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1218 
1219  return 0;
1220 }
1221 
1222 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1223 {
1224  struct wl18xx_priv *priv = wl->priv;
1225 
1226  /* If we have VIFs requiring extra spare, indulge them */
1227  if (priv->extra_spare_vif_count)
1228  return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1229 
1230  return WL18XX_TX_HW_BLOCK_SPARE;
1231 }
1232 
1233 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1234  struct ieee80211_vif *vif,
1235  struct ieee80211_sta *sta,
1236  struct ieee80211_key_conf *key_conf)
1237 {
1238  struct wl18xx_priv *priv = wl->priv;
1239  bool change_spare = false;
1240  int ret;
1241 
1242  /*
1243  * when adding the first or removing the last GEM/TKIP interface,
1244  * we have to adjust the number of spare blocks.
1245  */
1246  change_spare = (key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1247  key_conf->cipher == WLAN_CIPHER_SUITE_TKIP) &&
1248  ((priv->extra_spare_vif_count == 0 && cmd == SET_KEY) ||
1249  (priv->extra_spare_vif_count == 1 && cmd == DISABLE_KEY));
1250 
1251  /* no need to change spare - just regular set_key */
1252  if (!change_spare)
1253  return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1254 
1255  ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1256  if (ret < 0)
1257  goto out;
1258 
1259  /* key is now set, change the spare blocks */
1260  if (cmd == SET_KEY) {
1261  ret = wl18xx_set_host_cfg_bitmap(wl,
1262  WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1263  if (ret < 0)
1264  goto out;
1265 
1266  priv->extra_spare_vif_count++;
1267  } else {
1268  ret = wl18xx_set_host_cfg_bitmap(wl,
1269  WL18XX_TX_HW_BLOCK_SPARE);
1270  if (ret < 0)
1271  goto out;
1272 
1273  priv->extra_spare_vif_count--;
1274  }
1275 
1276 out:
1277  return ret;
1278 }
1279 
1280 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1281  u32 buf_offset, u32 last_len)
1282 {
1283  if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1284  struct wl1271_tx_hw_descr *last_desc;
1285 
1286  /* get the last TX HW descriptor written to the aggr buf */
1287  last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1288  buf_offset - last_len);
1289 
1290  /* the last frame is padded up to an SDIO block */
1291  last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1292  return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1293  }
1294 
1295  /* no modifications */
1296  return buf_offset;
1297 }
1298 
1299 static int wl18xx_setup(struct wl1271 *wl);
1300 
1301 static struct wlcore_ops wl18xx_ops = {
1302  .setup = wl18xx_setup,
1303  .identify_chip = wl18xx_identify_chip,
1304  .boot = wl18xx_boot,
1305  .plt_init = wl18xx_plt_init,
1306  .trigger_cmd = wl18xx_trigger_cmd,
1307  .ack_event = wl18xx_ack_event,
1308  .calc_tx_blocks = wl18xx_calc_tx_blocks,
1309  .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1310  .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1311  .get_rx_buf_align = wl18xx_get_rx_buf_align,
1312  .get_rx_packet_len = wl18xx_get_rx_packet_len,
1313  .tx_immediate_compl = wl18xx_tx_immediate_completion,
1314  .tx_delayed_compl = NULL,
1315  .hw_init = wl18xx_hw_init,
1316  .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1317  .get_pg_ver = wl18xx_get_pg_ver,
1318  .set_rx_csum = wl18xx_set_rx_csum,
1319  .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1320  .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1321  .get_mac = wl18xx_get_mac,
1322  .debugfs_init = wl18xx_debugfs_add_files,
1323  .handle_static_data = wl18xx_handle_static_data,
1324  .get_spare_blocks = wl18xx_get_spare_blocks,
1325  .set_key = wl18xx_set_key,
1326  .pre_pkt_send = wl18xx_pre_pkt_send,
1327 };
1328 
1329 /* HT cap appropriate for wide channels in 2Ghz */
1330 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1331  .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1332  IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
1333  .ht_supported = true,
1334  .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1335  .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1336  .mcs = {
1337  .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1338  .rx_highest = cpu_to_le16(150),
1339  .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1340  },
1341 };
1342 
1343 /* HT cap appropriate for wide channels in 5Ghz */
1344 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1345  .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1346  IEEE80211_HT_CAP_SUP_WIDTH_20_40,
1347  .ht_supported = true,
1348  .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1349  .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1350  .mcs = {
1351  .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1352  .rx_highest = cpu_to_le16(150),
1353  .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1354  },
1355 };
1356 
1357 /* HT cap appropriate for SISO 20 */
1358 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1359  .cap = IEEE80211_HT_CAP_SGI_20,
1360  .ht_supported = true,
1361  .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1362  .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1363  .mcs = {
1364  .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1365  .rx_highest = cpu_to_le16(72),
1366  .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1367  },
1368 };
1369 
1370 /* HT cap appropriate for MIMO rates in 20mhz channel */
1371 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1372  .cap = IEEE80211_HT_CAP_SGI_20,
1373  .ht_supported = true,
1374  .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1375  .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1376  .mcs = {
1377  .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1378  .rx_highest = cpu_to_le16(144),
1379  .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1380  },
1381 };
1382 
1383 static int wl18xx_setup(struct wl1271 *wl)
1384 {
1385  struct wl18xx_priv *priv = wl->priv;
1386  int ret;
1387 
1388  wl->rtable = wl18xx_rtable;
1389  wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1390  wl->num_rx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1391  wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
1392  wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1393  wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1394  wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1395  wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1396  wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1397  wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1398 
1399  if (num_rx_desc_param != -1)
1400  wl->num_rx_desc = num_rx_desc_param;
1401 
1402  ret = wl18xx_conf_init(wl, wl->dev);
1403  if (ret < 0)
1404  return ret;
1405 
1406  /* If the module param is set, update it in conf */
1407  if (board_type_param) {
1408  if (!strcmp(board_type_param, "fpga")) {
1409  priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1410  } else if (!strcmp(board_type_param, "hdk")) {
1411  priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1412  } else if (!strcmp(board_type_param, "dvp")) {
1413  priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1414  } else if (!strcmp(board_type_param, "evb")) {
1415  priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1416  } else if (!strcmp(board_type_param, "com8")) {
1417  priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1418  } else {
1419  wl1271_error("invalid board type '%s'",
1420  board_type_param);
1421  return -EINVAL;
1422  }
1423  }
1424 
1425  if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) {
1426  wl1271_error("invalid board type '%d'",
1427  priv->conf.phy.board_type);
1428  return -EINVAL;
1429  }
1430 
1431  if (low_band_component_param != -1)
1432  priv->conf.phy.low_band_component = low_band_component_param;
1433  if (low_band_component_type_param != -1)
1434  priv->conf.phy.low_band_component_type =
1435  low_band_component_type_param;
1436  if (high_band_component_param != -1)
1437  priv->conf.phy.high_band_component = high_band_component_param;
1438  if (high_band_component_type_param != -1)
1439  priv->conf.phy.high_band_component_type =
1440  high_band_component_type_param;
1441  if (pwr_limit_reference_11_abg_param != -1)
1442  priv->conf.phy.pwr_limit_reference_11_abg =
1443  pwr_limit_reference_11_abg_param;
1444  if (n_antennas_2_param != -1)
1445  priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1446  if (n_antennas_5_param != -1)
1447  priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1448  if (dc2dc_param != -1)
1449  priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1450 
1451  if (ht_mode_param) {
1452  if (!strcmp(ht_mode_param, "default"))
1453  priv->conf.ht.mode = HT_MODE_DEFAULT;
1454  else if (!strcmp(ht_mode_param, "wide"))
1455  priv->conf.ht.mode = HT_MODE_WIDE;
1456  else if (!strcmp(ht_mode_param, "siso20"))
1457  priv->conf.ht.mode = HT_MODE_SISO20;
1458  else {
1459  wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1460  return -EINVAL;
1461  }
1462  }
1463 
1464  if (priv->conf.ht.mode == HT_MODE_DEFAULT) {
1465  /*
1466  * Only support mimo with multiple antennas. Fall back to
1467  * siso40.
1468  */
1469  if (wl18xx_is_mimo_supported(wl))
1470  wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1471  &wl18xx_mimo_ht_cap_2ghz);
1472  else
1473  wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1474  &wl18xx_siso40_ht_cap_2ghz);
1475 
1476  /* 5Ghz is always wide */
1477  wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1478  &wl18xx_siso40_ht_cap_5ghz);
1479  } else if (priv->conf.ht.mode == HT_MODE_WIDE) {
1480  wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1481  &wl18xx_siso40_ht_cap_2ghz);
1482  wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1483  &wl18xx_siso40_ht_cap_5ghz);
1484  } else if (priv->conf.ht.mode == HT_MODE_SISO20) {
1485  wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1486  &wl18xx_siso20_ht_cap);
1487  wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1488  &wl18xx_siso20_ht_cap);
1489  }
1490 
1491  if (!checksum_param) {
1492  wl18xx_ops.set_rx_csum = NULL;
1493  wl18xx_ops.init_vif = NULL;
1494  }
1495 
1496  /* Enable 11a Band only if we have 5G antennas */
1497  wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
1498 
1499  return 0;
1500 }
1501 
1502 static int __devinit wl18xx_probe(struct platform_device *pdev)
1503 {
1504  struct wl1271 *wl;
1505  struct ieee80211_hw *hw;
1506  int ret;
1507 
1508  hw = wlcore_alloc_hw(sizeof(struct wl18xx_priv),
1509  WL18XX_AGGR_BUFFER_SIZE);
1510  if (IS_ERR(hw)) {
1511  wl1271_error("can't allocate hw");
1512  ret = PTR_ERR(hw);
1513  goto out;
1514  }
1515 
1516  wl = hw->priv;
1517  wl->ops = &wl18xx_ops;
1518  wl->ptable = wl18xx_ptable;
1519  ret = wlcore_probe(wl, pdev);
1520  if (ret)
1521  goto out_free;
1522 
1523  return ret;
1524 
1525 out_free:
1526  wlcore_free_hw(wl);
1527 out:
1528  return ret;
1529 }
1530 
1531 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1532  { "wl18xx", 0 },
1533  { } /* Terminating Entry */
1534 };
1535 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1536 
1537 static struct platform_driver wl18xx_driver = {
1538  .probe = wl18xx_probe,
1539  .remove = __devexit_p(wlcore_remove),
1540  .id_table = wl18xx_id_table,
1541  .driver = {
1542  .name = "wl18xx_driver",
1543  .owner = THIS_MODULE,
1544  }
1545 };
1546 
1547 module_platform_driver(wl18xx_driver);
1548 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1549 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
1550 
1551 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1552 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1553  "dvp");
1554 
1555 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1556 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
1557 
1558 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
1559 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
1560 
1561 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
1562 MODULE_PARM_DESC(n_antennas_2,
1563  "Number of installed 2.4GHz antennas: 1 (default) or 2");
1564 
1565 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
1566 MODULE_PARM_DESC(n_antennas_5,
1567  "Number of installed 5GHz antennas: 1 (default) or 2");
1568 
1569 module_param_named(low_band_component, low_band_component_param, int,
1570  S_IRUSR);
1571 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1572  "(default is 0x01)");
1573 
1574 module_param_named(low_band_component_type, low_band_component_type_param,
1575  int, S_IRUSR);
1576 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1577  "(default is 0x05 or 0x06 depending on the board_type)");
1578 
1579 module_param_named(high_band_component, high_band_component_param, int,
1580  S_IRUSR);
1581 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1582  "(default is 0x01)");
1583 
1584 module_param_named(high_band_component_type, high_band_component_type_param,
1585  int, S_IRUSR);
1586 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1587  "(default is 0x09)");
1588 
1589 module_param_named(pwr_limit_reference_11_abg,
1590  pwr_limit_reference_11_abg_param, int, S_IRUSR);
1591 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1592  "(default is 0xc8)");
1593 
1594 module_param_named(num_rx_desc,
1595  num_rx_desc_param, int, S_IRUSR);
1596 MODULE_PARM_DESC(num_rx_desc_param,
1597  "Number of Rx descriptors: u8 (default is 32)");
1598 
1599 MODULE_LICENSE("GPL v2");
1600 MODULE_AUTHOR("Luciano Coelho <[email protected]>");
1601 MODULE_FIRMWARE(WL18XX_FW_NAME);
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