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evergreen.c
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1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <drm/drmP.h>
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include <drm/radeon_drm.h>
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36 
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39 
40 static const u32 crtc_offsets[6] =
41 {
42  EVERGREEN_CRTC0_REGISTER_OFFSET,
43  EVERGREEN_CRTC1_REGISTER_OFFSET,
44  EVERGREEN_CRTC2_REGISTER_OFFSET,
45  EVERGREEN_CRTC3_REGISTER_OFFSET,
46  EVERGREEN_CRTC4_REGISTER_OFFSET,
47  EVERGREEN_CRTC5_REGISTER_OFFSET
48 };
49 
50 static void evergreen_gpu_init(struct radeon_device *rdev);
51 void evergreen_fini(struct radeon_device *rdev);
52 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
53 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54  int ring, u32 cp_int_cntl);
55 
56 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57  unsigned *bankh, unsigned *mtaspect,
58  unsigned *tile_split)
59 {
60  *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
61  *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
62  *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
63  *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
64  switch (*bankw) {
65  default:
66  case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
67  case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
68  case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
69  case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
70  }
71  switch (*bankh) {
72  default:
73  case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
74  case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
75  case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
76  case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
77  }
78  switch (*mtaspect) {
79  default:
80  case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
81  case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
82  case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
83  case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
84  }
85 }
86 
87 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
88 {
89  u16 ctl, v;
90  int err;
91 
92  err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
93  if (err)
94  return;
95 
96  v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
97 
98  /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
99  * to avoid hangs or perfomance issues
100  */
101  if ((v == 0) || (v == 6) || (v == 7)) {
102  ctl &= ~PCI_EXP_DEVCTL_READRQ;
103  ctl |= (2 << 12);
104  pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
105  }
106 }
107 
116 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
117 {
118  int i;
119 
120  if (crtc >= rdev->num_crtc)
121  return;
122 
123  if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
124  for (i = 0; i < rdev->usec_timeout; i++) {
125  if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
126  break;
127  udelay(1);
128  }
129  for (i = 0; i < rdev->usec_timeout; i++) {
130  if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
131  break;
132  udelay(1);
133  }
134  }
135 }
136 
146 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
147 {
148  /* enable the pflip int */
149  radeon_irq_kms_pflip_irq_get(rdev, crtc);
150 }
151 
161 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
162 {
163  /* disable the pflip int */
164  radeon_irq_kms_pflip_irq_put(rdev, crtc);
165 }
166 
180 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
181 {
182  struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
183  u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
184  int i;
185 
186  /* Lock the graphics update lock */
187  tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
188  WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
189 
190  /* update the scanout addresses */
191  WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
192  upper_32_bits(crtc_base));
193  WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
194  (u32)crtc_base);
195 
196  WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
197  upper_32_bits(crtc_base));
198  WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
199  (u32)crtc_base);
200 
201  /* Wait for update_pending to go high. */
202  for (i = 0; i < rdev->usec_timeout; i++) {
203  if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
204  break;
205  udelay(1);
206  }
207  DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
208 
209  /* Unlock the lock, so double-buffering can take place inside vblank */
210  tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
211  WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
212 
213  /* Return current update_pending status: */
214  return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
215 }
216 
217 /* get temperature in millidegrees */
218 int evergreen_get_temp(struct radeon_device *rdev)
219 {
220  u32 temp, toffset;
221  int actual_temp = 0;
222 
223  if (rdev->family == CHIP_JUNIPER) {
224  toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
225  TOFFSET_SHIFT;
226  temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
227  TS0_ADC_DOUT_SHIFT;
228 
229  if (toffset & 0x100)
230  actual_temp = temp / 2 - (0x200 - toffset);
231  else
232  actual_temp = temp / 2 + toffset;
233 
234  actual_temp = actual_temp * 1000;
235 
236  } else {
237  temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
238  ASIC_T_SHIFT;
239 
240  if (temp & 0x400)
241  actual_temp = -256;
242  else if (temp & 0x200)
243  actual_temp = 255;
244  else if (temp & 0x100) {
245  actual_temp = temp & 0x1ff;
246  actual_temp |= ~0x1ff;
247  } else
248  actual_temp = temp & 0xff;
249 
250  actual_temp = (actual_temp * 1000) / 2;
251  }
252 
253  return actual_temp;
254 }
255 
256 int sumo_get_temp(struct radeon_device *rdev)
257 {
258  u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
259  int actual_temp = temp - 49;
260 
261  return actual_temp * 1000;
262 }
263 
273 void sumo_pm_init_profile(struct radeon_device *rdev)
274 {
275  int idx;
276 
277  /* default */
278  rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
279  rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
280  rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
281  rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
282 
283  /* low,mid sh/mh */
284  if (rdev->flags & RADEON_IS_MOBILITY)
285  idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
286  else
287  idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
288 
289  rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
290  rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
291  rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
292  rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
293 
294  rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
295  rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
296  rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
297  rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
298 
299  rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
300  rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
301  rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
302  rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
303 
304  rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
305  rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
306  rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
307  rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
308 
309  /* high sh/mh */
310  idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
311  rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
312  rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
313  rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314  rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
315  rdev->pm.power_state[idx].num_clock_modes - 1;
316 
317  rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
318  rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
319  rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
320  rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
321  rdev->pm.power_state[idx].num_clock_modes - 1;
322 }
323 
333 void btc_pm_init_profile(struct radeon_device *rdev)
334 {
335  int idx;
336 
337  /* default */
338  rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
339  rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
340  rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
341  rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
342  /* starting with BTC, there is one state that is used for both
343  * MH and SH. Difference is that we always use the high clock index for
344  * mclk.
345  */
346  if (rdev->flags & RADEON_IS_MOBILITY)
347  idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
348  else
349  idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
350  /* low sh */
351  rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
352  rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
353  rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
354  rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
355  /* mid sh */
356  rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
357  rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
358  rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
359  rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
360  /* high sh */
361  rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
362  rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
363  rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
364  rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
365  /* low mh */
366  rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
367  rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
368  rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
369  rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
370  /* mid mh */
371  rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
372  rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
373  rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
374  rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
375  /* high mh */
376  rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
377  rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
378  rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
379  rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
380 }
381 
390 void evergreen_pm_misc(struct radeon_device *rdev)
391 {
392  int req_ps_idx = rdev->pm.requested_power_state_index;
393  int req_cm_idx = rdev->pm.requested_clock_mode_index;
394  struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
395  struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
396 
397  if (voltage->type == VOLTAGE_SW) {
398  /* 0xff01 is a flag rather then an actual voltage */
399  if (voltage->voltage == 0xff01)
400  return;
401  if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
402  radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
403  rdev->pm.current_vddc = voltage->voltage;
404  DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
405  }
406  /* 0xff01 is a flag rather then an actual voltage */
407  if (voltage->vddci == 0xff01)
408  return;
409  if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
410  radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
411  rdev->pm.current_vddci = voltage->vddci;
412  DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
413  }
414  }
415 }
416 
424 void evergreen_pm_prepare(struct radeon_device *rdev)
425 {
426  struct drm_device *ddev = rdev->ddev;
427  struct drm_crtc *crtc;
428  struct radeon_crtc *radeon_crtc;
429  u32 tmp;
430 
431  /* disable any active CRTCs */
432  list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
433  radeon_crtc = to_radeon_crtc(crtc);
434  if (radeon_crtc->enabled) {
435  tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
436  tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
437  WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
438  }
439  }
440 }
441 
449 void evergreen_pm_finish(struct radeon_device *rdev)
450 {
451  struct drm_device *ddev = rdev->ddev;
452  struct drm_crtc *crtc;
453  struct radeon_crtc *radeon_crtc;
454  u32 tmp;
455 
456  /* enable any active CRTCs */
457  list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
458  radeon_crtc = to_radeon_crtc(crtc);
459  if (radeon_crtc->enabled) {
460  tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
461  tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
462  WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
463  }
464  }
465 }
466 
476 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
477 {
478  bool connected = false;
479 
480  switch (hpd) {
481  case RADEON_HPD_1:
482  if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
483  connected = true;
484  break;
485  case RADEON_HPD_2:
486  if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
487  connected = true;
488  break;
489  case RADEON_HPD_3:
490  if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
491  connected = true;
492  break;
493  case RADEON_HPD_4:
494  if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
495  connected = true;
496  break;
497  case RADEON_HPD_5:
498  if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
499  connected = true;
500  break;
501  case RADEON_HPD_6:
502  if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
503  connected = true;
504  break;
505  default:
506  break;
507  }
508 
509  return connected;
510 }
511 
520 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
521  enum radeon_hpd_id hpd)
522 {
523  u32 tmp;
524  bool connected = evergreen_hpd_sense(rdev, hpd);
525 
526  switch (hpd) {
527  case RADEON_HPD_1:
528  tmp = RREG32(DC_HPD1_INT_CONTROL);
529  if (connected)
530  tmp &= ~DC_HPDx_INT_POLARITY;
531  else
532  tmp |= DC_HPDx_INT_POLARITY;
533  WREG32(DC_HPD1_INT_CONTROL, tmp);
534  break;
535  case RADEON_HPD_2:
536  tmp = RREG32(DC_HPD2_INT_CONTROL);
537  if (connected)
538  tmp &= ~DC_HPDx_INT_POLARITY;
539  else
540  tmp |= DC_HPDx_INT_POLARITY;
541  WREG32(DC_HPD2_INT_CONTROL, tmp);
542  break;
543  case RADEON_HPD_3:
544  tmp = RREG32(DC_HPD3_INT_CONTROL);
545  if (connected)
546  tmp &= ~DC_HPDx_INT_POLARITY;
547  else
548  tmp |= DC_HPDx_INT_POLARITY;
549  WREG32(DC_HPD3_INT_CONTROL, tmp);
550  break;
551  case RADEON_HPD_4:
552  tmp = RREG32(DC_HPD4_INT_CONTROL);
553  if (connected)
554  tmp &= ~DC_HPDx_INT_POLARITY;
555  else
556  tmp |= DC_HPDx_INT_POLARITY;
557  WREG32(DC_HPD4_INT_CONTROL, tmp);
558  break;
559  case RADEON_HPD_5:
560  tmp = RREG32(DC_HPD5_INT_CONTROL);
561  if (connected)
562  tmp &= ~DC_HPDx_INT_POLARITY;
563  else
564  tmp |= DC_HPDx_INT_POLARITY;
565  WREG32(DC_HPD5_INT_CONTROL, tmp);
566  break;
567  case RADEON_HPD_6:
568  tmp = RREG32(DC_HPD6_INT_CONTROL);
569  if (connected)
570  tmp &= ~DC_HPDx_INT_POLARITY;
571  else
572  tmp |= DC_HPDx_INT_POLARITY;
573  WREG32(DC_HPD6_INT_CONTROL, tmp);
574  break;
575  default:
576  break;
577  }
578 }
579 
588 void evergreen_hpd_init(struct radeon_device *rdev)
589 {
590  struct drm_device *dev = rdev->ddev;
591  struct drm_connector *connector;
592  unsigned enabled = 0;
593  u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
594  DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
595 
596  list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
597  struct radeon_connector *radeon_connector = to_radeon_connector(connector);
598  switch (radeon_connector->hpd.hpd) {
599  case RADEON_HPD_1:
600  WREG32(DC_HPD1_CONTROL, tmp);
601  break;
602  case RADEON_HPD_2:
603  WREG32(DC_HPD2_CONTROL, tmp);
604  break;
605  case RADEON_HPD_3:
606  WREG32(DC_HPD3_CONTROL, tmp);
607  break;
608  case RADEON_HPD_4:
609  WREG32(DC_HPD4_CONTROL, tmp);
610  break;
611  case RADEON_HPD_5:
612  WREG32(DC_HPD5_CONTROL, tmp);
613  break;
614  case RADEON_HPD_6:
615  WREG32(DC_HPD6_CONTROL, tmp);
616  break;
617  default:
618  break;
619  }
620  radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
621  enabled |= 1 << radeon_connector->hpd.hpd;
622  }
623  radeon_irq_kms_enable_hpd(rdev, enabled);
624 }
625 
634 void evergreen_hpd_fini(struct radeon_device *rdev)
635 {
636  struct drm_device *dev = rdev->ddev;
637  struct drm_connector *connector;
638  unsigned disabled = 0;
639 
640  list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
641  struct radeon_connector *radeon_connector = to_radeon_connector(connector);
642  switch (radeon_connector->hpd.hpd) {
643  case RADEON_HPD_1:
644  WREG32(DC_HPD1_CONTROL, 0);
645  break;
646  case RADEON_HPD_2:
647  WREG32(DC_HPD2_CONTROL, 0);
648  break;
649  case RADEON_HPD_3:
650  WREG32(DC_HPD3_CONTROL, 0);
651  break;
652  case RADEON_HPD_4:
653  WREG32(DC_HPD4_CONTROL, 0);
654  break;
655  case RADEON_HPD_5:
656  WREG32(DC_HPD5_CONTROL, 0);
657  break;
658  case RADEON_HPD_6:
659  WREG32(DC_HPD6_CONTROL, 0);
660  break;
661  default:
662  break;
663  }
664  disabled |= 1 << radeon_connector->hpd.hpd;
665  }
666  radeon_irq_kms_disable_hpd(rdev, disabled);
667 }
668 
669 /* watermark setup */
670 
671 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
672  struct radeon_crtc *radeon_crtc,
673  struct drm_display_mode *mode,
674  struct drm_display_mode *other_mode)
675 {
676  u32 tmp;
677  /*
678  * Line Buffer Setup
679  * There are 3 line buffers, each one shared by 2 display controllers.
680  * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
681  * the display controllers. The paritioning is done via one of four
682  * preset allocations specified in bits 2:0:
683  * first display controller
684  * 0 - first half of lb (3840 * 2)
685  * 1 - first 3/4 of lb (5760 * 2)
686  * 2 - whole lb (7680 * 2), other crtc must be disabled
687  * 3 - first 1/4 of lb (1920 * 2)
688  * second display controller
689  * 4 - second half of lb (3840 * 2)
690  * 5 - second 3/4 of lb (5760 * 2)
691  * 6 - whole lb (7680 * 2), other crtc must be disabled
692  * 7 - last 1/4 of lb (1920 * 2)
693  */
694  /* this can get tricky if we have two large displays on a paired group
695  * of crtcs. Ideally for multiple large displays we'd assign them to
696  * non-linked crtcs for maximum line buffer allocation.
697  */
698  if (radeon_crtc->base.enabled && mode) {
699  if (other_mode)
700  tmp = 0; /* 1/2 */
701  else
702  tmp = 2; /* whole */
703  } else
704  tmp = 0;
705 
706  /* second controller of the pair uses second half of the lb */
707  if (radeon_crtc->crtc_id % 2)
708  tmp += 4;
709  WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
710 
711  if (radeon_crtc->base.enabled && mode) {
712  switch (tmp) {
713  case 0:
714  case 4:
715  default:
716  if (ASIC_IS_DCE5(rdev))
717  return 4096 * 2;
718  else
719  return 3840 * 2;
720  case 1:
721  case 5:
722  if (ASIC_IS_DCE5(rdev))
723  return 6144 * 2;
724  else
725  return 5760 * 2;
726  case 2:
727  case 6:
728  if (ASIC_IS_DCE5(rdev))
729  return 8192 * 2;
730  else
731  return 7680 * 2;
732  case 3:
733  case 7:
734  if (ASIC_IS_DCE5(rdev))
735  return 2048 * 2;
736  else
737  return 1920 * 2;
738  }
739  }
740 
741  /* controller not enabled, so no lb used */
742  return 0;
743 }
744 
745 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
746 {
747  u32 tmp = RREG32(MC_SHARED_CHMAP);
748 
749  switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
750  case 0:
751  default:
752  return 1;
753  case 1:
754  return 2;
755  case 2:
756  return 4;
757  case 3:
758  return 8;
759  }
760 }
761 
762 struct evergreen_wm_params {
763  u32 dram_channels; /* number of dram channels */
764  u32 yclk; /* bandwidth per dram data pin in kHz */
765  u32 sclk; /* engine clock in kHz */
766  u32 disp_clk; /* display clock in kHz */
767  u32 src_width; /* viewport width */
768  u32 active_time; /* active display time in ns */
769  u32 blank_time; /* blank time in ns */
770  bool interlaced; /* mode is interlaced */
771  fixed20_12 vsc; /* vertical scale ratio */
772  u32 num_heads; /* number of active crtcs */
773  u32 bytes_per_pixel; /* bytes per pixel display + overlay */
774  u32 lb_size; /* line buffer allocated to pipe */
775  u32 vtaps; /* vertical scaler taps */
776 };
777 
778 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
779 {
780  /* Calculate DRAM Bandwidth and the part allocated to display. */
781  fixed20_12 dram_efficiency; /* 0.7 */
782  fixed20_12 yclk, dram_channels, bandwidth;
783  fixed20_12 a;
784 
785  a.full = dfixed_const(1000);
786  yclk.full = dfixed_const(wm->yclk);
787  yclk.full = dfixed_div(yclk, a);
788  dram_channels.full = dfixed_const(wm->dram_channels * 4);
789  a.full = dfixed_const(10);
790  dram_efficiency.full = dfixed_const(7);
791  dram_efficiency.full = dfixed_div(dram_efficiency, a);
792  bandwidth.full = dfixed_mul(dram_channels, yclk);
793  bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
794 
795  return dfixed_trunc(bandwidth);
796 }
797 
798 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
799 {
800  /* Calculate DRAM Bandwidth and the part allocated to display. */
801  fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
802  fixed20_12 yclk, dram_channels, bandwidth;
803  fixed20_12 a;
804 
805  a.full = dfixed_const(1000);
806  yclk.full = dfixed_const(wm->yclk);
807  yclk.full = dfixed_div(yclk, a);
808  dram_channels.full = dfixed_const(wm->dram_channels * 4);
809  a.full = dfixed_const(10);
810  disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
811  disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
812  bandwidth.full = dfixed_mul(dram_channels, yclk);
813  bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
814 
815  return dfixed_trunc(bandwidth);
816 }
817 
818 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
819 {
820  /* Calculate the display Data return Bandwidth */
821  fixed20_12 return_efficiency; /* 0.8 */
822  fixed20_12 sclk, bandwidth;
823  fixed20_12 a;
824 
825  a.full = dfixed_const(1000);
826  sclk.full = dfixed_const(wm->sclk);
827  sclk.full = dfixed_div(sclk, a);
828  a.full = dfixed_const(10);
829  return_efficiency.full = dfixed_const(8);
830  return_efficiency.full = dfixed_div(return_efficiency, a);
831  a.full = dfixed_const(32);
832  bandwidth.full = dfixed_mul(a, sclk);
833  bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
834 
835  return dfixed_trunc(bandwidth);
836 }
837 
838 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
839 {
840  /* Calculate the DMIF Request Bandwidth */
841  fixed20_12 disp_clk_request_efficiency; /* 0.8 */
842  fixed20_12 disp_clk, bandwidth;
843  fixed20_12 a;
844 
845  a.full = dfixed_const(1000);
846  disp_clk.full = dfixed_const(wm->disp_clk);
847  disp_clk.full = dfixed_div(disp_clk, a);
848  a.full = dfixed_const(10);
849  disp_clk_request_efficiency.full = dfixed_const(8);
850  disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
851  a.full = dfixed_const(32);
852  bandwidth.full = dfixed_mul(a, disp_clk);
853  bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
854 
855  return dfixed_trunc(bandwidth);
856 }
857 
858 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
859 {
860  /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
861  u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
862  u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
863  u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
864 
865  return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
866 }
867 
868 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
869 {
870  /* Calculate the display mode Average Bandwidth
871  * DisplayMode should contain the source and destination dimensions,
872  * timing, etc.
873  */
874  fixed20_12 bpp;
875  fixed20_12 line_time;
876  fixed20_12 src_width;
877  fixed20_12 bandwidth;
878  fixed20_12 a;
879 
880  a.full = dfixed_const(1000);
881  line_time.full = dfixed_const(wm->active_time + wm->blank_time);
882  line_time.full = dfixed_div(line_time, a);
883  bpp.full = dfixed_const(wm->bytes_per_pixel);
884  src_width.full = dfixed_const(wm->src_width);
885  bandwidth.full = dfixed_mul(src_width, bpp);
886  bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
887  bandwidth.full = dfixed_div(bandwidth, line_time);
888 
889  return dfixed_trunc(bandwidth);
890 }
891 
892 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
893 {
894  /* First calcualte the latency in ns */
895  u32 mc_latency = 2000; /* 2000 ns. */
896  u32 available_bandwidth = evergreen_available_bandwidth(wm);
897  u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
898  u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
899  u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
900  u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
901  (wm->num_heads * cursor_line_pair_return_time);
902  u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
903  u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
904  fixed20_12 a, b, c;
905 
906  if (wm->num_heads == 0)
907  return 0;
908 
909  a.full = dfixed_const(2);
910  b.full = dfixed_const(1);
911  if ((wm->vsc.full > a.full) ||
912  ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
913  (wm->vtaps >= 5) ||
914  ((wm->vsc.full >= a.full) && wm->interlaced))
915  max_src_lines_per_dst_line = 4;
916  else
917  max_src_lines_per_dst_line = 2;
918 
919  a.full = dfixed_const(available_bandwidth);
920  b.full = dfixed_const(wm->num_heads);
921  a.full = dfixed_div(a, b);
922 
923  b.full = dfixed_const(1000);
924  c.full = dfixed_const(wm->disp_clk);
925  b.full = dfixed_div(c, b);
926  c.full = dfixed_const(wm->bytes_per_pixel);
927  b.full = dfixed_mul(b, c);
928 
929  lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
930 
931  a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
932  b.full = dfixed_const(1000);
933  c.full = dfixed_const(lb_fill_bw);
934  b.full = dfixed_div(c, b);
935  a.full = dfixed_div(a, b);
936  line_fill_time = dfixed_trunc(a);
937 
938  if (line_fill_time < wm->active_time)
939  return latency;
940  else
941  return latency + (line_fill_time - wm->active_time);
942 
943 }
944 
945 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
946 {
947  if (evergreen_average_bandwidth(wm) <=
948  (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
949  return true;
950  else
951  return false;
952 };
953 
954 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
955 {
956  if (evergreen_average_bandwidth(wm) <=
957  (evergreen_available_bandwidth(wm) / wm->num_heads))
958  return true;
959  else
960  return false;
961 };
962 
963 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
964 {
965  u32 lb_partitions = wm->lb_size / wm->src_width;
966  u32 line_time = wm->active_time + wm->blank_time;
967  u32 latency_tolerant_lines;
968  u32 latency_hiding;
969  fixed20_12 a;
970 
971  a.full = dfixed_const(1);
972  if (wm->vsc.full > a.full)
973  latency_tolerant_lines = 1;
974  else {
975  if (lb_partitions <= (wm->vtaps + 1))
976  latency_tolerant_lines = 1;
977  else
978  latency_tolerant_lines = 2;
979  }
980 
981  latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
982 
983  if (evergreen_latency_watermark(wm) <= latency_hiding)
984  return true;
985  else
986  return false;
987 }
988 
989 static void evergreen_program_watermarks(struct radeon_device *rdev,
990  struct radeon_crtc *radeon_crtc,
991  u32 lb_size, u32 num_heads)
992 {
993  struct drm_display_mode *mode = &radeon_crtc->base.mode;
994  struct evergreen_wm_params wm;
995  u32 pixel_period;
996  u32 line_time = 0;
997  u32 latency_watermark_a = 0, latency_watermark_b = 0;
998  u32 priority_a_mark = 0, priority_b_mark = 0;
999  u32 priority_a_cnt = PRIORITY_OFF;
1000  u32 priority_b_cnt = PRIORITY_OFF;
1001  u32 pipe_offset = radeon_crtc->crtc_id * 16;
1002  u32 tmp, arb_control3;
1003  fixed20_12 a, b, c;
1004 
1005  if (radeon_crtc->base.enabled && num_heads && mode) {
1006  pixel_period = 1000000 / (u32)mode->clock;
1007  line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1008  priority_a_cnt = 0;
1009  priority_b_cnt = 0;
1010 
1011  wm.yclk = rdev->pm.current_mclk * 10;
1012  wm.sclk = rdev->pm.current_sclk * 10;
1013  wm.disp_clk = mode->clock;
1014  wm.src_width = mode->crtc_hdisplay;
1015  wm.active_time = mode->crtc_hdisplay * pixel_period;
1016  wm.blank_time = line_time - wm.active_time;
1017  wm.interlaced = false;
1018  if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1019  wm.interlaced = true;
1020  wm.vsc = radeon_crtc->vsc;
1021  wm.vtaps = 1;
1022  if (radeon_crtc->rmx_type != RMX_OFF)
1023  wm.vtaps = 2;
1024  wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1025  wm.lb_size = lb_size;
1026  wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1027  wm.num_heads = num_heads;
1028 
1029  /* set for high clocks */
1030  latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1031  /* set for low clocks */
1032  /* wm.yclk = low clk; wm.sclk = low clk */
1033  latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1034 
1035  /* possibly force display priority to high */
1036  /* should really do this at mode validation time... */
1037  if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1038  !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1039  !evergreen_check_latency_hiding(&wm) ||
1040  (rdev->disp_priority == 2)) {
1041  DRM_DEBUG_KMS("force priority to high\n");
1042  priority_a_cnt |= PRIORITY_ALWAYS_ON;
1043  priority_b_cnt |= PRIORITY_ALWAYS_ON;
1044  }
1045 
1046  a.full = dfixed_const(1000);
1047  b.full = dfixed_const(mode->clock);
1048  b.full = dfixed_div(b, a);
1049  c.full = dfixed_const(latency_watermark_a);
1050  c.full = dfixed_mul(c, b);
1051  c.full = dfixed_mul(c, radeon_crtc->hsc);
1052  c.full = dfixed_div(c, a);
1053  a.full = dfixed_const(16);
1054  c.full = dfixed_div(c, a);
1055  priority_a_mark = dfixed_trunc(c);
1056  priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1057 
1058  a.full = dfixed_const(1000);
1059  b.full = dfixed_const(mode->clock);
1060  b.full = dfixed_div(b, a);
1061  c.full = dfixed_const(latency_watermark_b);
1062  c.full = dfixed_mul(c, b);
1063  c.full = dfixed_mul(c, radeon_crtc->hsc);
1064  c.full = dfixed_div(c, a);
1065  a.full = dfixed_const(16);
1066  c.full = dfixed_div(c, a);
1067  priority_b_mark = dfixed_trunc(c);
1068  priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1069  }
1070 
1071  /* select wm A */
1072  arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1073  tmp = arb_control3;
1074  tmp &= ~LATENCY_WATERMARK_MASK(3);
1075  tmp |= LATENCY_WATERMARK_MASK(1);
1076  WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1077  WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1078  (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1079  LATENCY_HIGH_WATERMARK(line_time)));
1080  /* select wm B */
1081  tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1082  tmp &= ~LATENCY_WATERMARK_MASK(3);
1083  tmp |= LATENCY_WATERMARK_MASK(2);
1084  WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1085  WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1086  (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1087  LATENCY_HIGH_WATERMARK(line_time)));
1088  /* restore original selection */
1089  WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1090 
1091  /* write the priority marks */
1092  WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1093  WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1094 
1095 }
1096 
1105 void evergreen_bandwidth_update(struct radeon_device *rdev)
1106 {
1107  struct drm_display_mode *mode0 = NULL;
1108  struct drm_display_mode *mode1 = NULL;
1109  u32 num_heads = 0, lb_size;
1110  int i;
1111 
1112  radeon_update_display_priority(rdev);
1113 
1114  for (i = 0; i < rdev->num_crtc; i++) {
1115  if (rdev->mode_info.crtcs[i]->base.enabled)
1116  num_heads++;
1117  }
1118  for (i = 0; i < rdev->num_crtc; i += 2) {
1119  mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1120  mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1121  lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1122  evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1123  lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1124  evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1125  }
1126 }
1127 
1137 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
1138 {
1139  unsigned i;
1140  u32 tmp;
1141 
1142  for (i = 0; i < rdev->usec_timeout; i++) {
1143  /* read MC_STATUS */
1144  tmp = RREG32(SRBM_STATUS) & 0x1F00;
1145  if (!tmp)
1146  return 0;
1147  udelay(1);
1148  }
1149  return -1;
1150 }
1151 
1152 /*
1153  * GART
1154  */
1155 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1156 {
1157  unsigned i;
1158  u32 tmp;
1159 
1160  WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1161 
1162  WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1163  for (i = 0; i < rdev->usec_timeout; i++) {
1164  /* read MC_STATUS */
1165  tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1166  tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1167  if (tmp == 2) {
1168  printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1169  return;
1170  }
1171  if (tmp) {
1172  return;
1173  }
1174  udelay(1);
1175  }
1176 }
1177 
1178 static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1179 {
1180  u32 tmp;
1181  int r;
1182 
1183  if (rdev->gart.robj == NULL) {
1184  dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1185  return -EINVAL;
1186  }
1187  r = radeon_gart_table_vram_pin(rdev);
1188  if (r)
1189  return r;
1190  radeon_gart_restore(rdev);
1191  /* Setup L2 cache */
1192  WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1193  ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1194  EFFECTIVE_L2_QUEUE_SIZE(7));
1195  WREG32(VM_L2_CNTL2, 0);
1196  WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1197  /* Setup TLB control */
1198  tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1199  SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1200  SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1201  EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1202  if (rdev->flags & RADEON_IS_IGP) {
1203  WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1204  WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1205  WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1206  } else {
1207  WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1208  WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1209  WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1210  if ((rdev->family == CHIP_JUNIPER) ||
1211  (rdev->family == CHIP_CYPRESS) ||
1212  (rdev->family == CHIP_HEMLOCK) ||
1213  (rdev->family == CHIP_BARTS))
1214  WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1215  }
1216  WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1217  WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1218  WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1219  WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1220  WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1221  WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1222  WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1223  WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1224  RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1225  WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1226  (u32)(rdev->dummy_page.addr >> 12));
1227  WREG32(VM_CONTEXT1_CNTL, 0);
1228 
1229  evergreen_pcie_gart_tlb_flush(rdev);
1230  DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1231  (unsigned)(rdev->mc.gtt_size >> 20),
1232  (unsigned long long)rdev->gart.table_addr);
1233  rdev->gart.ready = true;
1234  return 0;
1235 }
1236 
1237 static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1238 {
1239  u32 tmp;
1240 
1241  /* Disable all tables */
1242  WREG32(VM_CONTEXT0_CNTL, 0);
1243  WREG32(VM_CONTEXT1_CNTL, 0);
1244 
1245  /* Setup L2 cache */
1246  WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1247  EFFECTIVE_L2_QUEUE_SIZE(7));
1248  WREG32(VM_L2_CNTL2, 0);
1249  WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1250  /* Setup TLB control */
1251  tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1252  WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1253  WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1254  WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1255  WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1256  WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1257  WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1258  WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1259  radeon_gart_table_vram_unpin(rdev);
1260 }
1261 
1262 static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1263 {
1264  evergreen_pcie_gart_disable(rdev);
1265  radeon_gart_table_vram_free(rdev);
1266  radeon_gart_fini(rdev);
1267 }
1268 
1269 
1270 static void evergreen_agp_enable(struct radeon_device *rdev)
1271 {
1272  u32 tmp;
1273 
1274  /* Setup L2 cache */
1275  WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1276  ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1277  EFFECTIVE_L2_QUEUE_SIZE(7));
1278  WREG32(VM_L2_CNTL2, 0);
1279  WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1280  /* Setup TLB control */
1281  tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1282  SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1283  SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1284  EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1285  WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1286  WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1287  WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1288  WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1289  WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1290  WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1291  WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1292  WREG32(VM_CONTEXT0_CNTL, 0);
1293  WREG32(VM_CONTEXT1_CNTL, 0);
1294 }
1295 
1296 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1297 {
1298  u32 crtc_enabled, tmp, frame_count, blackout;
1299  int i, j;
1300 
1301  save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1302  save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1303 
1304  /* disable VGA render */
1305  WREG32(VGA_RENDER_CONTROL, 0);
1306  /* blank the display controllers */
1307  for (i = 0; i < rdev->num_crtc; i++) {
1308  crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1309  if (crtc_enabled) {
1310  save->crtc_enabled[i] = true;
1311  if (ASIC_IS_DCE6(rdev)) {
1312  tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1313  if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1314  radeon_wait_for_vblank(rdev, i);
1315  tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1316  WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1317  }
1318  } else {
1319  tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1320  if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1321  radeon_wait_for_vblank(rdev, i);
1322  tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1323  WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1324  }
1325  }
1326  /* wait for the next frame */
1327  frame_count = radeon_get_vblank_counter(rdev, i);
1328  for (j = 0; j < rdev->usec_timeout; j++) {
1329  if (radeon_get_vblank_counter(rdev, i) != frame_count)
1330  break;
1331  udelay(1);
1332  }
1333  } else {
1334  save->crtc_enabled[i] = false;
1335  }
1336  }
1337 
1338  radeon_mc_wait_for_idle(rdev);
1339 
1340  blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1341  if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1342  /* Block CPU access */
1343  WREG32(BIF_FB_EN, 0);
1344  /* blackout the MC */
1345  blackout &= ~BLACKOUT_MODE_MASK;
1346  WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1347  }
1348 }
1349 
1350 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1351 {
1352  u32 tmp, frame_count;
1353  int i, j;
1354 
1355  /* update crtc base addresses */
1356  for (i = 0; i < rdev->num_crtc; i++) {
1357  WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1358  upper_32_bits(rdev->mc.vram_start));
1359  WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1360  upper_32_bits(rdev->mc.vram_start));
1361  WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1362  (u32)rdev->mc.vram_start);
1363  WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1364  (u32)rdev->mc.vram_start);
1365  }
1366  WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1367  WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1368 
1369  /* unblackout the MC */
1370  tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1371  tmp &= ~BLACKOUT_MODE_MASK;
1372  WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1373  /* allow CPU access */
1374  WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1375 
1376  for (i = 0; i < rdev->num_crtc; i++) {
1377  if (save->crtc_enabled[i]) {
1378  if (ASIC_IS_DCE6(rdev)) {
1379  tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1380  tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1381  WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1382  } else {
1383  tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1384  tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1385  WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1386  }
1387  /* wait for the next frame */
1388  frame_count = radeon_get_vblank_counter(rdev, i);
1389  for (j = 0; j < rdev->usec_timeout; j++) {
1390  if (radeon_get_vblank_counter(rdev, i) != frame_count)
1391  break;
1392  udelay(1);
1393  }
1394  }
1395  }
1396  /* Unlock vga access */
1397  WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1398  mdelay(1);
1399  WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1400 }
1401 
1402 void evergreen_mc_program(struct radeon_device *rdev)
1403 {
1404  struct evergreen_mc_save save;
1405  u32 tmp;
1406  int i, j;
1407 
1408  /* Initialize HDP */
1409  for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1410  WREG32((0x2c14 + j), 0x00000000);
1411  WREG32((0x2c18 + j), 0x00000000);
1412  WREG32((0x2c1c + j), 0x00000000);
1413  WREG32((0x2c20 + j), 0x00000000);
1414  WREG32((0x2c24 + j), 0x00000000);
1415  }
1416  WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1417 
1418  evergreen_mc_stop(rdev, &save);
1419  if (evergreen_mc_wait_for_idle(rdev)) {
1420  dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1421  }
1422  /* Lockout access through VGA aperture*/
1423  WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1424  /* Update configuration */
1425  if (rdev->flags & RADEON_IS_AGP) {
1426  if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1427  /* VRAM before AGP */
1428  WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1429  rdev->mc.vram_start >> 12);
1430  WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1431  rdev->mc.gtt_end >> 12);
1432  } else {
1433  /* VRAM after AGP */
1434  WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1435  rdev->mc.gtt_start >> 12);
1436  WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1437  rdev->mc.vram_end >> 12);
1438  }
1439  } else {
1440  WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1441  rdev->mc.vram_start >> 12);
1442  WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1443  rdev->mc.vram_end >> 12);
1444  }
1445  WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1446  /* llano/ontario only */
1447  if ((rdev->family == CHIP_PALM) ||
1448  (rdev->family == CHIP_SUMO) ||
1449  (rdev->family == CHIP_SUMO2)) {
1450  tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1451  tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1452  tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1453  WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1454  }
1455  tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1456  tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1457  WREG32(MC_VM_FB_LOCATION, tmp);
1458  WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1459  WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1460  WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1461  if (rdev->flags & RADEON_IS_AGP) {
1462  WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1463  WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1464  WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1465  } else {
1466  WREG32(MC_VM_AGP_BASE, 0);
1467  WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1468  WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1469  }
1470  if (evergreen_mc_wait_for_idle(rdev)) {
1471  dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1472  }
1473  evergreen_mc_resume(rdev, &save);
1474  /* we need to own VRAM, so turn off the VGA renderer here
1475  * to stop it overwriting our objects */
1476  rv515_vga_render_disable(rdev);
1477 }
1478 
1479 /*
1480  * CP.
1481  */
1482 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1483 {
1484  struct radeon_ring *ring = &rdev->ring[ib->ring];
1485  u32 next_rptr;
1486 
1487  /* set to DX10/11 mode */
1488  radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1489  radeon_ring_write(ring, 1);
1490 
1491  if (ring->rptr_save_reg) {
1492  next_rptr = ring->wptr + 3 + 4;
1493  radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1494  radeon_ring_write(ring, ((ring->rptr_save_reg -
1495  PACKET3_SET_CONFIG_REG_START) >> 2));
1496  radeon_ring_write(ring, next_rptr);
1497  } else if (rdev->wb.enabled) {
1498  next_rptr = ring->wptr + 5 + 4;
1499  radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1500  radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1501  radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1502  radeon_ring_write(ring, next_rptr);
1503  radeon_ring_write(ring, 0);
1504  }
1505 
1506  radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1507  radeon_ring_write(ring,
1508 #ifdef __BIG_ENDIAN
1509  (2 << 0) |
1510 #endif
1511  (ib->gpu_addr & 0xFFFFFFFC));
1512  radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1513  radeon_ring_write(ring, ib->length_dw);
1514 }
1515 
1516 
1517 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1518 {
1519  const __be32 *fw_data;
1520  int i;
1521 
1522  if (!rdev->me_fw || !rdev->pfp_fw)
1523  return -EINVAL;
1524 
1525  r700_cp_stop(rdev);
1526  WREG32(CP_RB_CNTL,
1527 #ifdef __BIG_ENDIAN
1528  BUF_SWAP_32BIT |
1529 #endif
1530  RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1531 
1532  fw_data = (const __be32 *)rdev->pfp_fw->data;
1533  WREG32(CP_PFP_UCODE_ADDR, 0);
1534  for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1535  WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1536  WREG32(CP_PFP_UCODE_ADDR, 0);
1537 
1538  fw_data = (const __be32 *)rdev->me_fw->data;
1539  WREG32(CP_ME_RAM_WADDR, 0);
1540  for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1541  WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1542 
1543  WREG32(CP_PFP_UCODE_ADDR, 0);
1544  WREG32(CP_ME_RAM_WADDR, 0);
1545  WREG32(CP_ME_RAM_RADDR, 0);
1546  return 0;
1547 }
1548 
1549 static int evergreen_cp_start(struct radeon_device *rdev)
1550 {
1551  struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1552  int r, i;
1553  uint32_t cp_me;
1554 
1555  r = radeon_ring_lock(rdev, ring, 7);
1556  if (r) {
1557  DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1558  return r;
1559  }
1560  radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1561  radeon_ring_write(ring, 0x1);
1562  radeon_ring_write(ring, 0x0);
1563  radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1564  radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1565  radeon_ring_write(ring, 0);
1566  radeon_ring_write(ring, 0);
1567  radeon_ring_unlock_commit(rdev, ring);
1568 
1569  cp_me = 0xff;
1570  WREG32(CP_ME_CNTL, cp_me);
1571 
1572  r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1573  if (r) {
1574  DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1575  return r;
1576  }
1577 
1578  /* setup clear context state */
1579  radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1580  radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1581 
1582  for (i = 0; i < evergreen_default_size; i++)
1583  radeon_ring_write(ring, evergreen_default_state[i]);
1584 
1585  radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1586  radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1587 
1588  /* set clear context state */
1589  radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1590  radeon_ring_write(ring, 0);
1591 
1592  /* SQ_VTX_BASE_VTX_LOC */
1593  radeon_ring_write(ring, 0xc0026f00);
1594  radeon_ring_write(ring, 0x00000000);
1595  radeon_ring_write(ring, 0x00000000);
1596  radeon_ring_write(ring, 0x00000000);
1597 
1598  /* Clear consts */
1599  radeon_ring_write(ring, 0xc0036f00);
1600  radeon_ring_write(ring, 0x00000bc4);
1601  radeon_ring_write(ring, 0xffffffff);
1602  radeon_ring_write(ring, 0xffffffff);
1603  radeon_ring_write(ring, 0xffffffff);
1604 
1605  radeon_ring_write(ring, 0xc0026900);
1606  radeon_ring_write(ring, 0x00000316);
1607  radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1608  radeon_ring_write(ring, 0x00000010); /* */
1609 
1610  radeon_ring_unlock_commit(rdev, ring);
1611 
1612  return 0;
1613 }
1614 
1615 static int evergreen_cp_resume(struct radeon_device *rdev)
1616 {
1617  struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1618  u32 tmp;
1619  u32 rb_bufsz;
1620  int r;
1621 
1622  /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1623  WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1624  SOFT_RESET_PA |
1625  SOFT_RESET_SH |
1626  SOFT_RESET_VGT |
1627  SOFT_RESET_SPI |
1628  SOFT_RESET_SX));
1629  RREG32(GRBM_SOFT_RESET);
1630  mdelay(15);
1631  WREG32(GRBM_SOFT_RESET, 0);
1632  RREG32(GRBM_SOFT_RESET);
1633 
1634  /* Set ring buffer size */
1635  rb_bufsz = drm_order(ring->ring_size / 8);
1636  tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1637 #ifdef __BIG_ENDIAN
1638  tmp |= BUF_SWAP_32BIT;
1639 #endif
1640  WREG32(CP_RB_CNTL, tmp);
1641  WREG32(CP_SEM_WAIT_TIMER, 0x0);
1642  WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1643 
1644  /* Set the write pointer delay */
1645  WREG32(CP_RB_WPTR_DELAY, 0);
1646 
1647  /* Initialize the ring buffer's read and write pointers */
1648  WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1649  WREG32(CP_RB_RPTR_WR, 0);
1650  ring->wptr = 0;
1651  WREG32(CP_RB_WPTR, ring->wptr);
1652 
1653  /* set the wb address wether it's enabled or not */
1654  WREG32(CP_RB_RPTR_ADDR,
1655  ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1656  WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1657  WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1658 
1659  if (rdev->wb.enabled)
1660  WREG32(SCRATCH_UMSK, 0xff);
1661  else {
1662  tmp |= RB_NO_UPDATE;
1663  WREG32(SCRATCH_UMSK, 0);
1664  }
1665 
1666  mdelay(1);
1667  WREG32(CP_RB_CNTL, tmp);
1668 
1669  WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1670  WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1671 
1672  ring->rptr = RREG32(CP_RB_RPTR);
1673 
1674  evergreen_cp_start(rdev);
1675  ring->ready = true;
1676  r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1677  if (r) {
1678  ring->ready = false;
1679  return r;
1680  }
1681  return 0;
1682 }
1683 
1684 /*
1685  * Core functions
1686  */
1687 static void evergreen_gpu_init(struct radeon_device *rdev)
1688 {
1689  u32 gb_addr_config;
1690  u32 mc_shared_chmap, mc_arb_ramcfg;
1691  u32 sx_debug_1;
1692  u32 smx_dc_ctl0;
1693  u32 sq_config;
1694  u32 sq_lds_resource_mgmt;
1695  u32 sq_gpr_resource_mgmt_1;
1696  u32 sq_gpr_resource_mgmt_2;
1697  u32 sq_gpr_resource_mgmt_3;
1698  u32 sq_thread_resource_mgmt;
1699  u32 sq_thread_resource_mgmt_2;
1700  u32 sq_stack_resource_mgmt_1;
1701  u32 sq_stack_resource_mgmt_2;
1702  u32 sq_stack_resource_mgmt_3;
1703  u32 vgt_cache_invalidation;
1704  u32 hdp_host_path_cntl, tmp;
1705  u32 disabled_rb_mask;
1706  int i, j, num_shader_engines, ps_thread_count;
1707 
1708  switch (rdev->family) {
1709  case CHIP_CYPRESS:
1710  case CHIP_HEMLOCK:
1711  rdev->config.evergreen.num_ses = 2;
1712  rdev->config.evergreen.max_pipes = 4;
1713  rdev->config.evergreen.max_tile_pipes = 8;
1714  rdev->config.evergreen.max_simds = 10;
1715  rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1716  rdev->config.evergreen.max_gprs = 256;
1717  rdev->config.evergreen.max_threads = 248;
1718  rdev->config.evergreen.max_gs_threads = 32;
1719  rdev->config.evergreen.max_stack_entries = 512;
1720  rdev->config.evergreen.sx_num_of_sets = 4;
1721  rdev->config.evergreen.sx_max_export_size = 256;
1722  rdev->config.evergreen.sx_max_export_pos_size = 64;
1723  rdev->config.evergreen.sx_max_export_smx_size = 192;
1724  rdev->config.evergreen.max_hw_contexts = 8;
1725  rdev->config.evergreen.sq_num_cf_insts = 2;
1726 
1727  rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1728  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1729  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1730  gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1731  break;
1732  case CHIP_JUNIPER:
1733  rdev->config.evergreen.num_ses = 1;
1734  rdev->config.evergreen.max_pipes = 4;
1735  rdev->config.evergreen.max_tile_pipes = 4;
1736  rdev->config.evergreen.max_simds = 10;
1737  rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1738  rdev->config.evergreen.max_gprs = 256;
1739  rdev->config.evergreen.max_threads = 248;
1740  rdev->config.evergreen.max_gs_threads = 32;
1741  rdev->config.evergreen.max_stack_entries = 512;
1742  rdev->config.evergreen.sx_num_of_sets = 4;
1743  rdev->config.evergreen.sx_max_export_size = 256;
1744  rdev->config.evergreen.sx_max_export_pos_size = 64;
1745  rdev->config.evergreen.sx_max_export_smx_size = 192;
1746  rdev->config.evergreen.max_hw_contexts = 8;
1747  rdev->config.evergreen.sq_num_cf_insts = 2;
1748 
1749  rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1750  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1751  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1752  gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1753  break;
1754  case CHIP_REDWOOD:
1755  rdev->config.evergreen.num_ses = 1;
1756  rdev->config.evergreen.max_pipes = 4;
1757  rdev->config.evergreen.max_tile_pipes = 4;
1758  rdev->config.evergreen.max_simds = 5;
1759  rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1760  rdev->config.evergreen.max_gprs = 256;
1761  rdev->config.evergreen.max_threads = 248;
1762  rdev->config.evergreen.max_gs_threads = 32;
1763  rdev->config.evergreen.max_stack_entries = 256;
1764  rdev->config.evergreen.sx_num_of_sets = 4;
1765  rdev->config.evergreen.sx_max_export_size = 256;
1766  rdev->config.evergreen.sx_max_export_pos_size = 64;
1767  rdev->config.evergreen.sx_max_export_smx_size = 192;
1768  rdev->config.evergreen.max_hw_contexts = 8;
1769  rdev->config.evergreen.sq_num_cf_insts = 2;
1770 
1771  rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1772  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1773  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1774  gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1775  break;
1776  case CHIP_CEDAR:
1777  default:
1778  rdev->config.evergreen.num_ses = 1;
1779  rdev->config.evergreen.max_pipes = 2;
1780  rdev->config.evergreen.max_tile_pipes = 2;
1781  rdev->config.evergreen.max_simds = 2;
1782  rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1783  rdev->config.evergreen.max_gprs = 256;
1784  rdev->config.evergreen.max_threads = 192;
1785  rdev->config.evergreen.max_gs_threads = 16;
1786  rdev->config.evergreen.max_stack_entries = 256;
1787  rdev->config.evergreen.sx_num_of_sets = 4;
1788  rdev->config.evergreen.sx_max_export_size = 128;
1789  rdev->config.evergreen.sx_max_export_pos_size = 32;
1790  rdev->config.evergreen.sx_max_export_smx_size = 96;
1791  rdev->config.evergreen.max_hw_contexts = 4;
1792  rdev->config.evergreen.sq_num_cf_insts = 1;
1793 
1794  rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1795  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1796  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1797  gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1798  break;
1799  case CHIP_PALM:
1800  rdev->config.evergreen.num_ses = 1;
1801  rdev->config.evergreen.max_pipes = 2;
1802  rdev->config.evergreen.max_tile_pipes = 2;
1803  rdev->config.evergreen.max_simds = 2;
1804  rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1805  rdev->config.evergreen.max_gprs = 256;
1806  rdev->config.evergreen.max_threads = 192;
1807  rdev->config.evergreen.max_gs_threads = 16;
1808  rdev->config.evergreen.max_stack_entries = 256;
1809  rdev->config.evergreen.sx_num_of_sets = 4;
1810  rdev->config.evergreen.sx_max_export_size = 128;
1811  rdev->config.evergreen.sx_max_export_pos_size = 32;
1812  rdev->config.evergreen.sx_max_export_smx_size = 96;
1813  rdev->config.evergreen.max_hw_contexts = 4;
1814  rdev->config.evergreen.sq_num_cf_insts = 1;
1815 
1816  rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1817  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1818  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1819  gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1820  break;
1821  case CHIP_SUMO:
1822  rdev->config.evergreen.num_ses = 1;
1823  rdev->config.evergreen.max_pipes = 4;
1824  rdev->config.evergreen.max_tile_pipes = 2;
1825  if (rdev->pdev->device == 0x9648)
1826  rdev->config.evergreen.max_simds = 3;
1827  else if ((rdev->pdev->device == 0x9647) ||
1828  (rdev->pdev->device == 0x964a))
1829  rdev->config.evergreen.max_simds = 4;
1830  else
1831  rdev->config.evergreen.max_simds = 5;
1832  rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1833  rdev->config.evergreen.max_gprs = 256;
1834  rdev->config.evergreen.max_threads = 248;
1835  rdev->config.evergreen.max_gs_threads = 32;
1836  rdev->config.evergreen.max_stack_entries = 256;
1837  rdev->config.evergreen.sx_num_of_sets = 4;
1838  rdev->config.evergreen.sx_max_export_size = 256;
1839  rdev->config.evergreen.sx_max_export_pos_size = 64;
1840  rdev->config.evergreen.sx_max_export_smx_size = 192;
1841  rdev->config.evergreen.max_hw_contexts = 8;
1842  rdev->config.evergreen.sq_num_cf_insts = 2;
1843 
1844  rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1845  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1846  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1847  gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1848  break;
1849  case CHIP_SUMO2:
1850  rdev->config.evergreen.num_ses = 1;
1851  rdev->config.evergreen.max_pipes = 4;
1852  rdev->config.evergreen.max_tile_pipes = 4;
1853  rdev->config.evergreen.max_simds = 2;
1854  rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1855  rdev->config.evergreen.max_gprs = 256;
1856  rdev->config.evergreen.max_threads = 248;
1857  rdev->config.evergreen.max_gs_threads = 32;
1858  rdev->config.evergreen.max_stack_entries = 512;
1859  rdev->config.evergreen.sx_num_of_sets = 4;
1860  rdev->config.evergreen.sx_max_export_size = 256;
1861  rdev->config.evergreen.sx_max_export_pos_size = 64;
1862  rdev->config.evergreen.sx_max_export_smx_size = 192;
1863  rdev->config.evergreen.max_hw_contexts = 8;
1864  rdev->config.evergreen.sq_num_cf_insts = 2;
1865 
1866  rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1867  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1868  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1869  gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1870  break;
1871  case CHIP_BARTS:
1872  rdev->config.evergreen.num_ses = 2;
1873  rdev->config.evergreen.max_pipes = 4;
1874  rdev->config.evergreen.max_tile_pipes = 8;
1875  rdev->config.evergreen.max_simds = 7;
1876  rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1877  rdev->config.evergreen.max_gprs = 256;
1878  rdev->config.evergreen.max_threads = 248;
1879  rdev->config.evergreen.max_gs_threads = 32;
1880  rdev->config.evergreen.max_stack_entries = 512;
1881  rdev->config.evergreen.sx_num_of_sets = 4;
1882  rdev->config.evergreen.sx_max_export_size = 256;
1883  rdev->config.evergreen.sx_max_export_pos_size = 64;
1884  rdev->config.evergreen.sx_max_export_smx_size = 192;
1885  rdev->config.evergreen.max_hw_contexts = 8;
1886  rdev->config.evergreen.sq_num_cf_insts = 2;
1887 
1888  rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1889  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1890  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1891  gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1892  break;
1893  case CHIP_TURKS:
1894  rdev->config.evergreen.num_ses = 1;
1895  rdev->config.evergreen.max_pipes = 4;
1896  rdev->config.evergreen.max_tile_pipes = 4;
1897  rdev->config.evergreen.max_simds = 6;
1898  rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1899  rdev->config.evergreen.max_gprs = 256;
1900  rdev->config.evergreen.max_threads = 248;
1901  rdev->config.evergreen.max_gs_threads = 32;
1902  rdev->config.evergreen.max_stack_entries = 256;
1903  rdev->config.evergreen.sx_num_of_sets = 4;
1904  rdev->config.evergreen.sx_max_export_size = 256;
1905  rdev->config.evergreen.sx_max_export_pos_size = 64;
1906  rdev->config.evergreen.sx_max_export_smx_size = 192;
1907  rdev->config.evergreen.max_hw_contexts = 8;
1908  rdev->config.evergreen.sq_num_cf_insts = 2;
1909 
1910  rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1911  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1912  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1913  gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1914  break;
1915  case CHIP_CAICOS:
1916  rdev->config.evergreen.num_ses = 1;
1917  rdev->config.evergreen.max_pipes = 4;
1918  rdev->config.evergreen.max_tile_pipes = 2;
1919  rdev->config.evergreen.max_simds = 2;
1920  rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1921  rdev->config.evergreen.max_gprs = 256;
1922  rdev->config.evergreen.max_threads = 192;
1923  rdev->config.evergreen.max_gs_threads = 16;
1924  rdev->config.evergreen.max_stack_entries = 256;
1925  rdev->config.evergreen.sx_num_of_sets = 4;
1926  rdev->config.evergreen.sx_max_export_size = 128;
1927  rdev->config.evergreen.sx_max_export_pos_size = 32;
1928  rdev->config.evergreen.sx_max_export_smx_size = 96;
1929  rdev->config.evergreen.max_hw_contexts = 4;
1930  rdev->config.evergreen.sq_num_cf_insts = 1;
1931 
1932  rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1933  rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1934  rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1935  gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1936  break;
1937  }
1938 
1939  /* Initialize HDP */
1940  for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1941  WREG32((0x2c14 + j), 0x00000000);
1942  WREG32((0x2c18 + j), 0x00000000);
1943  WREG32((0x2c1c + j), 0x00000000);
1944  WREG32((0x2c20 + j), 0x00000000);
1945  WREG32((0x2c24 + j), 0x00000000);
1946  }
1947 
1948  WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1949 
1950  evergreen_fix_pci_max_read_req_size(rdev);
1951 
1952  mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1953  if ((rdev->family == CHIP_PALM) ||
1954  (rdev->family == CHIP_SUMO) ||
1955  (rdev->family == CHIP_SUMO2))
1956  mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1957  else
1958  mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1959 
1960  /* setup tiling info dword. gb_addr_config is not adequate since it does
1961  * not have bank info, so create a custom tiling dword.
1962  * bits 3:0 num_pipes
1963  * bits 7:4 num_banks
1964  * bits 11:8 group_size
1965  * bits 15:12 row_size
1966  */
1967  rdev->config.evergreen.tile_config = 0;
1968  switch (rdev->config.evergreen.max_tile_pipes) {
1969  case 1:
1970  default:
1971  rdev->config.evergreen.tile_config |= (0 << 0);
1972  break;
1973  case 2:
1974  rdev->config.evergreen.tile_config |= (1 << 0);
1975  break;
1976  case 4:
1977  rdev->config.evergreen.tile_config |= (2 << 0);
1978  break;
1979  case 8:
1980  rdev->config.evergreen.tile_config |= (3 << 0);
1981  break;
1982  }
1983  /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1984  if (rdev->flags & RADEON_IS_IGP)
1985  rdev->config.evergreen.tile_config |= 1 << 4;
1986  else {
1987  switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1988  case 0: /* four banks */
1989  rdev->config.evergreen.tile_config |= 0 << 4;
1990  break;
1991  case 1: /* eight banks */
1992  rdev->config.evergreen.tile_config |= 1 << 4;
1993  break;
1994  case 2: /* sixteen banks */
1995  default:
1996  rdev->config.evergreen.tile_config |= 2 << 4;
1997  break;
1998  }
1999  }
2000  rdev->config.evergreen.tile_config |= 0 << 8;
2001  rdev->config.evergreen.tile_config |=
2002  ((gb_addr_config & 0x30000000) >> 28) << 12;
2003 
2004  num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
2005 
2006  if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
2007  u32 efuse_straps_4;
2008  u32 efuse_straps_3;
2009 
2010  WREG32(RCU_IND_INDEX, 0x204);
2011  efuse_straps_4 = RREG32(RCU_IND_DATA);
2012  WREG32(RCU_IND_INDEX, 0x203);
2013  efuse_straps_3 = RREG32(RCU_IND_DATA);
2014  tmp = (((efuse_straps_4 & 0xf) << 4) |
2015  ((efuse_straps_3 & 0xf0000000) >> 28));
2016  } else {
2017  tmp = 0;
2018  for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2019  u32 rb_disable_bitmap;
2020 
2021  WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2022  WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2023  rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2024  tmp <<= 4;
2025  tmp |= rb_disable_bitmap;
2026  }
2027  }
2028  /* enabled rb are just the one not disabled :) */
2029  disabled_rb_mask = tmp;
2030 
2031  WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2032  WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2033 
2034  WREG32(GB_ADDR_CONFIG, gb_addr_config);
2035  WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2036  WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2037 
2038  tmp = gb_addr_config & NUM_PIPES_MASK;
2039  tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2040  EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2041  WREG32(GB_BACKEND_MAP, tmp);
2042 
2043  WREG32(CGTS_SYS_TCC_DISABLE, 0);
2044  WREG32(CGTS_TCC_DISABLE, 0);
2045  WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2046  WREG32(CGTS_USER_TCC_DISABLE, 0);
2047 
2048  /* set HW defaults for 3D engine */
2049  WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2050  ROQ_IB2_START(0x2b)));
2051 
2052  WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2053 
2054  WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2055  SYNC_GRADIENT |
2056  SYNC_WALKER |
2057  SYNC_ALIGNER));
2058 
2059  sx_debug_1 = RREG32(SX_DEBUG_1);
2060  sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2061  WREG32(SX_DEBUG_1, sx_debug_1);
2062 
2063 
2064  smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2065  smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2066  smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2067  WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2068 
2069  if (rdev->family <= CHIP_SUMO2)
2070  WREG32(SMX_SAR_CTL0, 0x00010000);
2071 
2072  WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2073  POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2074  SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2075 
2076  WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2077  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2078  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2079 
2080  WREG32(VGT_NUM_INSTANCES, 1);
2081  WREG32(SPI_CONFIG_CNTL, 0);
2082  WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2083  WREG32(CP_PERFMON_CNTL, 0);
2084 
2085  WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2086  FETCH_FIFO_HIWATER(0x4) |
2087  DONE_FIFO_HIWATER(0xe0) |
2088  ALU_UPDATE_FIFO_HIWATER(0x8)));
2089 
2090  sq_config = RREG32(SQ_CONFIG);
2091  sq_config &= ~(PS_PRIO(3) |
2092  VS_PRIO(3) |
2093  GS_PRIO(3) |
2094  ES_PRIO(3));
2095  sq_config |= (VC_ENABLE |
2096  EXPORT_SRC_C |
2097  PS_PRIO(0) |
2098  VS_PRIO(1) |
2099  GS_PRIO(2) |
2100  ES_PRIO(3));
2101 
2102  switch (rdev->family) {
2103  case CHIP_CEDAR:
2104  case CHIP_PALM:
2105  case CHIP_SUMO:
2106  case CHIP_SUMO2:
2107  case CHIP_CAICOS:
2108  /* no vertex cache */
2109  sq_config &= ~VC_ENABLE;
2110  break;
2111  default:
2112  break;
2113  }
2114 
2115  sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2116 
2117  sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2118  sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2119  sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2120  sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2121  sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2122  sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2123  sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2124 
2125  switch (rdev->family) {
2126  case CHIP_CEDAR:
2127  case CHIP_PALM:
2128  case CHIP_SUMO:
2129  case CHIP_SUMO2:
2130  ps_thread_count = 96;
2131  break;
2132  default:
2133  ps_thread_count = 128;
2134  break;
2135  }
2136 
2137  sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2138  sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2139  sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2140  sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2141  sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2142  sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2143 
2144  sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2145  sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2146  sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2147  sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2148  sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2149  sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2150 
2151  WREG32(SQ_CONFIG, sq_config);
2152  WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2153  WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2154  WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2155  WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2156  WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2157  WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2158  WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2159  WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2160  WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2161  WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2162 
2163  WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2164  FORCE_EOV_MAX_REZ_CNT(255)));
2165 
2166  switch (rdev->family) {
2167  case CHIP_CEDAR:
2168  case CHIP_PALM:
2169  case CHIP_SUMO:
2170  case CHIP_SUMO2:
2171  case CHIP_CAICOS:
2172  vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2173  break;
2174  default:
2175  vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2176  break;
2177  }
2178  vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2179  WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2180 
2181  WREG32(VGT_GS_VERTEX_REUSE, 16);
2182  WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2183  WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2184 
2185  WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2186  WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2187 
2188  WREG32(CB_PERF_CTR0_SEL_0, 0);
2189  WREG32(CB_PERF_CTR0_SEL_1, 0);
2190  WREG32(CB_PERF_CTR1_SEL_0, 0);
2191  WREG32(CB_PERF_CTR1_SEL_1, 0);
2192  WREG32(CB_PERF_CTR2_SEL_0, 0);
2193  WREG32(CB_PERF_CTR2_SEL_1, 0);
2194  WREG32(CB_PERF_CTR3_SEL_0, 0);
2195  WREG32(CB_PERF_CTR3_SEL_1, 0);
2196 
2197  /* clear render buffer base addresses */
2198  WREG32(CB_COLOR0_BASE, 0);
2199  WREG32(CB_COLOR1_BASE, 0);
2200  WREG32(CB_COLOR2_BASE, 0);
2201  WREG32(CB_COLOR3_BASE, 0);
2202  WREG32(CB_COLOR4_BASE, 0);
2203  WREG32(CB_COLOR5_BASE, 0);
2204  WREG32(CB_COLOR6_BASE, 0);
2205  WREG32(CB_COLOR7_BASE, 0);
2206  WREG32(CB_COLOR8_BASE, 0);
2207  WREG32(CB_COLOR9_BASE, 0);
2208  WREG32(CB_COLOR10_BASE, 0);
2209  WREG32(CB_COLOR11_BASE, 0);
2210 
2211  /* set the shader const cache sizes to 0 */
2212  for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2213  WREG32(i, 0);
2214  for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2215  WREG32(i, 0);
2216 
2217  tmp = RREG32(HDP_MISC_CNTL);
2218  tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2219  WREG32(HDP_MISC_CNTL, tmp);
2220 
2221  hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2222  WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2223 
2224  WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2225 
2226  udelay(50);
2227 
2228 }
2229 
2230 int evergreen_mc_init(struct radeon_device *rdev)
2231 {
2232  u32 tmp;
2233  int chansize, numchan;
2234 
2235  /* Get VRAM informations */
2236  rdev->mc.vram_is_ddr = true;
2237  if ((rdev->family == CHIP_PALM) ||
2238  (rdev->family == CHIP_SUMO) ||
2239  (rdev->family == CHIP_SUMO2))
2240  tmp = RREG32(FUS_MC_ARB_RAMCFG);
2241  else
2242  tmp = RREG32(MC_ARB_RAMCFG);
2243  if (tmp & CHANSIZE_OVERRIDE) {
2244  chansize = 16;
2245  } else if (tmp & CHANSIZE_MASK) {
2246  chansize = 64;
2247  } else {
2248  chansize = 32;
2249  }
2250  tmp = RREG32(MC_SHARED_CHMAP);
2251  switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2252  case 0:
2253  default:
2254  numchan = 1;
2255  break;
2256  case 1:
2257  numchan = 2;
2258  break;
2259  case 2:
2260  numchan = 4;
2261  break;
2262  case 3:
2263  numchan = 8;
2264  break;
2265  }
2266  rdev->mc.vram_width = numchan * chansize;
2267  /* Could aper size report 0 ? */
2268  rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2269  rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2270  /* Setup GPU memory space */
2271  if ((rdev->family == CHIP_PALM) ||
2272  (rdev->family == CHIP_SUMO) ||
2273  (rdev->family == CHIP_SUMO2)) {
2274  /* size in bytes on fusion */
2275  rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2276  rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2277  } else {
2278  /* size in MB on evergreen/cayman/tn */
2279  rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2280  rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2281  }
2282  rdev->mc.visible_vram_size = rdev->mc.aper_size;
2283  r700_vram_gtt_location(rdev, &rdev->mc);
2284  radeon_update_bandwidth_info(rdev);
2285 
2286  return 0;
2287 }
2288 
2289 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2290 {
2291  u32 srbm_status;
2292  u32 grbm_status;
2293  u32 grbm_status_se0, grbm_status_se1;
2294 
2295  srbm_status = RREG32(SRBM_STATUS);
2296  grbm_status = RREG32(GRBM_STATUS);
2297  grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2298  grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2299  if (!(grbm_status & GUI_ACTIVE)) {
2300  radeon_ring_lockup_update(ring);
2301  return false;
2302  }
2303  /* force CP activities */
2304  radeon_ring_force_activity(rdev, ring);
2305  return radeon_ring_test_lockup(rdev, ring);
2306 }
2307 
2308 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2309 {
2310  struct evergreen_mc_save save;
2311  u32 grbm_reset = 0;
2312 
2313  if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2314  return 0;
2315 
2316  dev_info(rdev->dev, "GPU softreset \n");
2317  dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2318  RREG32(GRBM_STATUS));
2319  dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2320  RREG32(GRBM_STATUS_SE0));
2321  dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2322  RREG32(GRBM_STATUS_SE1));
2323  dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2324  RREG32(SRBM_STATUS));
2325  dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2326  RREG32(CP_STALLED_STAT1));
2327  dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2328  RREG32(CP_STALLED_STAT2));
2329  dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2330  RREG32(CP_BUSY_STAT));
2331  dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2332  RREG32(CP_STAT));
2333  evergreen_mc_stop(rdev, &save);
2334  if (evergreen_mc_wait_for_idle(rdev)) {
2335  dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2336  }
2337  /* Disable CP parsing/prefetching */
2338  WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2339 
2340  /* reset all the gfx blocks */
2341  grbm_reset = (SOFT_RESET_CP |
2342  SOFT_RESET_CB |
2343  SOFT_RESET_DB |
2344  SOFT_RESET_PA |
2345  SOFT_RESET_SC |
2346  SOFT_RESET_SPI |
2347  SOFT_RESET_SH |
2348  SOFT_RESET_SX |
2349  SOFT_RESET_TC |
2350  SOFT_RESET_TA |
2351  SOFT_RESET_VC |
2352  SOFT_RESET_VGT);
2353 
2354  dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2355  WREG32(GRBM_SOFT_RESET, grbm_reset);
2356  (void)RREG32(GRBM_SOFT_RESET);
2357  udelay(50);
2358  WREG32(GRBM_SOFT_RESET, 0);
2359  (void)RREG32(GRBM_SOFT_RESET);
2360  /* Wait a little for things to settle down */
2361  udelay(50);
2362  dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2363  RREG32(GRBM_STATUS));
2364  dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2365  RREG32(GRBM_STATUS_SE0));
2366  dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2367  RREG32(GRBM_STATUS_SE1));
2368  dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2369  RREG32(SRBM_STATUS));
2370  dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2371  RREG32(CP_STALLED_STAT1));
2372  dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2373  RREG32(CP_STALLED_STAT2));
2374  dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2375  RREG32(CP_BUSY_STAT));
2376  dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2377  RREG32(CP_STAT));
2378  evergreen_mc_resume(rdev, &save);
2379  return 0;
2380 }
2381 
2382 int evergreen_asic_reset(struct radeon_device *rdev)
2383 {
2384  return evergreen_gpu_soft_reset(rdev);
2385 }
2386 
2387 /* Interrupts */
2388 
2389 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2390 {
2391  if (crtc >= rdev->num_crtc)
2392  return 0;
2393  else
2394  return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
2395 }
2396 
2397 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2398 {
2399  u32 tmp;
2400 
2401  if (rdev->family >= CHIP_CAYMAN) {
2402  cayman_cp_int_cntl_setup(rdev, 0,
2403  CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2404  cayman_cp_int_cntl_setup(rdev, 1, 0);
2405  cayman_cp_int_cntl_setup(rdev, 2, 0);
2406  } else
2407  WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2408  WREG32(GRBM_INT_CNTL, 0);
2409  WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2410  WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2411  if (rdev->num_crtc >= 4) {
2412  WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2413  WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2414  }
2415  if (rdev->num_crtc >= 6) {
2416  WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2417  WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2418  }
2419 
2420  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2421  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2422  if (rdev->num_crtc >= 4) {
2423  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2424  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2425  }
2426  if (rdev->num_crtc >= 6) {
2427  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2428  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2429  }
2430 
2431  /* only one DAC on DCE6 */
2432  if (!ASIC_IS_DCE6(rdev))
2433  WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2434  WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2435 
2436  tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2437  WREG32(DC_HPD1_INT_CONTROL, tmp);
2438  tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2439  WREG32(DC_HPD2_INT_CONTROL, tmp);
2440  tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2441  WREG32(DC_HPD3_INT_CONTROL, tmp);
2442  tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2443  WREG32(DC_HPD4_INT_CONTROL, tmp);
2444  tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2445  WREG32(DC_HPD5_INT_CONTROL, tmp);
2446  tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2447  WREG32(DC_HPD6_INT_CONTROL, tmp);
2448 
2449 }
2450 
2451 int evergreen_irq_set(struct radeon_device *rdev)
2452 {
2453  u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2454  u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2455  u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2456  u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2457  u32 grbm_int_cntl = 0;
2458  u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2459  u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2460 
2461  if (!rdev->irq.installed) {
2462  WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2463  return -EINVAL;
2464  }
2465  /* don't enable anything if the ih is disabled */
2466  if (!rdev->ih.enabled) {
2467  r600_disable_interrupts(rdev);
2468  /* force the active interrupt state to all disabled */
2469  evergreen_disable_interrupt_state(rdev);
2470  return 0;
2471  }
2472 
2473  hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2474  hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2475  hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2476  hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2477  hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2478  hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2479 
2480  afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2481  afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2482  afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2483  afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2484  afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2485  afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2486 
2487  if (rdev->family >= CHIP_CAYMAN) {
2488  /* enable CP interrupts on all rings */
2489  if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2490  DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2491  cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2492  }
2493  if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
2494  DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2495  cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2496  }
2497  if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
2498  DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2499  cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2500  }
2501  } else {
2502  if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2503  DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2504  cp_int_cntl |= RB_INT_ENABLE;
2505  cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2506  }
2507  }
2508 
2509  if (rdev->irq.crtc_vblank_int[0] ||
2510  atomic_read(&rdev->irq.pflip[0])) {
2511  DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2512  crtc1 |= VBLANK_INT_MASK;
2513  }
2514  if (rdev->irq.crtc_vblank_int[1] ||
2515  atomic_read(&rdev->irq.pflip[1])) {
2516  DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2517  crtc2 |= VBLANK_INT_MASK;
2518  }
2519  if (rdev->irq.crtc_vblank_int[2] ||
2520  atomic_read(&rdev->irq.pflip[2])) {
2521  DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2522  crtc3 |= VBLANK_INT_MASK;
2523  }
2524  if (rdev->irq.crtc_vblank_int[3] ||
2525  atomic_read(&rdev->irq.pflip[3])) {
2526  DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2527  crtc4 |= VBLANK_INT_MASK;
2528  }
2529  if (rdev->irq.crtc_vblank_int[4] ||
2530  atomic_read(&rdev->irq.pflip[4])) {
2531  DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2532  crtc5 |= VBLANK_INT_MASK;
2533  }
2534  if (rdev->irq.crtc_vblank_int[5] ||
2535  atomic_read(&rdev->irq.pflip[5])) {
2536  DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2537  crtc6 |= VBLANK_INT_MASK;
2538  }
2539  if (rdev->irq.hpd[0]) {
2540  DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2541  hpd1 |= DC_HPDx_INT_EN;
2542  }
2543  if (rdev->irq.hpd[1]) {
2544  DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2545  hpd2 |= DC_HPDx_INT_EN;
2546  }
2547  if (rdev->irq.hpd[2]) {
2548  DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2549  hpd3 |= DC_HPDx_INT_EN;
2550  }
2551  if (rdev->irq.hpd[3]) {
2552  DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2553  hpd4 |= DC_HPDx_INT_EN;
2554  }
2555  if (rdev->irq.hpd[4]) {
2556  DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2557  hpd5 |= DC_HPDx_INT_EN;
2558  }
2559  if (rdev->irq.hpd[5]) {
2560  DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2561  hpd6 |= DC_HPDx_INT_EN;
2562  }
2563  if (rdev->irq.afmt[0]) {
2564  DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2565  afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2566  }
2567  if (rdev->irq.afmt[1]) {
2568  DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2569  afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2570  }
2571  if (rdev->irq.afmt[2]) {
2572  DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2573  afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2574  }
2575  if (rdev->irq.afmt[3]) {
2576  DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2577  afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2578  }
2579  if (rdev->irq.afmt[4]) {
2580  DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2581  afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2582  }
2583  if (rdev->irq.afmt[5]) {
2584  DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2585  afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2586  }
2587 
2588  if (rdev->family >= CHIP_CAYMAN) {
2589  cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2590  cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2591  cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2592  } else
2593  WREG32(CP_INT_CNTL, cp_int_cntl);
2594  WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2595 
2596  WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2597  WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2598  if (rdev->num_crtc >= 4) {
2599  WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2600  WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2601  }
2602  if (rdev->num_crtc >= 6) {
2603  WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2604  WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2605  }
2606 
2607  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2608  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2609  if (rdev->num_crtc >= 4) {
2610  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2611  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2612  }
2613  if (rdev->num_crtc >= 6) {
2614  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2615  WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2616  }
2617 
2618  WREG32(DC_HPD1_INT_CONTROL, hpd1);
2619  WREG32(DC_HPD2_INT_CONTROL, hpd2);
2620  WREG32(DC_HPD3_INT_CONTROL, hpd3);
2621  WREG32(DC_HPD4_INT_CONTROL, hpd4);
2622  WREG32(DC_HPD5_INT_CONTROL, hpd5);
2623  WREG32(DC_HPD6_INT_CONTROL, hpd6);
2624 
2625  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2626  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2627  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2628  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2629  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2630  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2631 
2632  return 0;
2633 }
2634 
2635 static void evergreen_irq_ack(struct radeon_device *rdev)
2636 {
2637  u32 tmp;
2638 
2639  rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2640  rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2641  rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2642  rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2643  rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2644  rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2645  rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2646  rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2647  if (rdev->num_crtc >= 4) {
2648  rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2649  rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2650  }
2651  if (rdev->num_crtc >= 6) {
2652  rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2653  rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2654  }
2655 
2656  rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2657  rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2658  rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2659  rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2660  rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2661  rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2662 
2663  if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2664  WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2665  if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2666  WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2667  if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2668  WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2669  if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2670  WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2671  if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2672  WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2673  if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2674  WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2675 
2676  if (rdev->num_crtc >= 4) {
2677  if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2678  WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2679  if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2680  WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2681  if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2682  WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2683  if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2684  WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2685  if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2686  WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2687  if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2688  WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2689  }
2690 
2691  if (rdev->num_crtc >= 6) {
2692  if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2693  WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2694  if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2695  WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2696  if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2697  WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2698  if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2699  WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2700  if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2701  WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2702  if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2703  WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2704  }
2705 
2706  if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2707  tmp = RREG32(DC_HPD1_INT_CONTROL);
2708  tmp |= DC_HPDx_INT_ACK;
2709  WREG32(DC_HPD1_INT_CONTROL, tmp);
2710  }
2711  if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2712  tmp = RREG32(DC_HPD2_INT_CONTROL);
2713  tmp |= DC_HPDx_INT_ACK;
2714  WREG32(DC_HPD2_INT_CONTROL, tmp);
2715  }
2716  if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2717  tmp = RREG32(DC_HPD3_INT_CONTROL);
2718  tmp |= DC_HPDx_INT_ACK;
2719  WREG32(DC_HPD3_INT_CONTROL, tmp);
2720  }
2721  if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2722  tmp = RREG32(DC_HPD4_INT_CONTROL);
2723  tmp |= DC_HPDx_INT_ACK;
2724  WREG32(DC_HPD4_INT_CONTROL, tmp);
2725  }
2726  if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2727  tmp = RREG32(DC_HPD5_INT_CONTROL);
2728  tmp |= DC_HPDx_INT_ACK;
2729  WREG32(DC_HPD5_INT_CONTROL, tmp);
2730  }
2731  if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2732  tmp = RREG32(DC_HPD5_INT_CONTROL);
2733  tmp |= DC_HPDx_INT_ACK;
2734  WREG32(DC_HPD6_INT_CONTROL, tmp);
2735  }
2736  if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2737  tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2738  tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2739  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2740  }
2741  if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2742  tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2743  tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2744  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2745  }
2746  if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2747  tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2748  tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2749  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2750  }
2751  if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2752  tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2753  tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2754  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2755  }
2756  if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2757  tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2758  tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2759  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2760  }
2761  if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2762  tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2763  tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2764  WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2765  }
2766 }
2767 
2768 static void evergreen_irq_disable(struct radeon_device *rdev)
2769 {
2770  r600_disable_interrupts(rdev);
2771  /* Wait and acknowledge irq */
2772  mdelay(1);
2773  evergreen_irq_ack(rdev);
2774  evergreen_disable_interrupt_state(rdev);
2775 }
2776 
2777 void evergreen_irq_suspend(struct radeon_device *rdev)
2778 {
2779  evergreen_irq_disable(rdev);
2780  r600_rlc_stop(rdev);
2781 }
2782 
2783 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2784 {
2785  u32 wptr, tmp;
2786 
2787  if (rdev->wb.enabled)
2788  wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2789  else
2790  wptr = RREG32(IH_RB_WPTR);
2791 
2792  if (wptr & RB_OVERFLOW) {
2793  /* When a ring buffer overflow happen start parsing interrupt
2794  * from the last not overwritten vector (wptr + 16). Hopefully
2795  * this should allow us to catchup.
2796  */
2797  dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2798  wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2799  rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2800  tmp = RREG32(IH_RB_CNTL);
2801  tmp |= IH_WPTR_OVERFLOW_CLEAR;
2802  WREG32(IH_RB_CNTL, tmp);
2803  }
2804  return (wptr & rdev->ih.ptr_mask);
2805 }
2806 
2807 int evergreen_irq_process(struct radeon_device *rdev)
2808 {
2809  u32 wptr;
2810  u32 rptr;
2811  u32 src_id, src_data;
2812  u32 ring_index;
2813  bool queue_hotplug = false;
2814  bool queue_hdmi = false;
2815 
2816  if (!rdev->ih.enabled || rdev->shutdown)
2817  return IRQ_NONE;
2818 
2819  wptr = evergreen_get_ih_wptr(rdev);
2820 
2821 restart_ih:
2822  /* is somebody else already processing irqs? */
2823  if (atomic_xchg(&rdev->ih.lock, 1))
2824  return IRQ_NONE;
2825 
2826  rptr = rdev->ih.rptr;
2827  DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2828 
2829  /* Order reading of wptr vs. reading of IH ring data */
2830  rmb();
2831 
2832  /* display interrupts */
2833  evergreen_irq_ack(rdev);
2834 
2835  while (rptr != wptr) {
2836  /* wptr/rptr are in bytes! */
2837  ring_index = rptr / 4;
2838  src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2839  src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2840 
2841  switch (src_id) {
2842  case 1: /* D1 vblank/vline */
2843  switch (src_data) {
2844  case 0: /* D1 vblank */
2845  if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2846  if (rdev->irq.crtc_vblank_int[0]) {
2847  drm_handle_vblank(rdev->ddev, 0);
2848  rdev->pm.vblank_sync = true;
2849  wake_up(&rdev->irq.vblank_queue);
2850  }
2851  if (atomic_read(&rdev->irq.pflip[0]))
2852  radeon_crtc_handle_flip(rdev, 0);
2853  rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2854  DRM_DEBUG("IH: D1 vblank\n");
2855  }
2856  break;
2857  case 1: /* D1 vline */
2858  if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2859  rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2860  DRM_DEBUG("IH: D1 vline\n");
2861  }
2862  break;
2863  default:
2864  DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2865  break;
2866  }
2867  break;
2868  case 2: /* D2 vblank/vline */
2869  switch (src_data) {
2870  case 0: /* D2 vblank */
2871  if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2872  if (rdev->irq.crtc_vblank_int[1]) {
2873  drm_handle_vblank(rdev->ddev, 1);
2874  rdev->pm.vblank_sync = true;
2875  wake_up(&rdev->irq.vblank_queue);
2876  }
2877  if (atomic_read(&rdev->irq.pflip[1]))
2878  radeon_crtc_handle_flip(rdev, 1);
2879  rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2880  DRM_DEBUG("IH: D2 vblank\n");
2881  }
2882  break;
2883  case 1: /* D2 vline */
2884  if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2885  rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2886  DRM_DEBUG("IH: D2 vline\n");
2887  }
2888  break;
2889  default:
2890  DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2891  break;
2892  }
2893  break;
2894  case 3: /* D3 vblank/vline */
2895  switch (src_data) {
2896  case 0: /* D3 vblank */
2897  if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2898  if (rdev->irq.crtc_vblank_int[2]) {
2899  drm_handle_vblank(rdev->ddev, 2);
2900  rdev->pm.vblank_sync = true;
2901  wake_up(&rdev->irq.vblank_queue);
2902  }
2903  if (atomic_read(&rdev->irq.pflip[2]))
2904  radeon_crtc_handle_flip(rdev, 2);
2905  rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2906  DRM_DEBUG("IH: D3 vblank\n");
2907  }
2908  break;
2909  case 1: /* D3 vline */
2910  if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2911  rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2912  DRM_DEBUG("IH: D3 vline\n");
2913  }
2914  break;
2915  default:
2916  DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2917  break;
2918  }
2919  break;
2920  case 4: /* D4 vblank/vline */
2921  switch (src_data) {
2922  case 0: /* D4 vblank */
2923  if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2924  if (rdev->irq.crtc_vblank_int[3]) {
2925  drm_handle_vblank(rdev->ddev, 3);
2926  rdev->pm.vblank_sync = true;
2927  wake_up(&rdev->irq.vblank_queue);
2928  }
2929  if (atomic_read(&rdev->irq.pflip[3]))
2930  radeon_crtc_handle_flip(rdev, 3);
2931  rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2932  DRM_DEBUG("IH: D4 vblank\n");
2933  }
2934  break;
2935  case 1: /* D4 vline */
2936  if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2937  rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2938  DRM_DEBUG("IH: D4 vline\n");
2939  }
2940  break;
2941  default:
2942  DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2943  break;
2944  }
2945  break;
2946  case 5: /* D5 vblank/vline */
2947  switch (src_data) {
2948  case 0: /* D5 vblank */
2949  if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2950  if (rdev->irq.crtc_vblank_int[4]) {
2951  drm_handle_vblank(rdev->ddev, 4);
2952  rdev->pm.vblank_sync = true;
2953  wake_up(&rdev->irq.vblank_queue);
2954  }
2955  if (atomic_read(&rdev->irq.pflip[4]))
2956  radeon_crtc_handle_flip(rdev, 4);
2957  rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2958  DRM_DEBUG("IH: D5 vblank\n");
2959  }
2960  break;
2961  case 1: /* D5 vline */
2962  if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2963  rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2964  DRM_DEBUG("IH: D5 vline\n");
2965  }
2966  break;
2967  default:
2968  DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2969  break;
2970  }
2971  break;
2972  case 6: /* D6 vblank/vline */
2973  switch (src_data) {
2974  case 0: /* D6 vblank */
2975  if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2976  if (rdev->irq.crtc_vblank_int[5]) {
2977  drm_handle_vblank(rdev->ddev, 5);
2978  rdev->pm.vblank_sync = true;
2979  wake_up(&rdev->irq.vblank_queue);
2980  }
2981  if (atomic_read(&rdev->irq.pflip[5]))
2982  radeon_crtc_handle_flip(rdev, 5);
2983  rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2984  DRM_DEBUG("IH: D6 vblank\n");
2985  }
2986  break;
2987  case 1: /* D6 vline */
2988  if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2989  rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2990  DRM_DEBUG("IH: D6 vline\n");
2991  }
2992  break;
2993  default:
2994  DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2995  break;
2996  }
2997  break;
2998  case 42: /* HPD hotplug */
2999  switch (src_data) {
3000  case 0:
3001  if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3002  rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3003  queue_hotplug = true;
3004  DRM_DEBUG("IH: HPD1\n");
3005  }
3006  break;
3007  case 1:
3008  if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3009  rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3010  queue_hotplug = true;
3011  DRM_DEBUG("IH: HPD2\n");
3012  }
3013  break;
3014  case 2:
3015  if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3016  rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3017  queue_hotplug = true;
3018  DRM_DEBUG("IH: HPD3\n");
3019  }
3020  break;
3021  case 3:
3022  if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3023  rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3024  queue_hotplug = true;
3025  DRM_DEBUG("IH: HPD4\n");
3026  }
3027  break;
3028  case 4:
3029  if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3030  rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3031  queue_hotplug = true;
3032  DRM_DEBUG("IH: HPD5\n");
3033  }
3034  break;
3035  case 5:
3036  if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3037  rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3038  queue_hotplug = true;
3039  DRM_DEBUG("IH: HPD6\n");
3040  }
3041  break;
3042  default:
3043  DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3044  break;
3045  }
3046  break;
3047  case 44: /* hdmi */
3048  switch (src_data) {
3049  case 0:
3050  if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3051  rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3052  queue_hdmi = true;
3053  DRM_DEBUG("IH: HDMI0\n");
3054  }
3055  break;
3056  case 1:
3057  if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3058  rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3059  queue_hdmi = true;
3060  DRM_DEBUG("IH: HDMI1\n");
3061  }
3062  break;
3063  case 2:
3064  if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3065  rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3066  queue_hdmi = true;
3067  DRM_DEBUG("IH: HDMI2\n");
3068  }
3069  break;
3070  case 3:
3071  if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3072  rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3073  queue_hdmi = true;
3074  DRM_DEBUG("IH: HDMI3\n");
3075  }
3076  break;
3077  case 4:
3078  if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3079  rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3080  queue_hdmi = true;
3081  DRM_DEBUG("IH: HDMI4\n");
3082  }
3083  break;
3084  case 5:
3085  if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3086  rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3087  queue_hdmi = true;
3088  DRM_DEBUG("IH: HDMI5\n");
3089  }
3090  break;
3091  default:
3092  DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3093  break;
3094  }
3095  break;
3096  case 176: /* CP_INT in ring buffer */
3097  case 177: /* CP_INT in IB1 */
3098  case 178: /* CP_INT in IB2 */
3099  DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3100  radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3101  break;
3102  case 181: /* CP EOP event */
3103  DRM_DEBUG("IH: CP EOP\n");
3104  if (rdev->family >= CHIP_CAYMAN) {
3105  switch (src_data) {
3106  case 0:
3107  radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3108  break;
3109  case 1:
3110  radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3111  break;
3112  case 2:
3113  radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3114  break;
3115  }
3116  } else
3117  radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3118  break;
3119  case 233: /* GUI IDLE */
3120  DRM_DEBUG("IH: GUI idle\n");
3121  break;
3122  default:
3123  DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3124  break;
3125  }
3126 
3127  /* wptr/rptr are in bytes! */
3128  rptr += 16;
3129  rptr &= rdev->ih.ptr_mask;
3130  }
3131  if (queue_hotplug)
3132  schedule_work(&rdev->hotplug_work);
3133  if (queue_hdmi)
3134  schedule_work(&rdev->audio_work);
3135  rdev->ih.rptr = rptr;
3136  WREG32(IH_RB_RPTR, rdev->ih.rptr);
3137  atomic_set(&rdev->ih.lock, 0);
3138 
3139  /* make sure wptr hasn't changed while processing */
3140  wptr = evergreen_get_ih_wptr(rdev);
3141  if (wptr != rptr)
3142  goto restart_ih;
3143 
3144  return IRQ_HANDLED;
3145 }
3146 
3147 static int evergreen_startup(struct radeon_device *rdev)
3148 {
3149  struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3150  int r;
3151 
3152  /* enable pcie gen2 link */
3153  evergreen_pcie_gen2_enable(rdev);
3154 
3155  if (ASIC_IS_DCE5(rdev)) {
3156  if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3157  r = ni_init_microcode(rdev);
3158  if (r) {
3159  DRM_ERROR("Failed to load firmware!\n");
3160  return r;
3161  }
3162  }
3163  r = ni_mc_load_microcode(rdev);
3164  if (r) {
3165  DRM_ERROR("Failed to load MC firmware!\n");
3166  return r;
3167  }
3168  } else {
3169  if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3170  r = r600_init_microcode(rdev);
3171  if (r) {
3172  DRM_ERROR("Failed to load firmware!\n");
3173  return r;
3174  }
3175  }
3176  }
3177 
3178  r = r600_vram_scratch_init(rdev);
3179  if (r)
3180  return r;
3181 
3182  evergreen_mc_program(rdev);
3183  if (rdev->flags & RADEON_IS_AGP) {
3184  evergreen_agp_enable(rdev);
3185  } else {
3186  r = evergreen_pcie_gart_enable(rdev);
3187  if (r)
3188  return r;
3189  }
3190  evergreen_gpu_init(rdev);
3191 
3192  r = evergreen_blit_init(rdev);
3193  if (r) {
3194  r600_blit_fini(rdev);
3195  rdev->asic->copy.copy = NULL;
3196  dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3197  }
3198 
3199  /* allocate wb buffer */
3200  r = radeon_wb_init(rdev);
3201  if (r)
3202  return r;
3203 
3204  r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3205  if (r) {
3206  dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3207  return r;
3208  }
3209 
3210  /* Enable IRQ */
3211  r = r600_irq_init(rdev);
3212  if (r) {
3213  DRM_ERROR("radeon: IH init failed (%d).\n", r);
3214  radeon_irq_kms_fini(rdev);
3215  return r;
3216  }
3217  evergreen_irq_set(rdev);
3218 
3219  r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3220  R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3221  0, 0xfffff, RADEON_CP_PACKET2);
3222  if (r)
3223  return r;
3224  r = evergreen_cp_load_microcode(rdev);
3225  if (r)
3226  return r;
3227  r = evergreen_cp_resume(rdev);
3228  if (r)
3229  return r;
3230 
3231  r = radeon_ib_pool_init(rdev);
3232  if (r) {
3233  dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3234  return r;
3235  }
3236 
3237  r = r600_audio_init(rdev);
3238  if (r) {
3239  DRM_ERROR("radeon: audio init failed\n");
3240  return r;
3241  }
3242 
3243  return 0;
3244 }
3245 
3246 int evergreen_resume(struct radeon_device *rdev)
3247 {
3248  int r;
3249 
3250  /* reset the asic, the gfx blocks are often in a bad state
3251  * after the driver is unloaded or after a resume
3252  */
3253  if (radeon_asic_reset(rdev))
3254  dev_warn(rdev->dev, "GPU reset failed !\n");
3255  /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3256  * posting will perform necessary task to bring back GPU into good
3257  * shape.
3258  */
3259  /* post card */
3260  atom_asic_init(rdev->mode_info.atom_context);
3261 
3262  rdev->accel_working = true;
3263  r = evergreen_startup(rdev);
3264  if (r) {
3265  DRM_ERROR("evergreen startup failed on resume\n");
3266  rdev->accel_working = false;
3267  return r;
3268  }
3269 
3270  return r;
3271 
3272 }
3273 
3274 int evergreen_suspend(struct radeon_device *rdev)
3275 {
3276  struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3277 
3278  r600_audio_fini(rdev);
3279  r700_cp_stop(rdev);
3280  ring->ready = false;
3281  evergreen_irq_suspend(rdev);
3282  radeon_wb_disable(rdev);
3283  evergreen_pcie_gart_disable(rdev);
3284 
3285  return 0;
3286 }
3287 
3288 /* Plan is to move initialization in that function and use
3289  * helper function so that radeon_device_init pretty much
3290  * do nothing more than calling asic specific function. This
3291  * should also allow to remove a bunch of callback function
3292  * like vram_info.
3293  */
3294 int evergreen_init(struct radeon_device *rdev)
3295 {
3296  int r;
3297 
3298  /* Read BIOS */
3299  if (!radeon_get_bios(rdev)) {
3300  if (ASIC_IS_AVIVO(rdev))
3301  return -EINVAL;
3302  }
3303  /* Must be an ATOMBIOS */
3304  if (!rdev->is_atom_bios) {
3305  dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3306  return -EINVAL;
3307  }
3308  r = radeon_atombios_init(rdev);
3309  if (r)
3310  return r;
3311  /* reset the asic, the gfx blocks are often in a bad state
3312  * after the driver is unloaded or after a resume
3313  */
3314  if (radeon_asic_reset(rdev))
3315  dev_warn(rdev->dev, "GPU reset failed !\n");
3316  /* Post card if necessary */
3317  if (!radeon_card_posted(rdev)) {
3318  if (!rdev->bios) {
3319  dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3320  return -EINVAL;
3321  }
3322  DRM_INFO("GPU not posted. posting now...\n");
3323  atom_asic_init(rdev->mode_info.atom_context);
3324  }
3325  /* Initialize scratch registers */
3326  r600_scratch_init(rdev);
3327  /* Initialize surface registers */
3328  radeon_surface_init(rdev);
3329  /* Initialize clocks */
3330  radeon_get_clock_info(rdev->ddev);
3331  /* Fence driver */
3332  r = radeon_fence_driver_init(rdev);
3333  if (r)
3334  return r;
3335  /* initialize AGP */
3336  if (rdev->flags & RADEON_IS_AGP) {
3337  r = radeon_agp_init(rdev);
3338  if (r)
3339  radeon_agp_disable(rdev);
3340  }
3341  /* initialize memory controller */
3342  r = evergreen_mc_init(rdev);
3343  if (r)
3344  return r;
3345  /* Memory manager */
3346  r = radeon_bo_init(rdev);
3347  if (r)
3348  return r;
3349 
3350  r = radeon_irq_kms_init(rdev);
3351  if (r)
3352  return r;
3353 
3354  rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3355  r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3356 
3357  rdev->ih.ring_obj = NULL;
3358  r600_ih_ring_init(rdev, 64 * 1024);
3359 
3360  r = r600_pcie_gart_init(rdev);
3361  if (r)
3362  return r;
3363 
3364  rdev->accel_working = true;
3365  r = evergreen_startup(rdev);
3366  if (r) {
3367  dev_err(rdev->dev, "disabling GPU acceleration\n");
3368  r700_cp_fini(rdev);
3369  r600_irq_fini(rdev);
3370  radeon_wb_fini(rdev);
3371  radeon_ib_pool_fini(rdev);
3372  radeon_irq_kms_fini(rdev);
3373  evergreen_pcie_gart_fini(rdev);
3374  rdev->accel_working = false;
3375  }
3376 
3377  /* Don't start up if the MC ucode is missing on BTC parts.
3378  * The default clocks and voltages before the MC ucode
3379  * is loaded are not suffient for advanced operations.
3380  */
3381  if (ASIC_IS_DCE5(rdev)) {
3382  if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3383  DRM_ERROR("radeon: MC ucode required for NI+.\n");
3384  return -EINVAL;
3385  }
3386  }
3387 
3388  return 0;
3389 }
3390 
3391 void evergreen_fini(struct radeon_device *rdev)
3392 {
3393  r600_audio_fini(rdev);
3394  r600_blit_fini(rdev);
3395  r700_cp_fini(rdev);
3396  r600_irq_fini(rdev);
3397  radeon_wb_fini(rdev);
3398  radeon_ib_pool_fini(rdev);
3399  radeon_irq_kms_fini(rdev);
3400  evergreen_pcie_gart_fini(rdev);
3401  r600_vram_scratch_fini(rdev);
3402  radeon_gem_fini(rdev);
3403  radeon_fence_driver_fini(rdev);
3404  radeon_agp_fini(rdev);
3405  radeon_bo_fini(rdev);
3406  radeon_atombios_fini(rdev);
3407  kfree(rdev->bios);
3408  rdev->bios = NULL;
3409 }
3410 
3411 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3412 {
3413  u32 link_width_cntl, speed_cntl, mask;
3414  int ret;
3415 
3416  if (radeon_pcie_gen2 == 0)
3417  return;
3418 
3419  if (rdev->flags & RADEON_IS_IGP)
3420  return;
3421 
3422  if (!(rdev->flags & RADEON_IS_PCIE))
3423  return;
3424 
3425  /* x2 cards have a special sequence */
3426  if (ASIC_IS_X2(rdev))
3427  return;
3428 
3429  ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3430  if (ret != 0)
3431  return;
3432 
3433  if (!(mask & DRM_PCIE_SPEED_50))
3434  return;
3435 
3436  speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3437  if (speed_cntl & LC_CURRENT_DATA_RATE) {
3438  DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3439  return;
3440  }
3441 
3442  DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3443 
3444  if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3445  (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3446 
3447  link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3448  link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3449  WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3450 
3451  speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3452  speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3453  WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3454 
3455  speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3456  speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3457  WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3458 
3459  speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3460  speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3461  WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3462 
3463  speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3464  speed_cntl |= LC_GEN2_EN_STRAP;
3465  WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3466 
3467  } else {
3468  link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3469  /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3470  if (1)
3471  link_width_cntl |= LC_UPCONFIGURE_DIS;
3472  else
3473  link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3474  WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3475  }
3476 }
Generated on Thu Jan 10 2013 13:33:05 for Linux Kernel by   doxygen 1.8.2