#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mod_devicetable.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/scatterlist.h>
#include <linux/highmem.h>
#include <linux/crypto.h>
#include <linux/hw_random.h>
#include <linux/ktime.h>
#include <crypto/algapi.h>
#include <crypto/des.h>
#include <asm/kmap_types.h>

Data Structures
struct	hifn_desc

struct	hifn_dma

struct	hifn_device

struct	hifn_base_command

struct	hifn_crypt_command

struct	hifn_mac_command

struct	hifn_comp_command

struct	hifn_base_result

struct	hifn_comp_result

struct	hifn_mac_result

struct	hifn_crypt_result

struct	hifn_crypto_alg

struct	hifn_cipher_walk

struct	hifn_context

struct	hifn_request_context

struct	pci2id

struct	hifn_alg_template

Macros
#define	dprintk(f, a...) do {} while (0)

#define	ACRYPTO_OP_DECRYPT 0

#define	ACRYPTO_OP_ENCRYPT 1

#define	ACRYPTO_OP_HMAC 2

#define	ACRYPTO_OP_RNG 3

#define	ACRYPTO_MODE_ECB 0

#define	ACRYPTO_MODE_CBC 1

#define	ACRYPTO_MODE_CFB 2

#define	ACRYPTO_MODE_OFB 3

#define	ACRYPTO_TYPE_AES_128 0

#define	ACRYPTO_TYPE_AES_192 1

#define	ACRYPTO_TYPE_AES_256 2

#define	ACRYPTO_TYPE_3DES 3

#define	ACRYPTO_TYPE_DES 4

#define	PCI_VENDOR_ID_HIFN 0x13A3

#define	PCI_DEVICE_ID_HIFN_7955 0x0020

#define	PCI_DEVICE_ID_HIFN_7956 0x001d

#define	HIFN_BAR0_SIZE 0x1000

#define	HIFN_BAR1_SIZE 0x2000

#define	HIFN_BAR2_SIZE 0x8000

#define	HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */

#define	HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */

#define	HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */

#define	HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */

#define	HIFN_DMA_STCTL 0x40 /* DMA Status and Control */

#define	HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */

#define	HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */

#define	HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */

#define	HIFN_CHIP_ID 0x98 /* Chip ID */

#define	HIFN_0_PUDATA 0x00 /* Processing Unit Data */

#define	HIFN_0_PUCTRL 0x04 /* Processing Unit Control */

#define	HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */

#define	HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */

#define	HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */

#define	HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */

#define	HIFN_0_FIFOSTAT 0x18 /* FIFO Status */

#define	HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */

#define	HIFN_0_SPACESIZE 0x20 /* Register space size */

#define	HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */

#define	HIFN_PUCTRL_STOP 0x0008 /* stop pu */

#define	HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */

#define	HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */

#define	HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */

#define	HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */

#define	HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */

#define	HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */

#define	HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */

#define	HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */

#define	HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */

#define	HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */

#define	HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */

#define	HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */

#define	HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */

#define	HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */

#define	HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */

#define	HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */

#define	HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */

#define	HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */

#define	HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */

#define	HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */

#define	HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */

#define	HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */

#define	HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */

#define	HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */

#define	HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */

#define	HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */

#define	HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */

#define	HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */

#define	HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */

#define	HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */

#define	HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */

#define	HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */

#define	HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */

#define	HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */

#define	HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */

#define	HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */

#define	HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */

#define	HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */

#define	HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */

#define	HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */

#define	HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */

#define	HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */

#define	HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */

#define	HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */

#define	HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */

#define	HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */

#define	HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */

#define	HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */

#define	HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */

#define	HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */

#define	HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */

#define	HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */

#define	HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */

#define	HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */

#define	HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */

#define	HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */

#define	HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */

#define	HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */

#define	HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */

#define	HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */

#define	HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */

#define	HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */

#define	HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */

#define	HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */

#define	HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */

#define	HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */

#define	HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */

#define	HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */

#define	HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */

#define	HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */

#define	HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */

#define	HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */

#define	HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */

#define	HIFN_1_PLL 0x4c /* 795x: PLL config */

#define	HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */

#define	HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */

#define	HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */

#define	HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */

#define	HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */

#define	HIFN_1_REVID 0x98 /* Revision ID */

#define	HIFN_1_UNLOCK_SECRET1 0xf4

#define	HIFN_1_UNLOCK_SECRET2 0xfc

#define	HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */

#define	HIFN_1_PUB_BASE 0x300 /* Public Base Address */

#define	HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */

#define	HIFN_1_PUB_OP 0x308 /* Public Operand */

#define	HIFN_1_PUB_STATUS 0x30c /* Public Status */

#define	HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */

#define	HIFN_1_RNG_CONFIG 0x314 /* RNG config */

#define	HIFN_1_RNG_DATA 0x318 /* RNG data */

#define	HIFN_1_PUB_MEM 0x400 /* start of Public key memory */

#define	HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */

#define	HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */

#define	HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */

#define	HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */

#define	HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */

#define	HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */

#define	HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */

#define	HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */

#define	HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */

#define	HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */

#define	HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */

#define	HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */

#define	HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */

#define	HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */

#define	HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */

#define	HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */

#define	HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */

#define	HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */

#define	HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */

#define	HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */

#define	HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */

#define	HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */

#define	HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */

#define	HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */

#define	HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */

#define	HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */

#define	HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */

#define	HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */

#define	HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */

#define	HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */

#define	HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */

#define	HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */

#define	HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */

#define	HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */

#define	HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */

#define	HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */

#define	HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */

#define	HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */

#define	HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */

#define	HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */

#define	HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */

#define	HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */

#define	HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */

#define	HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */

#define	HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */

#define	HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */

#define	HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */

#define	HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */

#define	HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */

#define	HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */

#define	HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */

#define	HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */

#define	HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */

#define	HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */

#define	HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */

#define	HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */

#define	HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */

#define	HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */

#define	HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */

#define	HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */

#define	HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */

#define	HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */

#define	HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */

#define	HIFN_DMACNFG_UNLOCK 0x00000800

#define	HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */

#define	HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */

#define	HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */

#define	HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */

#define	HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */

#define	HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */

#define	HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */

#define	HIFN_PLL_BP 0x00000002 /* Reference clock bypass */

#define	HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */

#define	HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */

#define	HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */

#define	HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */

#define	HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */

#define	HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */

#define	HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */

#define	HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */

#define	HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */

#define	HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */

#define	HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */

#define	HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */

#define	HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */

#define	HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */

#define	HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */

#define	HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */

#define	HIFN_PUBBASE_ADDR 0x00003fff /* base address */

#define	HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */

#define	HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */

#define	HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */

#define	HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */

#define	HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */

#define	HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */

#define	HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */

#define	HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */

#define	HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */

#define	HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */

#define	HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */

#define	HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */

#define	HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */

#define	HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */

#define	HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */

#define	HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */

#define	HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */

#define	HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */

#define	HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */

#define	HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */

#define	HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */

#define	HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */

#define	HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */

#define	HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */

#define	HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */

#define	HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */

#define	HIFN_PUBSTS_DONE 0x00000001 /* operation done */

#define	HIFN_PUBSTS_CARRY 0x00000002 /* carry */

#define	HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */

#define	HIFN_RNGCFG_ENA 0x00000001 /* enable rng */

#define	HIFN_NAMESIZE 32

#define	HIFN_MAX_RESULT_ORDER 5

#define	HIFN_D_CMD_RSIZE 24*1

#define	HIFN_D_SRC_RSIZE 80*1

#define	HIFN_D_DST_RSIZE 80*1

#define	HIFN_D_RES_RSIZE 24*1

#define	HIFN_D_DST_DALIGN 4

#define	HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1)

#define	AES_MIN_KEY_SIZE 16

#define	AES_MAX_KEY_SIZE 32

#define	HIFN_DES_KEY_LENGTH 8

#define	HIFN_3DES_KEY_LENGTH 24

#define	HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE

#define	HIFN_IV_LENGTH 8

#define	HIFN_AES_IV_LENGTH 16

#define	HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH

#define	HIFN_MAC_KEY_LENGTH 64

#define	HIFN_MD5_LENGTH 16

#define	HIFN_SHA1_LENGTH 20

#define	HIFN_MAC_TRUNC_LENGTH 12

#define	HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)

#define	HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)

#define	HIFN_USED_RESULT 12

#define	HIFN_FLAG_CMD_BUSY (1<<0)

#define	HIFN_FLAG_SRC_BUSY (1<<1)

#define	HIFN_FLAG_DST_BUSY (1<<2)

#define	HIFN_FLAG_RES_BUSY (1<<3)

#define	HIFN_FLAG_OLD_KEY (1<<4)

#define	HIFN_DEFAULT_ACTIVE_NUM 5

#define	HIFN_D_LENGTH 0x0000ffff

#define	HIFN_D_NOINVALID 0x01000000

#define	HIFN_D_MASKDONEIRQ 0x02000000

#define	HIFN_D_DESTOVER 0x04000000

#define	HIFN_D_OVER 0x08000000

#define	HIFN_D_LAST 0x20000000

#define	HIFN_D_JUMP 0x40000000

#define	HIFN_D_VALID 0x80000000

#define	HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */

#define	HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */

#define	HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */

#define	HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */

#define	HIFN_BASE_CMD_DECODE 0x2000

#define	HIFN_BASE_CMD_SRCLEN_M 0xc000

#define	HIFN_BASE_CMD_SRCLEN_S 14

#define	HIFN_BASE_CMD_DSTLEN_M 0x3000

#define	HIFN_BASE_CMD_DSTLEN_S 12

#define	HIFN_BASE_CMD_LENMASK_HI 0x30000

#define	HIFN_BASE_CMD_LENMASK_LO 0x0ffff

#define	HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */

#define	HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */

#define	HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */

#define	HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */

#define	HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */

#define	HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */

#define	HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */

#define	HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */

#define	HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */

#define	HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */

#define	HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */

#define	HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */

#define	HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */

#define	HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */

#define	HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */

#define	HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */

#define	HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */

#define	HIFN_CRYPT_CMD_SRCLEN_M 0xc000

#define	HIFN_CRYPT_CMD_SRCLEN_S 14

#define	HIFN_MAC_CMD_ALG_MASK 0x0001

#define	HIFN_MAC_CMD_ALG_SHA1 0x0000

#define	HIFN_MAC_CMD_ALG_MD5 0x0001

#define	HIFN_MAC_CMD_MODE_MASK 0x000c

#define	HIFN_MAC_CMD_MODE_HMAC 0x0000

#define	HIFN_MAC_CMD_MODE_SSL_MAC 0x0004

#define	HIFN_MAC_CMD_MODE_HASH 0x0008

#define	HIFN_MAC_CMD_MODE_FULL 0x0004

#define	HIFN_MAC_CMD_TRUNC 0x0010

#define	HIFN_MAC_CMD_RESULT 0x0020

#define	HIFN_MAC_CMD_APPEND 0x0040

#define	HIFN_MAC_CMD_SRCLEN_M 0xc000

#define	HIFN_MAC_CMD_SRCLEN_S 14

#define	HIFN_MAC_CMD_POS_IPSEC 0x0200

#define	HIFN_MAC_CMD_NEW_KEY 0x0800

#define	HIFN_COMP_CMD_SRCLEN_M 0xc000

#define	HIFN_COMP_CMD_SRCLEN_S 14

#define	HIFN_COMP_CMD_ONE 0x0100 /* must be one */

#define	HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */

#define	HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */

#define	HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */

#define	HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */

#define	HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */

#define	HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */

#define	HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */

#define	HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */

#define	HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */

#define	HIFN_BASE_RES_SRCLEN_S 14

#define	HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */

#define	HIFN_BASE_RES_DSTLEN_S 12

#define	HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */

#define	HIFN_COMP_RES_LCB_S 8

#define	HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */

#define	HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */

#define	HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */

#define	HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */

#define	HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */

#define	HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */

#define	HIFN_POLL_FREQUENCY 0x1

#define	HIFN_POLL_SCALAR 0x0

#define	HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */

#define	HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */

#define	ASYNC_SCATTERLIST_CACHE 16

#define	ASYNC_FLAGS_MISALIGNED (1<<0)

#define	crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg)

#define	hifn_register_rng(dev) 0

#define	hifn_unregister_rng(dev)

Functions
	module_param_string (hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444)

	MODULE_PARM_DESC (hifn_pll_ref,"PLL reference clock (pci[freq] or ext[freq], default ext)")

	MODULE_DEVICE_TABLE (pci, hifn_pci_tbl)

	module_init (hifn_init)

	module_exit (hifn_fini)

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Evgeniy Polyakov <[email protected]>")

	MODULE_DESCRIPTION ("Driver for HIFN 795x crypto accelerator chip.")

Macro Definition Documentation

#define ACRYPTO_MODE_CBC 1

Definition at line 62 of file hifn_795x.c.

#define ACRYPTO_MODE_CFB 2

Definition at line 63 of file hifn_795x.c.

#define ACRYPTO_MODE_ECB 0

Definition at line 61 of file hifn_795x.c.

#define ACRYPTO_MODE_OFB 3

Definition at line 64 of file hifn_795x.c.

#define ACRYPTO_OP_DECRYPT 0

Definition at line 56 of file hifn_795x.c.

#define ACRYPTO_OP_ENCRYPT 1

Definition at line 57 of file hifn_795x.c.

#define ACRYPTO_OP_HMAC 2

Definition at line 58 of file hifn_795x.c.

#define ACRYPTO_OP_RNG 3

Definition at line 59 of file hifn_795x.c.

#define ACRYPTO_TYPE_3DES 3

Definition at line 69 of file hifn_795x.c.

#define ACRYPTO_TYPE_AES_128 0

Definition at line 66 of file hifn_795x.c.

#define ACRYPTO_TYPE_AES_192 1

Definition at line 67 of file hifn_795x.c.

#define ACRYPTO_TYPE_AES_256 2

Definition at line 68 of file hifn_795x.c.

#define ACRYPTO_TYPE_DES 4

Definition at line 70 of file hifn_795x.c.

#define AES_MAX_KEY_SIZE 32

Definition at line 373 of file hifn_795x.c.

#define AES_MIN_KEY_SIZE 16

Definition at line 372 of file hifn_795x.c.

#define ASYNC_FLAGS_MISALIGNED (1<<0)

Definition at line 639 of file hifn_795x.c.

#define ASYNC_SCATTERLIST_CACHE 16

Definition at line 637 of file hifn_795x.c.

#define crypto_alg_to_hifn ( a ) container_of(a, struct hifn_crypto_alg, alg)

Definition at line 663 of file hifn_795x.c.

#define dprintk	(	f,
		a...
	)	do {} while (0)

Definition at line 46 of file hifn_795x.c.

#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */

Definition at line 104 of file hifn_795x.c.

#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */

Definition at line 103 of file hifn_795x.c.

#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */

Definition at line 100 of file hifn_795x.c.

#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */

Definition at line 98 of file hifn_795x.c.

#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */

Definition at line 97 of file hifn_795x.c.

#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */

Definition at line 101 of file hifn_795x.c.

#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */

Definition at line 99 of file hifn_795x.c.

#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */

Definition at line 102 of file hifn_795x.c.

#define HIFN_0_SPACESIZE 0x20 /* Register space size */

Definition at line 105 of file hifn_795x.c.

#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */

Definition at line 204 of file hifn_795x.c.

#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */

Definition at line 201 of file hifn_795x.c.

#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */

Definition at line 202 of file hifn_795x.c.

#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */

Definition at line 200 of file hifn_795x.c.

#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */

Definition at line 203 of file hifn_795x.c.

#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */

Definition at line 198 of file hifn_795x.c.

#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */

Definition at line 192 of file hifn_795x.c.

#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */

Definition at line 196 of file hifn_795x.c.

#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */

Definition at line 195 of file hifn_795x.c.

#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */

Definition at line 197 of file hifn_795x.c.

#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */

Definition at line 194 of file hifn_795x.c.

#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */

Definition at line 193 of file hifn_795x.c.

#define HIFN_1_PLL 0x4c /* 795x: PLL config */

Definition at line 199 of file hifn_795x.c.

#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */

Definition at line 209 of file hifn_795x.c.

#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */

Definition at line 213 of file hifn_795x.c.

#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */

Definition at line 216 of file hifn_795x.c.

#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */

Definition at line 217 of file hifn_795x.c.

#define HIFN_1_PUB_OP 0x308 /* Public Operand */

Definition at line 211 of file hifn_795x.c.

#define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */

Definition at line 210 of file hifn_795x.c.

#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */

Definition at line 208 of file hifn_795x.c.

#define HIFN_1_PUB_STATUS 0x30c /* Public Status */

Definition at line 212 of file hifn_795x.c.

#define HIFN_1_REVID 0x98 /* Revision ID */

Definition at line 205 of file hifn_795x.c.

#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */

Definition at line 214 of file hifn_795x.c.

#define HIFN_1_RNG_DATA 0x318 /* RNG data */

Definition at line 215 of file hifn_795x.c.

#define HIFN_1_UNLOCK_SECRET1 0xf4

Definition at line 206 of file hifn_795x.c.

#define HIFN_1_UNLOCK_SECRET2 0xfc

Definition at line 207 of file hifn_795x.c.

#define HIFN_3DES_KEY_LENGTH 24

Definition at line 376 of file hifn_795x.c.

#define HIFN_AES_IV_LENGTH 16

Definition at line 379 of file hifn_795x.c.

#define HIFN_BAR0_SIZE 0x1000

Definition at line 78 of file hifn_795x.c.

#define HIFN_BAR1_SIZE 0x2000

Definition at line 79 of file hifn_795x.c.

#define HIFN_BAR2_SIZE 0x8000

Definition at line 80 of file hifn_795x.c.

#define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */

Definition at line 481 of file hifn_795x.c.

#define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */

Definition at line 484 of file hifn_795x.c.

#define HIFN_BASE_CMD_DECODE 0x2000

Definition at line 485 of file hifn_795x.c.

#define HIFN_BASE_CMD_DSTLEN_M 0x3000

Definition at line 488 of file hifn_795x.c.

#define HIFN_BASE_CMD_DSTLEN_S 12

Definition at line 489 of file hifn_795x.c.

#define HIFN_BASE_CMD_LENMASK_HI 0x30000

Definition at line 490 of file hifn_795x.c.

#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff

Definition at line 491 of file hifn_795x.c.

#define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */

Definition at line 483 of file hifn_795x.c.

#define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */

Definition at line 482 of file hifn_795x.c.

#define HIFN_BASE_CMD_SRCLEN_M 0xc000

Definition at line 486 of file hifn_795x.c.

#define HIFN_BASE_CMD_SRCLEN_S 14

Definition at line 487 of file hifn_795x.c.

#define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */

Definition at line 586 of file hifn_795x.c.

#define HIFN_BASE_RES_DSTLEN_S 12

Definition at line 587 of file hifn_795x.c.

#define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */

Definition at line 583 of file hifn_795x.c.

#define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */

Definition at line 584 of file hifn_795x.c.

#define HIFN_BASE_RES_SRCLEN_S 14

Definition at line 585 of file hifn_795x.c.

#define HIFN_CHIP_ID 0x98 /* Chip ID */

Definition at line 92 of file hifn_795x.c.

#define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */

Definition at line 573 of file hifn_795x.c.

#define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */

Definition at line 571 of file hifn_795x.c.

#define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */

Definition at line 572 of file hifn_795x.c.

#define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */

Definition at line 567 of file hifn_795x.c.

#define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */

Definition at line 569 of file hifn_795x.c.

#define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */

Definition at line 570 of file hifn_795x.c.

#define HIFN_COMP_CMD_ONE 0x0100 /* must be one */

Definition at line 566 of file hifn_795x.c.

#define HIFN_COMP_CMD_SRCLEN_M 0xc000

Definition at line 564 of file hifn_795x.c.

#define HIFN_COMP_CMD_SRCLEN_S 14

Definition at line 565 of file hifn_795x.c.

#define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */

Definition at line 568 of file hifn_795x.c.

#define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */

Definition at line 598 of file hifn_795x.c.

#define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */

Definition at line 595 of file hifn_795x.c.

#define HIFN_COMP_RES_LCB_S 8

Definition at line 596 of file hifn_795x.c.

#define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */

Definition at line 597 of file hifn_795x.c.

#define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */

Definition at line 599 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */

Definition at line 506 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */

Definition at line 508 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */

Definition at line 505 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */

Definition at line 504 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */

Definition at line 507 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */

Definition at line 514 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */

Definition at line 516 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */

Definition at line 517 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */

Definition at line 518 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */

Definition at line 515 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */

Definition at line 511 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */

Definition at line 512 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */

Definition at line 510 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */

Definition at line 509 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */

Definition at line 513 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */

Definition at line 520 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */

Definition at line 519 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000

Definition at line 521 of file hifn_795x.c.

#define HIFN_CRYPT_CMD_SRCLEN_S 14

Definition at line 522 of file hifn_795x.c.

#define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */

Definition at line 617 of file hifn_795x.c.

#define HIFN_D_CMD_RSIZE 24*1

Definition at line 363 of file hifn_795x.c.

#define HIFN_D_DESTOVER 0x04000000

Definition at line 467 of file hifn_795x.c.

#define HIFN_D_DST_DALIGN 4

Definition at line 368 of file hifn_795x.c.

#define HIFN_D_DST_RSIZE 80*1

Definition at line 365 of file hifn_795x.c.

#define HIFN_D_JUMP 0x40000000

Definition at line 470 of file hifn_795x.c.

#define HIFN_D_LAST 0x20000000

Definition at line 469 of file hifn_795x.c.

#define HIFN_D_LENGTH 0x0000ffff

Definition at line 464 of file hifn_795x.c.

#define HIFN_D_MASKDONEIRQ 0x02000000

Definition at line 466 of file hifn_795x.c.

#define HIFN_D_NOINVALID 0x01000000

Definition at line 465 of file hifn_795x.c.

#define HIFN_D_OVER 0x08000000

Definition at line 468 of file hifn_795x.c.

#define HIFN_D_RES_RSIZE 24*1

Definition at line 366 of file hifn_795x.c.

#define HIFN_D_SRC_RSIZE 80*1

Definition at line 364 of file hifn_795x.c.

#define HIFN_D_VALID 0x80000000

Definition at line 471 of file hifn_795x.c.

#define HIFN_DEFAULT_ACTIVE_NUM 5

Definition at line 421 of file hifn_795x.c.

#define HIFN_DES_KEY_LENGTH 8

Definition at line 375 of file hifn_795x.c.

#define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */

Definition at line 90 of file hifn_795x.c.

#define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */

Definition at line 91 of file hifn_795x.c.

#define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */

Definition at line 84 of file hifn_795x.c.

#define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */

Definition at line 87 of file hifn_795x.c.

#define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */

Definition at line 89 of file hifn_795x.c.

#define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */

Definition at line 86 of file hifn_795x.c.

#define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */

Definition at line 85 of file hifn_795x.c.

#define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */

Definition at line 88 of file hifn_795x.c.

#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */

Definition at line 284 of file hifn_795x.c.

#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */

Definition at line 290 of file hifn_795x.c.

#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */

Definition at line 288 of file hifn_795x.c.

#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */

Definition at line 289 of file hifn_795x.c.

#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */

Definition at line 291 of file hifn_795x.c.

#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */

Definition at line 285 of file hifn_795x.c.

#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */

Definition at line 287 of file hifn_795x.c.

#define HIFN_DMACNFG_UNLOCK 0x00000800

Definition at line 286 of file hifn_795x.c.

#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */

Definition at line 252 of file hifn_795x.c.

#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */

Definition at line 248 of file hifn_795x.c.

#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */

Definition at line 250 of file hifn_795x.c.

#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */

Definition at line 251 of file hifn_795x.c.

#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */

Definition at line 249 of file hifn_795x.c.

#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */

Definition at line 253 of file hifn_795x.c.

#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */

Definition at line 254 of file hifn_795x.c.

#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */

Definition at line 255 of file hifn_795x.c.

#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */

Definition at line 224 of file hifn_795x.c.

#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */

Definition at line 222 of file hifn_795x.c.

#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */

Definition at line 223 of file hifn_795x.c.

#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */

Definition at line 221 of file hifn_795x.c.

#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */

Definition at line 220 of file hifn_795x.c.

#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */

Definition at line 225 of file hifn_795x.c.

#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */

Definition at line 226 of file hifn_795x.c.

#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */

Definition at line 228 of file hifn_795x.c.

#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */

Definition at line 227 of file hifn_795x.c.

#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */

Definition at line 257 of file hifn_795x.c.

#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */

Definition at line 247 of file hifn_795x.c.

#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */

Definition at line 246 of file hifn_795x.c.

#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */

Definition at line 256 of file hifn_795x.c.

#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */

Definition at line 233 of file hifn_795x.c.

#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */

Definition at line 229 of file hifn_795x.c.

#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */

Definition at line 231 of file hifn_795x.c.

#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */

Definition at line 232 of file hifn_795x.c.

#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */

Definition at line 230 of file hifn_795x.c.

#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */

Definition at line 234 of file hifn_795x.c.

#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */

Definition at line 235 of file hifn_795x.c.

#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */

Definition at line 237 of file hifn_795x.c.

#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */

Definition at line 236 of file hifn_795x.c.

#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */

Definition at line 242 of file hifn_795x.c.

#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */

Definition at line 238 of file hifn_795x.c.

#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */

Definition at line 240 of file hifn_795x.c.

#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */

Definition at line 241 of file hifn_795x.c.

#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */

Definition at line 239 of file hifn_795x.c.

#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */

Definition at line 243 of file hifn_795x.c.

#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */

Definition at line 244 of file hifn_795x.c.

#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */

Definition at line 245 of file hifn_795x.c.

#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */

Definition at line 276 of file hifn_795x.c.

#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */

Definition at line 277 of file hifn_795x.c.

#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */

Definition at line 278 of file hifn_795x.c.

#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */

Definition at line 279 of file hifn_795x.c.

#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */

Definition at line 260 of file hifn_795x.c.

#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */

Definition at line 261 of file hifn_795x.c.

#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */

Definition at line 262 of file hifn_795x.c.

#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */

Definition at line 264 of file hifn_795x.c.

#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */

Definition at line 263 of file hifn_795x.c.

#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */

Definition at line 281 of file hifn_795x.c.

#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */

Definition at line 275 of file hifn_795x.c.

#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */

Definition at line 274 of file hifn_795x.c.

#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */

Definition at line 280 of file hifn_795x.c.

#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */

Definition at line 265 of file hifn_795x.c.

#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */

Definition at line 266 of file hifn_795x.c.

#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */

Definition at line 267 of file hifn_795x.c.

#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */

Definition at line 269 of file hifn_795x.c.

#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */

Definition at line 268 of file hifn_795x.c.

#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */

Definition at line 270 of file hifn_795x.c.

#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */

Definition at line 271 of file hifn_795x.c.

#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */

Definition at line 272 of file hifn_795x.c.

#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */

Definition at line 273 of file hifn_795x.c.

#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */

Definition at line 187 of file hifn_795x.c.

#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */

Definition at line 184 of file hifn_795x.c.

#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */

Definition at line 183 of file hifn_795x.c.

#define HIFN_FLAG_CMD_BUSY (1<<0)

Definition at line 415 of file hifn_795x.c.

#define HIFN_FLAG_DST_BUSY (1<<2)

Definition at line 417 of file hifn_795x.c.

#define HIFN_FLAG_OLD_KEY (1<<4)

Definition at line 419 of file hifn_795x.c.

#define HIFN_FLAG_RES_BUSY (1<<3)

Definition at line 418 of file hifn_795x.c.

#define HIFN_FLAG_SRC_BUSY (1<<1)

Definition at line 416 of file hifn_795x.c.

#define HIFN_IV_LENGTH 8

Definition at line 378 of file hifn_795x.c.

#define HIFN_MAC_CMD_ALG_MASK 0x0001

Definition at line 535 of file hifn_795x.c.

#define HIFN_MAC_CMD_ALG_MD5 0x0001

Definition at line 537 of file hifn_795x.c.

#define HIFN_MAC_CMD_ALG_SHA1 0x0000

Definition at line 536 of file hifn_795x.c.

#define HIFN_MAC_CMD_APPEND 0x0040

Definition at line 545 of file hifn_795x.c.

#define HIFN_MAC_CMD_MODE_FULL 0x0004

Definition at line 542 of file hifn_795x.c.

#define HIFN_MAC_CMD_MODE_HASH 0x0008

Definition at line 541 of file hifn_795x.c.

#define HIFN_MAC_CMD_MODE_HMAC 0x0000

Definition at line 539 of file hifn_795x.c.

#define HIFN_MAC_CMD_MODE_MASK 0x000c

Definition at line 538 of file hifn_795x.c.

#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004

Definition at line 540 of file hifn_795x.c.

#define HIFN_MAC_CMD_NEW_KEY 0x0800

Definition at line 554 of file hifn_795x.c.

#define HIFN_MAC_CMD_POS_IPSEC 0x0200

Definition at line 553 of file hifn_795x.c.

#define HIFN_MAC_CMD_RESULT 0x0020

Definition at line 544 of file hifn_795x.c.

#define HIFN_MAC_CMD_SRCLEN_M 0xc000

Definition at line 546 of file hifn_795x.c.

#define HIFN_MAC_CMD_SRCLEN_S 14

Definition at line 547 of file hifn_795x.c.

#define HIFN_MAC_CMD_TRUNC 0x0010

Definition at line 543 of file hifn_795x.c.

#define HIFN_MAC_KEY_LENGTH 64

Definition at line 382 of file hifn_795x.c.

#define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */

Definition at line 608 of file hifn_795x.c.

#define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */

Definition at line 609 of file hifn_795x.c.

#define HIFN_MAC_TRUNC_LENGTH 12

Definition at line 385 of file hifn_795x.c.

#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)

Definition at line 387 of file hifn_795x.c.

#define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE

Definition at line 377 of file hifn_795x.c.

#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */

Definition at line 628 of file hifn_795x.c.

#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH

Definition at line 380 of file hifn_795x.c.

#define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)

Definition at line 388 of file hifn_795x.c.

#define HIFN_MAX_RESULT_ORDER 5

Definition at line 361 of file hifn_795x.c.

#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */

Definition at line 627 of file hifn_795x.c.

#define HIFN_MD5_LENGTH 16

Definition at line 383 of file hifn_795x.c.

#define HIFN_NAMESIZE 32

Definition at line 360 of file hifn_795x.c.

#define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */

Definition at line 296 of file hifn_795x.c.

#define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */

Definition at line 312 of file hifn_795x.c.

#define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */

Definition at line 309 of file hifn_795x.c.

#define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */

Definition at line 310 of file hifn_795x.c.

#define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */

Definition at line 307 of file hifn_795x.c.

#define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */

Definition at line 308 of file hifn_795x.c.

#define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */

Definition at line 303 of file hifn_795x.c.

#define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */

Definition at line 304 of file hifn_795x.c.

#define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */

Definition at line 305 of file hifn_795x.c.

#define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */

Definition at line 306 of file hifn_795x.c.

#define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */

Definition at line 302 of file hifn_795x.c.

#define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */

Definition at line 299 of file hifn_795x.c.

#define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */

Definition at line 300 of file hifn_795x.c.

#define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */

Definition at line 297 of file hifn_795x.c.

#define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */

Definition at line 298 of file hifn_795x.c.

#define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */

Definition at line 294 of file hifn_795x.c.

#define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */

Definition at line 295 of file hifn_795x.c.

#define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */

Definition at line 301 of file hifn_795x.c.

#define HIFN_POLL_FREQUENCY 0x1

Definition at line 620 of file hifn_795x.c.

#define HIFN_POLL_SCALAR 0x0

Definition at line 624 of file hifn_795x.c.

#define HIFN_PUBBASE_ADDR 0x00003fff /* base address */

Definition at line 318 of file hifn_795x.c.

#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */

Definition at line 355 of file hifn_795x.c.

#define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */

Definition at line 329 of file hifn_795x.c.

#define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */

Definition at line 330 of file hifn_795x.c.

#define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */

Definition at line 331 of file hifn_795x.c.

#define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */

Definition at line 332 of file hifn_795x.c.

#define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */

Definition at line 333 of file hifn_795x.c.

#define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */

Definition at line 334 of file hifn_795x.c.

#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */

Definition at line 337 of file hifn_795x.c.

#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */

Definition at line 338 of file hifn_795x.c.

#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */

Definition at line 344 of file hifn_795x.c.

#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */

Definition at line 343 of file hifn_795x.c.

#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */

Definition at line 335 of file hifn_795x.c.

#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */

Definition at line 341 of file hifn_795x.c.

#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */

Definition at line 348 of file hifn_795x.c.

#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */

Definition at line 346 of file hifn_795x.c.

#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */

Definition at line 347 of file hifn_795x.c.

#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */

Definition at line 342 of file hifn_795x.c.

#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */

Definition at line 345 of file hifn_795x.c.

#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */

Definition at line 336 of file hifn_795x.c.

#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */

Definition at line 339 of file hifn_795x.c.

#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */

Definition at line 340 of file hifn_795x.c.

#define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */

Definition at line 323 of file hifn_795x.c.

#define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */

Definition at line 324 of file hifn_795x.c.

#define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */

Definition at line 321 of file hifn_795x.c.

#define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */

Definition at line 322 of file hifn_795x.c.

#define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */

Definition at line 325 of file hifn_795x.c.

#define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */

Definition at line 326 of file hifn_795x.c.

#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */

Definition at line 315 of file hifn_795x.c.

#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */

Definition at line 352 of file hifn_795x.c.

#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */

Definition at line 351 of file hifn_795x.c.

#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */

Definition at line 142 of file hifn_795x.c.

#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */

Definition at line 144 of file hifn_795x.c.

#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */

Definition at line 143 of file hifn_795x.c.

#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */

Definition at line 145 of file hifn_795x.c.

#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */

Definition at line 148 of file hifn_795x.c.

#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */

Definition at line 146 of file hifn_795x.c.

#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */

Definition at line 127 of file hifn_795x.c.

#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */

Definition at line 136 of file hifn_795x.c.

#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */

Definition at line 139 of file hifn_795x.c.

#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */

Definition at line 138 of file hifn_795x.c.

#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */

Definition at line 137 of file hifn_795x.c.

#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */

Definition at line 130 of file hifn_795x.c.

#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */

Definition at line 128 of file hifn_795x.c.

#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */

Definition at line 131 of file hifn_795x.c.

#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */

Definition at line 135 of file hifn_795x.c.

#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */

Definition at line 132 of file hifn_795x.c.

#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */

Definition at line 129 of file hifn_795x.c.

#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */

Definition at line 133 of file hifn_795x.c.

#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */

Definition at line 149 of file hifn_795x.c.

#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */

Definition at line 147 of file hifn_795x.c.

#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */

Definition at line 140 of file hifn_795x.c.

#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */

Definition at line 141 of file hifn_795x.c.

#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */

Definition at line 108 of file hifn_795x.c.

#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */

Definition at line 111 of file hifn_795x.c.

#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */

Definition at line 110 of file hifn_795x.c.

#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */

Definition at line 112 of file hifn_795x.c.

#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */

Definition at line 109 of file hifn_795x.c.

#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */

Definition at line 152 of file hifn_795x.c.

#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */

Definition at line 153 of file hifn_795x.c.

#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */

Definition at line 160 of file hifn_795x.c.

#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */

Definition at line 155 of file hifn_795x.c.

#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */

Definition at line 156 of file hifn_795x.c.

#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */

Definition at line 161 of file hifn_795x.c.

#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */

Definition at line 157 of file hifn_795x.c.

#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */

Definition at line 158 of file hifn_795x.c.

#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */

Definition at line 159 of file hifn_795x.c.

#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */

Definition at line 154 of file hifn_795x.c.

#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */

Definition at line 115 of file hifn_795x.c.

#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */

Definition at line 116 of file hifn_795x.c.

#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */

Definition at line 123 of file hifn_795x.c.

#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */

Definition at line 118 of file hifn_795x.c.

#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */

Definition at line 119 of file hifn_795x.c.

#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */

Definition at line 124 of file hifn_795x.c.

#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */

Definition at line 120 of file hifn_795x.c.

#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */

Definition at line 121 of file hifn_795x.c.

#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */

Definition at line 122 of file hifn_795x.c.

#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */

Definition at line 117 of file hifn_795x.c.

#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */

Definition at line 134 of file hifn_795x.c.

#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */

Definition at line 175 of file hifn_795x.c.

#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */

Definition at line 174 of file hifn_795x.c.

#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */

Definition at line 164 of file hifn_795x.c.

#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */

Definition at line 165 of file hifn_795x.c.

#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */

Definition at line 172 of file hifn_795x.c.

#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */

Definition at line 167 of file hifn_795x.c.

#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */

Definition at line 168 of file hifn_795x.c.

#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */

Definition at line 173 of file hifn_795x.c.

#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */

Definition at line 178 of file hifn_795x.c.

#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */

Definition at line 177 of file hifn_795x.c.

#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */

Definition at line 176 of file hifn_795x.c.

#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */

Definition at line 179 of file hifn_795x.c.

#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */

Definition at line 180 of file hifn_795x.c.

#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */

Definition at line 169 of file hifn_795x.c.

#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */

Definition at line 170 of file hifn_795x.c.

#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */

Definition at line 171 of file hifn_795x.c.

#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */

Definition at line 166 of file hifn_795x.c.

#define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1)

Definition at line 370 of file hifn_795x.c.

#define hifn_register_rng ( dev ) 0

Definition at line 840 of file hifn_795x.c.

#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */

Definition at line 358 of file hifn_795x.c.

#define HIFN_SHA1_LENGTH 20

Definition at line 384 of file hifn_795x.c.

#define hifn_unregister_rng ( dev )

Definition at line 841 of file hifn_795x.c.

#define HIFN_USED_RESULT 12

Definition at line 389 of file hifn_795x.c.

#define PCI_DEVICE_ID_HIFN_7955 0x0020

Definition at line 73 of file hifn_795x.c.

#define PCI_DEVICE_ID_HIFN_7956 0x001d

Definition at line 74 of file hifn_795x.c.

#define PCI_VENDOR_ID_HIFN 0x13A3

Definition at line 72 of file hifn_795x.c.

Function Documentation

MODULE_AUTHOR ( "Evgeniy Polyakov <[email protected]>" )

MODULE_DESCRIPTION ( "Driver for HIFN 795x crypto accelerator chip." )

MODULE_DEVICE_TABLE	(	pci	,
		hifn_pci_tbl
	)

module_exit ( hifn_fini )

module_init ( hifn_init )

MODULE_LICENSE ( "GPL" )

module_param_string	(	hifn_pll_ref	,
		hifn_pll_ref	,
		sizeof(hifn_pll_ref)	,
		0444
	)

MODULE_PARM_DESC	(	hifn_pll_ref	,
		"PLL reference clock (pci[freq] or ext[freq], default ext)"
	)

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation