#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/edac.h>
#include <linux/mmzone.h>
#include "edac_core.h"

Data Structures
struct	i5400_dev_info

struct	i5400_dimm_info

struct	i5400_pvt

struct	i5400_error_info

Macros
#define	I5400_REVISION " Ver: 1.0.0"

#define	EDAC_MOD_STR "i5400_edac"

#define	i5400_printk(level, fmt, arg...) edac_printk(level, "i5400", fmt, ##arg)

#define	i5400_mc_printk(mci, level, fmt, arg...) edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg)

#define	MAX_BRANCHES 2

#define	CHANNELS_PER_BRANCH 2

#define	DIMMS_PER_CHANNEL 4

#define	MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH)

#define	AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */

#define	MAXCH 0x56 /* Max Channel Number */

#define	MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */

#define	TOLM 0x6C

#define	REDMEMB 0x7C

#define	REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */

#define	MIR0 0x80

#define	MIR1 0x84

#define	AMIR0 0x8c

#define	AMIR1 0x90

#define	FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */

#define	FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */

#define	NERR_FAT_FBD 0x9c

#define	FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */

#define	NERR_NF_FBD 0xa4

#define	EMASK_FBD 0xa8

#define	ERR0_FBD 0xac

#define	ERR1_FBD 0xb0

#define	ERR2_FBD 0xb4

#define	MCERR_FBD 0xb8

#define	AMBPRESENT_0 0x64

#define	AMBPRESENT_1 0x66

#define	MTR0 0x80

#define	MTR1 0x82

#define	MTR2 0x84

#define	MTR3 0x86

#define	NRECFGLOG 0x74

#define	RECFGLOG 0x78

#define	NRECMEMA 0xbe

#define	NRECMEMB 0xc0

#define	NRECFB_DIMMA 0xc4

#define	NRECFB_DIMMB 0xc8

#define	NRECFB_DIMMC 0xcc

#define	NRECFB_DIMMD 0xd0

#define	NRECFB_DIMME 0xd4

#define	NRECFB_DIMMF 0xd8

#define	REDMEMA 0xdC

#define	RECMEMA 0xf0

#define	RECMEMB 0xf4

#define	RECFB_DIMMA 0xf8

#define	RECFB_DIMMB 0xec

#define	RECFB_DIMMC 0xf0

#define	RECFB_DIMMD 0xf4

#define	RECFB_DIMME 0xf8

#define	RECFB_DIMMF 0xfC

#define	ERROR_FAT_MASK

#define	ERROR_NF_CORRECTABLE

#define	ERROR_NF_DIMM_SPARE

#define	ERROR_NF_SPD_PROTOCOL (EMASK_M22)

#define	ERROR_NF_NORTH_CRC (EMASK_M21)

#define	ERROR_NF_RECOVERABLE

#define	ERROR_NF_UNCORRECTABLE (EMASK_M4)

#define	ERROR_NF_MASK

#define	ENABLE_EMASK_ALL (ERROR_FAT_MASK \| ERROR_NF_MASK)

#define	FERR_FAT_MASK ERROR_FAT_MASK

#define	FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)

#define	FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)

#define	FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)

#define	FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)

#define	FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)

#define	FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)

#define	FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)

#define	MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10))

#define	MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9))

#define	MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4)

#define	MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4)

#define	MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)

#define	MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1)

#define	MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)

#define	MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)

#define	MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)

#define	MTR_DIMM_COLS(mtr) ((mtr) & 0x3)

#define	MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)

Enumerations
enum	error_mask { EMASK_M1 = 1<<0, EMASK_M2 = 1<<1, EMASK_M3 = 1<<2, EMASK_M4 = 1<<3, EMASK_M5 = 1<<4, EMASK_M6 = 1<<5, EMASK_M7 = 1<<6, EMASK_M8 = 1<<7, EMASK_M9 = 1<<8, EMASK_M10 = 1<<9, EMASK_M11 = 1<<10, EMASK_M12 = 1<<11, EMASK_M13 = 1<<12, EMASK_M14 = 1<<13, EMASK_M15 = 1<<14, EMASK_M16 = 1<<15, EMASK_M17 = 1<<16, EMASK_M18 = 1<<17, EMASK_M19 = 1<<18, EMASK_M20 = 1<<19, EMASK_M21 = 1<<20, EMASK_M22 = 1<<21, EMASK_M23 = 1<<22, EMASK_M24 = 1<<23, EMASK_M25 = 1<<24, EMASK_M26 = 1<<25, EMASK_M27 = 1<<26, EMASK_M28 = 1<<27, EMASK_M29 = 1<<28 }

Functions
	MODULE_DEVICE_TABLE (pci, i5400_pci_tbl)

	module_init (i5400_init)

	module_exit (i5400_exit)

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Ben Woodard <[email protected]>")

	MODULE_AUTHOR ("Mauro Carvalho Chehab <[email protected]>")

	MODULE_AUTHOR ("Red Hat Inc. (http://www.redhat.com)")

	MODULE_DESCRIPTION ("MC Driver for Intel I5400 memory controllers - "I5400_REVISION)

	module_param (edac_op_state, int, 0444)

	MODULE_PARM_DESC (edac_op_state,"EDAC Error Reporting state: 0=Poll,1=NMI")

Macro Definition Documentation

#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */

Definition at line 68 of file i5400_edac.c.

#define AMBPRESENT_0 0x64

Definition at line 110 of file i5400_edac.c.

#define AMBPRESENT_1 0x66

Definition at line 111 of file i5400_edac.c.

#define AMIR0 0x8c

Definition at line 78 of file i5400_edac.c.

#define AMIR1 0x90

Definition at line 79 of file i5400_edac.c.

#define CHANNELS_PER_BRANCH 2

Definition at line 52 of file i5400_edac.c.

#define DIMMS_PER_CHANNEL 4

Definition at line 53 of file i5400_edac.c.

#define EDAC_MOD_STR "i5400_edac"

Definition at line 42 of file i5400_edac.c.

#define EMASK_FBD 0xa8

Definition at line 92 of file i5400_edac.c.

#define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)

Definition at line 257 of file i5400_edac.c.

#define ERR0_FBD 0xac

Definition at line 94 of file i5400_edac.c.

#define ERR1_FBD 0xb0

Definition at line 95 of file i5400_edac.c.

#define ERR2_FBD 0xb4

Definition at line 96 of file i5400_edac.c.

#define ERROR_FAT_MASK

Value:

(EMASK_M1 | \
                 EMASK_M2 | \
                 EMASK_M23)

Definition at line 211 of file i5400_edac.c.

#define ERROR_NF_CORRECTABLE

Value:

(EMASK_M27 | \
                 EMASK_M20 | \
                 EMASK_M19 | \
                 EMASK_M18 | \
                 EMASK_M17 | \
                 EMASK_M16)

Definition at line 216 of file i5400_edac.c.

#define ERROR_NF_DIMM_SPARE

Value:

(EMASK_M29 | \

EMASK_M28)

Definition at line 222 of file i5400_edac.c.

#define ERROR_NF_MASK

Value:

(ERROR_NF_CORRECTABLE   | \
                 ERROR_NF_UNCORRECTABLE | \
                 ERROR_NF_RECOVERABLE   | \
                 ERROR_NF_DIMM_SPARE    | \
                 ERROR_NF_SPD_PROTOCOL  | \
                 ERROR_NF_NORTH_CRC)

Definition at line 245 of file i5400_edac.c.

#define ERROR_NF_NORTH_CRC (EMASK_M21)

Definition at line 225 of file i5400_edac.c.

#define ERROR_NF_RECOVERABLE

Value:

(EMASK_M26 | \
                 EMASK_M25 | \
                 EMASK_M24 | \
                 EMASK_M15 | \
                 EMASK_M14 | \
                 EMASK_M13 | \
                 EMASK_M12 | \
                 EMASK_M11 | \
                 EMASK_M9  | \
                 EMASK_M8  | \
                 EMASK_M7  | \
                 EMASK_M5)

Definition at line 228 of file i5400_edac.c.

#define ERROR_NF_SPD_PROTOCOL (EMASK_M22)

Definition at line 224 of file i5400_edac.c.

#define ERROR_NF_UNCORRECTABLE (EMASK_M4)

Definition at line 242 of file i5400_edac.c.

#define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */

Definition at line 82 of file i5400_edac.c.

#define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */

Definition at line 83 of file i5400_edac.c.

#define FERR_FAT_MASK ERROR_FAT_MASK

Definition at line 260 of file i5400_edac.c.

#define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)

Definition at line 275 of file i5400_edac.c.

#define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)

Definition at line 276 of file i5400_edac.c.

#define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */

Definition at line 86 of file i5400_edac.c.

#define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)

Definition at line 274 of file i5400_edac.c.

#define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)

Definition at line 278 of file i5400_edac.c.

#define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)

Definition at line 279 of file i5400_edac.c.

#define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)

Definition at line 277 of file i5400_edac.c.

#define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)

Definition at line 280 of file i5400_edac.c.

#define i5400_mc_printk	(	mci,
		level,
		fmt,
		arg...
	)	edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg)

Definition at line 47 of file i5400_edac.c.

#define i5400_printk	(	level,
		fmt,
		arg...
	)	edac_printk(level, "i5400", fmt, ##arg)

Definition at line 44 of file i5400_edac.c.

#define I5400_REVISION " Ver: 1.0.0"

Definition at line 40 of file i5400_edac.c.

#define MAX_BRANCHES 2

Definition at line 51 of file i5400_edac.c.

#define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH)

Definition at line 54 of file i5400_edac.c.

#define MAXCH 0x56 /* Max Channel Number */

Definition at line 69 of file i5400_edac.c.

#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */

Definition at line 70 of file i5400_edac.c.

#define MCERR_FBD 0xb8

Definition at line 97 of file i5400_edac.c.

#define MIR0 0x80

Definition at line 76 of file i5400_edac.c.

#define MIR1 0x84

Definition at line 77 of file i5400_edac.c.

#define MTR0 0x80

Definition at line 112 of file i5400_edac.c.

#define MTR1 0x82

Definition at line 113 of file i5400_edac.c.

#define MTR2 0x84

Definition at line 114 of file i5400_edac.c.

#define MTR3 0x86

Definition at line 115 of file i5400_edac.c.

#define MTR_DIMM_COLS ( mtr ) ((mtr) & 0x3)

Definition at line 294 of file i5400_edac.c.

#define MTR_DIMM_COLS_ADDR_BITS ( mtr ) (MTR_DIMM_COLS(mtr) + 10)

Definition at line 295 of file i5400_edac.c.

#define MTR_DIMM_RANK ( mtr ) (((mtr) >> 5) & 0x1)

Definition at line 290 of file i5400_edac.c.

#define MTR_DIMM_RANK_ADDR_BITS ( mtr ) (MTR_DIMM_RANK(mtr) ? 2 : 1)

Definition at line 291 of file i5400_edac.c.

#define MTR_DIMM_ROWS ( mtr ) (((mtr) >> 2) & 0x3)

Definition at line 292 of file i5400_edac.c.

#define MTR_DIMM_ROWS_ADDR_BITS ( mtr ) (MTR_DIMM_ROWS(mtr) + 13)

Definition at line 293 of file i5400_edac.c.

#define MTR_DIMMS_ETHROTTLE ( mtr ) ((mtr) & (1 << 9))

Definition at line 286 of file i5400_edac.c.

#define MTR_DIMMS_PRESENT ( mtr ) ((mtr) & (1 << 10))

Definition at line 285 of file i5400_edac.c.

#define MTR_DRAM_BANKS ( mtr ) (((mtr) & (1 << 6)) ? 8 : 4)

Definition at line 288 of file i5400_edac.c.

#define MTR_DRAM_BANKS_ADDR_BITS ( mtr ) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)

Definition at line 289 of file i5400_edac.c.

#define MTR_DRAM_WIDTH ( mtr ) (((mtr) & (1 << 8)) ? 8 : 4)

Definition at line 287 of file i5400_edac.c.

#define NERR_FAT_FBD 0x9c

Definition at line 85 of file i5400_edac.c.

#define NERR_NF_FBD 0xa4

Definition at line 89 of file i5400_edac.c.

#define NRECFB_DIMMA 0xc4

Definition at line 122 of file i5400_edac.c.

#define NRECFB_DIMMB 0xc8

Definition at line 123 of file i5400_edac.c.

#define NRECFB_DIMMC 0xcc

Definition at line 124 of file i5400_edac.c.

#define NRECFB_DIMMD 0xd0

Definition at line 125 of file i5400_edac.c.

#define NRECFB_DIMME 0xd4

Definition at line 126 of file i5400_edac.c.

#define NRECFB_DIMMF 0xd8

Definition at line 127 of file i5400_edac.c.

#define NRECFGLOG 0x74

Definition at line 118 of file i5400_edac.c.

#define NRECMEMA 0xbe

Definition at line 120 of file i5400_edac.c.

#define NRECMEMB 0xc0

Definition at line 121 of file i5400_edac.c.

#define REC_ECC_LOCATOR_ODD ( x ) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */

Definition at line 75 of file i5400_edac.c.

#define RECFB_DIMMA 0xf8

Definition at line 131 of file i5400_edac.c.

#define RECFB_DIMMB 0xec

Definition at line 132 of file i5400_edac.c.

#define RECFB_DIMMC 0xf0

Definition at line 133 of file i5400_edac.c.

#define RECFB_DIMMD 0xf4

Definition at line 134 of file i5400_edac.c.

#define RECFB_DIMME 0xf8

Definition at line 135 of file i5400_edac.c.

#define RECFB_DIMMF 0xfC

Definition at line 136 of file i5400_edac.c.

#define RECFGLOG 0x78

Definition at line 119 of file i5400_edac.c.

#define RECMEMA 0xf0

Definition at line 129 of file i5400_edac.c.

#define RECMEMB 0xf4

Definition at line 130 of file i5400_edac.c.

#define REDMEMA 0xdC

Definition at line 128 of file i5400_edac.c.

#define REDMEMB 0x7C

Definition at line 74 of file i5400_edac.c.

#define TOLM 0x6C

Definition at line 73 of file i5400_edac.c.

Enumeration Type Documentation

enum error_mask

Enumerator:

EMASK_M1
EMASK_M2
EMASK_M3
EMASK_M4
EMASK_M5
EMASK_M6
EMASK_M7
EMASK_M8
EMASK_M9
EMASK_M10
EMASK_M11
EMASK_M12
EMASK_M13
EMASK_M14
EMASK_M15
EMASK_M16
EMASK_M17
EMASK_M18
EMASK_M19
EMASK_M20
EMASK_M21
EMASK_M22
EMASK_M23
EMASK_M24
EMASK_M25
EMASK_M26
EMASK_M27
EMASK_M28
EMASK_M29

Definition at line 143 of file i5400_edac.c.

Function Documentation

MODULE_AUTHOR ( "Ben Woodard <[email protected]>" )

MODULE_AUTHOR ( "Mauro Carvalho Chehab <[email protected]>" )

MODULE_AUTHOR ( "Red Hat Inc. (http://www.redhat.com)" )

MODULE_DESCRIPTION ( "MC Driver for Intel I5400 memory controllers - " I5400_REVISION )

MODULE_DEVICE_TABLE	(	pci	,
		i5400_pci_tbl
	)

module_exit ( i5400_exit )

module_init ( i5400_init )

MODULE_LICENSE ( "GPL" )

module_param	(	edac_op_state	,
		int	,
		0444
	)

MODULE_PARM_DESC	(	edac_op_state	,
		"EDAC Error Reporting state:	0 = `Poll`
	)

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation