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i915_dma.c
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1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28 
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
45 #include <asm/pat.h>
46 
47 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
48 
49 #define BEGIN_LP_RING(n) \
50  intel_ring_begin(LP_RING(dev_priv), (n))
51 
52 #define OUT_RING(x) \
53  intel_ring_emit(LP_RING(dev_priv), x)
54 
55 #define ADVANCE_LP_RING() \
56  intel_ring_advance(LP_RING(dev_priv))
57 
64 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
65  if (LP_RING(dev->dev_private)->obj == NULL) \
66  LOCK_TEST_WITH_RETURN(dev, file); \
67 } while (0)
68 
69 static inline u32
70 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
71 {
72  if (I915_NEED_GFX_HWS(dev_priv->dev))
73  return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
74  else
75  return intel_read_status_page(LP_RING(dev_priv), reg);
76 }
77 
78 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
79 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
80 #define I915_BREADCRUMB_INDEX 0x21
81 
83 {
84  drm_i915_private_t *dev_priv = dev->dev_private;
85  struct drm_i915_master_private *master_priv;
86 
87  if (dev->primary->master) {
88  master_priv = dev->primary->master->driver_priv;
89  if (master_priv->sarea_priv)
90  master_priv->sarea_priv->last_dispatch =
91  READ_BREADCRUMB(dev_priv);
92  }
93 }
94 
95 static void i915_write_hws_pga(struct drm_device *dev)
96 {
97  drm_i915_private_t *dev_priv = dev->dev_private;
98  u32 addr;
99 
100  addr = dev_priv->status_page_dmah->busaddr;
101  if (INTEL_INFO(dev)->gen >= 4)
102  addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
103  I915_WRITE(HWS_PGA, addr);
104 }
105 
110 static int i915_init_phys_hws(struct drm_device *dev)
111 {
112  drm_i915_private_t *dev_priv = dev->dev_private;
113 
114  /* Program Hardware Status Page */
115  dev_priv->status_page_dmah =
117 
118  if (!dev_priv->status_page_dmah) {
119  DRM_ERROR("Can not allocate hardware status page\n");
120  return -ENOMEM;
121  }
122 
123  memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
124  0, PAGE_SIZE);
125 
126  i915_write_hws_pga(dev);
127 
128  DRM_DEBUG_DRIVER("Enabled hardware status page\n");
129  return 0;
130 }
131 
136 static void i915_free_hws(struct drm_device *dev)
137 {
138  drm_i915_private_t *dev_priv = dev->dev_private;
139  struct intel_ring_buffer *ring = LP_RING(dev_priv);
140 
141  if (dev_priv->status_page_dmah) {
142  drm_pci_free(dev, dev_priv->status_page_dmah);
143  dev_priv->status_page_dmah = NULL;
144  }
145 
146  if (ring->status_page.gfx_addr) {
147  ring->status_page.gfx_addr = 0;
148  iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
149  }
150 
151  /* Need to rewrite hardware status page */
152  I915_WRITE(HWS_PGA, 0x1ffff000);
153 }
154 
156 {
157  drm_i915_private_t *dev_priv = dev->dev_private;
158  struct drm_i915_master_private *master_priv;
159  struct intel_ring_buffer *ring = LP_RING(dev_priv);
160 
161  /*
162  * We should never lose context on the ring with modesetting
163  * as we don't expose it to userspace
164  */
165  if (drm_core_check_feature(dev, DRIVER_MODESET))
166  return;
167 
168  ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
169  ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
170  ring->space = ring->head - (ring->tail + 8);
171  if (ring->space < 0)
172  ring->space += ring->size;
173 
174  if (!dev->primary->master)
175  return;
176 
177  master_priv = dev->primary->master->driver_priv;
178  if (ring->head == ring->tail && master_priv->sarea_priv)
179  master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
180 }
181 
182 static int i915_dma_cleanup(struct drm_device * dev)
183 {
184  drm_i915_private_t *dev_priv = dev->dev_private;
185  int i;
186 
187  /* Make sure interrupts are disabled here because the uninstall ioctl
188  * may not have been called from userspace and after dev_private
189  * is freed, it's too late.
190  */
191  if (dev->irq_enabled)
192  drm_irq_uninstall(dev);
193 
194  mutex_lock(&dev->struct_mutex);
195  for (i = 0; i < I915_NUM_RINGS; i++)
196  intel_cleanup_ring_buffer(&dev_priv->ring[i]);
197  mutex_unlock(&dev->struct_mutex);
198 
199  /* Clear the HWS virtual address at teardown */
200  if (I915_NEED_GFX_HWS(dev))
201  i915_free_hws(dev);
202 
203  return 0;
204 }
205 
206 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
207 {
208  drm_i915_private_t *dev_priv = dev->dev_private;
209  struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
210  int ret;
211 
212  master_priv->sarea = drm_getsarea(dev);
213  if (master_priv->sarea) {
214  master_priv->sarea_priv = (drm_i915_sarea_t *)
215  ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
216  } else {
217  DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
218  }
219 
220  if (init->ring_size != 0) {
221  if (LP_RING(dev_priv)->obj != NULL) {
222  i915_dma_cleanup(dev);
223  DRM_ERROR("Client tried to initialize ringbuffer in "
224  "GEM mode\n");
225  return -EINVAL;
226  }
227 
228  ret = intel_render_ring_init_dri(dev,
229  init->ring_start,
230  init->ring_size);
231  if (ret) {
232  i915_dma_cleanup(dev);
233  return ret;
234  }
235  }
236 
237  dev_priv->dri1.cpp = init->cpp;
238  dev_priv->dri1.back_offset = init->back_offset;
239  dev_priv->dri1.front_offset = init->front_offset;
240  dev_priv->dri1.current_page = 0;
241  if (master_priv->sarea_priv)
242  master_priv->sarea_priv->pf_current_page = 0;
243 
244  /* Allow hardware batchbuffers unless told otherwise.
245  */
246  dev_priv->dri1.allow_batchbuffer = 1;
247 
248  return 0;
249 }
250 
251 static int i915_dma_resume(struct drm_device * dev)
252 {
253  drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
254  struct intel_ring_buffer *ring = LP_RING(dev_priv);
255 
256  DRM_DEBUG_DRIVER("%s\n", __func__);
257 
258  if (ring->virtual_start == NULL) {
259  DRM_ERROR("can not ioremap virtual address for"
260  " ring buffer\n");
261  return -ENOMEM;
262  }
263 
264  /* Program Hardware Status Page */
265  if (!ring->status_page.page_addr) {
266  DRM_ERROR("Can not find hardware status page\n");
267  return -EINVAL;
268  }
269  DRM_DEBUG_DRIVER("hw status page @ %p\n",
270  ring->status_page.page_addr);
271  if (ring->status_page.gfx_addr != 0)
273  else
274  i915_write_hws_pga(dev);
275 
276  DRM_DEBUG_DRIVER("Enabled hardware status page\n");
277 
278  return 0;
279 }
280 
281 static int i915_dma_init(struct drm_device *dev, void *data,
282  struct drm_file *file_priv)
283 {
284  drm_i915_init_t *init = data;
285  int retcode = 0;
286 
287  if (drm_core_check_feature(dev, DRIVER_MODESET))
288  return -ENODEV;
289 
290  switch (init->func) {
291  case I915_INIT_DMA:
292  retcode = i915_initialize(dev, init);
293  break;
294  case I915_CLEANUP_DMA:
295  retcode = i915_dma_cleanup(dev);
296  break;
297  case I915_RESUME_DMA:
298  retcode = i915_dma_resume(dev);
299  break;
300  default:
301  retcode = -EINVAL;
302  break;
303  }
304 
305  return retcode;
306 }
307 
308 /* Implement basically the same security restrictions as hardware does
309  * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
310  *
311  * Most of the calculations below involve calculating the size of a
312  * particular instruction. It's important to get the size right as
313  * that tells us where the next instruction to check is. Any illegal
314  * instruction detected will be given a size of zero, which is a
315  * signal to abort the rest of the buffer.
316  */
317 static int validate_cmd(int cmd)
318 {
319  switch (((cmd >> 29) & 0x7)) {
320  case 0x0:
321  switch ((cmd >> 23) & 0x3f) {
322  case 0x0:
323  return 1; /* MI_NOOP */
324  case 0x4:
325  return 1; /* MI_FLUSH */
326  default:
327  return 0; /* disallow everything else */
328  }
329  break;
330  case 0x1:
331  return 0; /* reserved */
332  case 0x2:
333  return (cmd & 0xff) + 2; /* 2d commands */
334  case 0x3:
335  if (((cmd >> 24) & 0x1f) <= 0x18)
336  return 1;
337 
338  switch ((cmd >> 24) & 0x1f) {
339  case 0x1c:
340  return 1;
341  case 0x1d:
342  switch ((cmd >> 16) & 0xff) {
343  case 0x3:
344  return (cmd & 0x1f) + 2;
345  case 0x4:
346  return (cmd & 0xf) + 2;
347  default:
348  return (cmd & 0xffff) + 2;
349  }
350  case 0x1e:
351  if (cmd & (1 << 23))
352  return (cmd & 0xffff) + 1;
353  else
354  return 1;
355  case 0x1f:
356  if ((cmd & (1 << 23)) == 0) /* inline vertices */
357  return (cmd & 0x1ffff) + 2;
358  else if (cmd & (1 << 17)) /* indirect random */
359  if ((cmd & 0xffff) == 0)
360  return 0; /* unknown length, too hard */
361  else
362  return (((cmd & 0xffff) + 1) / 2) + 1;
363  else
364  return 2; /* indirect sequential */
365  default:
366  return 0;
367  }
368  default:
369  return 0;
370  }
371 
372  return 0;
373 }
374 
375 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
376 {
377  drm_i915_private_t *dev_priv = dev->dev_private;
378  int i, ret;
379 
380  if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
381  return -EINVAL;
382 
383  for (i = 0; i < dwords;) {
384  int sz = validate_cmd(buffer[i]);
385  if (sz == 0 || i + sz > dwords)
386  return -EINVAL;
387  i += sz;
388  }
389 
390  ret = BEGIN_LP_RING((dwords+1)&~1);
391  if (ret)
392  return ret;
393 
394  for (i = 0; i < dwords; i++)
395  OUT_RING(buffer[i]);
396  if (dwords & 1)
397  OUT_RING(0);
398 
399  ADVANCE_LP_RING();
400 
401  return 0;
402 }
403 
404 int
406  struct drm_clip_rect *box,
407  int DR1, int DR4)
408 {
409  struct drm_i915_private *dev_priv = dev->dev_private;
410  int ret;
411 
412  if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
413  box->y2 <= 0 || box->x2 <= 0) {
414  DRM_ERROR("Bad box %d,%d..%d,%d\n",
415  box->x1, box->y1, box->x2, box->y2);
416  return -EINVAL;
417  }
418 
419  if (INTEL_INFO(dev)->gen >= 4) {
420  ret = BEGIN_LP_RING(4);
421  if (ret)
422  return ret;
423 
425  OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
426  OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
427  OUT_RING(DR4);
428  } else {
429  ret = BEGIN_LP_RING(6);
430  if (ret)
431  return ret;
432 
434  OUT_RING(DR1);
435  OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
436  OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
437  OUT_RING(DR4);
438  OUT_RING(0);
439  }
440  ADVANCE_LP_RING();
441 
442  return 0;
443 }
444 
445 /* XXX: Emitting the counter should really be moved to part of the IRQ
446  * emit. For now, do it in both places:
447  */
448 
449 static void i915_emit_breadcrumb(struct drm_device *dev)
450 {
451  drm_i915_private_t *dev_priv = dev->dev_private;
452  struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
453 
454  dev_priv->counter++;
455  if (dev_priv->counter > 0x7FFFFFFFUL)
456  dev_priv->counter = 0;
457  if (master_priv->sarea_priv)
458  master_priv->sarea_priv->last_enqueue = dev_priv->counter;
459 
460  if (BEGIN_LP_RING(4) == 0) {
463  OUT_RING(dev_priv->counter);
464  OUT_RING(0);
465  ADVANCE_LP_RING();
466  }
467 }
468 
469 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
471  struct drm_clip_rect *cliprects,
472  void *cmdbuf)
473 {
474  int nbox = cmd->num_cliprects;
475  int i = 0, count, ret;
476 
477  if (cmd->sz & 0x3) {
478  DRM_ERROR("alignment");
479  return -EINVAL;
480  }
481 
483 
484  count = nbox ? nbox : 1;
485 
486  for (i = 0; i < count; i++) {
487  if (i < nbox) {
488  ret = i915_emit_box(dev, &cliprects[i],
489  cmd->DR1, cmd->DR4);
490  if (ret)
491  return ret;
492  }
493 
494  ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
495  if (ret)
496  return ret;
497  }
498 
499  i915_emit_breadcrumb(dev);
500  return 0;
501 }
502 
503 static int i915_dispatch_batchbuffer(struct drm_device * dev,
504  drm_i915_batchbuffer_t * batch,
505  struct drm_clip_rect *cliprects)
506 {
507  struct drm_i915_private *dev_priv = dev->dev_private;
508  int nbox = batch->num_cliprects;
509  int i, count, ret;
510 
511  if ((batch->start | batch->used) & 0x7) {
512  DRM_ERROR("alignment");
513  return -EINVAL;
514  }
515 
517 
518  count = nbox ? nbox : 1;
519  for (i = 0; i < count; i++) {
520  if (i < nbox) {
521  ret = i915_emit_box(dev, &cliprects[i],
522  batch->DR1, batch->DR4);
523  if (ret)
524  return ret;
525  }
526 
527  if (!IS_I830(dev) && !IS_845G(dev)) {
528  ret = BEGIN_LP_RING(2);
529  if (ret)
530  return ret;
531 
532  if (INTEL_INFO(dev)->gen >= 4) {
534  OUT_RING(batch->start);
535  } else {
536  OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
538  }
539  } else {
540  ret = BEGIN_LP_RING(4);
541  if (ret)
542  return ret;
543 
546  OUT_RING(batch->start + batch->used - 4);
547  OUT_RING(0);
548  }
549  ADVANCE_LP_RING();
550  }
551 
552 
553  if (IS_G4X(dev) || IS_GEN5(dev)) {
554  if (BEGIN_LP_RING(2) == 0) {
556  OUT_RING(MI_NOOP);
557  ADVANCE_LP_RING();
558  }
559  }
560 
561  i915_emit_breadcrumb(dev);
562  return 0;
563 }
564 
565 static int i915_dispatch_flip(struct drm_device * dev)
566 {
567  drm_i915_private_t *dev_priv = dev->dev_private;
568  struct drm_i915_master_private *master_priv =
569  dev->primary->master->driver_priv;
570  int ret;
571 
572  if (!master_priv->sarea_priv)
573  return -EINVAL;
574 
575  DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
576  __func__,
577  dev_priv->dri1.current_page,
578  master_priv->sarea_priv->pf_current_page);
579 
581 
582  ret = BEGIN_LP_RING(10);
583  if (ret)
584  return ret;
585 
587  OUT_RING(0);
588 
590  OUT_RING(0);
591  if (dev_priv->dri1.current_page == 0) {
592  OUT_RING(dev_priv->dri1.back_offset);
593  dev_priv->dri1.current_page = 1;
594  } else {
595  OUT_RING(dev_priv->dri1.front_offset);
596  dev_priv->dri1.current_page = 0;
597  }
598  OUT_RING(0);
599 
601  OUT_RING(0);
602 
603  ADVANCE_LP_RING();
604 
605  master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
606 
607  if (BEGIN_LP_RING(4) == 0) {
610  OUT_RING(dev_priv->counter);
611  OUT_RING(0);
612  ADVANCE_LP_RING();
613  }
614 
615  master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
616  return 0;
617 }
618 
619 static int i915_quiescent(struct drm_device *dev)
620 {
621  struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
622 
624  return intel_wait_ring_idle(ring);
625 }
626 
627 static int i915_flush_ioctl(struct drm_device *dev, void *data,
628  struct drm_file *file_priv)
629 {
630  int ret;
631 
632  if (drm_core_check_feature(dev, DRIVER_MODESET))
633  return -ENODEV;
634 
635  RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
636 
637  mutex_lock(&dev->struct_mutex);
638  ret = i915_quiescent(dev);
639  mutex_unlock(&dev->struct_mutex);
640 
641  return ret;
642 }
643 
644 static int i915_batchbuffer(struct drm_device *dev, void *data,
645  struct drm_file *file_priv)
646 {
647  drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
648  struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
649  drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
650  master_priv->sarea_priv;
651  drm_i915_batchbuffer_t *batch = data;
652  int ret;
653  struct drm_clip_rect *cliprects = NULL;
654 
655  if (drm_core_check_feature(dev, DRIVER_MODESET))
656  return -ENODEV;
657 
658  if (!dev_priv->dri1.allow_batchbuffer) {
659  DRM_ERROR("Batchbuffer ioctl disabled\n");
660  return -EINVAL;
661  }
662 
663  DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
664  batch->start, batch->used, batch->num_cliprects);
665 
666  RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
667 
668  if (batch->num_cliprects < 0)
669  return -EINVAL;
670 
671  if (batch->num_cliprects) {
672  cliprects = kcalloc(batch->num_cliprects,
673  sizeof(struct drm_clip_rect),
674  GFP_KERNEL);
675  if (cliprects == NULL)
676  return -ENOMEM;
677 
678  ret = copy_from_user(cliprects, batch->cliprects,
679  batch->num_cliprects *
680  sizeof(struct drm_clip_rect));
681  if (ret != 0) {
682  ret = -EFAULT;
683  goto fail_free;
684  }
685  }
686 
687  mutex_lock(&dev->struct_mutex);
688  ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
689  mutex_unlock(&dev->struct_mutex);
690 
691  if (sarea_priv)
692  sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
693 
694 fail_free:
695  kfree(cliprects);
696 
697  return ret;
698 }
699 
700 static int i915_cmdbuffer(struct drm_device *dev, void *data,
701  struct drm_file *file_priv)
702 {
703  drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
704  struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
705  drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
706  master_priv->sarea_priv;
707  drm_i915_cmdbuffer_t *cmdbuf = data;
708  struct drm_clip_rect *cliprects = NULL;
709  void *batch_data;
710  int ret;
711 
712  DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
713  cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
714 
715  if (drm_core_check_feature(dev, DRIVER_MODESET))
716  return -ENODEV;
717 
718  RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
719 
720  if (cmdbuf->num_cliprects < 0)
721  return -EINVAL;
722 
723  batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
724  if (batch_data == NULL)
725  return -ENOMEM;
726 
727  ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
728  if (ret != 0) {
729  ret = -EFAULT;
730  goto fail_batch_free;
731  }
732 
733  if (cmdbuf->num_cliprects) {
734  cliprects = kcalloc(cmdbuf->num_cliprects,
735  sizeof(struct drm_clip_rect), GFP_KERNEL);
736  if (cliprects == NULL) {
737  ret = -ENOMEM;
738  goto fail_batch_free;
739  }
740 
741  ret = copy_from_user(cliprects, cmdbuf->cliprects,
742  cmdbuf->num_cliprects *
743  sizeof(struct drm_clip_rect));
744  if (ret != 0) {
745  ret = -EFAULT;
746  goto fail_clip_free;
747  }
748  }
749 
750  mutex_lock(&dev->struct_mutex);
751  ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
752  mutex_unlock(&dev->struct_mutex);
753  if (ret) {
754  DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
755  goto fail_clip_free;
756  }
757 
758  if (sarea_priv)
759  sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
760 
761 fail_clip_free:
762  kfree(cliprects);
763 fail_batch_free:
764  kfree(batch_data);
765 
766  return ret;
767 }
768 
769 static int i915_emit_irq(struct drm_device * dev)
770 {
771  drm_i915_private_t *dev_priv = dev->dev_private;
772  struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
773 
775 
776  DRM_DEBUG_DRIVER("\n");
777 
778  dev_priv->counter++;
779  if (dev_priv->counter > 0x7FFFFFFFUL)
780  dev_priv->counter = 1;
781  if (master_priv->sarea_priv)
782  master_priv->sarea_priv->last_enqueue = dev_priv->counter;
783 
784  if (BEGIN_LP_RING(4) == 0) {
787  OUT_RING(dev_priv->counter);
789  ADVANCE_LP_RING();
790  }
791 
792  return dev_priv->counter;
793 }
794 
795 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
796 {
797  drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
798  struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
799  int ret = 0;
800  struct intel_ring_buffer *ring = LP_RING(dev_priv);
801 
802  DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
803  READ_BREADCRUMB(dev_priv));
804 
805  if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
806  if (master_priv->sarea_priv)
807  master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
808  return 0;
809  }
810 
811  if (master_priv->sarea_priv)
812  master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
813 
814  if (ring->irq_get(ring)) {
815  DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
816  READ_BREADCRUMB(dev_priv) >= irq_nr);
817  ring->irq_put(ring);
818  } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
819  ret = -EBUSY;
820 
821  if (ret == -EBUSY) {
822  DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
823  READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
824  }
825 
826  return ret;
827 }
828 
829 /* Needs the lock as it touches the ring.
830  */
831 static int i915_irq_emit(struct drm_device *dev, void *data,
832  struct drm_file *file_priv)
833 {
834  drm_i915_private_t *dev_priv = dev->dev_private;
836  int result;
837 
838  if (drm_core_check_feature(dev, DRIVER_MODESET))
839  return -ENODEV;
840 
841  if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
842  DRM_ERROR("called with no initialization\n");
843  return -EINVAL;
844  }
845 
846  RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
847 
848  mutex_lock(&dev->struct_mutex);
849  result = i915_emit_irq(dev);
850  mutex_unlock(&dev->struct_mutex);
851 
852  if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
853  DRM_ERROR("copy_to_user\n");
854  return -EFAULT;
855  }
856 
857  return 0;
858 }
859 
860 /* Doesn't need the hardware lock.
861  */
862 static int i915_irq_wait(struct drm_device *dev, void *data,
863  struct drm_file *file_priv)
864 {
865  drm_i915_private_t *dev_priv = dev->dev_private;
866  drm_i915_irq_wait_t *irqwait = data;
867 
868  if (drm_core_check_feature(dev, DRIVER_MODESET))
869  return -ENODEV;
870 
871  if (!dev_priv) {
872  DRM_ERROR("called with no initialization\n");
873  return -EINVAL;
874  }
875 
876  return i915_wait_irq(dev, irqwait->irq_seq);
877 }
878 
879 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
880  struct drm_file *file_priv)
881 {
882  drm_i915_private_t *dev_priv = dev->dev_private;
884 
885  if (drm_core_check_feature(dev, DRIVER_MODESET))
886  return -ENODEV;
887 
888  if (!dev_priv) {
889  DRM_ERROR("called with no initialization\n");
890  return -EINVAL;
891  }
892 
894 
895  return 0;
896 }
897 
901 static int i915_vblank_swap(struct drm_device *dev, void *data,
902  struct drm_file *file_priv)
903 {
904  /* The delayed swap mechanism was fundamentally racy, and has been
905  * removed. The model was that the client requested a delayed flip/swap
906  * from the kernel, then waited for vblank before continuing to perform
907  * rendering. The problem was that the kernel might wake the client
908  * up before it dispatched the vblank swap (since the lock has to be
909  * held while touching the ringbuffer), in which case the client would
910  * clear and start the next frame before the swap occurred, and
911  * flicker would occur in addition to likely missing the vblank.
912  *
913  * In the absence of this ioctl, userland falls back to a correct path
914  * of waiting for a vblank, then dispatching the swap on its own.
915  * Context switching to userland and back is plenty fast enough for
916  * meeting the requirements of vblank swapping.
917  */
918  return -EINVAL;
919 }
920 
921 static int i915_flip_bufs(struct drm_device *dev, void *data,
922  struct drm_file *file_priv)
923 {
924  int ret;
925 
926  if (drm_core_check_feature(dev, DRIVER_MODESET))
927  return -ENODEV;
928 
929  DRM_DEBUG_DRIVER("%s\n", __func__);
930 
931  RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
932 
933  mutex_lock(&dev->struct_mutex);
934  ret = i915_dispatch_flip(dev);
935  mutex_unlock(&dev->struct_mutex);
936 
937  return ret;
938 }
939 
940 static int i915_getparam(struct drm_device *dev, void *data,
941  struct drm_file *file_priv)
942 {
943  drm_i915_private_t *dev_priv = dev->dev_private;
945  int value;
946 
947  if (!dev_priv) {
948  DRM_ERROR("called with no initialization\n");
949  return -EINVAL;
950  }
951 
952  switch (param->param) {
954  value = dev->pdev->irq ? 1 : 0;
955  break;
957  value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
958  break;
960  value = READ_BREADCRUMB(dev_priv);
961  break;
963  value = dev->pci_device;
964  break;
965  case I915_PARAM_HAS_GEM:
966  value = 1;
967  break;
969  value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
970  break;
972  value = dev_priv->overlay ? 1 : 0;
973  break;
975  value = 1;
976  break;
978  /* depends on GEM */
979  value = 1;
980  break;
981  case I915_PARAM_HAS_BSD:
982  value = intel_ring_initialized(&dev_priv->ring[VCS]);
983  break;
984  case I915_PARAM_HAS_BLT:
985  value = intel_ring_initialized(&dev_priv->ring[BCS]);
986  break;
988  value = 1;
989  break;
991  value = 1;
992  break;
994  value = INTEL_INFO(dev)->gen >= 4;
995  break;
997  value = 1;
998  break;
1000  value = 1;
1001  break;
1002  case I915_PARAM_HAS_LLC:
1003  value = HAS_LLC(dev);
1004  break;
1006  value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1007  break;
1009  value = 1;
1010  break;
1012  value = i915_semaphore_is_enabled(dev);
1013  break;
1015  value = 1;
1016  break;
1017  default:
1018  DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1019  param->param);
1020  return -EINVAL;
1021  }
1022 
1023  if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1024  DRM_ERROR("DRM_COPY_TO_USER failed\n");
1025  return -EFAULT;
1026  }
1027 
1028  return 0;
1029 }
1030 
1031 static int i915_setparam(struct drm_device *dev, void *data,
1032  struct drm_file *file_priv)
1033 {
1034  drm_i915_private_t *dev_priv = dev->dev_private;
1035  drm_i915_setparam_t *param = data;
1036 
1037  if (!dev_priv) {
1038  DRM_ERROR("called with no initialization\n");
1039  return -EINVAL;
1040  }
1041 
1042  switch (param->param) {
1044  break;
1046  break;
1048  dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1049  break;
1051  if (param->value > dev_priv->num_fence_regs ||
1052  param->value < 0)
1053  return -EINVAL;
1054  /* Userspace can use first N regs */
1055  dev_priv->fence_reg_start = param->value;
1056  break;
1057  default:
1058  DRM_DEBUG_DRIVER("unknown parameter %d\n",
1059  param->param);
1060  return -EINVAL;
1061  }
1062 
1063  return 0;
1064 }
1065 
1066 static int i915_set_status_page(struct drm_device *dev, void *data,
1067  struct drm_file *file_priv)
1068 {
1069  drm_i915_private_t *dev_priv = dev->dev_private;
1070  drm_i915_hws_addr_t *hws = data;
1071  struct intel_ring_buffer *ring = LP_RING(dev_priv);
1072 
1073  if (drm_core_check_feature(dev, DRIVER_MODESET))
1074  return -ENODEV;
1075 
1076  if (!I915_NEED_GFX_HWS(dev))
1077  return -EINVAL;
1078 
1079  if (!dev_priv) {
1080  DRM_ERROR("called with no initialization\n");
1081  return -EINVAL;
1082  }
1083 
1084  if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1085  WARN(1, "tried to set status page when mode setting active\n");
1086  return 0;
1087  }
1088 
1089  DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1090 
1091  ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1092 
1093  dev_priv->dri1.gfx_hws_cpu_addr =
1094  ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
1095  if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1096  i915_dma_cleanup(dev);
1097  ring->status_page.gfx_addr = 0;
1098  DRM_ERROR("can not ioremap virtual address for"
1099  " G33 hw status page\n");
1100  return -ENOMEM;
1101  }
1102 
1103  memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1104  I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1105 
1106  DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1107  ring->status_page.gfx_addr);
1108  DRM_DEBUG_DRIVER("load hws at %p\n",
1109  ring->status_page.page_addr);
1110  return 0;
1111 }
1112 
1113 static int i915_get_bridge_dev(struct drm_device *dev)
1114 {
1115  struct drm_i915_private *dev_priv = dev->dev_private;
1116 
1117  dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1118  if (!dev_priv->bridge_dev) {
1119  DRM_ERROR("bridge device not found\n");
1120  return -1;
1121  }
1122  return 0;
1123 }
1124 
1125 #define MCHBAR_I915 0x44
1126 #define MCHBAR_I965 0x48
1127 #define MCHBAR_SIZE (4*4096)
1128 
1129 #define DEVEN_REG 0x54
1130 #define DEVEN_MCHBAR_EN (1 << 28)
1131 
1132 /* Allocate space for the MCH regs if needed, return nonzero on error */
1133 static int
1134 intel_alloc_mchbar_resource(struct drm_device *dev)
1135 {
1136  drm_i915_private_t *dev_priv = dev->dev_private;
1137  int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1138  u32 temp_lo, temp_hi = 0;
1139  u64 mchbar_addr;
1140  int ret;
1141 
1142  if (INTEL_INFO(dev)->gen >= 4)
1143  pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1144  pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1145  mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1146 
1147  /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1148 #ifdef CONFIG_PNP
1149  if (mchbar_addr &&
1150  pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1151  return 0;
1152 #endif
1153 
1154  /* Get some space for it */
1155  dev_priv->mch_res.name = "i915 MCHBAR";
1156  dev_priv->mch_res.flags = IORESOURCE_MEM;
1157  ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1158  &dev_priv->mch_res,
1162  dev_priv->bridge_dev);
1163  if (ret) {
1164  DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1165  dev_priv->mch_res.start = 0;
1166  return ret;
1167  }
1168 
1169  if (INTEL_INFO(dev)->gen >= 4)
1170  pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1171  upper_32_bits(dev_priv->mch_res.start));
1172 
1173  pci_write_config_dword(dev_priv->bridge_dev, reg,
1174  lower_32_bits(dev_priv->mch_res.start));
1175  return 0;
1176 }
1177 
1178 /* Setup MCHBAR if possible, return true if we should disable it again */
1179 static void
1180 intel_setup_mchbar(struct drm_device *dev)
1181 {
1182  drm_i915_private_t *dev_priv = dev->dev_private;
1183  int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1184  u32 temp;
1185  bool enabled;
1186 
1187  dev_priv->mchbar_need_disable = false;
1188 
1189  if (IS_I915G(dev) || IS_I915GM(dev)) {
1190  pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1191  enabled = !!(temp & DEVEN_MCHBAR_EN);
1192  } else {
1193  pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1194  enabled = temp & 1;
1195  }
1196 
1197  /* If it's already enabled, don't have to do anything */
1198  if (enabled)
1199  return;
1200 
1201  if (intel_alloc_mchbar_resource(dev))
1202  return;
1203 
1204  dev_priv->mchbar_need_disable = true;
1205 
1206  /* Space is allocated or reserved, so enable it. */
1207  if (IS_I915G(dev) || IS_I915GM(dev)) {
1208  pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1209  temp | DEVEN_MCHBAR_EN);
1210  } else {
1211  pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1212  pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1213  }
1214 }
1215 
1216 static void
1217 intel_teardown_mchbar(struct drm_device *dev)
1218 {
1219  drm_i915_private_t *dev_priv = dev->dev_private;
1220  int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1221  u32 temp;
1222 
1223  if (dev_priv->mchbar_need_disable) {
1224  if (IS_I915G(dev) || IS_I915GM(dev)) {
1225  pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1226  temp &= ~DEVEN_MCHBAR_EN;
1227  pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1228  } else {
1229  pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1230  temp &= ~1;
1231  pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1232  }
1233  }
1234 
1235  if (dev_priv->mch_res.start)
1236  release_resource(&dev_priv->mch_res);
1237 }
1238 
1239 /* true = enable decode, false = disable decoder */
1240 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1241 {
1242  struct drm_device *dev = cookie;
1243 
1244  intel_modeset_vga_set_state(dev, state);
1245  if (state)
1248  else
1250 }
1251 
1252 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1253 {
1254  struct drm_device *dev = pci_get_drvdata(pdev);
1255  pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1256  if (state == VGA_SWITCHEROO_ON) {
1257  pr_info("switched on\n");
1258  dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1259  /* i915 resume handler doesn't set to D0 */
1260  pci_set_power_state(dev->pdev, PCI_D0);
1261  i915_resume(dev);
1262  dev->switch_power_state = DRM_SWITCH_POWER_ON;
1263  } else {
1264  pr_err("switched off\n");
1265  dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1266  i915_suspend(dev, pmm);
1267  dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1268  }
1269 }
1270 
1271 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1272 {
1273  struct drm_device *dev = pci_get_drvdata(pdev);
1274  bool can_switch;
1275 
1276  spin_lock(&dev->count_lock);
1277  can_switch = (dev->open_count == 0);
1278  spin_unlock(&dev->count_lock);
1279  return can_switch;
1280 }
1281 
1282 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1283  .set_gpu_state = i915_switcheroo_set_state,
1284  .reprobe = NULL,
1285  .can_switch = i915_switcheroo_can_switch,
1286 };
1287 
1288 static int i915_load_modeset_init(struct drm_device *dev)
1289 {
1290  struct drm_i915_private *dev_priv = dev->dev_private;
1291  int ret;
1292 
1293  ret = intel_parse_bios(dev);
1294  if (ret)
1295  DRM_INFO("failed to find VBIOS tables\n");
1296 
1297  /* If we have > 1 VGA cards, then we need to arbitrate access
1298  * to the common VGA resources.
1299  *
1300  * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1301  * then we do not take part in VGA arbitration and the
1302  * vga_client_register() fails with -ENODEV.
1303  */
1304  ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1305  if (ret && ret != -ENODEV)
1306  goto out;
1307 
1309 
1310  ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1311  if (ret)
1312  goto cleanup_vga_client;
1313 
1314  /* Initialise stolen first so that we may reserve preallocated
1315  * objects for the BIOS to KMS transition.
1316  */
1317  ret = i915_gem_init_stolen(dev);
1318  if (ret)
1319  goto cleanup_vga_switcheroo;
1320 
1321  intel_modeset_init(dev);
1322 
1323  ret = i915_gem_init(dev);
1324  if (ret)
1325  goto cleanup_gem_stolen;
1326 
1328 
1329  ret = drm_irq_install(dev);
1330  if (ret)
1331  goto cleanup_gem;
1332 
1333  /* Always safe in the mode setting case. */
1334  /* FIXME: do pre/post-mode set stuff in core KMS code */
1335  dev->vblank_disable_allowed = 1;
1336 
1337  ret = intel_fbdev_init(dev);
1338  if (ret)
1339  goto cleanup_irq;
1340 
1342 
1343  /* We're off and running w/KMS */
1344  dev_priv->mm.suspended = 0;
1345 
1346  return 0;
1347 
1348 cleanup_irq:
1349  drm_irq_uninstall(dev);
1350 cleanup_gem:
1351  mutex_lock(&dev->struct_mutex);
1353  mutex_unlock(&dev->struct_mutex);
1355 cleanup_gem_stolen:
1357 cleanup_vga_switcheroo:
1359 cleanup_vga_client:
1360  vga_client_register(dev->pdev, NULL, NULL, NULL);
1361 out:
1362  return ret;
1363 }
1364 
1365 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1366 {
1367  struct drm_i915_master_private *master_priv;
1368 
1369  master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1370  if (!master_priv)
1371  return -ENOMEM;
1372 
1373  master->driver_priv = master_priv;
1374  return 0;
1375 }
1376 
1377 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1378 {
1379  struct drm_i915_master_private *master_priv = master->driver_priv;
1380 
1381  if (!master_priv)
1382  return;
1383 
1384  kfree(master_priv);
1385 
1386  master->driver_priv = NULL;
1387 }
1388 
1389 static void
1390 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1391  unsigned long size)
1392 {
1393  dev_priv->mm.gtt_mtrr = -1;
1394 
1395 #if defined(CONFIG_X86_PAT)
1396  if (cpu_has_pat)
1397  return;
1398 #endif
1399 
1400  /* Set up a WC MTRR for non-PAT systems. This is more common than
1401  * one would think, because the kernel disables PAT on first
1402  * generation Core chips because WC PAT gets overridden by a UC
1403  * MTRR if present. Even if a UC MTRR isn't present.
1404  */
1405  dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1406  if (dev_priv->mm.gtt_mtrr < 0) {
1407  DRM_INFO("MTRR allocation failed. Graphics "
1408  "performance may suffer.\n");
1409  }
1410 }
1411 
1412 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1413 {
1414  struct apertures_struct *ap;
1415  struct pci_dev *pdev = dev_priv->dev->pdev;
1416  bool primary;
1417 
1418  ap = alloc_apertures(1);
1419  if (!ap)
1420  return;
1421 
1422  ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1423  ap->ranges[0].size =
1424  dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1425  primary =
1427 
1428  remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1429 
1430  kfree(ap);
1431 }
1432 
1433 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1434 {
1435  const struct intel_device_info *info = dev_priv->info;
1436 
1437 #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
1438 #define DEV_INFO_SEP ,
1439  DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1440  "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1441  info->gen,
1442  dev_priv->dev->pdev->device,
1443  DEV_INFO_FLAGS);
1444 #undef DEV_INFO_FLAG
1445 #undef DEV_INFO_SEP
1446 }
1447 
1459 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1460 {
1461  struct drm_i915_private *dev_priv;
1462  struct intel_device_info *info;
1463  int ret = 0, mmio_bar, mmio_size;
1464  uint32_t aperture_size;
1465 
1466  info = (struct intel_device_info *) flags;
1467 
1468  /* Refuse to load on gen6+ without kms enabled. */
1469  if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1470  return -ENODEV;
1471 
1472  /* i915 has 4 more counters */
1473  dev->counters += 4;
1474  dev->types[6] = _DRM_STAT_IRQ;
1475  dev->types[7] = _DRM_STAT_PRIMARY;
1476  dev->types[8] = _DRM_STAT_SECONDARY;
1477  dev->types[9] = _DRM_STAT_DMA;
1478 
1479  dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1480  if (dev_priv == NULL)
1481  return -ENOMEM;
1482 
1483  dev->dev_private = (void *)dev_priv;
1484  dev_priv->dev = dev;
1485  dev_priv->info = info;
1486 
1487  i915_dump_device_info(dev_priv);
1488 
1489  if (i915_get_bridge_dev(dev)) {
1490  ret = -EIO;
1491  goto free_priv;
1492  }
1493 
1494  ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
1495  if (!ret) {
1496  DRM_ERROR("failed to set up gmch\n");
1497  ret = -EIO;
1498  goto put_bridge;
1499  }
1500 
1501  dev_priv->mm.gtt = intel_gtt_get();
1502  if (!dev_priv->mm.gtt) {
1503  DRM_ERROR("Failed to initialize GTT\n");
1504  ret = -ENODEV;
1505  goto put_gmch;
1506  }
1507 
1508  if (drm_core_check_feature(dev, DRIVER_MODESET))
1509  i915_kick_out_firmware_fb(dev_priv);
1510 
1511  pci_set_master(dev->pdev);
1512 
1513  /* overlay on gen2 is broken and can't address above 1G */
1514  if (IS_GEN2(dev))
1515  dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1516 
1517  /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1518  * using 32bit addressing, overwriting memory if HWS is located
1519  * above 4GB.
1520  *
1521  * The documentation also mentions an issue with undefined
1522  * behaviour if any general state is accessed within a page above 4GB,
1523  * which also needs to be handled carefully.
1524  */
1525  if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1526  dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1527 
1528  mmio_bar = IS_GEN2(dev) ? 1 : 0;
1529  /* Before gen4, the registers and the GTT are behind different BARs.
1530  * However, from gen4 onwards, the registers and the GTT are shared
1531  * in the same BAR, so we want to restrict this ioremap from
1532  * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1533  * the register BAR remains the same size for all the earlier
1534  * generations up to Ironlake.
1535  */
1536  if (info->gen < 5)
1537  mmio_size = 512*1024;
1538  else
1539  mmio_size = 2*1024*1024;
1540 
1541  dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1542  if (!dev_priv->regs) {
1543  DRM_ERROR("failed to map registers\n");
1544  ret = -EIO;
1545  goto put_gmch;
1546  }
1547 
1548  aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1549  dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1550 
1551  dev_priv->mm.gtt_mapping =
1552  io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
1553  aperture_size);
1554  if (dev_priv->mm.gtt_mapping == NULL) {
1555  ret = -EIO;
1556  goto out_rmmap;
1557  }
1558 
1559  i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
1560  aperture_size);
1561 
1562  /* The i915 workqueue is primarily used for batched retirement of
1563  * requests (and thus managing bo) once the task has been completed
1564  * by the GPU. i915_gem_retire_requests() is called directly when we
1565  * need high-priority retirement, such as waiting for an explicit
1566  * bo.
1567  *
1568  * It is also used for periodic low-priority events, such as
1569  * idle-timers and recording error state.
1570  *
1571  * All tasks on the workqueue are expected to acquire the dev mutex
1572  * so there is no point in running more than one instance of the
1573  * workqueue at any time. Use an ordered one.
1574  */
1575  dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1576  if (dev_priv->wq == NULL) {
1577  DRM_ERROR("Failed to create our workqueue.\n");
1578  ret = -ENOMEM;
1579  goto out_mtrrfree;
1580  }
1581 
1582  /* This must be called before any calls to HAS_PCH_* */
1583  intel_detect_pch(dev);
1584 
1585  intel_irq_init(dev);
1586  intel_gt_init(dev);
1587 
1588  /* Try to make sure MCHBAR is enabled before poking at it */
1589  intel_setup_mchbar(dev);
1590  intel_setup_gmbus(dev);
1591  intel_opregion_setup(dev);
1592 
1593  /* Make sure the bios did its job and set up vital registers */
1594  intel_setup_bios(dev);
1595 
1596  i915_gem_load(dev);
1597 
1598  /* Init HWS */
1599  if (!I915_NEED_GFX_HWS(dev)) {
1600  ret = i915_init_phys_hws(dev);
1601  if (ret)
1602  goto out_gem_unload;
1603  }
1604 
1605  /* On the 945G/GM, the chipset reports the MSI capability on the
1606  * integrated graphics even though the support isn't actually there
1607  * according to the published specs. It doesn't appear to function
1608  * correctly in testing on 945G.
1609  * This may be a side effect of MSI having been made available for PEG
1610  * and the registers being closely associated.
1611  *
1612  * According to chipset errata, on the 965GM, MSI interrupts may
1613  * be lost or delayed, but we use them anyways to avoid
1614  * stuck interrupts on some machines.
1615  */
1616  if (!IS_I945G(dev) && !IS_I945GM(dev))
1617  pci_enable_msi(dev->pdev);
1618 
1619  spin_lock_init(&dev_priv->irq_lock);
1620  spin_lock_init(&dev_priv->error_lock);
1621  spin_lock_init(&dev_priv->rps.lock);
1622  spin_lock_init(&dev_priv->dpio_lock);
1623 
1624  if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1625  dev_priv->num_pipe = 3;
1626  else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1627  dev_priv->num_pipe = 2;
1628  else
1629  dev_priv->num_pipe = 1;
1630 
1631  ret = drm_vblank_init(dev, dev_priv->num_pipe);
1632  if (ret)
1633  goto out_gem_unload;
1634 
1635  /* Start out suspended */
1636  dev_priv->mm.suspended = 1;
1637 
1638  if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1639  ret = i915_load_modeset_init(dev);
1640  if (ret < 0) {
1641  DRM_ERROR("failed to init modeset\n");
1642  goto out_gem_unload;
1643  }
1644  }
1645 
1646  i915_setup_sysfs(dev);
1647 
1648  /* Must be done after probing outputs */
1649  intel_opregion_init(dev);
1651 
1653  (unsigned long) dev);
1654 
1655  if (IS_GEN5(dev))
1656  intel_gpu_ips_init(dev_priv);
1657 
1658  return 0;
1659 
1660 out_gem_unload:
1661  if (dev_priv->mm.inactive_shrinker.shrink)
1662  unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1663 
1664  if (dev->pdev->msi_enabled)
1665  pci_disable_msi(dev->pdev);
1666 
1667  intel_teardown_gmbus(dev);
1668  intel_teardown_mchbar(dev);
1669  destroy_workqueue(dev_priv->wq);
1670 out_mtrrfree:
1671  if (dev_priv->mm.gtt_mtrr >= 0) {
1672  mtrr_del(dev_priv->mm.gtt_mtrr,
1673  dev_priv->mm.gtt_base_addr,
1674  aperture_size);
1675  dev_priv->mm.gtt_mtrr = -1;
1676  }
1677  io_mapping_free(dev_priv->mm.gtt_mapping);
1678 out_rmmap:
1679  pci_iounmap(dev->pdev, dev_priv->regs);
1680 put_gmch:
1682 put_bridge:
1683  pci_dev_put(dev_priv->bridge_dev);
1684 free_priv:
1685  kfree(dev_priv);
1686  return ret;
1687 }
1688 
1690 {
1691  struct drm_i915_private *dev_priv = dev->dev_private;
1692  int ret;
1693 
1695 
1696  i915_teardown_sysfs(dev);
1697 
1698  if (dev_priv->mm.inactive_shrinker.shrink)
1699  unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1700 
1701  mutex_lock(&dev->struct_mutex);
1702  ret = i915_gpu_idle(dev);
1703  if (ret)
1704  DRM_ERROR("failed to idle hardware: %d\n", ret);
1706  mutex_unlock(&dev->struct_mutex);
1707 
1708  /* Cancel the retire work handler, which should be idle now. */
1709  cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1710 
1711  io_mapping_free(dev_priv->mm.gtt_mapping);
1712  if (dev_priv->mm.gtt_mtrr >= 0) {
1713  mtrr_del(dev_priv->mm.gtt_mtrr,
1714  dev_priv->mm.gtt_base_addr,
1715  dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1716  dev_priv->mm.gtt_mtrr = -1;
1717  }
1718 
1720 
1721  if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1722  intel_fbdev_fini(dev);
1723  intel_modeset_cleanup(dev);
1724 
1725  /*
1726  * free the memory space allocated for the child device
1727  * config parsed from VBT
1728  */
1729  if (dev_priv->child_dev && dev_priv->child_dev_num) {
1730  kfree(dev_priv->child_dev);
1731  dev_priv->child_dev = NULL;
1732  dev_priv->child_dev_num = 0;
1733  }
1734 
1736  vga_client_register(dev->pdev, NULL, NULL, NULL);
1737  }
1738 
1739  /* Free error state after interrupts are fully disabled. */
1740  del_timer_sync(&dev_priv->hangcheck_timer);
1741  cancel_work_sync(&dev_priv->error_work);
1743 
1744  if (dev->pdev->msi_enabled)
1745  pci_disable_msi(dev->pdev);
1746 
1747  intel_opregion_fini(dev);
1748 
1749  if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1750  /* Flush any outstanding unpin_work. */
1751  flush_workqueue(dev_priv->wq);
1752 
1753  mutex_lock(&dev->struct_mutex);
1756  i915_gem_context_fini(dev);
1757  mutex_unlock(&dev->struct_mutex);
1760  drm_mm_takedown(&dev_priv->mm.stolen);
1761 
1762  intel_cleanup_overlay(dev);
1763 
1764  if (!I915_NEED_GFX_HWS(dev))
1765  i915_free_hws(dev);
1766  }
1767 
1768  if (dev_priv->regs != NULL)
1769  pci_iounmap(dev->pdev, dev_priv->regs);
1770 
1771  intel_teardown_gmbus(dev);
1772  intel_teardown_mchbar(dev);
1773 
1774  destroy_workqueue(dev_priv->wq);
1775 
1776  pci_dev_put(dev_priv->bridge_dev);
1777  kfree(dev->dev_private);
1778 
1779  return 0;
1780 }
1781 
1782 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1783 {
1784  struct drm_i915_file_private *file_priv;
1785 
1786  DRM_DEBUG_DRIVER("\n");
1787  file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1788  if (!file_priv)
1789  return -ENOMEM;
1790 
1791  file->driver_priv = file_priv;
1792 
1793  spin_lock_init(&file_priv->mm.lock);
1794  INIT_LIST_HEAD(&file_priv->mm.request_list);
1795 
1796  idr_init(&file_priv->context_idr);
1797 
1798  return 0;
1799 }
1800 
1814 {
1815  drm_i915_private_t *dev_priv = dev->dev_private;
1816 
1817  /* On gen6+ we refuse to init without kms enabled, but then the drm core
1818  * goes right around and calls lastclose. Check for this and don't clean
1819  * up anything. */
1820  if (!dev_priv)
1821  return;
1822 
1823  if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1824  intel_fb_restore_mode(dev);
1826  return;
1827  }
1828 
1829  i915_gem_lastclose(dev);
1830 
1831  i915_dma_cleanup(dev);
1832 }
1833 
1834 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1835 {
1836  i915_gem_context_close(dev, file_priv);
1837  i915_gem_release(dev, file_priv);
1838 }
1839 
1840 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1841 {
1842  struct drm_i915_file_private *file_priv = file->driver_priv;
1843 
1844  kfree(file_priv);
1845 }
1846 
1847 struct drm_ioctl_desc i915_ioctls[] = {
1848  DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1849  DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1850  DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1851  DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1852  DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1853  DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1854  DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1855  DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1856  DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1857  DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1858  DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1859  DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1860  DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1861  DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1862  DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1863  DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1864  DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1865  DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1866  DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1867  DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1868  DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1869  DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1870  DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1871  DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1872  DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1873  DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1874  DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1875  DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1876  DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1877  DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1878  DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1879  DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1880  DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1881  DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1882  DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1883  DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1884  DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1885  DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1886  DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1887  DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1888  DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1889  DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1890  DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1891  DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1892  DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1893  DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1894  DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1895  DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1896 };
1897 
1898 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1899 
1900 /*
1901  * This is really ugly: Because old userspace abused the linux agp interface to
1902  * manage the gtt, we need to claim that all intel devices are agp. For
1903  * otherwise the drm core refuses to initialize the agp support code.
1904  */
1906 {
1907  return 1;
1908 }