|
| enum | {
MLX4_FLAG_MSI_X = 1 << 0,
MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
MLX4_FLAG_MASTER = 1 << 2,
MLX4_FLAG_SLAVE = 1 << 3,
MLX4_FLAG_SRIOV = 1 << 4
} |
| |
| enum | { MLX4_PORT_CAP_IS_SM = 1 << 1,
MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19
} |
| |
| enum | { MLX4_MAX_PORTS = 2,
MLX4_MAX_PORT_PKEYS = 128
} |
| |
| enum | { MLX4_BOARD_ID_LEN = 64
} |
| |
| enum | {
MLX4_MAX_NUM_PF = 16,
MLX4_MAX_NUM_VF = 64,
MLX4_MFUNC_MAX = 80,
MLX4_MAX_EQ_NUM = 1024,
MLX4_MFUNC_EQ_NUM = 4,
MLX4_MFUNC_MAX_EQES = 8,
MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
} |
| |
| enum | { MLX4_STEERING_MODE_A0,
MLX4_STEERING_MODE_B0,
MLX4_STEERING_MODE_DEVICE_MANAGED
} |
| |
| enum | {
MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59
} |
| |
| enum | { MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3
} |
| |
| enum | {
MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11
} |
| |
| enum | mlx4_event {
MLX4_EVENT_TYPE_COMP = 0x00,
MLX4_EVENT_TYPE_PATH_MIG = 0x01,
MLX4_EVENT_TYPE_COMM_EST = 0x02,
MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
MLX4_EVENT_TYPE_CMD = 0x0a,
MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
MLX4_EVENT_TYPE_NONE = 0xff
} |
| |
| enum | { MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
} |
| |
| enum | { MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0
} |
| |
| enum | slave_port_state { SLAVE_PORT_DOWN = 0,
SLAVE_PENDING_UP,
SLAVE_PORT_UP
} |
| |
| enum | slave_port_gen_event { SLAVE_PORT_GEN_EVENT_DOWN = 0,
SLAVE_PORT_GEN_EVENT_UP,
SLAVE_PORT_GEN_EVENT_NONE
} |
| |
| enum | slave_port_state_event { MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
MLX4_PORT_STATE_IB_EVENT_GID_INVALID
} |
| |
| enum | {
MLX4_PERM_LOCAL_READ = 1 << 10,
MLX4_PERM_LOCAL_WRITE = 1 << 11,
MLX4_PERM_REMOTE_READ = 1 << 12,
MLX4_PERM_REMOTE_WRITE = 1 << 13,
MLX4_PERM_ATOMIC = 1 << 14
} |
| |
| enum | {
MLX4_OPCODE_NOP = 0x00,
MLX4_OPCODE_SEND_INVAL = 0x01,
MLX4_OPCODE_RDMA_WRITE = 0x08,
MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
MLX4_OPCODE_SEND = 0x0a,
MLX4_OPCODE_SEND_IMM = 0x0b,
MLX4_OPCODE_LSO = 0x0e,
MLX4_OPCODE_RDMA_READ = 0x10,
MLX4_OPCODE_ATOMIC_CS = 0x11,
MLX4_OPCODE_ATOMIC_FA = 0x12,
MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
MLX4_OPCODE_BIND_MW = 0x18,
MLX4_OPCODE_FMR = 0x19,
MLX4_OPCODE_LOCAL_INVAL = 0x1b,
MLX4_OPCODE_CONFIG_CMD = 0x1f,
MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
MLX4_RECV_OPCODE_SEND = 0x01,
MLX4_RECV_OPCODE_SEND_IMM = 0x02,
MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
MLX4_CQE_OPCODE_ERROR = 0x1e,
MLX4_CQE_OPCODE_RESIZE = 0x16
} |
| |
| enum | { MLX4_STAT_RATE_OFFSET = 5
} |
| |
| enum | mlx4_protocol { MLX4_PROT_IB_IPV6 = 0,
MLX4_PROT_ETH,
MLX4_PROT_IB_IPV4,
MLX4_PROT_FCOE
} |
| |
| enum | { MLX4_MTT_FLAG_PRESENT = 1
} |
| |
| enum | mlx4_qp_region {
MLX4_QP_REGION_FW = 0,
MLX4_QP_REGION_ETH_ADDR,
MLX4_QP_REGION_FC_ADDR,
MLX4_QP_REGION_FC_EXCH,
MLX4_NUM_QP_REGION
} |
| |
| enum | mlx4_port_type { MLX4_PORT_TYPE_NONE = 0,
MLX4_PORT_TYPE_IB = 1,
MLX4_PORT_TYPE_ETH = 2,
MLX4_PORT_TYPE_AUTO = 3
} |
| |
| enum | mlx4_special_vlan_idx { MLX4_NO_VLAN_IDX = 0,
MLX4_VLAN_MISS_IDX,
MLX4_VLAN_REGULAR
} |
| |
| enum | mlx4_steer_type { MLX4_MC_STEER = 0,
MLX4_UC_STEER,
MLX4_NUM_STEERS
} |
| |
| enum | { MLX4_NUM_FEXCH = 64 * 1024
} |
| |
| enum | { MLX4_MAX_FAST_REG_PAGES = 511
} |
| |
| enum | { MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16
} |
| |
| enum | {
MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4
} |
| |
| enum | { MLX4_DB_PER_PAGE = PAGE_SIZE / 4
} |
| |
| enum | { MLX4_DOMAIN_UVERBS = 0x1000,
MLX4_DOMAIN_ETHTOOL = 0x2000,
MLX4_DOMAIN_RFS = 0x3000,
MLX4_DOMAIN_NIC = 0x5000
} |
| |
| enum | mlx4_net_trans_rule_id {
MLX4_NET_TRANS_RULE_ID_ETH = 0,
MLX4_NET_TRANS_RULE_ID_IB,
MLX4_NET_TRANS_RULE_ID_IPV6,
MLX4_NET_TRANS_RULE_ID_IPV4,
MLX4_NET_TRANS_RULE_ID_TCP,
MLX4_NET_TRANS_RULE_ID_UDP,
MLX4_NET_TRANS_RULE_NUM
} |
| |
| enum | mlx4_net_trans_promisc_mode { MLX4_FS_PROMISC_NONE = 0,
MLX4_FS_PROMISC_UPLINK,
MLX4_FS_PROMISC_FUNCTION_PORT,
MLX4_FS_PROMISC_ALL_MULTI
} |
| |
| enum | mlx4_net_trans_hw_rule_queue { MLX4_NET_TRANS_Q_FIFO,
MLX4_NET_TRANS_Q_LIFO
} |
| |
|
| void | handle_port_mgmt_change_event (struct work_struct *work) |
| |
| int | mlx4_buf_alloc (struct mlx4_dev *dev, int size, int max_direct, struct mlx4_buf *buf) |
| |
| void | mlx4_buf_free (struct mlx4_dev *dev, int size, struct mlx4_buf *buf) |
| |
| int | mlx4_pd_alloc (struct mlx4_dev *dev, u32 *pdn) |
| |
| void | mlx4_pd_free (struct mlx4_dev *dev, u32 pdn) |
| |
| int | mlx4_xrcd_alloc (struct mlx4_dev *dev, u32 *xrcdn) |
| |
| void | mlx4_xrcd_free (struct mlx4_dev *dev, u32 xrcdn) |
| |
| int | mlx4_uar_alloc (struct mlx4_dev *dev, struct mlx4_uar *uar) |
| |
| void | mlx4_uar_free (struct mlx4_dev *dev, struct mlx4_uar *uar) |
| |
| int | mlx4_bf_alloc (struct mlx4_dev *dev, struct mlx4_bf *bf) |
| |
| void | mlx4_bf_free (struct mlx4_dev *dev, struct mlx4_bf *bf) |
| |
| int | mlx4_mtt_init (struct mlx4_dev *dev, int npages, int page_shift, struct mlx4_mtt *mtt) |
| |
| void | mlx4_mtt_cleanup (struct mlx4_dev *dev, struct mlx4_mtt *mtt) |
| |
| u64 | mlx4_mtt_addr (struct mlx4_dev *dev, struct mlx4_mtt *mtt) |
| |
| int | mlx4_mr_alloc (struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, int npages, int page_shift, struct mlx4_mr *mr) |
| |
| void | mlx4_mr_free (struct mlx4_dev *dev, struct mlx4_mr *mr) |
| |
| int | mlx4_mr_enable (struct mlx4_dev *dev, struct mlx4_mr *mr) |
| |
| int | mlx4_write_mtt (struct mlx4_dev *dev, struct mlx4_mtt *mtt, int start_index, int npages, u64 *page_list) |
| |
| int | mlx4_buf_write_mtt (struct mlx4_dev *dev, struct mlx4_mtt *mtt, struct mlx4_buf *buf) |
| |
| int | mlx4_db_alloc (struct mlx4_dev *dev, struct mlx4_db *db, int order) |
| |
| void | mlx4_db_free (struct mlx4_dev *dev, struct mlx4_db *db) |
| |
| int | mlx4_alloc_hwq_res (struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, int size, int max_direct) |
| |
| void | mlx4_free_hwq_res (struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, int size) |
| |
| int | mlx4_cq_alloc (struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, unsigned vector, int collapsed) |
| |
| void | mlx4_cq_free (struct mlx4_dev *dev, struct mlx4_cq *cq) |
| |
| int | mlx4_qp_reserve_range (struct mlx4_dev *dev, int cnt, int align, int *base) |
| |
| void | mlx4_qp_release_range (struct mlx4_dev *dev, int base_qpn, int cnt) |
| |
| int | mlx4_qp_alloc (struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp) |
| |
| void | mlx4_qp_free (struct mlx4_dev *dev, struct mlx4_qp *qp) |
| |
| int | mlx4_srq_alloc (struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq) |
| |
| void | mlx4_srq_free (struct mlx4_dev *dev, struct mlx4_srq *srq) |
| |
| int | mlx4_srq_arm (struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark) |
| |
| int | mlx4_srq_query (struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark) |
| |
| int | mlx4_INIT_PORT (struct mlx4_dev *dev, int port) |
| |
| int | mlx4_CLOSE_PORT (struct mlx4_dev *dev, int port) |
| |
| int | mlx4_unicast_attach (struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], int block_mcast_loopback, enum mlx4_protocol prot) |
| |
| int | mlx4_unicast_detach (struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], enum mlx4_protocol prot) |
| |
| int | mlx4_multicast_attach (struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], u8 port, int block_mcast_loopback, enum mlx4_protocol protocol, u64 *reg_id) |
| |
| int | mlx4_multicast_detach (struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], enum mlx4_protocol protocol, u64 reg_id) |
| |
| int | mlx4_flow_steer_promisc_add (struct mlx4_dev *dev, u8 port, u32 qpn, enum mlx4_net_trans_promisc_mode mode) |
| |
| int | mlx4_flow_steer_promisc_remove (struct mlx4_dev *dev, u8 port, enum mlx4_net_trans_promisc_mode mode) |
| |
| int | mlx4_multicast_promisc_add (struct mlx4_dev *dev, u32 qpn, u8 port) |
| |
| int | mlx4_multicast_promisc_remove (struct mlx4_dev *dev, u32 qpn, u8 port) |
| |
| int | mlx4_unicast_promisc_add (struct mlx4_dev *dev, u32 qpn, u8 port) |
| |
| int | mlx4_unicast_promisc_remove (struct mlx4_dev *dev, u32 qpn, u8 port) |
| |
| int | mlx4_SET_MCAST_FLTR (struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode) |
| |
| int | mlx4_register_mac (struct mlx4_dev *dev, u8 port, u64 mac) |
| |
| void | mlx4_unregister_mac (struct mlx4_dev *dev, u8 port, u64 mac) |
| |
| int | mlx4_replace_mac (struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac) |
| |
| int | mlx4_get_eth_qp (struct mlx4_dev *dev, u8 port, u64 mac, int *qpn) |
| |
| void | mlx4_put_eth_qp (struct mlx4_dev *dev, u8 port, u64 mac, int qpn) |
| |
| void | mlx4_set_stats_bitmap (struct mlx4_dev *dev, u64 *stats_bitmap) |
| |
| int | mlx4_SET_PORT_general (struct mlx4_dev *dev, u8 port, int mtu, u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx) |
| |
| int | mlx4_SET_PORT_qpn_calc (struct mlx4_dev *dev, u8 port, u32 base_qpn, u8 promisc) |
| |
| int | mlx4_SET_PORT_PRIO2TC (struct mlx4_dev *dev, u8 port, u8 *prio2tc) |
| |
| int | mlx4_SET_PORT_SCHEDULER (struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, u8 *pg, u16 *ratelimit) |
| |
| int | mlx4_find_cached_vlan (struct mlx4_dev *dev, u8 port, u16 vid, int *idx) |
| |
| int | mlx4_register_vlan (struct mlx4_dev *dev, u8 port, u16 vlan, int *index) |
| |
| void | mlx4_unregister_vlan (struct mlx4_dev *dev, u8 port, int index) |
| |
| int | mlx4_map_phys_fmr (struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, int npages, u64 iova, u32 *lkey, u32 *rkey) |
| |
| int | mlx4_fmr_alloc (struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, int max_maps, u8 page_shift, struct mlx4_fmr *fmr) |
| |
| int | mlx4_fmr_enable (struct mlx4_dev *dev, struct mlx4_fmr *fmr) |
| |
| void | mlx4_fmr_unmap (struct mlx4_dev *dev, struct mlx4_fmr *fmr, u32 *lkey, u32 *rkey) |
| |
| int | mlx4_fmr_free (struct mlx4_dev *dev, struct mlx4_fmr *fmr) |
| |
| int | mlx4_SYNC_TPT (struct mlx4_dev *dev) |
| |
| int | mlx4_test_interrupts (struct mlx4_dev *dev) |
| |
| int | mlx4_assign_eq (struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, int *vector) |
| |
| void | mlx4_release_eq (struct mlx4_dev *dev, int vec) |
| |
| int | mlx4_wol_read (struct mlx4_dev *dev, u64 *config, int port) |
| |
| int | mlx4_wol_write (struct mlx4_dev *dev, u64 config, int port) |
| |
| int | mlx4_counter_alloc (struct mlx4_dev *dev, u32 *idx) |
| |
| void | mlx4_counter_free (struct mlx4_dev *dev, u32 idx) |
| |
| int | mlx4_flow_attach (struct mlx4_dev *dev, struct mlx4_net_trans_rule *rule, u64 *reg_id) |
| |
| int | mlx4_flow_detach (struct mlx4_dev *dev, u64 reg_id) |
| |
| void | mlx4_sync_pkey_table (struct mlx4_dev *dev, int slave, int port, int i, int val) |
| |
| int | mlx4_get_parav_qkey (struct mlx4_dev *dev, u32 qpn, u32 *qkey) |
| |
| int | mlx4_is_slave_active (struct mlx4_dev *dev, int slave) |
| |
| int | mlx4_gen_pkey_eqe (struct mlx4_dev *dev, int slave, u8 port) |
| |
| int | mlx4_gen_guid_change_eqe (struct mlx4_dev *dev, int slave, u8 port) |
| |
| int | mlx4_gen_slaves_port_mgt_ev (struct mlx4_dev *dev, u8 port, int attr) |
| |
| int | mlx4_gen_port_state_change_eqe (struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change) |
| |
| enum slave_port_state | mlx4_get_slave_port_state (struct mlx4_dev *dev, int slave, u8 port) |
| |
| int | set_and_calc_slave_port_state (struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event) |
| |
| void | mlx4_put_slave_node_guid (struct mlx4_dev *dev, int slave, __be64 guid) |
| |
| __be64 | mlx4_get_slave_node_guid (struct mlx4_dev *dev, int slave) |
| |
1.8.2