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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <asm/io.h>#include <linux/delay.h>#include <linux/interrupt.h>#include <linux/init.h>#include <linux/pci.h>#include <linux/slab.h>#include <linux/module.h>#include <sound/core.h>#include <sound/pcm.h>#include <sound/ac97_codec.h>#include <sound/info.h>#include <sound/initval.h>#include <asm/pgtable.h>#include <asm/cacheflush.h>Go to the source code of this file.
Data Structures | |
| struct | ichdev |
| struct | intel8x0 |
| struct | ich_pcm_table |
| struct | ich_reg_info |
| struct | shortname_table |
Macros | |
| #define | kvm_para_available() (0) |
| #define | ICHREG(x) ICH_REG_##x |
| #define | DEFINE_REGSET(name, base) |
| #define | ICH_REG_LVI_MASK 0x1f |
| #define | ICH_FIFOE 0x10 /* FIFO error */ |
| #define | ICH_BCIS 0x08 /* buffer completion interrupt status */ |
| #define | ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ |
| #define | ICH_CELV 0x02 /* current equals last valid */ |
| #define | ICH_DCH 0x01 /* DMA controller halted */ |
| #define | ICH_REG_PIV_MASK 0x1f /* mask */ |
| #define | ICH_IOCE 0x10 /* interrupt on completion enable */ |
| #define | ICH_FEIE 0x08 /* fifo error interrupt enable */ |
| #define | ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ |
| #define | ICH_RESETREGS 0x02 /* reset busmaster registers */ |
| #define | ICH_STARTBM 0x01 /* start busmaster operation */ |
| #define | ICH_REG_GLOB_CNT 0x2c /* dword - global control */ |
| #define | ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ |
| #define | ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ |
| #define | ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ |
| #define | ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ |
| #define | ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ |
| #define | ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ |
| #define | ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ |
| #define | ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ |
| #define | ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ |
| #define | ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ |
| #define | ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ |
| #define | ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ |
| #define | ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ |
| #define | ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ |
| #define | ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ |
| #define | ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ |
| #define | ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ |
| #define | ICH_PRIE 0x00000010 /* primary resume interrupt enable */ |
| #define | ICH_ACLINK 0x00000008 /* AClink shut off */ |
| #define | ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ |
| #define | ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ |
| #define | ICH_GIE 0x00000001 /* GPI interrupt enable */ |
| #define | ICH_REG_GLOB_STA 0x30 /* dword - global status */ |
| #define | ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ |
| #define | ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ |
| #define | ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ |
| #define | ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ |
| #define | ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ |
| #define | ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ |
| #define | ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ |
| #define | ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ |
| #define | ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ |
| #define | ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ |
| #define | ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ |
| #define | ICH_MD3 0x00020000 /* modem power down semaphore */ |
| #define | ICH_AD3 0x00010000 /* audio power down semaphore */ |
| #define | ICH_RCS 0x00008000 /* read completion status */ |
| #define | ICH_BIT3 0x00004000 /* bit 3 slot 12 */ |
| #define | ICH_BIT2 0x00002000 /* bit 2 slot 12 */ |
| #define | ICH_BIT1 0x00001000 /* bit 1 slot 12 */ |
| #define | ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ |
| #define | ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ |
| #define | ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ |
| #define | ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ |
| #define | ICH_MCINT 0x00000080 /* MIC capture interrupt */ |
| #define | ICH_POINT 0x00000040 /* playback interrupt */ |
| #define | ICH_PIINT 0x00000020 /* capture interrupt */ |
| #define | ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ |
| #define | ICH_MOINT 0x00000004 /* modem playback interrupt */ |
| #define | ICH_MIINT 0x00000002 /* modem capture interrupt */ |
| #define | ICH_GSCI 0x00000001 /* GPI status change interrupt */ |
| #define | ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ |
| #define | ICH_CAS 0x01 /* codec access semaphore */ |
| #define | ICH_REG_SDM 0x80 |
| #define | ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ |
| #define | ICH_DI2L_SHIFT 6 |
| #define | ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ |
| #define | ICH_DI1L_SHIFT 4 |
| #define | ICH_SE 0x00000008 /* steer enable */ |
| #define | ICH_LDI_MASK 0x00000003 /* last codec read data input */ |
| #define | ICH_MAX_FRAGS 32 /* max hw frags */ |
| #define | ALI_CAS_SEM_BUSY 0x80000000 |
| #define | ALI_CPR_ADDR_SECONDARY 0x100 |
| #define | ALI_CPR_ADDR_READ 0x80 |
| #define | ALI_CSPSR_CODEC_READY 0x08 |
| #define | ALI_CSPSR_READ_OK 0x02 |
| #define | ALI_CSPSR_WRITE_OK 0x01 |
| #define | ALI_INT_MICIN2 (1<<26) |
| #define | ALI_INT_PCMIN2 (1<<25) |
| #define | ALI_INT_I2SIN (1<<24) |
| #define | ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ |
| #define | ALI_INT_SPDIFIN (1<<22) |
| #define | ALI_INT_LFEOUT (1<<21) |
| #define | ALI_INT_CENTEROUT (1<<20) |
| #define | ALI_INT_CODECSPDIFOUT (1<<19) |
| #define | ALI_INT_MICIN (1<<18) |
| #define | ALI_INT_PCMOUT (1<<17) |
| #define | ALI_INT_PCMIN (1<<16) |
| #define | ALI_INT_CPRAIS (1<<7) /* command port available */ |
| #define | ALI_INT_SPRAIS (1<<5) /* status port available */ |
| #define | ALI_INT_GPIO (1<<1) |
| #define | ALI_INT_MASK |
| #define | ICH_ALI_SC_RESET (1<<31) /* master reset */ |
| #define | ICH_ALI_SC_AC97_DBL (1<<30) |
| #define | ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ |
| #define | ICH_ALI_SC_IN_BITS (3<<18) |
| #define | ICH_ALI_SC_OUT_BITS (3<<16) |
| #define | ICH_ALI_SC_6CH_CFG (3<<14) |
| #define | ICH_ALI_SC_PCM_4 (1<<8) |
| #define | ICH_ALI_SC_PCM_6 (2<<8) |
| #define | ICH_ALI_SC_PCM_246_MASK (3<<8) |
| #define | ICH_ALI_SS_SEC_ID (3<<5) |
| #define | ICH_ALI_SS_PRI_ID (3<<3) |
| #define | ICH_ALI_IF_AC97SP (1<<21) |
| #define | ICH_ALI_IF_MC (1<<20) |
| #define | ICH_ALI_IF_PI (1<<19) |
| #define | ICH_ALI_IF_MC2 (1<<18) |
| #define | ICH_ALI_IF_PI2 (1<<17) |
| #define | ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ |
| #define | ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ |
| #define | ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ |
| #define | ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ |
| #define | ICH_ALI_IF_PO_SPDF (1<<3) |
| #define | ICH_ALI_IF_PO (1<<1) |
| #define | get_ichdev(substream) (substream->runtime->private_data) |
| #define | fill_nocache(buf, size, nocache) do { ; } while (0) |
| #define | snd_intel8x0_ich_chip_cold_reset(chip) 0 |
| #define | snd_intel8x0_ich_chip_can_cold_reset(chip) (0) |
| #define | INTEL8X0_PM_OPS NULL |
| #define | INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ |
| #define | snd_intel8x0_proc_init(x) |
Enumerations | |
| enum | { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE } |
| enum | { ICH_REG_ALI_SCR = 0x00, ICH_REG_ALI_SSR = 0x04, ICH_REG_ALI_DMACR = 0x08, ICH_REG_ALI_FIFOCR1 = 0x0c, ICH_REG_ALI_INTERFACECR = 0x10, ICH_REG_ALI_INTERRUPTCR = 0x14, ICH_REG_ALI_INTERRUPTSR = 0x18, ICH_REG_ALI_FIFOCR2 = 0x1c, ICH_REG_ALI_CPR = 0x20, ICH_REG_ALI_CPR_ADDR = 0x22, ICH_REG_ALI_SPR = 0x24, ICH_REG_ALI_SPR_ADDR = 0x26, ICH_REG_ALI_FIFOCR3 = 0x2c, ICH_REG_ALI_TTSR = 0x30, ICH_REG_ALI_RTSR = 0x34, ICH_REG_ALI_CSPSR = 0x38, ICH_REG_ALI_CAS = 0x3c, ICH_REG_ALI_HWVOL = 0xf0, ICH_REG_ALI_I2SCR = 0xf4, ICH_REG_ALI_SPDIFCSR = 0xf8, ICH_REG_ALI_SPDIFICS = 0xfc } |
| enum | { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR } |
| enum | { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR } |
| enum | { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT } |
Functions | |
| MODULE_AUTHOR ("Jaroslav Kysela <[email protected]>") | |
| MODULE_DESCRIPTION ("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455") | |
| MODULE_LICENSE ("GPL") | |
| MODULE_SUPPORTED_DEVICE ("{{Intel,82801AA-ICH},""{Intel,82901AB-ICH0},""{Intel,82801BA-ICH2},""{Intel,82801CA-ICH3},""{Intel,82801DB-ICH4},""{Intel,ICH5},""{Intel,ICH6},""{Intel,ICH7},""{Intel,6300ESB},""{Intel,ESB2},""{Intel,MX440},""{SiS,SI7012},""{NVidia,nForce Audio},""{NVidia,nForce2 Audio},""{NVidia,nForce3 Audio},""{NVidia,MCP04},""{NVidia,MCP501},""{NVidia,CK804},""{NVidia,CK8},""{NVidia,CK8S},""{AMD,AMD768},""{AMD,AMD8111},""{ALI,M5455}}") | |
| module_param (index, int, 0444) | |
| MODULE_PARM_DESC (index,"Index value for Intel i8x0 soundcard.") | |
| module_param (id, charp, 0444) | |
| MODULE_PARM_DESC (id,"ID string for Intel i8x0 soundcard.") | |
| module_param (ac97_clock, int, 0444) | |
| MODULE_PARM_DESC (ac97_clock,"AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).") | |
| module_param (ac97_quirk, charp, 0444) | |
| MODULE_PARM_DESC (ac97_quirk,"AC'97 workaround for strange hardware.") | |
| module_param (buggy_semaphore, bool, 0444) | |
| MODULE_PARM_DESC (buggy_semaphore,"Enable workaround for hardwares with problematic codec semaphores.") | |
| module_param (buggy_irq, bint, 0444) | |
| MODULE_PARM_DESC (buggy_irq,"Enable workaround for buggy interrupts on some motherboards.") | |
| module_param (xbox, bool, 0444) | |
| MODULE_PARM_DESC (xbox,"Set to 1 for Xbox, if you have problems with the AC'97 codec detection.") | |
| module_param (spdif_aclink, int, 0444) | |
| MODULE_PARM_DESC (spdif_aclink,"S/PDIF over AC-link.") | |
| module_param (inside_vm, bint, 0444) | |
| MODULE_PARM_DESC (inside_vm,"KVM/Parallels optimization.") | |
| module_param (enable, bool, 0444) | |
| module_param (joystick, int, 0444) | |
| DEFINE_REGSET (OFF, 0) | |
| DEFINE_REGSET (PI, 0x00) | |
| DEFINE_REGSET (PO, 0x10) | |
| DEFINE_REGSET (MC, 0x20) | |
| DEFINE_REGSET (MC2, 0x40) | |
| DEFINE_REGSET (PI2, 0x50) | |
| DEFINE_REGSET (SP, 0x60) | |
| DEFINE_REGSET (AL_PI, 0x40) | |
| DEFINE_REGSET (AL_PO, 0x50) | |
| DEFINE_REGSET (AL_MC, 0x60) | |
| DEFINE_REGSET (AL_CDC_SPO, 0x70) | |
| DEFINE_REGSET (AL_CENTER, 0x80) | |
| DEFINE_REGSET (AL_LFE, 0x90) | |
| DEFINE_REGSET (AL_CLR_SPI, 0xa0) | |
| DEFINE_REGSET (AL_CLR_SPO, 0xb0) | |
| DEFINE_REGSET (AL_I2S, 0xc0) | |
| DEFINE_REGSET (AL_PI2, 0xd0) | |
| DEFINE_REGSET (AL_MC2, 0xe0) | |
| MODULE_DEVICE_TABLE (pci, snd_intel8x0_ids) | |
| module_pci_driver (intel8x0_driver) | |
| #define ALI_CAS_SEM_BUSY 0x80000000 |
Definition at line 272 of file intel8x0.c.
| #define ALI_CPR_ADDR_READ 0x80 |
Definition at line 274 of file intel8x0.c.
| #define ALI_CPR_ADDR_SECONDARY 0x100 |
Definition at line 273 of file intel8x0.c.
| #define ALI_CSPSR_CODEC_READY 0x08 |
Definition at line 275 of file intel8x0.c.
| #define ALI_CSPSR_READ_OK 0x02 |
Definition at line 276 of file intel8x0.c.
| #define ALI_CSPSR_WRITE_OK 0x01 |
Definition at line 277 of file intel8x0.c.
| #define ALI_INT_CENTEROUT (1<<20) |
Definition at line 287 of file intel8x0.c.
| #define ALI_INT_CODECSPDIFOUT (1<<19) |
Definition at line 288 of file intel8x0.c.
Definition at line 292 of file intel8x0.c.
| #define ALI_INT_GPIO (1<<1) |
Definition at line 294 of file intel8x0.c.
| #define ALI_INT_I2SIN (1<<24) |
Definition at line 283 of file intel8x0.c.
| #define ALI_INT_LFEOUT (1<<21) |
Definition at line 286 of file intel8x0.c.
| #define ALI_INT_MASK |
Definition at line 295 of file intel8x0.c.
| #define ALI_INT_MICIN (1<<18) |
Definition at line 289 of file intel8x0.c.
| #define ALI_INT_MICIN2 (1<<26) |
Definition at line 281 of file intel8x0.c.
| #define ALI_INT_PCMIN (1<<16) |
Definition at line 291 of file intel8x0.c.
| #define ALI_INT_PCMIN2 (1<<25) |
Definition at line 282 of file intel8x0.c.
| #define ALI_INT_PCMOUT (1<<17) |
Definition at line 290 of file intel8x0.c.
| #define ALI_INT_SPDIFIN (1<<22) |
Definition at line 285 of file intel8x0.c.
| #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ |
Definition at line 284 of file intel8x0.c.
Definition at line 293 of file intel8x0.c.
Definition at line 120 of file intel8x0.c.
Definition at line 740 of file intel8x0.c.
| #define get_ichdev | ( | substream | ) | (substream->runtime->private_data) |
Definition at line 353 of file intel8x0.c.
| #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ |
Definition at line 187 of file intel8x0.c.
| #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ |
Definition at line 186 of file intel8x0.c.
| #define ICH_ACLINK 0x00000008 /* AClink shut off */ |
Definition at line 185 of file intel8x0.c.
| #define ICH_AD3 0x00010000 /* audio power down semaphore */ |
Definition at line 202 of file intel8x0.c.
Definition at line 319 of file intel8x0.c.
| #define ICH_ALI_IF_AC97SP (1<<21) |
Definition at line 311 of file intel8x0.c.
| #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ |
Definition at line 316 of file intel8x0.c.
| #define ICH_ALI_IF_MC (1<<20) |
Definition at line 312 of file intel8x0.c.
| #define ICH_ALI_IF_MC2 (1<<18) |
Definition at line 314 of file intel8x0.c.
| #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ |
Definition at line 317 of file intel8x0.c.
| #define ICH_ALI_IF_PI (1<<19) |
Definition at line 313 of file intel8x0.c.
| #define ICH_ALI_IF_PI2 (1<<17) |
Definition at line 315 of file intel8x0.c.
| #define ICH_ALI_IF_PO (1<<1) |
Definition at line 321 of file intel8x0.c.
| #define ICH_ALI_IF_PO_SPDF (1<<3) |
Definition at line 320 of file intel8x0.c.
Definition at line 318 of file intel8x0.c.
| #define ICH_ALI_SC_6CH_CFG (3<<14) |
Definition at line 303 of file intel8x0.c.
| #define ICH_ALI_SC_AC97_DBL (1<<30) |
Definition at line 299 of file intel8x0.c.
| #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ |
Definition at line 300 of file intel8x0.c.
| #define ICH_ALI_SC_IN_BITS (3<<18) |
Definition at line 301 of file intel8x0.c.
| #define ICH_ALI_SC_OUT_BITS (3<<16) |
Definition at line 302 of file intel8x0.c.
| #define ICH_ALI_SC_PCM_246_MASK (3<<8) |
Definition at line 306 of file intel8x0.c.
| #define ICH_ALI_SC_PCM_4 (1<<8) |
Definition at line 304 of file intel8x0.c.
| #define ICH_ALI_SC_PCM_6 (2<<8) |
Definition at line 305 of file intel8x0.c.
| #define ICH_ALI_SC_RESET (1<<31) /* master reset */ |
Definition at line 298 of file intel8x0.c.
| #define ICH_ALI_SS_PRI_ID (3<<3) |
Definition at line 309 of file intel8x0.c.
| #define ICH_ALI_SS_SEC_ID (3<<5) |
Definition at line 308 of file intel8x0.c.
| #define ICH_BCIS 0x08 /* buffer completion interrupt status */ |
Definition at line 149 of file intel8x0.c.
| #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ |
Definition at line 192 of file intel8x0.c.
| #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ |
Definition at line 206 of file intel8x0.c.
| #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ |
Definition at line 205 of file intel8x0.c.
| #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ |
Definition at line 204 of file intel8x0.c.
| #define ICH_CAS 0x01 /* codec access semaphore */ |
Definition at line 219 of file intel8x0.c.
| #define ICH_CELV 0x02 /* current equals last valid */ |
Definition at line 151 of file intel8x0.c.
| #define ICH_DCH 0x01 /* DMA controller halted */ |
Definition at line 152 of file intel8x0.c.
| #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ |
Definition at line 223 of file intel8x0.c.
| #define ICH_DI1L_SHIFT 4 |
Definition at line 224 of file intel8x0.c.
| #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ |
Definition at line 221 of file intel8x0.c.
| #define ICH_DI2L_SHIFT 6 |
Definition at line 222 of file intel8x0.c.
| #define ICH_FEIE 0x08 /* fifo error interrupt enable */ |
Definition at line 159 of file intel8x0.c.
| #define ICH_FIFOE 0x10 /* FIFO error */ |
Definition at line 148 of file intel8x0.c.
| #define ICH_GIE 0x00000001 /* GPI interrupt enable */ |
Definition at line 188 of file intel8x0.c.
| #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ |
Definition at line 217 of file intel8x0.c.
| #define ICH_IOCE 0x10 /* interrupt on completion enable */ |
Definition at line 158 of file intel8x0.c.
| #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ |
Definition at line 226 of file intel8x0.c.
| #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ |
Definition at line 150 of file intel8x0.c.
| #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ |
Definition at line 160 of file intel8x0.c.
| #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ |
Definition at line 195 of file intel8x0.c.
Definition at line 228 of file intel8x0.c.
| #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ |
Definition at line 211 of file intel8x0.c.
| #define ICH_MD3 0x00020000 /* modem power down semaphore */ |
Definition at line 201 of file intel8x0.c.
| #define ICH_MIINT 0x00000002 /* modem capture interrupt */ |
Definition at line 216 of file intel8x0.c.
| #define ICH_MOINT 0x00000004 /* modem playback interrupt */ |
Definition at line 215 of file intel8x0.c.
| #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ |
Definition at line 198 of file intel8x0.c.
| #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ |
Definition at line 214 of file intel8x0.c.
| #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ |
Definition at line 194 of file intel8x0.c.
| #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ |
Definition at line 177 of file intel8x0.c.
| #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ |
Definition at line 172 of file intel8x0.c.
| #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ |
Definition at line 173 of file intel8x0.c.
| #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ |
Definition at line 176 of file intel8x0.c.
| #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ |
Definition at line 175 of file intel8x0.c.
| #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ |
Definition at line 174 of file intel8x0.c.
| #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ |
Definition at line 171 of file intel8x0.c.
| #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ |
Definition at line 170 of file intel8x0.c.
| #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ |
Definition at line 169 of file intel8x0.c.
| #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ |
Definition at line 167 of file intel8x0.c.
| #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ |
Definition at line 168 of file intel8x0.c.
| #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ |
Definition at line 210 of file intel8x0.c.
| #define ICH_PIINT 0x00000020 /* capture interrupt */ |
Definition at line 213 of file intel8x0.c.
| #define ICH_POINT 0x00000040 /* playback interrupt */ |
Definition at line 212 of file intel8x0.c.
| #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ |
Definition at line 208 of file intel8x0.c.
| #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ |
Definition at line 184 of file intel8x0.c.
| #define ICH_RCS 0x00008000 /* read completion status */ |
Definition at line 203 of file intel8x0.c.
| #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ |
Definition at line 218 of file intel8x0.c.
| #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ |
Definition at line 166 of file intel8x0.c.
| #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ |
Definition at line 189 of file intel8x0.c.
| #define ICH_REG_LVI_MASK 0x1f |
Definition at line 145 of file intel8x0.c.
| #define ICH_REG_PIV_MASK 0x1f /* mask */ |
Definition at line 155 of file intel8x0.c.
| #define ICH_REG_SDM 0x80 |
Definition at line 220 of file intel8x0.c.
| #define ICH_RESETREGS 0x02 /* reset busmaster registers */ |
Definition at line 161 of file intel8x0.c.
| #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ |
Definition at line 197 of file intel8x0.c.
| #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ |
Definition at line 196 of file intel8x0.c.
| #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ |
Definition at line 209 of file intel8x0.c.
| #define ICH_SE 0x00000008 /* steer enable */ |
Definition at line 225 of file intel8x0.c.
| #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ |
Definition at line 181 of file intel8x0.c.
| #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ |
Definition at line 178 of file intel8x0.c.
| #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ |
Definition at line 180 of file intel8x0.c.
| #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ |
Definition at line 179 of file intel8x0.c.
| #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ |
Definition at line 200 of file intel8x0.c.
| #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ |
Definition at line 199 of file intel8x0.c.
| #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ |
Definition at line 193 of file intel8x0.c.
| #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ |
Definition at line 207 of file intel8x0.c.
| #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ |
Definition at line 183 of file intel8x0.c.
| #define ICH_STARTBM 0x01 /* start busmaster operation */ |
Definition at line 162 of file intel8x0.c.
| #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ |
Definition at line 191 of file intel8x0.c.
| #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ |
Definition at line 190 of file intel8x0.c.
| #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ |
Definition at line 182 of file intel8x0.c.
Definition at line 118 of file intel8x0.c.
| #define INTEL8X0_PM_OPS NULL |
Definition at line 2763 of file intel8x0.c.
Definition at line 2766 of file intel8x0.c.
| #define kvm_para_available | ( | void | ) | (0) |
Definition at line 48 of file intel8x0.c.
| #define snd_intel8x0_ich_chip_can_cold_reset | ( | chip | ) | (0) |
Definition at line 2426 of file intel8x0.c.
| #define snd_intel8x0_ich_chip_cold_reset | ( | chip | ) | 0 |
Definition at line 2425 of file intel8x0.c.
| #define snd_intel8x0_proc_init | ( | x | ) |
Definition at line 2952 of file intel8x0.c.
| anonymous enum |
Definition at line 116 of file intel8x0.c.
| anonymous enum |
Definition at line 248 of file intel8x0.c.
| anonymous enum |
Definition at line 327 of file intel8x0.c.
| anonymous enum |
Definition at line 336 of file intel8x0.c.
| anonymous enum |
Definition at line 343 of file intel8x0.c.
| DEFINE_REGSET | ( | OFF | , |
| 0 | |||
| ) |
| DEFINE_REGSET | ( | PI | , |
| 0x00 | |||
| ) |
| DEFINE_REGSET | ( | PO | , |
| 0x10 | |||
| ) |
| DEFINE_REGSET | ( | MC | , |
| 0x20 | |||
| ) |
| DEFINE_REGSET | ( | MC2 | , |
| 0x40 | |||
| ) |
| DEFINE_REGSET | ( | PI2 | , |
| 0x50 | |||
| ) |
| DEFINE_REGSET | ( | SP | , |
| 0x60 | |||
| ) |
| DEFINE_REGSET | ( | AL_PI | , |
| 0x40 | |||
| ) |
| DEFINE_REGSET | ( | AL_PO | , |
| 0x50 | |||
| ) |
| DEFINE_REGSET | ( | AL_MC | , |
| 0x60 | |||
| ) |
| DEFINE_REGSET | ( | AL_CDC_SPO | , |
| 0x70 | |||
| ) |
| DEFINE_REGSET | ( | AL_CENTER | , |
| 0x80 | |||
| ) |
| DEFINE_REGSET | ( | AL_LFE | , |
| 0x90 | |||
| ) |
| DEFINE_REGSET | ( | AL_CLR_SPI | , |
| 0xa0 | |||
| ) |
| DEFINE_REGSET | ( | AL_CLR_SPO | , |
| 0xb0 | |||
| ) |
| DEFINE_REGSET | ( | AL_I2S | , |
| 0xc0 | |||
| ) |
| DEFINE_REGSET | ( | AL_PI2 | , |
| 0xd0 | |||
| ) |
| DEFINE_REGSET | ( | AL_MC2 | , |
| 0xe0 | |||
| ) |
| MODULE_AUTHOR | ( | "Jaroslav Kysela <[email protected]>" | ) |
| MODULE_DESCRIPTION | ( | "Intel | 82801AA, |
| 82901AB | , | ||
| i810 | , | ||
| i820 | , | ||
| i830 | , | ||
| i840 | , | ||
| i845 | , | ||
| MX440;SiS 7012;Ali 5455" | |||
| ) |
| MODULE_DEVICE_TABLE | ( | pci | , |
| snd_intel8x0_ids | |||
| ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_param | ( | id | , |
| charp | , | ||
| 0444 | |||
| ) |
| module_param | ( | ac97_clock | , |
| int | , | ||
| 0444 | |||
| ) |
| module_param | ( | ac97_quirk | , |
| charp | , | ||
| 0444 | |||
| ) |
| module_param | ( | buggy_semaphore | , |
| bool | , | ||
| 0444 | |||
| ) |
| module_param | ( | buggy_irq | , |
| bint | , | ||
| 0444 | |||
| ) |
| module_param | ( | xbox | , |
| bool | , | ||
| 0444 | |||
| ) |
| module_param | ( | spdif_aclink | , |
| int | , | ||
| 0444 | |||
| ) |
| module_param | ( | inside_vm | , |
| bint | , | ||
| 0444 | |||
| ) |
| module_param | ( | joystick | , |
| int | , | ||
| 0444 | |||
| ) |
| MODULE_PARM_DESC | ( | ac97_clock | , |
| "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect)." | |||
| ) |
| MODULE_PARM_DESC | ( | ac97_quirk | , |
| "AC'97 workaround for strange hardware." | |||
| ) |
| MODULE_PARM_DESC | ( | buggy_semaphore | , |
| "Enable workaround for hardwares with problematic codec semaphores." | |||
| ) |
| MODULE_PARM_DESC | ( | buggy_irq | , |
| "Enable workaround for buggy interrupts on some motherboards." | |||
| ) |
| MODULE_PARM_DESC | ( | xbox | , |
| "Set to 1 for | Xbox, | ||
| if you have problems with the AC'97 codec detection." | |||
| ) |
| MODULE_PARM_DESC | ( | spdif_aclink | , |
| "S/PDIF over AC-link." | |||
| ) |
| MODULE_PARM_DESC | ( | inside_vm | , |
| "KVM/Parallels optimization." | |||
| ) |
| module_pci_driver | ( | intel8x0_driver | ) |
| MODULE_SUPPORTED_DEVICE | ( | "{{Intel,82801AA-ICH},""{Intel,82901AB-ICH0},""{Intel,82801BA-ICH2},""{Intel,82801CA-ICH3},""{Intel,82801DB-ICH4},""{Intel,ICH5},""{Intel,ICH6},""{Intel,ICH7},""{Intel,6300ESB},""{Intel,ESB2},""{Intel,MX440},""{SiS,SI7012},""{NVidia,nForce Audio},""{NVidia,nForce2 Audio},""{NVidia,nForce3 Audio},""{NVidia,MCP04},""{NVidia,MCP501},""{NVidia,CK804},""{NVidia,CK8},""{NVidia,CK8S},""{AMD,AMD768},""{AMD,AMD8111},""{ALI,M5455}}" | ) |
1.8.2