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intel8x0.c
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1 /*
2  * ALSA driver for Intel ICH (i8x0) chipsets
3  *
4  * Copyright (c) 2000 Jaroslav Kysela <[email protected]>
5  *
6  *
7  * This code also contains alpha support for SiS 735 chipsets provided
8  * by Mike Pieper <[email protected]>. We have no datasheet
9  * for SiS735, so the code is not fully functional.
10  *
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 
26  *
27  */
28 
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/pcm.h>
38 #include <sound/ac97_codec.h>
39 #include <sound/info.h>
40 #include <sound/initval.h>
41 /* for 440MX workaround */
42 #include <asm/pgtable.h>
43 #include <asm/cacheflush.h>
44 
45 #ifdef CONFIG_KVM_GUEST
46 #include <linux/kvm_para.h>
47 #else
48 #define kvm_para_available() (0)
49 #endif
50 
51 MODULE_AUTHOR("Jaroslav Kysela <[email protected]>");
52 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
53 MODULE_LICENSE("GPL");
54 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
55  "{Intel,82901AB-ICH0},"
56  "{Intel,82801BA-ICH2},"
57  "{Intel,82801CA-ICH3},"
58  "{Intel,82801DB-ICH4},"
59  "{Intel,ICH5},"
60  "{Intel,ICH6},"
61  "{Intel,ICH7},"
62  "{Intel,6300ESB},"
63  "{Intel,ESB2},"
64  "{Intel,MX440},"
65  "{SiS,SI7012},"
66  "{NVidia,nForce Audio},"
67  "{NVidia,nForce2 Audio},"
68  "{NVidia,nForce3 Audio},"
69  "{NVidia,MCP04},"
70  "{NVidia,MCP501},"
71  "{NVidia,CK804},"
72  "{NVidia,CK8},"
73  "{NVidia,CK8S},"
74  "{AMD,AMD768},"
75  "{AMD,AMD8111},"
76  "{ALI,M5455}}");
77 
78 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
79 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
80 static int ac97_clock;
81 static char *ac97_quirk;
82 static bool buggy_semaphore;
83 static int buggy_irq = -1; /* auto-check */
84 static bool xbox;
85 static int spdif_aclink = -1;
86 static int inside_vm = -1;
87 
88 module_param(index, int, 0444);
89 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
90 module_param(id, charp, 0444);
91 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
92 module_param(ac97_clock, int, 0444);
93 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
94 module_param(ac97_quirk, charp, 0444);
95 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
96 module_param(buggy_semaphore, bool, 0444);
97 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
98 module_param(buggy_irq, bint, 0444);
99 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
100 module_param(xbox, bool, 0444);
101 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
102 module_param(spdif_aclink, int, 0444);
103 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
104 module_param(inside_vm, bint, 0444);
105 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
106 
107 /* just for backward compatibility */
108 static bool enable;
109 module_param(enable, bool, 0444);
110 static int joystick;
111 module_param(joystick, int, 0444);
112 
113 /*
114  * Direct registers
115  */
116 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
117 
118 #define ICHREG(x) ICH_REG_##x
119 
120 #define DEFINE_REGSET(name,base) \
121 enum { \
122  ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
123  ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
124  ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
125  ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
126  ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
127  ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
128  ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
129 };
130 
131 /* busmaster blocks */
132 DEFINE_REGSET(OFF, 0); /* offset */
133 DEFINE_REGSET(PI, 0x00); /* PCM in */
134 DEFINE_REGSET(PO, 0x10); /* PCM out */
135 DEFINE_REGSET(MC, 0x20); /* Mic in */
136 
137 /* ICH4 busmaster blocks */
138 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
139 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
140 DEFINE_REGSET(SP, 0x60); /* SPDIF out */
141 
142 /* values for each busmaster block */
143 
144 /* LVI */
145 #define ICH_REG_LVI_MASK 0x1f
146 
147 /* SR */
148 #define ICH_FIFOE 0x10 /* FIFO error */
149 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
150 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
151 #define ICH_CELV 0x02 /* current equals last valid */
152 #define ICH_DCH 0x01 /* DMA controller halted */
153 
154 /* PIV */
155 #define ICH_REG_PIV_MASK 0x1f /* mask */
156 
157 /* CR */
158 #define ICH_IOCE 0x10 /* interrupt on completion enable */
159 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
160 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
161 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
162 #define ICH_STARTBM 0x01 /* start busmaster operation */
163 
164 
165 /* global block */
166 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
167 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
168 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
169 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
170 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
171 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
172 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
173 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
174 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
175 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
176 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
177 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
178 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
179 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
180 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
181 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
182 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
183 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
184 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
185 #define ICH_ACLINK 0x00000008 /* AClink shut off */
186 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
187 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
188 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
189 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
190 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
191 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
192 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
193 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
194 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
195 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
196 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
197 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
198 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
199 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
200 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
201 #define ICH_MD3 0x00020000 /* modem power down semaphore */
202 #define ICH_AD3 0x00010000 /* audio power down semaphore */
203 #define ICH_RCS 0x00008000 /* read completion status */
204 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
205 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
206 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
207 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
208 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
209 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
210 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
211 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
212 #define ICH_POINT 0x00000040 /* playback interrupt */
213 #define ICH_PIINT 0x00000020 /* capture interrupt */
214 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
215 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
216 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
217 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
218 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
219 #define ICH_CAS 0x01 /* codec access semaphore */
220 #define ICH_REG_SDM 0x80
221 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
222 #define ICH_DI2L_SHIFT 6
223 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
224 #define ICH_DI1L_SHIFT 4
225 #define ICH_SE 0x00000008 /* steer enable */
226 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
227 
228 #define ICH_MAX_FRAGS 32 /* max hw frags */
229 
230 
231 /*
232  * registers for Ali5455
233  */
234 
235 /* ALi 5455 busmaster blocks */
236 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
237 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
238 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
239 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
240 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
241 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
242 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
243 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
244 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
245 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
246 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
247 
248 enum {
249  ICH_REG_ALI_SCR = 0x00, /* System Control Register */
250  ICH_REG_ALI_SSR = 0x04, /* System Status Register */
251  ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
252  ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
253  ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
254  ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
255  ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
256  ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
257  ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
258  ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
259  ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
260  ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
261  ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
262  ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
263  ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
264  ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
265  ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
266  ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
267  ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
268  ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
269  ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
270 };
271 
272 #define ALI_CAS_SEM_BUSY 0x80000000
273 #define ALI_CPR_ADDR_SECONDARY 0x100
274 #define ALI_CPR_ADDR_READ 0x80
275 #define ALI_CSPSR_CODEC_READY 0x08
276 #define ALI_CSPSR_READ_OK 0x02
277 #define ALI_CSPSR_WRITE_OK 0x01
278 
279 /* interrupts for the whole chip by interrupt status register finish */
280 
281 #define ALI_INT_MICIN2 (1<<26)
282 #define ALI_INT_PCMIN2 (1<<25)
283 #define ALI_INT_I2SIN (1<<24)
284 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
285 #define ALI_INT_SPDIFIN (1<<22)
286 #define ALI_INT_LFEOUT (1<<21)
287 #define ALI_INT_CENTEROUT (1<<20)
288 #define ALI_INT_CODECSPDIFOUT (1<<19)
289 #define ALI_INT_MICIN (1<<18)
290 #define ALI_INT_PCMOUT (1<<17)
291 #define ALI_INT_PCMIN (1<<16)
292 #define ALI_INT_CPRAIS (1<<7) /* command port available */
293 #define ALI_INT_SPRAIS (1<<5) /* status port available */
294 #define ALI_INT_GPIO (1<<1)
295 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
296  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
297 
298 #define ICH_ALI_SC_RESET (1<<31) /* master reset */
299 #define ICH_ALI_SC_AC97_DBL (1<<30)
300 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
301 #define ICH_ALI_SC_IN_BITS (3<<18)
302 #define ICH_ALI_SC_OUT_BITS (3<<16)
303 #define ICH_ALI_SC_6CH_CFG (3<<14)
304 #define ICH_ALI_SC_PCM_4 (1<<8)
305 #define ICH_ALI_SC_PCM_6 (2<<8)
306 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
307 
308 #define ICH_ALI_SS_SEC_ID (3<<5)
309 #define ICH_ALI_SS_PRI_ID (3<<3)
310 
311 #define ICH_ALI_IF_AC97SP (1<<21)
312 #define ICH_ALI_IF_MC (1<<20)
313 #define ICH_ALI_IF_PI (1<<19)
314 #define ICH_ALI_IF_MC2 (1<<18)
315 #define ICH_ALI_IF_PI2 (1<<17)
316 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
317 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
318 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
319 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
320 #define ICH_ALI_IF_PO_SPDF (1<<3)
321 #define ICH_ALI_IF_PO (1<<1)
322 
323 /*
324  *
325  */
326 
327 enum {
328  ICHD_PCMIN,
329  ICHD_PCMOUT,
330  ICHD_MIC,
331  ICHD_MIC2,
332  ICHD_PCM2IN,
333  ICHD_SPBAR,
334  ICHD_LAST = ICHD_SPBAR
335 };
336 enum {
337  NVD_PCMIN,
338  NVD_PCMOUT,
339  NVD_MIC,
340  NVD_SPBAR,
341  NVD_LAST = NVD_SPBAR
342 };
343 enum {
344  ALID_PCMIN,
345  ALID_PCMOUT,
346  ALID_MIC,
347  ALID_AC97SPDIFOUT,
348  ALID_SPDIFIN,
349  ALID_SPDIFOUT,
350  ALID_LAST = ALID_SPDIFOUT
351 };
352 
353 #define get_ichdev(substream) (substream->runtime->private_data)
354 
355 struct ichdev {
356  unsigned int ichd; /* ich device number */
357  unsigned long reg_offset; /* offset to bmaddr */
358  u32 *bdbar; /* CPU address (32bit) */
359  unsigned int bdbar_addr; /* PCI bus address (32bit) */
360  struct snd_pcm_substream *substream;
361  unsigned int physbuf; /* physical address (32bit) */
362  unsigned int size;
363  unsigned int fragsize;
364  unsigned int fragsize1;
365  unsigned int position;
366  unsigned int pos_shift;
367  unsigned int last_pos;
368  int frags;
369  int lvi;
370  int lvi_frag;
371  int civ;
372  int ack;
373  int ack_reload;
374  unsigned int ack_bit;
375  unsigned int roff_sr;
376  unsigned int roff_picb;
377  unsigned int int_sta_mask; /* interrupt status mask */
378  unsigned int ali_slot; /* ALI DMA slot */
379  struct ac97_pcm *pcm;
380  int pcm_open_flag;
381  unsigned int page_attr_changed: 1;
382  unsigned int suspended: 1;
383 };
384 
385 struct intel8x0 {
386  unsigned int device_type;
387 
388  int irq;
389 
390  void __iomem *addr;
391  void __iomem *bmaddr;
392 
393  struct pci_dev *pci;
394  struct snd_card *card;
395 
396  int pcm_devs;
397  struct snd_pcm *pcm[6];
398  struct ichdev ichd[6];
399 
400  unsigned multi4: 1,
401  multi6: 1,
402  multi8 :1,
403  dra: 1,
404  smp20bit: 1;
405  unsigned in_ac97_init: 1,
406  in_sdin_init: 1;
407  unsigned in_measurement: 1; /* during ac97 clock measurement */
408  unsigned fix_nocache: 1; /* workaround for 440MX */
409  unsigned buggy_irq: 1; /* workaround for buggy mobos */
410  unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
411  unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
412  unsigned inside_vm: 1; /* enable VM optimization */
413 
414  int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
415  unsigned int sdm_saved; /* SDM reg value */
416 
417  struct snd_ac97_bus *ac97_bus;
418  struct snd_ac97 *ac97[3];
419  unsigned int ac97_sdin[3];
420  unsigned int max_codecs, ncodecs;
421  unsigned int *codec_bit;
422  unsigned int codec_isr_bits;
423  unsigned int codec_ready_bits;
424 
425  spinlock_t reg_lock;
426 
427  u32 bdbars_count;
428  struct snd_dma_buffer bdbars;
429  u32 int_sta_reg; /* interrupt status register */
430  u32 int_sta_mask; /* interrupt status mask */
431 };
432 
433 static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = {
434  { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
435  { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
436  { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
437  { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
438  { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
439  { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
440  { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
441  { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
442  { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
443  { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
444  { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
445  { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
446  { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
447  { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
448  { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
449  { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
450  { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
451  { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
452  { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
453  { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
454  { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
455  { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
456  { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
457  { 0, }
458 };
459 
460 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
461 
462 /*
463  * Lowlevel I/O - busmaster
464  */
465 
466 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
467 {
468  return ioread8(chip->bmaddr + offset);
469 }
470 
471 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
472 {
473  return ioread16(chip->bmaddr + offset);
474 }
475 
476 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
477 {
478  return ioread32(chip->bmaddr + offset);
479 }
480 
481 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
482 {
483  iowrite8(val, chip->bmaddr + offset);
484 }
485 
486 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
487 {
488  iowrite16(val, chip->bmaddr + offset);
489 }
490 
491 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
492 {
493  iowrite32(val, chip->bmaddr + offset);
494 }
495 
496 /*
497  * Lowlevel I/O - AC'97 registers
498  */
499 
500 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
501 {
502  return ioread16(chip->addr + offset);
503 }
504 
505 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
506 {
507  iowrite16(val, chip->addr + offset);
508 }
509 
510 /*
511  * Basic I/O
512  */
513 
514 /*
515  * access to AC97 codec via normal i/o (for ICH and SIS7012)
516  */
517 
518 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
519 {
520  int time;
521 
522  if (codec > 2)
523  return -EIO;
524  if (chip->in_sdin_init) {
525  /* we don't know the ready bit assignment at the moment */
526  /* so we check any */
527  codec = chip->codec_isr_bits;
528  } else {
529  codec = chip->codec_bit[chip->ac97_sdin[codec]];
530  }
531 
532  /* codec ready ? */
533  if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
534  return -EIO;
535 
536  if (chip->buggy_semaphore)
537  return 0; /* just ignore ... */
538 
539  /* Anyone holding a semaphore for 1 msec should be shot... */
540  time = 100;
541  do {
542  if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
543  return 0;
544  udelay(10);
545  } while (time--);
546 
547  /* access to some forbidden (non existent) ac97 registers will not
548  * reset the semaphore. So even if you don't get the semaphore, still
549  * continue the access. We don't need the semaphore anyway. */
550  snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
551  igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
552  iagetword(chip, 0); /* clear semaphore flag */
553  /* I don't care about the semaphore */
554  return -EBUSY;
555 }
556 
557 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
558  unsigned short reg,
559  unsigned short val)
560 {
561  struct intel8x0 *chip = ac97->private_data;
562 
563  if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
564  if (! chip->in_ac97_init)
565  snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
566  }
567  iaputword(chip, reg + ac97->num * 0x80, val);
568 }
569 
570 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
571  unsigned short reg)
572 {
573  struct intel8x0 *chip = ac97->private_data;
574  unsigned short res;
575  unsigned int tmp;
576 
577  if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
578  if (! chip->in_ac97_init)
579  snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
580  res = 0xffff;
581  } else {
582  res = iagetword(chip, reg + ac97->num * 0x80);
583  if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
584  /* reset RCS and preserve other R/WC bits */
585  iputdword(chip, ICHREG(GLOB_STA), tmp &
586  ~(chip->codec_ready_bits | ICH_GSCI));
587  if (! chip->in_ac97_init)
588  snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
589  res = 0xffff;
590  }
591  }
592  return res;
593 }
594 
595 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
596  unsigned int codec)
597 {
598  unsigned int tmp;
599 
600  if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
601  iagetword(chip, codec * 0x80);
602  if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
603  /* reset RCS and preserve other R/WC bits */
604  iputdword(chip, ICHREG(GLOB_STA), tmp &
605  ~(chip->codec_ready_bits | ICH_GSCI));
606  }
607  }
608 }
609 
610 /*
611  * access to AC97 for Ali5455
612  */
613 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
614 {
615  int count = 0;
616  for (count = 0; count < 0x7f; count++) {
617  int val = igetbyte(chip, ICHREG(ALI_CSPSR));
618  if (val & mask)
619  return 0;
620  }
621  if (! chip->in_ac97_init)
622  snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
623  return -EBUSY;
624 }
625 
626 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
627 {
628  int time = 100;
629  if (chip->buggy_semaphore)
630  return 0; /* just ignore ... */
631  while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
632  udelay(1);
633  if (! time && ! chip->in_ac97_init)
634  snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
635  return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
636 }
637 
638 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
639 {
640  struct intel8x0 *chip = ac97->private_data;
641  unsigned short data = 0xffff;
642 
643  if (snd_intel8x0_ali_codec_semaphore(chip))
644  goto __err;
645  reg |= ALI_CPR_ADDR_READ;
646  if (ac97->num)
647  reg |= ALI_CPR_ADDR_SECONDARY;
648  iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
649  if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
650  goto __err;
651  data = igetword(chip, ICHREG(ALI_SPR));
652  __err:
653  return data;
654 }
655 
656 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
657  unsigned short val)
658 {
659  struct intel8x0 *chip = ac97->private_data;
660 
661  if (snd_intel8x0_ali_codec_semaphore(chip))
662  return;
663  iputword(chip, ICHREG(ALI_CPR), val);
664  if (ac97->num)
665  reg |= ALI_CPR_ADDR_SECONDARY;
666  iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
667  snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
668 }
669 
670 
671 /*
672  * DMA I/O
673  */
674 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
675 {
676  int idx;
677  u32 *bdbar = ichdev->bdbar;
678  unsigned long port = ichdev->reg_offset;
679 
680  iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
681  if (ichdev->size == ichdev->fragsize) {
682  ichdev->ack_reload = ichdev->ack = 2;
683  ichdev->fragsize1 = ichdev->fragsize >> 1;
684  for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
685  bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
686  bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
687  ichdev->fragsize1 >> ichdev->pos_shift);
688  bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
689  bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
690  ichdev->fragsize1 >> ichdev->pos_shift);
691  }
692  ichdev->frags = 2;
693  } else {
694  ichdev->ack_reload = ichdev->ack = 1;
695  ichdev->fragsize1 = ichdev->fragsize;
696  for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
697  bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
698  (((idx >> 1) * ichdev->fragsize) %
699  ichdev->size));
700  bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
701  ichdev->fragsize >> ichdev->pos_shift);
702 #if 0
703  printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
704  idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
705 #endif
706  }
707  ichdev->frags = ichdev->size / ichdev->fragsize;
708  }
709  iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
710  ichdev->civ = 0;
711  iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
712  ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
713  ichdev->position = 0;
714 #if 0
715  printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
716  "period_size1 = 0x%x\n",
717  ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
718  ichdev->fragsize1);
719 #endif
720  /* clear interrupts */
721  iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
722 }
723 
724 #ifdef __i386__
725 /*
726  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
727  * which aborts PCI busmaster for audio transfer. A workaround is to set
728  * the pages as non-cached. For details, see the errata in
729  * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
730  */
731 static void fill_nocache(void *buf, int size, int nocache)
732 {
733  size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
734  if (nocache)
735  set_pages_uc(virt_to_page(buf), size);
736  else
737  set_pages_wb(virt_to_page(buf), size);
738 }
739 #else
740 #define fill_nocache(buf, size, nocache) do { ; } while (0)
741 #endif
742 
743 /*
744  * Interrupt handler
745  */
746 
747 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
748 {
749  unsigned long port = ichdev->reg_offset;
750  unsigned long flags;
751  int status, civ, i, step;
752  int ack = 0;
753 
754  spin_lock_irqsave(&chip->reg_lock, flags);
755  status = igetbyte(chip, port + ichdev->roff_sr);
756  civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
757  if (!(status & ICH_BCIS)) {
758  step = 0;
759  } else if (civ == ichdev->civ) {
760  // snd_printd("civ same %d\n", civ);
761  step = 1;
762  ichdev->civ++;
763  ichdev->civ &= ICH_REG_LVI_MASK;
764  } else {
765  step = civ - ichdev->civ;
766  if (step < 0)
767  step += ICH_REG_LVI_MASK + 1;
768  // if (step != 1)
769  // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
770  ichdev->civ = civ;
771  }
772 
773  ichdev->position += step * ichdev->fragsize1;
774  if (! chip->in_measurement)
775  ichdev->position %= ichdev->size;
776  ichdev->lvi += step;
777  ichdev->lvi &= ICH_REG_LVI_MASK;
778  iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
779  for (i = 0; i < step; i++) {
780  ichdev->lvi_frag++;
781  ichdev->lvi_frag %= ichdev->frags;
782  ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
783 #if 0
784  printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
785  "all = 0x%x, 0x%x\n",
786  ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
787  ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
788  inl(port + 4), inb(port + ICH_REG_OFF_CR));
789 #endif
790  if (--ichdev->ack == 0) {
791  ichdev->ack = ichdev->ack_reload;
792  ack = 1;
793  }
794  }
795  spin_unlock_irqrestore(&chip->reg_lock, flags);
796  if (ack && ichdev->substream) {
797  snd_pcm_period_elapsed(ichdev->substream);
798  }
799  iputbyte(chip, port + ichdev->roff_sr,
800  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
801 }
802 
803 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
804 {
805  struct intel8x0 *chip = dev_id;
806  struct ichdev *ichdev;
807  unsigned int status;
808  unsigned int i;
809 
810  status = igetdword(chip, chip->int_sta_reg);
811  if (status == 0xffffffff) /* we are not yet resumed */
812  return IRQ_NONE;
813 
814  if ((status & chip->int_sta_mask) == 0) {
815  if (status) {
816  /* ack */
817  iputdword(chip, chip->int_sta_reg, status);
818  if (! chip->buggy_irq)
819  status = 0;
820  }
821  return IRQ_RETVAL(status);
822  }
823 
824  for (i = 0; i < chip->bdbars_count; i++) {
825  ichdev = &chip->ichd[i];
826  if (status & ichdev->int_sta_mask)
827  snd_intel8x0_update(chip, ichdev);
828  }
829 
830  /* ack them */
831  iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
832 
833  return IRQ_HANDLED;
834 }
835 
836 /*
837  * PCM part
838  */
839 
840 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
841 {
842  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
843  struct ichdev *ichdev = get_ichdev(substream);
844  unsigned char val = 0;
845  unsigned long port = ichdev->reg_offset;
846 
847  switch (cmd) {
848  case SNDRV_PCM_TRIGGER_RESUME:
849  ichdev->suspended = 0;
850  /* fallthru */
851  case SNDRV_PCM_TRIGGER_START:
852  case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
853  val = ICH_IOCE | ICH_STARTBM;
854  ichdev->last_pos = ichdev->position;
855  break;
856  case SNDRV_PCM_TRIGGER_SUSPEND:
857  ichdev->suspended = 1;
858  /* fallthru */
859  case SNDRV_PCM_TRIGGER_STOP:
860  val = 0;
861  break;
862  case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
863  val = ICH_IOCE;
864  break;
865  default:
866  return -EINVAL;
867  }
868  iputbyte(chip, port + ICH_REG_OFF_CR, val);
869  if (cmd == SNDRV_PCM_TRIGGER_STOP) {
870  /* wait until DMA stopped */
871  while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
872  /* reset whole DMA things */
873  iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
874  }
875  return 0;
876 }
877 
878 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
879 {
880  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
881  struct ichdev *ichdev = get_ichdev(substream);
882  unsigned long port = ichdev->reg_offset;
883  static int fiforeg[] = {
884  ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
885  };
886  unsigned int val, fifo;
887 
888  val = igetdword(chip, ICHREG(ALI_DMACR));
889  switch (cmd) {
890  case SNDRV_PCM_TRIGGER_RESUME:
891  ichdev->suspended = 0;
892  /* fallthru */
893  case SNDRV_PCM_TRIGGER_START:
894  case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
895  if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
896  /* clear FIFO for synchronization of channels */
897  fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
898  fifo &= ~(0xff << (ichdev->ali_slot % 4));
899  fifo |= 0x83 << (ichdev->ali_slot % 4);
900  iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
901  }
902  iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
903  val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
904  /* start DMA */
905  iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
906  break;
907  case SNDRV_PCM_TRIGGER_SUSPEND:
908  ichdev->suspended = 1;
909  /* fallthru */
910  case SNDRV_PCM_TRIGGER_STOP:
911  case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
912  /* pause */
913  iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
914  iputbyte(chip, port + ICH_REG_OFF_CR, 0);
915  while (igetbyte(chip, port + ICH_REG_OFF_CR))
916  ;
917  if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
918  break;
919  /* reset whole DMA things */
920  iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
921  /* clear interrupts */
922  iputbyte(chip, port + ICH_REG_OFF_SR,
923  igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
924  iputdword(chip, ICHREG(ALI_INTERRUPTSR),
925  igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
926  break;
927  default:
928  return -EINVAL;
929  }
930  return 0;
931 }
932 
933 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
934  struct snd_pcm_hw_params *hw_params)
935 {
936  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
937  struct ichdev *ichdev = get_ichdev(substream);
938  struct snd_pcm_runtime *runtime = substream->runtime;
939  int dbl = params_rate(hw_params) > 48000;
940  int err;
941 
942  if (chip->fix_nocache && ichdev->page_attr_changed) {
943  fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
944  ichdev->page_attr_changed = 0;
945  }
946  err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
947  if (err < 0)
948  return err;
949  if (chip->fix_nocache) {
950  if (runtime->dma_area && ! ichdev->page_attr_changed) {
951  fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
952  ichdev->page_attr_changed = 1;
953  }
954  }
955  if (ichdev->pcm_open_flag) {
956  snd_ac97_pcm_close(ichdev->pcm);
957  ichdev->pcm_open_flag = 0;
958  }
959  err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
960  params_channels(hw_params),
961  ichdev->pcm->r[dbl].slots);
962  if (err >= 0) {
963  ichdev->pcm_open_flag = 1;
964  /* Force SPDIF setting */
965  if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
966  snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
967  params_rate(hw_params));
968  }
969  return err;
970 }
971 
972 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
973 {
974  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
975  struct ichdev *ichdev = get_ichdev(substream);
976 
977  if (ichdev->pcm_open_flag) {
978  snd_ac97_pcm_close(ichdev->pcm);
979  ichdev->pcm_open_flag = 0;
980  }
981  if (chip->fix_nocache && ichdev->page_attr_changed) {
982  fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
983  ichdev->page_attr_changed = 0;
984  }
985  return snd_pcm_lib_free_pages(substream);
986 }
987 
988 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
989  struct snd_pcm_runtime *runtime)
990 {
991  unsigned int cnt;
992  int dbl = runtime->rate > 48000;
993 
994  spin_lock_irq(&chip->reg_lock);
995  switch (chip->device_type) {
996  case DEVICE_ALI:
997  cnt = igetdword(chip, ICHREG(ALI_SCR));
998  cnt &= ~ICH_ALI_SC_PCM_246_MASK;
999  if (runtime->channels == 4 || dbl)
1000  cnt |= ICH_ALI_SC_PCM_4;
1001  else if (runtime->channels == 6)
1002  cnt |= ICH_ALI_SC_PCM_6;
1003  iputdword(chip, ICHREG(ALI_SCR), cnt);
1004  break;
1005  case DEVICE_SIS:
1006  cnt = igetdword(chip, ICHREG(GLOB_CNT));
1007  cnt &= ~ICH_SIS_PCM_246_MASK;
1008  if (runtime->channels == 4 || dbl)
1009  cnt |= ICH_SIS_PCM_4;
1010  else if (runtime->channels == 6)
1011  cnt |= ICH_SIS_PCM_6;
1012  iputdword(chip, ICHREG(GLOB_CNT), cnt);
1013  break;
1014  default:
1015  cnt = igetdword(chip, ICHREG(GLOB_CNT));
1016  cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1017  if (runtime->channels == 4 || dbl)
1018  cnt |= ICH_PCM_4;
1019  else if (runtime->channels == 6)
1020  cnt |= ICH_PCM_6;
1021  else if (runtime->channels == 8)
1022  cnt |= ICH_PCM_8;
1023  if (chip->device_type == DEVICE_NFORCE) {
1024  /* reset to 2ch once to keep the 6 channel data in alignment,
1025  * to start from Front Left always
1026  */
1027  if (cnt & ICH_PCM_246_MASK) {
1028  iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1029  spin_unlock_irq(&chip->reg_lock);
1030  msleep(50); /* grrr... */
1031  spin_lock_irq(&chip->reg_lock);
1032  }
1033  } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1034  if (runtime->sample_bits > 16)
1035  cnt |= ICH_PCM_20BIT;
1036  }
1037  iputdword(chip, ICHREG(GLOB_CNT), cnt);
1038  break;
1039  }
1040  spin_unlock_irq(&chip->reg_lock);
1041 }
1042 
1043 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1044 {
1045  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1046  struct snd_pcm_runtime *runtime = substream->runtime;
1047  struct ichdev *ichdev = get_ichdev(substream);
1048 
1049  ichdev->physbuf = runtime->dma_addr;
1050  ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1051  ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1052  if (ichdev->ichd == ICHD_PCMOUT) {
1053  snd_intel8x0_setup_pcm_out(chip, runtime);
1054  if (chip->device_type == DEVICE_INTEL_ICH4)
1055  ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1056  }
1057  snd_intel8x0_setup_periods(chip, ichdev);
1058  return 0;
1059 }
1060 
1061 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1062 {
1063  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1064  struct ichdev *ichdev = get_ichdev(substream);
1065  size_t ptr1, ptr;
1066  int civ, timeout = 10;
1067  unsigned int position;
1068 
1069  spin_lock(&chip->reg_lock);
1070  do {
1071  civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1072  ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1073  position = ichdev->position;
1074  if (ptr1 == 0) {
1075  udelay(10);
1076  continue;
1077  }
1078  if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1079  continue;
1080 
1081  /* IO read operation is very expensive inside virtual machine
1082  * as it is emulated. The probability that subsequent PICB read
1083  * will return different result is high enough to loop till
1084  * timeout here.
1085  * Same CIV is strict enough condition to be sure that PICB
1086  * is valid inside VM on emulated card. */
1087  if (chip->inside_vm)
1088  break;
1089  if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1090  break;
1091  } while (timeout--);
1092  ptr = ichdev->last_pos;
1093  if (ptr1 != 0) {
1094  ptr1 <<= ichdev->pos_shift;
1095  ptr = ichdev->fragsize1 - ptr1;
1096  ptr += position;
1097  if (ptr < ichdev->last_pos) {
1098  unsigned int pos_base, last_base;
1099  pos_base = position / ichdev->fragsize1;
1100  last_base = ichdev->last_pos / ichdev->fragsize1;
1101  /* another sanity check; ptr1 can go back to full
1102  * before the base position is updated
1103  */
1104  if (pos_base == last_base)
1105  ptr = ichdev->last_pos;
1106  }
1107  }
1108  ichdev->last_pos = ptr;
1109  spin_unlock(&chip->reg_lock);
1110  if (ptr >= ichdev->size)
1111  return 0;
1112  return bytes_to_frames(substream->runtime, ptr);
1113 }
1114 
1115 static struct snd_pcm_hardware snd_intel8x0_stream =
1116 {
1117  .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1118  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1119  SNDRV_PCM_INFO_MMAP_VALID |
1120  SNDRV_PCM_INFO_PAUSE |
1121  SNDRV_PCM_INFO_RESUME),
1122  .formats = SNDRV_PCM_FMTBIT_S16_LE,
1123  .rates = SNDRV_PCM_RATE_48000,
1124  .rate_min = 48000,
1125  .rate_max = 48000,
1126  .channels_min = 2,
1127  .channels_max = 2,
1128  .buffer_bytes_max = 128 * 1024,
1129  .period_bytes_min = 32,
1130  .period_bytes_max = 128 * 1024,
1131  .periods_min = 1,
1132  .periods_max = 1024,
1133  .fifo_size = 0,
1134 };
1135 
1136 static unsigned int channels4[] = {
1137  2, 4,
1138 };
1139 
1140 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1141  .count = ARRAY_SIZE(channels4),
1142  .list = channels4,
1143  .mask = 0,
1144 };
1145 
1146 static unsigned int channels6[] = {
1147  2, 4, 6,
1148 };
1149 
1150 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1151  .count = ARRAY_SIZE(channels6),
1152  .list = channels6,
1153  .mask = 0,
1154 };
1155 
1156 static unsigned int channels8[] = {
1157  2, 4, 6, 8,
1158 };
1159 
1160 static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1161  .count = ARRAY_SIZE(channels8),
1162  .list = channels8,
1163  .mask = 0,
1164 };
1165 
1166 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1167 {
1168  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1169  struct snd_pcm_runtime *runtime = substream->runtime;
1170  int err;
1171 
1172  ichdev->substream = substream;
1173  runtime->hw = snd_intel8x0_stream;
1174  runtime->hw.rates = ichdev->pcm->rates;
1175  snd_pcm_limit_hw_rates(runtime);
1176  if (chip->device_type == DEVICE_SIS) {
1177  runtime->hw.buffer_bytes_max = 64*1024;
1178  runtime->hw.period_bytes_max = 64*1024;
1179  }
1180  if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1181  return err;
1182  runtime->private_data = ichdev;
1183  return 0;
1184 }
1185 
1186 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1187 {
1188  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1189  struct snd_pcm_runtime *runtime = substream->runtime;
1190  int err;
1191 
1192  err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1193  if (err < 0)
1194  return err;
1195 
1196  if (chip->multi8) {
1197  runtime->hw.channels_max = 8;
1198  snd_pcm_hw_constraint_list(runtime, 0,
1199  SNDRV_PCM_HW_PARAM_CHANNELS,
1200  &hw_constraints_channels8);
1201  } else if (chip->multi6) {
1202  runtime->hw.channels_max = 6;
1203  snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1204  &hw_constraints_channels6);
1205  } else if (chip->multi4) {
1206  runtime->hw.channels_max = 4;
1207  snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1208  &hw_constraints_channels4);
1209  }
1210  if (chip->dra) {
1211  snd_ac97_pcm_double_rate_rules(runtime);
1212  }
1213  if (chip->smp20bit) {
1214  runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1215  snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1216  }
1217  return 0;
1218 }
1219 
1220 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1221 {
1222  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1223 
1224  chip->ichd[ICHD_PCMOUT].substream = NULL;
1225  return 0;
1226 }
1227 
1228 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1229 {
1230  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1231 
1232  return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1233 }
1234 
1235 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1236 {
1237  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1238 
1239  chip->ichd[ICHD_PCMIN].substream = NULL;
1240  return 0;
1241 }
1242 
1243 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1244 {
1245  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1246 
1247  return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1248 }
1249 
1250 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1251 {
1252  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1253 
1254  chip->ichd[ICHD_MIC].substream = NULL;
1255  return 0;
1256 }
1257 
1258 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1259 {
1260  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1261 
1262  return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1263 }
1264 
1265 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1266 {
1267  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1268 
1269  chip->ichd[ICHD_MIC2].substream = NULL;
1270  return 0;
1271 }
1272 
1273 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1274 {
1275  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1276 
1277  return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1278 }
1279 
1280 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1281 {
1282  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1283 
1284  chip->ichd[ICHD_PCM2IN].substream = NULL;
1285  return 0;
1286 }
1287 
1288 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1289 {
1290  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1291  int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1292 
1293  return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1294 }
1295 
1296 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1297 {
1298  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1299  int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1300 
1301  chip->ichd[idx].substream = NULL;
1302  return 0;
1303 }
1304 
1305 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1306 {
1307  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1308  unsigned int val;
1309 
1310  spin_lock_irq(&chip->reg_lock);
1311  val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1312  val |= ICH_ALI_IF_AC97SP;
1313  iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1314  /* also needs to set ALI_SC_CODEC_SPDF correctly */
1315  spin_unlock_irq(&chip->reg_lock);
1316 
1317  return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1318 }
1319 
1320 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1321 {
1322  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1323  unsigned int val;
1324 
1325  chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1326  spin_lock_irq(&chip->reg_lock);
1327  val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1328  val &= ~ICH_ALI_IF_AC97SP;
1329  iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1330  spin_unlock_irq(&chip->reg_lock);
1331 
1332  return 0;
1333 }
1334 
1335 #if 0 // NYI
1336 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1337 {
1338  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1339 
1340  return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1341 }
1342 
1343 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1344 {
1345  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1346 
1347  chip->ichd[ALID_SPDIFIN].substream = NULL;
1348  return 0;
1349 }
1350 
1351 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1352 {
1353  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1354 
1355  return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1356 }
1357 
1358 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1359 {
1360  struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1361 
1362  chip->ichd[ALID_SPDIFOUT].substream = NULL;
1363  return 0;
1364 }
1365 #endif
1366 
1367 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1368  .open = snd_intel8x0_playback_open,
1369  .close = snd_intel8x0_playback_close,
1370  .ioctl = snd_pcm_lib_ioctl,
1371  .hw_params = snd_intel8x0_hw_params,
1372  .hw_free = snd_intel8x0_hw_free,
1373  .prepare = snd_intel8x0_pcm_prepare,
1374  .trigger = snd_intel8x0_pcm_trigger,
1375  .pointer = snd_intel8x0_pcm_pointer,
1376 };
1377 
1378 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1379  .open = snd_intel8x0_capture_open,
1380  .close = snd_intel8x0_capture_close,
1381  .ioctl = snd_pcm_lib_ioctl,
1382  .hw_params = snd_intel8x0_hw_params,
1383  .hw_free = snd_intel8x0_hw_free,
1384  .prepare = snd_intel8x0_pcm_prepare,
1385  .trigger = snd_intel8x0_pcm_trigger,
1386  .pointer = snd_intel8x0_pcm_pointer,
1387 };
1388 
1389 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1390  .open = snd_intel8x0_mic_open,
1391  .close = snd_intel8x0_mic_close,
1392  .ioctl = snd_pcm_lib_ioctl,
1393  .hw_params = snd_intel8x0_hw_params,
1394  .hw_free = snd_intel8x0_hw_free,
1395  .prepare = snd_intel8x0_pcm_prepare,
1396  .trigger = snd_intel8x0_pcm_trigger,
1397  .pointer = snd_intel8x0_pcm_pointer,
1398 };
1399 
1400 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1401  .open = snd_intel8x0_mic2_open,
1402  .close = snd_intel8x0_mic2_close,
1403  .ioctl = snd_pcm_lib_ioctl,
1404  .hw_params = snd_intel8x0_hw_params,
1405  .hw_free = snd_intel8x0_hw_free,
1406  .prepare = snd_intel8x0_pcm_prepare,
1407  .trigger = snd_intel8x0_pcm_trigger,
1408  .pointer = snd_intel8x0_pcm_pointer,
1409 };
1410 
1411 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1412  .open = snd_intel8x0_capture2_open,
1413  .close = snd_intel8x0_capture2_close,
1414  .ioctl = snd_pcm_lib_ioctl,
1415  .hw_params = snd_intel8x0_hw_params,
1416  .hw_free = snd_intel8x0_hw_free,
1417  .prepare = snd_intel8x0_pcm_prepare,
1418  .trigger = snd_intel8x0_pcm_trigger,
1419  .pointer = snd_intel8x0_pcm_pointer,
1420 };
1421 
1422 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1423  .open = snd_intel8x0_spdif_open,
1424  .close = snd_intel8x0_spdif_close,
1425  .ioctl = snd_pcm_lib_ioctl,
1426  .hw_params = snd_intel8x0_hw_params,
1427  .hw_free = snd_intel8x0_hw_free,
1428  .prepare = snd_intel8x0_pcm_prepare,
1429  .trigger = snd_intel8x0_pcm_trigger,
1430  .pointer = snd_intel8x0_pcm_pointer,
1431 };
1432 
1433 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1434  .open = snd_intel8x0_playback_open,
1435  .close = snd_intel8x0_playback_close,
1436  .ioctl = snd_pcm_lib_ioctl,
1437  .hw_params = snd_intel8x0_hw_params,
1438  .hw_free = snd_intel8x0_hw_free,
1439  .prepare = snd_intel8x0_pcm_prepare,
1440  .trigger = snd_intel8x0_ali_trigger,
1441  .pointer = snd_intel8x0_pcm_pointer,
1442 };
1443 
1444 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1445  .open = snd_intel8x0_capture_open,
1446  .close = snd_intel8x0_capture_close,
1447  .ioctl = snd_pcm_lib_ioctl,
1448  .hw_params = snd_intel8x0_hw_params,
1449  .hw_free = snd_intel8x0_hw_free,
1450  .prepare = snd_intel8x0_pcm_prepare,
1451  .trigger = snd_intel8x0_ali_trigger,
1452  .pointer = snd_intel8x0_pcm_pointer,
1453 };
1454 
1455 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1456  .open = snd_intel8x0_mic_open,
1457  .close = snd_intel8x0_mic_close,
1458  .ioctl = snd_pcm_lib_ioctl,
1459  .hw_params = snd_intel8x0_hw_params,
1460  .hw_free = snd_intel8x0_hw_free,
1461  .prepare = snd_intel8x0_pcm_prepare,
1462  .trigger = snd_intel8x0_ali_trigger,
1463  .pointer = snd_intel8x0_pcm_pointer,
1464 };
1465 
1466 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1467  .open = snd_intel8x0_ali_ac97spdifout_open,
1468  .close = snd_intel8x0_ali_ac97spdifout_close,
1469  .ioctl = snd_pcm_lib_ioctl,
1470  .hw_params = snd_intel8x0_hw_params,
1471  .hw_free = snd_intel8x0_hw_free,
1472  .prepare = snd_intel8x0_pcm_prepare,
1473  .trigger = snd_intel8x0_ali_trigger,
1474  .pointer = snd_intel8x0_pcm_pointer,
1475 };
1476 
1477 #if 0 // NYI
1478 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1479  .open = snd_intel8x0_ali_spdifin_open,
1480  .close = snd_intel8x0_ali_spdifin_close,
1481  .ioctl = snd_pcm_lib_ioctl,
1482  .hw_params = snd_intel8x0_hw_params,
1483  .hw_free = snd_intel8x0_hw_free,
1484  .prepare = snd_intel8x0_pcm_prepare,
1485  .trigger = snd_intel8x0_pcm_trigger,
1486  .pointer = snd_intel8x0_pcm_pointer,
1487 };
1488 
1489 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1490  .open = snd_intel8x0_ali_spdifout_open,
1491  .close = snd_intel8x0_ali_spdifout_close,
1492  .ioctl = snd_pcm_lib_ioctl,
1493  .hw_params = snd_intel8x0_hw_params,
1494  .hw_free = snd_intel8x0_hw_free,
1495  .prepare = snd_intel8x0_pcm_prepare,
1496  .trigger = snd_intel8x0_pcm_trigger,
1497  .pointer = snd_intel8x0_pcm_pointer,
1498 };
1499 #endif // NYI
1500 
1501 struct ich_pcm_table {
1502  char *suffix;
1503  struct snd_pcm_ops *playback_ops;
1504  struct snd_pcm_ops *capture_ops;
1505  size_t prealloc_size;
1506  size_t prealloc_max_size;
1507  int ac97_idx;
1508 };
1509 
1510 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1511  struct ich_pcm_table *rec)
1512 {
1513  struct snd_pcm *pcm;
1514  int err;
1515  char name[32];
1516 
1517  if (rec->suffix)
1518  sprintf(name, "Intel ICH - %s", rec->suffix);
1519  else
1520  strcpy(name, "Intel ICH");
1521  err = snd_pcm_new(chip->card, name, device,
1522  rec->playback_ops ? 1 : 0,
1523  rec->capture_ops ? 1 : 0, &pcm);
1524  if (err < 0)
1525  return err;
1526 
1527  if (rec->playback_ops)
1528  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1529  if (rec->capture_ops)
1530  snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1531 
1532  pcm->private_data = chip;
1533  pcm->info_flags = 0;
1534  if (rec->suffix)
1535  sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1536  else
1537  strcpy(pcm->name, chip->card->shortname);
1538  chip->pcm[device] = pcm;
1539 
1540  snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1541  snd_dma_pci_data(chip->pci),
1542  rec->prealloc_size, rec->prealloc_max_size);
1543 
1544  if (rec->ac97_idx == ICHD_PCMOUT && rec->playback_ops) {
1545  struct snd_pcm_chmap *chmap;
1546  int chs = 2;
1547  if (rec->ac97_idx == ICHD_PCMOUT) {
1548  if (chip->multi8)
1549  chs = 8;
1550  else if (chip->multi6)
1551  chs = 6;
1552  else if (chip->multi4)
1553  chs = 4;
1554  }
1555  err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1556  snd_pcm_alt_chmaps, chs, 0,
1557  &chmap);
1558  if (err < 0)
1559  return err;
1560  chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1561  chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1562  }
1563 
1564  return 0;
1565 }
1566 
1567 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1568  {
1569  .playback_ops = &snd_intel8x0_playback_ops,
1570  .capture_ops = &snd_intel8x0_capture_ops,
1571  .prealloc_size = 64 * 1024,
1572  .prealloc_max_size = 128 * 1024,
1573  },
1574  {
1575  .suffix = "MIC ADC",
1576  .capture_ops = &snd_intel8x0_capture_mic_ops,
1577  .prealloc_size = 0,
1578  .prealloc_max_size = 128 * 1024,
1579  .ac97_idx = ICHD_MIC,
1580  },
1581  {
1582  .suffix = "MIC2 ADC",
1583  .capture_ops = &snd_intel8x0_capture_mic2_ops,
1584  .prealloc_size = 0,
1585  .prealloc_max_size = 128 * 1024,
1586  .ac97_idx = ICHD_MIC2,
1587  },
1588  {
1589  .suffix = "ADC2",
1590  .capture_ops = &snd_intel8x0_capture2_ops,
1591  .prealloc_size = 0,
1592  .prealloc_max_size = 128 * 1024,
1593  .ac97_idx = ICHD_PCM2IN,
1594  },
1595  {
1596  .suffix = "IEC958",
1597  .playback_ops = &snd_intel8x0_spdif_ops,
1598  .prealloc_size = 64 * 1024,
1599  .prealloc_max_size = 128 * 1024,
1600  .ac97_idx = ICHD_SPBAR,
1601  },
1602 };
1603 
1604 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1605  {
1606  .playback_ops = &snd_intel8x0_playback_ops,
1607  .capture_ops = &snd_intel8x0_capture_ops,
1608  .prealloc_size = 64 * 1024,
1609  .prealloc_max_size = 128 * 1024,
1610  },
1611  {
1612  .suffix = "MIC ADC",
1613  .capture_ops = &snd_intel8x0_capture_mic_ops,
1614  .prealloc_size = 0,
1615  .prealloc_max_size = 128 * 1024,
1616  .ac97_idx = NVD_MIC,
1617  },
1618  {
1619  .suffix = "IEC958",
1620  .playback_ops = &snd_intel8x0_spdif_ops,
1621  .prealloc_size = 64 * 1024,
1622  .prealloc_max_size = 128 * 1024,
1623  .ac97_idx = NVD_SPBAR,
1624  },
1625 };
1626 
1627 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1628  {
1629  .playback_ops = &snd_intel8x0_ali_playback_ops,
1630  .capture_ops = &snd_intel8x0_ali_capture_ops,
1631  .prealloc_size = 64 * 1024,
1632  .prealloc_max_size = 128 * 1024,
1633  },
1634  {
1635  .suffix = "MIC ADC",
1636  .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1637  .prealloc_size = 0,
1638  .prealloc_max_size = 128 * 1024,
1639  .ac97_idx = ALID_MIC,
1640  },
1641  {
1642  .suffix = "IEC958",
1643  .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1644  /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1645  .prealloc_size = 64 * 1024,
1646  .prealloc_max_size = 128 * 1024,
1647  .ac97_idx = ALID_AC97SPDIFOUT,
1648  },
1649 #if 0 // NYI
1650  {
1651  .suffix = "HW IEC958",
1652  .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1653  .prealloc_size = 64 * 1024,
1654  .prealloc_max_size = 128 * 1024,
1655  },
1656 #endif
1657 };
1658 
1659 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1660 {
1661  int i, tblsize, device, err;
1662  struct ich_pcm_table *tbl, *rec;
1663 
1664  switch (chip->device_type) {
1665  case DEVICE_INTEL_ICH4:
1666  tbl = intel_pcms;
1667  tblsize = ARRAY_SIZE(intel_pcms);
1668  if (spdif_aclink)
1669  tblsize--;
1670  break;
1671  case DEVICE_NFORCE:
1672  tbl = nforce_pcms;
1673  tblsize = ARRAY_SIZE(nforce_pcms);
1674  if (spdif_aclink)
1675  tblsize--;
1676  break;
1677  case DEVICE_ALI:
1678  tbl = ali_pcms;
1679  tblsize = ARRAY_SIZE(ali_pcms);
1680  break;
1681  default:
1682  tbl = intel_pcms;
1683  tblsize = 2;
1684  break;
1685  }
1686 
1687  device = 0;
1688  for (i = 0; i < tblsize; i++) {
1689  rec = tbl + i;
1690  if (i > 0 && rec->ac97_idx) {
1691  /* activate PCM only when associated AC'97 codec */
1692  if (! chip->ichd[rec->ac97_idx].pcm)
1693  continue;
1694  }
1695  err = snd_intel8x0_pcm1(chip, device, rec);
1696  if (err < 0)
1697  return err;
1698  device++;
1699  }
1700 
1701  chip->pcm_devs = device;
1702  return 0;
1703 }
1704 
1705 
1706 /*
1707  * Mixer part
1708  */
1709 
1710 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1711 {
1712  struct intel8x0 *chip = bus->private_data;
1713  chip->ac97_bus = NULL;
1714 }
1715 
1716 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1717 {
1718  struct intel8x0 *chip = ac97->private_data;
1719  chip->ac97[ac97->num] = NULL;
1720 }
1721 
1722 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1723  /* front PCM */
1724  {
1725  .exclusive = 1,
1726  .r = { {
1727  .slots = (1 << AC97_SLOT_PCM_LEFT) |
1728  (1 << AC97_SLOT_PCM_RIGHT) |
1729  (1 << AC97_SLOT_PCM_CENTER) |
1730  (1 << AC97_SLOT_PCM_SLEFT) |
1731  (1 << AC97_SLOT_PCM_SRIGHT) |
1732  (1 << AC97_SLOT_LFE)
1733  },
1734  {
1735  .slots = (1 << AC97_SLOT_PCM_LEFT) |
1736  (1 << AC97_SLOT_PCM_RIGHT) |
1737  (1 << AC97_SLOT_PCM_LEFT_0) |
1738  (1 << AC97_SLOT_PCM_RIGHT_0)
1739  }
1740  }
1741  },
1742  /* PCM IN #1 */
1743  {
1744  .stream = 1,
1745  .exclusive = 1,
1746  .r = { {
1747  .slots = (1 << AC97_SLOT_PCM_LEFT) |
1748  (1 << AC97_SLOT_PCM_RIGHT)
1749  }
1750  }
1751  },
1752  /* MIC IN #1 */
1753  {
1754  .stream = 1,
1755  .exclusive = 1,
1756  .r = { {
1757  .slots = (1 << AC97_SLOT_MIC)
1758  }
1759  }
1760  },
1761  /* S/PDIF PCM */
1762  {
1763  .exclusive = 1,
1764  .spdif = 1,
1765  .r = { {
1766  .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1767  (1 << AC97_SLOT_SPDIF_RIGHT2)
1768  }
1769  }
1770  },
1771  /* PCM IN #2 */
1772  {
1773  .stream = 1,
1774  .exclusive = 1,
1775  .r = { {
1776  .slots = (1 << AC97_SLOT_PCM_LEFT) |
1777  (1 << AC97_SLOT_PCM_RIGHT)
1778  }
1779  }
1780  },
1781  /* MIC IN #2 */
1782  {
1783  .stream = 1,
1784  .exclusive = 1,
1785  .r = { {
1786  .slots = (1 << AC97_SLOT_MIC)
1787  }
1788  }
1789  },
1790 };
1791 
1792 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1793  {
1794  .subvendor = 0x0e11,
1795  .subdevice = 0x000e,
1796  .name = "Compaq Deskpro EN", /* AD1885 */
1797  .type = AC97_TUNE_HP_ONLY
1798  },
1799  {
1800  .subvendor = 0x0e11,
1801  .subdevice = 0x008a,
1802  .name = "Compaq Evo W4000", /* AD1885 */
1803  .type = AC97_TUNE_HP_ONLY
1804  },
1805  {
1806  .subvendor = 0x0e11,
1807  .subdevice = 0x00b8,
1808  .name = "Compaq Evo D510C",
1809  .type = AC97_TUNE_HP_ONLY
1810  },
1811  {
1812  .subvendor = 0x0e11,
1813  .subdevice = 0x0860,
1814  .name = "HP/Compaq nx7010",
1815  .type = AC97_TUNE_MUTE_LED
1816  },
1817  {
1818  .subvendor = 0x1014,
1819  .subdevice = 0x0534,
1820  .name = "ThinkPad X31",
1821  .type = AC97_TUNE_INV_EAPD
1822  },
1823  {
1824  .subvendor = 0x1014,
1825  .subdevice = 0x1f00,
1826  .name = "MS-9128",
1827  .type = AC97_TUNE_ALC_JACK
1828  },
1829  {
1830  .subvendor = 0x1014,
1831  .subdevice = 0x0267,
1832  .name = "IBM NetVista A30p", /* AD1981B */
1833  .type = AC97_TUNE_HP_ONLY
1834  },
1835  {
1836  .subvendor = 0x1025,
1837  .subdevice = 0x0082,
1838  .name = "Acer Travelmate 2310",
1839  .type = AC97_TUNE_HP_ONLY
1840  },
1841  {
1842  .subvendor = 0x1025,
1843  .subdevice = 0x0083,
1844  .name = "Acer Aspire 3003LCi",
1845  .type = AC97_TUNE_HP_ONLY
1846  },
1847  {
1848  .subvendor = 0x1028,
1849  .subdevice = 0x00d8,
1850  .name = "Dell Precision 530", /* AD1885 */
1851  .type = AC97_TUNE_HP_ONLY
1852  },
1853  {
1854  .subvendor = 0x1028,
1855  .subdevice = 0x010d,
1856  .name = "Dell", /* which model? AD1885 */
1857  .type = AC97_TUNE_HP_ONLY
1858  },
1859  {
1860  .subvendor = 0x1028,
1861  .subdevice = 0x0126,
1862  .name = "Dell Optiplex GX260", /* AD1981A */
1863  .type = AC97_TUNE_HP_ONLY
1864  },
1865  {
1866  .subvendor = 0x1028,
1867  .subdevice = 0x012c,
1868  .name = "Dell Precision 650", /* AD1981A */
1869  .type = AC97_TUNE_HP_ONLY
1870  },
1871  {
1872  .subvendor = 0x1028,
1873  .subdevice = 0x012d,
1874  .name = "Dell Precision 450", /* AD1981B*/
1875  .type = AC97_TUNE_HP_ONLY
1876  },
1877  {
1878  .subvendor = 0x1028,
1879  .subdevice = 0x0147,
1880  .name = "Dell", /* which model? AD1981B*/
1881  .type = AC97_TUNE_HP_ONLY
1882  },
1883  {
1884  .subvendor = 0x1028,
1885  .subdevice = 0x0151,
1886  .name = "Dell Optiplex GX270", /* AD1981B */
1887  .type = AC97_TUNE_HP_ONLY
1888  },
1889  {
1890  .subvendor = 0x1028,
1891  .subdevice = 0x014e,
1892  .name = "Dell D800", /* STAC9750/51 */
1893  .type = AC97_TUNE_HP_ONLY
1894  },
1895  {
1896  .subvendor = 0x1028,
1897  .subdevice = 0x0163,
1898  .name = "Dell Unknown", /* STAC9750/51 */
1899  .type = AC97_TUNE_HP_ONLY
1900  },
1901  {
1902  .subvendor = 0x1028,
1903  .subdevice = 0x016a,
1904  .name = "Dell Inspiron 8600", /* STAC9750/51 */
1905  .type = AC97_TUNE_HP_ONLY
1906  },
1907  {
1908  .subvendor = 0x1028,
1909  .subdevice = 0x0182,
1910  .name = "Dell Latitude D610", /* STAC9750/51 */
1911  .type = AC97_TUNE_HP_ONLY
1912  },
1913  {
1914  .subvendor = 0x1028,
1915  .subdevice = 0x0186,
1916  .name = "Dell Latitude D810", /* cf. Malone #41015 */
1917  .type = AC97_TUNE_HP_MUTE_LED
1918  },
1919  {
1920  .subvendor = 0x1028,
1921  .subdevice = 0x0188,
1922  .name = "Dell Inspiron 6000",
1923  .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1924  },
1925  {
1926  .subvendor = 0x1028,
1927  .subdevice = 0x0189,
1928  .name = "Dell Inspiron 9300",
1929  .type = AC97_TUNE_HP_MUTE_LED
1930  },
1931  {
1932  .subvendor = 0x1028,
1933  .subdevice = 0x0191,
1934  .name = "Dell Inspiron 8600",
1935  .type = AC97_TUNE_HP_ONLY
1936  },
1937  {
1938  .subvendor = 0x103c,
1939  .subdevice = 0x006d,
1940  .name = "HP zv5000",
1941  .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1942  },
1943  { /* FIXME: which codec? */
1944  .subvendor = 0x103c,
1945  .subdevice = 0x00c3,
1946  .name = "HP xw6000",
1947  .type = AC97_TUNE_HP_ONLY
1948  },
1949  {
1950  .subvendor = 0x103c,
1951  .subdevice = 0x088c,
1952  .name = "HP nc8000",
1953  .type = AC97_TUNE_HP_MUTE_LED
1954  },
1955  {
1956  .subvendor = 0x103c,
1957  .subdevice = 0x0890,
1958  .name = "HP nc6000",
1959  .type = AC97_TUNE_MUTE_LED
1960  },
1961  {
1962  .subvendor = 0x103c,
1963  .subdevice = 0x129d,
1964  .name = "HP xw8000",
1965  .type = AC97_TUNE_HP_ONLY
1966  },
1967  {
1968  .subvendor = 0x103c,
1969  .subdevice = 0x0938,
1970  .name = "HP nc4200",
1971  .type = AC97_TUNE_HP_MUTE_LED
1972  },
1973  {
1974  .subvendor = 0x103c,
1975  .subdevice = 0x099c,
1976  .name = "HP nx6110/nc6120",
1977  .type = AC97_TUNE_HP_MUTE_LED
1978  },
1979  {
1980  .subvendor = 0x103c,
1981  .subdevice = 0x0944,
1982  .name = "HP nc6220",
1983  .type = AC97_TUNE_HP_MUTE_LED
1984  },
1985  {
1986  .subvendor = 0x103c,
1987  .subdevice = 0x0934,
1988  .name = "HP nc8220",
1989  .type = AC97_TUNE_HP_MUTE_LED
1990  },
1991  {
1992  .subvendor = 0x103c,
1993  .subdevice = 0x12f1,
1994  .name = "HP xw8200", /* AD1981B*/
1995  .type = AC97_TUNE_HP_ONLY
1996  },
1997  {
1998  .subvendor = 0x103c,
1999  .subdevice = 0x12f2,
2000  .name = "HP xw6200",
2001  .type = AC97_TUNE_HP_ONLY
2002  },
2003  {
2004  .subvendor = 0x103c,
2005  .subdevice = 0x3008,
2006  .name = "HP xw4200", /* AD1981B*/
2007  .type = AC97_TUNE_HP_ONLY
2008  },
2009  {
2010  .subvendor = 0x104d,
2011  .subdevice = 0x8144,
2012  .name = "Sony",
2013  .type = AC97_TUNE_INV_EAPD
2014  },
2015  {
2016  .subvendor = 0x104d,
2017  .subdevice = 0x8197,
2018  .name = "Sony S1XP",
2019  .type = AC97_TUNE_INV_EAPD
2020  },
2021  {
2022  .subvendor = 0x104d,
2023  .subdevice = 0x81c0,
2024  .name = "Sony VAIO VGN-T350P", /*AD1981B*/
2025  .type = AC97_TUNE_INV_EAPD
2026  },
2027  {
2028  .subvendor = 0x104d,
2029  .subdevice = 0x81c5,
2030  .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
2031  .type = AC97_TUNE_INV_EAPD
2032  },
2033  {
2034  .subvendor = 0x1043,
2035  .subdevice = 0x80f3,
2036  .name = "ASUS ICH5/AD1985",
2037  .type = AC97_TUNE_AD_SHARING
2038  },
2039  {
2040  .subvendor = 0x10cf,
2041  .subdevice = 0x11c3,
2042  .name = "Fujitsu-Siemens E4010",
2043  .type = AC97_TUNE_HP_ONLY
2044  },
2045  {
2046  .subvendor = 0x10cf,
2047  .subdevice = 0x1225,
2048  .name = "Fujitsu-Siemens T3010",
2049  .type = AC97_TUNE_HP_ONLY
2050  },
2051  {
2052  .subvendor = 0x10cf,
2053  .subdevice = 0x1253,
2054  .name = "Fujitsu S6210", /* STAC9750/51 */
2055  .type = AC97_TUNE_HP_ONLY
2056  },
2057  {
2058  .subvendor = 0x10cf,
2059  .subdevice = 0x127d,
2060  .name = "Fujitsu Lifebook P7010",
2061  .type = AC97_TUNE_HP_ONLY
2062  },
2063  {
2064  .subvendor = 0x10cf,
2065  .subdevice = 0x127e,
2066  .name = "Fujitsu Lifebook C1211D",
2067  .type = AC97_TUNE_HP_ONLY
2068  },
2069  {
2070  .subvendor = 0x10cf,
2071  .subdevice = 0x12ec,
2072  .name = "Fujitsu-Siemens 4010",
2073  .type = AC97_TUNE_HP_ONLY
2074  },
2075  {
2076  .subvendor = 0x10cf,
2077  .subdevice = 0x12f2,
2078  .name = "Fujitsu-Siemens Celsius H320",
2079  .type = AC97_TUNE_SWAP_HP
2080  },
2081  {
2082  .subvendor = 0x10f1,
2083  .subdevice = 0x2665,
2084  .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2085  .type = AC97_TUNE_HP_ONLY
2086  },
2087  {
2088  .subvendor = 0x10f1,
2089  .subdevice = 0x2885,
2090  .name = "AMD64 Mobo", /* ALC650 */
2091  .type = AC97_TUNE_HP_ONLY
2092  },
2093  {
2094  .subvendor = 0x10f1,
2095  .subdevice = 0x2895,
2096  .name = "Tyan Thunder K8WE",
2097  .type = AC97_TUNE_HP_ONLY
2098  },
2099  {
2100  .subvendor = 0x10f7,
2101  .subdevice = 0x834c,
2102  .name = "Panasonic CF-R4",
2103  .type = AC97_TUNE_HP_ONLY,
2104  },
2105  {
2106  .subvendor = 0x110a,
2107  .subdevice = 0x0056,
2108  .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2109  .type = AC97_TUNE_HP_ONLY
2110  },
2111  {
2112  .subvendor = 0x11d4,
2113  .subdevice = 0x5375,
2114  .name = "ADI AD1985 (discrete)",
2115  .type = AC97_TUNE_HP_ONLY
2116  },
2117  {
2118  .subvendor = 0x1462,
2119  .subdevice = 0x5470,
2120  .name = "MSI P4 ATX 645 Ultra",
2121  .type = AC97_TUNE_HP_ONLY
2122  },
2123  {
2124  .subvendor = 0x161f,
2125  .subdevice = 0x202f,
2126  .name = "Gateway M520",
2127  .type = AC97_TUNE_INV_EAPD
2128  },
2129  {
2130  .subvendor = 0x161f,
2131  .subdevice = 0x203a,
2132  .name = "Gateway 4525GZ", /* AD1981B */
2133  .type = AC97_TUNE_INV_EAPD
2134  },
2135  {
2136  .subvendor = 0x1734,
2137  .subdevice = 0x0088,
2138  .name = "Fujitsu-Siemens D1522", /* AD1981 */
2139  .type = AC97_TUNE_HP_ONLY
2140  },
2141  {
2142  .subvendor = 0x8086,
2143  .subdevice = 0x2000,
2144  .mask = 0xfff0,
2145  .name = "Intel ICH5/AD1985",
2146  .type = AC97_TUNE_AD_SHARING
2147  },
2148  {
2149  .subvendor = 0x8086,
2150  .subdevice = 0x4000,
2151  .mask = 0xfff0,
2152  .name = "Intel ICH5/AD1985",
2153  .type = AC97_TUNE_AD_SHARING
2154  },
2155  {
2156  .subvendor = 0x8086,
2157  .subdevice = 0x4856,
2158  .name = "Intel D845WN (82801BA)",
2159  .type = AC97_TUNE_SWAP_HP
2160  },
2161  {
2162  .subvendor = 0x8086,
2163  .subdevice = 0x4d44,
2164  .name = "Intel D850EMV2", /* AD1885 */
2165  .type = AC97_TUNE_HP_ONLY
2166  },
2167  {
2168  .subvendor = 0x8086,
2169  .subdevice = 0x4d56,
2170  .name = "Intel ICH/AD1885",
2171  .type = AC97_TUNE_HP_ONLY
2172  },
2173  {
2174  .subvendor = 0x8086,
2175  .subdevice = 0x6000,
2176  .mask = 0xfff0,
2177  .name = "Intel ICH5/AD1985",
2178  .type = AC97_TUNE_AD_SHARING
2179  },
2180  {
2181  .subvendor = 0x8086,
2182  .subdevice = 0xe000,
2183  .mask = 0xfff0,
2184  .name = "Intel ICH5/AD1985",
2185  .type = AC97_TUNE_AD_SHARING
2186  },
2187 #if 0 /* FIXME: this seems wrong on most boards */
2188  {
2189  .subvendor = 0x8086,
2190  .subdevice = 0xa000,
2191  .mask = 0xfff0,
2192  .name = "Intel ICH5/AD1985",
2193  .type = AC97_TUNE_HP_ONLY
2194  },
2195 #endif
2196  { } /* terminator */
2197 };
2198 
2199 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2200  const char *quirk_override)
2201 {
2202  struct snd_ac97_bus *pbus;
2203  struct snd_ac97_template ac97;
2204  int err;
2205  unsigned int i, codecs;
2206  unsigned int glob_sta = 0;
2207  struct snd_ac97_bus_ops *ops;
2208  static struct snd_ac97_bus_ops standard_bus_ops = {
2209  .write = snd_intel8x0_codec_write,
2210  .read = snd_intel8x0_codec_read,
2211  };
2212  static struct snd_ac97_bus_ops ali_bus_ops = {
2213  .write = snd_intel8x0_ali_codec_write,
2214  .read = snd_intel8x0_ali_codec_read,
2215  };
2216 
2217  chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2218  if (!spdif_aclink) {
2219  switch (chip->device_type) {
2220  case DEVICE_NFORCE:
2221  chip->spdif_idx = NVD_SPBAR;
2222  break;
2223  case DEVICE_ALI:
2224  chip->spdif_idx = ALID_AC97SPDIFOUT;
2225  break;
2226  case DEVICE_INTEL_ICH4:
2227  chip->spdif_idx = ICHD_SPBAR;
2228  break;
2229  }
2230  }
2231 
2232  chip->in_ac97_init = 1;
2233 
2234  memset(&ac97, 0, sizeof(ac97));
2235  ac97.private_data = chip;
2236  ac97.private_free = snd_intel8x0_mixer_free_ac97;
2237  ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2238  if (chip->xbox)
2239  ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2240  if (chip->device_type != DEVICE_ALI) {
2241  glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2242  ops = &standard_bus_ops;
2243  chip->in_sdin_init = 1;
2244  codecs = 0;
2245  for (i = 0; i < chip->max_codecs; i++) {
2246  if (! (glob_sta & chip->codec_bit[i]))
2247  continue;
2248  if (chip->device_type == DEVICE_INTEL_ICH4) {
2249  snd_intel8x0_codec_read_test(chip, codecs);
2250  chip->ac97_sdin[codecs] =
2251  igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2252  if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2253  chip->ac97_sdin[codecs] = 0;
2254  } else
2255  chip->ac97_sdin[codecs] = i;
2256  codecs++;
2257  }
2258  chip->in_sdin_init = 0;
2259  if (! codecs)
2260  codecs = 1;
2261  } else {
2262  ops = &ali_bus_ops;
2263  codecs = 1;
2264  /* detect the secondary codec */
2265  for (i = 0; i < 100; i++) {
2266  unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2267  if (reg & 0x40) {
2268  codecs = 2;
2269  break;
2270  }
2271  iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2272  udelay(1);
2273  }
2274  }
2275  if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2276  goto __err;
2277  pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2278  if (ac97_clock >= 8000 && ac97_clock <= 48000)
2279  pbus->clock = ac97_clock;
2280  /* FIXME: my test board doesn't work well with VRA... */
2281  if (chip->device_type == DEVICE_ALI)
2282  pbus->no_vra = 1;
2283  else
2284  pbus->dra = 1;
2285  chip->ac97_bus = pbus;
2286  chip->ncodecs = codecs;
2287 
2288  ac97.pci = chip->pci;
2289  for (i = 0; i < codecs; i++) {
2290  ac97.num = i;
2291  if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2292  if (err != -EACCES)
2293  snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2294  if (i == 0)
2295  goto __err;
2296  }
2297  }
2298  /* tune up the primary codec */
2299  snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2300  /* enable separate SDINs for ICH4 */
2301  if (chip->device_type == DEVICE_INTEL_ICH4)
2302  pbus->isdin = 1;
2303  /* find the available PCM streams */
2304  i = ARRAY_SIZE(ac97_pcm_defs);
2305  if (chip->device_type != DEVICE_INTEL_ICH4)
2306  i -= 2; /* do not allocate PCM2IN and MIC2 */
2307  if (chip->spdif_idx < 0)
2308  i--; /* do not allocate S/PDIF */
2309  err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2310  if (err < 0)
2311  goto __err;
2312  chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2313  chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2314  chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2315  if (chip->spdif_idx >= 0)
2316  chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2317  if (chip->device_type == DEVICE_INTEL_ICH4) {
2318  chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2319  chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2320  }
2321  /* enable separate SDINs for ICH4 */
2322  if (chip->device_type == DEVICE_INTEL_ICH4) {
2323  struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2324  u8 tmp = igetbyte(chip, ICHREG(SDM));
2325  tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2326  if (pcm) {
2327  tmp |= ICH_SE; /* steer enable for multiple SDINs */
2328  tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2329  for (i = 1; i < 4; i++) {
2330  if (pcm->r[0].codec[i]) {
2331  tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2332  break;
2333  }
2334  }
2335  } else {
2336  tmp &= ~ICH_SE; /* steer disable */
2337  }
2338  iputbyte(chip, ICHREG(SDM), tmp);
2339  }
2340  if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2341  chip->multi4 = 1;
2342  if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2343  chip->multi6 = 1;
2344  if (chip->ac97[0]->flags & AC97_HAS_8CH)
2345  chip->multi8 = 1;
2346  }
2347  }
2348  if (pbus->pcms[0].r[1].rslots[0]) {
2349  chip->dra = 1;
2350  }
2351  if (chip->device_type == DEVICE_INTEL_ICH4) {
2352  if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2353  chip->smp20bit = 1;
2354  }
2355  if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2356  /* 48kHz only */
2357  chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2358  }
2359  if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2360  /* use slot 10/11 for SPDIF */
2361  u32 val;
2362  val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2363  val |= ICH_PCM_SPDIF_1011;
2364  iputdword(chip, ICHREG(GLOB_CNT), val);
2365  snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2366  }
2367  chip->in_ac97_init = 0;
2368  return 0;
2369 
2370  __err:
2371  /* clear the cold-reset bit for the next chance */
2372  if (chip->device_type != DEVICE_ALI)
2373  iputdword(chip, ICHREG(GLOB_CNT),
2374  igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2375  return err;
2376 }
2377 
2378 
2379 /*
2380  *
2381  */
2382 
2383 static void do_ali_reset(struct intel8x0 *chip)
2384 {
2385  iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2386  iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2387  iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2388  iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2389  iputdword(chip, ICHREG(ALI_INTERFACECR),
2390  ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2391  iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2392  iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2393 }
2394 
2395 #ifdef CONFIG_SND_AC97_POWER_SAVE
2396 static struct snd_pci_quirk ich_chip_reset_mode[] = {
2397  SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2398  { } /* end */
2399 };
2400 
2401 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2402 {
2403  unsigned int cnt;
2404  /* ACLink on, 2 channels */
2405 
2406  if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2407  return -EIO;
2408 
2409  cnt = igetdword(chip, ICHREG(GLOB_CNT));
2410  cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2411 
2412  /* do cold reset - the full ac97 powerdown may leave the controller
2413  * in a warm state but actually it cannot communicate with the codec.
2414  */
2415  iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2416  cnt = igetdword(chip, ICHREG(GLOB_CNT));
2417  udelay(10);
2418  iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2419  msleep(1);
2420  return 0;
2421 }
2422 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2423  (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2424 #else
2425 #define snd_intel8x0_ich_chip_cold_reset(chip) 0
2426 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2427 #endif
2428 
2429 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2430 {
2431  unsigned long end_time;
2432  unsigned int cnt;
2433  /* ACLink on, 2 channels */
2434  cnt = igetdword(chip, ICHREG(GLOB_CNT));
2435  cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2436  /* finish cold or do warm reset */
2437  cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2438  iputdword(chip, ICHREG(GLOB_CNT), cnt);
2439  end_time = (jiffies + (HZ / 4)) + 1;
2440  do {
2441  if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2442  return 0;
2443  schedule_timeout_uninterruptible(1);
2444  } while (time_after_eq(end_time, jiffies));
2445  snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2446  igetdword(chip, ICHREG(GLOB_CNT)));
2447  return -EIO;
2448 }
2449 
2450 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2451 {
2452  unsigned long end_time;
2453  unsigned int status, nstatus;
2454  unsigned int cnt;
2455  int err;
2456 
2457  /* put logic to right state */
2458  /* first clear status bits */
2459  status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2460  if (chip->device_type == DEVICE_NFORCE)
2461  status |= ICH_NVSPINT;
2462  cnt = igetdword(chip, ICHREG(GLOB_STA));
2463  iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2464 
2465  if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2466  err = snd_intel8x0_ich_chip_cold_reset(chip);
2467  else
2468  err = snd_intel8x0_ich_chip_reset(chip);
2469  if (err < 0)
2470  return err;
2471 
2472  if (probing) {
2473  /* wait for any codec ready status.
2474  * Once it becomes ready it should remain ready
2475  * as long as we do not disable the ac97 link.
2476  */
2477  end_time = jiffies + HZ;
2478  do {
2479  status = igetdword(chip, ICHREG(GLOB_STA)) &
2480  chip->codec_isr_bits;
2481  if (status)
2482  break;
2483  schedule_timeout_uninterruptible(1);
2484  } while (time_after_eq(end_time, jiffies));
2485  if (! status) {
2486  /* no codec is found */
2487  snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2488  igetdword(chip, ICHREG(GLOB_STA)));
2489  return -EIO;
2490  }
2491 
2492  /* wait for other codecs ready status. */
2493  end_time = jiffies + HZ / 4;
2494  while (status != chip->codec_isr_bits &&
2495  time_after_eq(end_time, jiffies)) {
2496  schedule_timeout_uninterruptible(1);
2497  status |= igetdword(chip, ICHREG(GLOB_STA)) &
2498  chip->codec_isr_bits;
2499  }
2500 
2501  } else {
2502  /* resume phase */
2503  int i;
2504  status = 0;
2505  for (i = 0; i < chip->ncodecs; i++)
2506  if (chip->ac97[i])
2507  status |= chip->codec_bit[chip->ac97_sdin[i]];
2508  /* wait until all the probed codecs are ready */
2509  end_time = jiffies + HZ;
2510  do {
2511  nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2512  chip->codec_isr_bits;
2513  if (status == nstatus)
2514  break;
2515  schedule_timeout_uninterruptible(1);
2516  } while (time_after_eq(end_time, jiffies));
2517  }
2518 
2519  if (chip->device_type == DEVICE_SIS) {
2520  /* unmute the output on SIS7012 */
2521  iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2522  }
2523  if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2524  /* enable SPDIF interrupt */
2525  unsigned int val;
2526  pci_read_config_dword(chip->pci, 0x4c, &val);
2527  val |= 0x1000000;
2528  pci_write_config_dword(chip->pci, 0x4c, val);
2529  }
2530  return 0;
2531 }
2532 
2533 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2534 {
2535  u32 reg;
2536  int i = 0;
2537 
2538  reg = igetdword(chip, ICHREG(ALI_SCR));
2539  if ((reg & 2) == 0) /* Cold required */
2540  reg |= 2;
2541  else
2542  reg |= 1; /* Warm */
2543  reg &= ~0x80000000; /* ACLink on */
2544  iputdword(chip, ICHREG(ALI_SCR), reg);
2545 
2546  for (i = 0; i < HZ / 2; i++) {
2547  if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2548  goto __ok;
2549  schedule_timeout_uninterruptible(1);
2550  }
2551  snd_printk(KERN_ERR "AC'97 reset failed.\n");
2552  if (probing)
2553  return -EIO;
2554 
2555  __ok:
2556  for (i = 0; i < HZ / 2; i++) {
2557  reg = igetdword(chip, ICHREG(ALI_RTSR));
2558  if (reg & 0x80) /* primary codec */
2559  break;
2560  iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2561  schedule_timeout_uninterruptible(1);
2562  }
2563 
2564  do_ali_reset(chip);
2565  return 0;
2566 }
2567 
2568 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2569 {
2570  unsigned int i, timeout;
2571  int err;
2572 
2573  if (chip->device_type != DEVICE_ALI) {
2574  if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2575  return err;
2576  iagetword(chip, 0); /* clear semaphore flag */
2577  } else {
2578  if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2579  return err;
2580  }
2581 
2582  /* disable interrupts */
2583  for (i = 0; i < chip->bdbars_count; i++)
2584  iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2585  /* reset channels */
2586  for (i = 0; i < chip->bdbars_count; i++)
2587  iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2588  for (i = 0; i < chip->bdbars_count; i++) {
2589  timeout = 100000;
2590  while (--timeout != 0) {
2591  if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2592  break;
2593  }
2594  if (timeout == 0)
2595  printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2596  }
2597  /* initialize Buffer Descriptor Lists */
2598  for (i = 0; i < chip->bdbars_count; i++)
2599  iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2600  chip->ichd[i].bdbar_addr);
2601  return 0;
2602 }
2603 
2604 static int snd_intel8x0_free(struct intel8x0 *chip)
2605 {
2606  unsigned int i;
2607 
2608  if (chip->irq < 0)
2609  goto __hw_end;
2610  /* disable interrupts */
2611  for (i = 0; i < chip->bdbars_count; i++)
2612  iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2613  /* reset channels */
2614  for (i = 0; i < chip->bdbars_count; i++)
2615  iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2616  if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2617  /* stop the spdif interrupt */
2618  unsigned int val;
2619  pci_read_config_dword(chip->pci, 0x4c, &val);
2620  val &= ~0x1000000;
2621  pci_write_config_dword(chip->pci, 0x4c, val);
2622  }
2623  /* --- */
2624 
2625  __hw_end:
2626  if (chip->irq >= 0)
2627  free_irq(chip->irq, chip);
2628  if (chip->bdbars.area) {
2629  if (chip->fix_nocache)
2630  fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2631  snd_dma_free_pages(&chip->bdbars);
2632  }
2633  if (chip->addr)
2634  pci_iounmap(chip->pci, chip->addr);
2635  if (chip->bmaddr)
2636  pci_iounmap(chip->pci, chip->bmaddr);
2637  pci_release_regions(chip->pci);
2638  pci_disable_device(chip->pci);
2639  kfree(chip);
2640  return 0;
2641 }
2642 
2643 #ifdef CONFIG_PM_SLEEP
2644 /*
2645  * power management
2646  */
2647 static int intel8x0_suspend(struct device *dev)
2648 {
2649  struct pci_dev *pci = to_pci_dev(dev);
2650  struct snd_card *card = dev_get_drvdata(dev);
2651  struct intel8x0 *chip = card->private_data;
2652  int i;
2653 
2654  snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2655  for (i = 0; i < chip->pcm_devs; i++)
2656  snd_pcm_suspend_all(chip->pcm[i]);
2657  /* clear nocache */
2658  if (chip->fix_nocache) {
2659  for (i = 0; i < chip->bdbars_count; i++) {
2660  struct ichdev *ichdev = &chip->ichd[i];
2661  if (ichdev->substream && ichdev->page_attr_changed) {
2662  struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2663  if (runtime->dma_area)
2664  fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2665  }
2666  }
2667  }
2668  for (i = 0; i < chip->ncodecs; i++)
2669  snd_ac97_suspend(chip->ac97[i]);
2670  if (chip->device_type == DEVICE_INTEL_ICH4)
2671  chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2672 
2673  if (chip->irq >= 0) {
2674  free_irq(chip->irq, chip);
2675  chip->irq = -1;
2676  }
2677  pci_disable_device(pci);
2678  pci_save_state(pci);
2679  /* The call below may disable built-in speaker on some laptops
2680  * after S2RAM. So, don't touch it.
2681  */
2682  /* pci_set_power_state(pci, PCI_D3hot); */
2683  return 0;
2684 }
2685 
2686 static int intel8x0_resume(struct device *dev)
2687 {
2688  struct pci_dev *pci = to_pci_dev(dev);
2689  struct snd_card *card = dev_get_drvdata(dev);
2690  struct intel8x0 *chip = card->private_data;
2691  int i;
2692 
2693  pci_set_power_state(pci, PCI_D0);
2694  pci_restore_state(pci);
2695  if (pci_enable_device(pci) < 0) {
2696  printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2697  "disabling device\n");
2698  snd_card_disconnect(card);
2699  return -EIO;
2700  }
2701  pci_set_master(pci);
2702  snd_intel8x0_chip_init(chip, 0);
2703  if (request_irq(pci->irq, snd_intel8x0_interrupt,
2704  IRQF_SHARED, KBUILD_MODNAME, chip)) {
2705  printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2706  "disabling device\n", pci->irq);
2707  snd_card_disconnect(card);
2708  return -EIO;
2709  }
2710  chip->irq = pci->irq;
2711  synchronize_irq(chip->irq);
2712 
2713  /* re-initialize mixer stuff */
2714  if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2715  /* enable separate SDINs for ICH4 */
2716  iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2717  /* use slot 10/11 for SPDIF */
2718  iputdword(chip, ICHREG(GLOB_CNT),
2719  (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2720  ICH_PCM_SPDIF_1011);
2721  }
2722 
2723  /* refill nocache */
2724  if (chip->fix_nocache)
2725  fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2726 
2727  for (i = 0; i < chip->ncodecs; i++)
2728  snd_ac97_resume(chip->ac97[i]);
2729 
2730  /* refill nocache */
2731  if (chip->fix_nocache) {
2732  for (i = 0; i < chip->bdbars_count; i++) {
2733  struct ichdev *ichdev = &chip->ichd[i];
2734  if (ichdev->substream && ichdev->page_attr_changed) {
2735  struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2736  if (runtime->dma_area)
2737  fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2738  }
2739  }
2740  }
2741 
2742  /* resume status */
2743  for (i = 0; i < chip->bdbars_count; i++) {
2744  struct ichdev *ichdev = &chip->ichd[i];
2745  unsigned long port = ichdev->reg_offset;
2746  if (! ichdev->substream || ! ichdev->suspended)
2747  continue;
2748  if (ichdev->ichd == ICHD_PCMOUT)
2749  snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2750  iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2751  iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2752  iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2753  iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2754  }
2755 
2756  snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2757  return 0;
2758 }
2759 
2760 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2761 #define INTEL8X0_PM_OPS &intel8x0_pm
2762 #else
2763 #define INTEL8X0_PM_OPS NULL
2764 #endif /* CONFIG_PM_SLEEP */
2765 
2766 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2767 
2768 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2769 {
2770  struct snd_pcm_substream *subs;
2771  struct ichdev *ichdev;
2772  unsigned long port;
2773  unsigned long pos, pos1, t;
2774  int civ, timeout = 1000, attempt = 1;
2775  struct timespec start_time, stop_time;
2776 
2777  if (chip->ac97_bus->clock != 48000)
2778  return; /* specified in module option */
2779 
2780  __again:
2781  subs = chip->pcm[0]->streams[0].substream;
2782  if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2783  snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2784  return;
2785  }
2786  ichdev = &chip->ichd[ICHD_PCMOUT];
2787  ichdev->physbuf = subs->dma_buffer.addr;
2788  ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2789  ichdev->substream = NULL; /* don't process interrupts */
2790 
2791  /* set rate */
2792  if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2793  snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2794  return;
2795  }
2796  snd_intel8x0_setup_periods(chip, ichdev);
2797  port = ichdev->reg_offset;
2798  spin_lock_irq(&chip->reg_lock);
2799  chip->in_measurement = 1;
2800  /* trigger */
2801  if (chip->device_type != DEVICE_ALI)
2802  iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2803  else {
2804  iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2805  iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2806  }
2807  do_posix_clock_monotonic_gettime(&start_time);
2808  spin_unlock_irq(&chip->reg_lock);
2809  msleep(50);
2810  spin_lock_irq(&chip->reg_lock);
2811  /* check the position */
2812  do {
2813  civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2814  pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2815  if (pos1 == 0) {
2816  udelay(10);
2817  continue;
2818  }
2819  if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2820  pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2821  break;
2822  } while (timeout--);
2823  if (pos1 == 0) { /* oops, this value is not reliable */
2824  pos = 0;
2825  } else {
2826  pos = ichdev->fragsize1;
2827  pos -= pos1 << ichdev->pos_shift;
2828  pos += ichdev->position;
2829  }
2830  chip->in_measurement = 0;
2831  do_posix_clock_monotonic_gettime(&stop_time);
2832  /* stop */
2833  if (chip->device_type == DEVICE_ALI) {
2834  iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2835  iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2836  while (igetbyte(chip, port + ICH_REG_OFF_CR))
2837  ;
2838  } else {
2839  iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2840  while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2841  ;
2842  }
2843  iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2844  spin_unlock_irq(&chip->reg_lock);
2845 
2846  if (pos == 0) {
2847  snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2848  __retry:
2849  if (attempt < 3) {
2850  msleep(300);
2851  attempt++;
2852  goto __again;
2853  }
2854  goto __end;
2855  }
2856 
2857  pos /= 4;
2858  t = stop_time.tv_sec - start_time.tv_sec;
2859  t *= 1000000;
2860  t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2861  printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2862  if (t == 0) {
2863  snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2864  goto __retry;
2865  }
2866  pos *= 1000;
2867  pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2868  if (pos < 40000 || pos >= 60000) {
2869  /* abnormal value. hw problem? */
2870  printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2871  goto __retry;
2872  } else if (pos > 40500 && pos < 41500)
2873  /* first exception - 41000Hz reference clock */
2874  chip->ac97_bus->clock = 41000;
2875  else if (pos > 43600 && pos < 44600)
2876  /* second exception - 44100HZ reference clock */
2877  chip->ac97_bus->clock = 44100;
2878  else if (pos < 47500 || pos > 48500)
2879  /* not 48000Hz, tuning the clock.. */
2880  chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2881  __end:
2882  printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2883  snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2884 }
2885 
2886 static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2887  SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2888  SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2889  SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2890  SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2891  SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2892  { } /* terminator */
2893 };
2894 
2895 static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2896 {
2897  struct pci_dev *pci = chip->pci;
2898  const struct snd_pci_quirk *wl;
2899 
2900  wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2901  if (!wl)
2902  return 0;
2903  printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2904  pci->subsystem_vendor, pci->subsystem_device, wl->value);
2905  chip->ac97_bus->clock = wl->value;
2906  return 1;
2907 }
2908 
2909 #ifdef CONFIG_PROC_FS
2910 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2911  struct snd_info_buffer *buffer)
2912 {
2913  struct intel8x0 *chip = entry->private_data;
2914  unsigned int tmp;
2915 
2916  snd_iprintf(buffer, "Intel8x0\n\n");
2917  if (chip->device_type == DEVICE_ALI)
2918  return;
2919  tmp = igetdword(chip, ICHREG(GLOB_STA));
2920  snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2921  snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2922  if (chip->device_type == DEVICE_INTEL_ICH4)
2923  snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2924  snd_iprintf(buffer, "AC'97 codecs ready :");
2925  if (tmp & chip->codec_isr_bits) {
2926  int i;
2927  static const char *codecs[3] = {
2928  "primary", "secondary", "tertiary"
2929  };
2930  for (i = 0; i < chip->max_codecs; i++)
2931  if (tmp & chip->codec_bit[i])
2932  snd_iprintf(buffer, " %s", codecs[i]);
2933  } else
2934  snd_iprintf(buffer, " none");
2935  snd_iprintf(buffer, "\n");
2936  if (chip->device_type == DEVICE_INTEL_ICH4 ||
2937  chip->device_type == DEVICE_SIS)
2938  snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2939  chip->ac97_sdin[0],
2940  chip->ac97_sdin[1],
2941  chip->ac97_sdin[2]);
2942 }
2943 
2944 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2945 {
2946  struct snd_info_entry *entry;
2947 
2948  if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2949  snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2950 }
2951 #else
2952 #define snd_intel8x0_proc_init(x)
2953 #endif
2954 
2955 static int snd_intel8x0_dev_free(struct snd_device *device)
2956 {
2957  struct intel8x0 *chip = device->device_data;
2958  return snd_intel8x0_free(chip);
2959 }
2960 
2961 struct ich_reg_info {
2962  unsigned int int_sta_mask;
2963  unsigned int offset;
2964 };
2965 
2966 static unsigned int ich_codec_bits[3] = {
2967  ICH_PCR, ICH_SCR, ICH_TCR
2968 };
2969 static unsigned int sis_codec_bits[3] = {
2970  ICH_PCR, ICH_SCR, ICH_SIS_TCR
2971 };
2972 
2973 static int __devinit snd_intel8x0_inside_vm(struct pci_dev *pci)
2974 {
2975  int result = inside_vm;
2976  char *msg = NULL;
2977 
2978  /* check module parameter first (override detection) */
2979  if (result >= 0) {
2980  msg = result ? "enable (forced) VM" : "disable (forced) VM";
2981  goto fini;
2982  }
2983 
2984  /* detect KVM and Parallels virtual environments */
2985  result = kvm_para_available();
2986 #ifdef X86_FEATURE_HYPERVISOR
2987  result = result || boot_cpu_has(X86_FEATURE_HYPERVISOR);
2988 #endif
2989  if (!result)
2990  goto fini;
2991 
2992  /* check for known (emulated) devices */
2993  if (pci->subsystem_vendor == 0x1af4 &&
2994  pci->subsystem_device == 0x1100) {
2995  /* KVM emulated sound, PCI SSID: 1af4:1100 */
2996  msg = "enable KVM";
2997  } else if (pci->subsystem_vendor == 0x1ab8) {
2998  /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2999  msg = "enable Parallels VM";
3000  } else {
3001  msg = "disable (unknown or VT-d) VM";
3002  result = 0;
3003  }
3004 
3005 fini:
3006  if (msg != NULL)
3007  printk(KERN_INFO "intel8x0: %s optimization\n", msg);
3008 
3009  return result;
3010 }
3011 
3012 static int __devinit snd_intel8x0_create(struct snd_card *card,
3013  struct pci_dev *pci,
3014  unsigned long device_type,
3015  struct intel8x0 ** r_intel8x0)
3016 {
3017  struct intel8x0 *chip;
3018  int err;
3019  unsigned int i;
3020  unsigned int int_sta_masks;
3021  struct ichdev *ichdev;
3022  static struct snd_device_ops ops = {
3023  .dev_free = snd_intel8x0_dev_free,
3024  };
3025 
3026  static unsigned int bdbars[] = {
3027  3, /* DEVICE_INTEL */
3028  6, /* DEVICE_INTEL_ICH4 */
3029  3, /* DEVICE_SIS */
3030  6, /* DEVICE_ALI */
3031  4, /* DEVICE_NFORCE */
3032  };
3033  static struct ich_reg_info intel_regs[6] = {
3034  { ICH_PIINT, 0 },
3035  { ICH_POINT, 0x10 },
3036  { ICH_MCINT, 0x20 },
3037  { ICH_M2INT, 0x40 },
3038  { ICH_P2INT, 0x50 },
3039  { ICH_SPINT, 0x60 },
3040  };
3041  static struct ich_reg_info nforce_regs[4] = {
3042  { ICH_PIINT, 0 },
3043  { ICH_POINT, 0x10 },
3044  { ICH_MCINT, 0x20 },
3045  { ICH_NVSPINT, 0x70 },
3046  };
3047  static struct ich_reg_info ali_regs[6] = {
3048  { ALI_INT_PCMIN, 0x40 },
3049  { ALI_INT_PCMOUT, 0x50 },
3050  { ALI_INT_MICIN, 0x60 },
3051  { ALI_INT_CODECSPDIFOUT, 0x70 },
3052  { ALI_INT_SPDIFIN, 0xa0 },
3053  { ALI_INT_SPDIFOUT, 0xb0 },
3054  };
3055  struct ich_reg_info *tbl;
3056 
3057  *r_intel8x0 = NULL;
3058 
3059  if ((err = pci_enable_device(pci)) < 0)
3060  return err;
3061 
3062  chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3063  if (chip == NULL) {
3064  pci_disable_device(pci);
3065  return -ENOMEM;
3066  }
3067  spin_lock_init(&chip->reg_lock);
3068  chip->device_type = device_type;
3069  chip->card = card;
3070  chip->pci = pci;
3071  chip->irq = -1;
3072 
3073  /* module parameters */
3074  chip->buggy_irq = buggy_irq;
3075  chip->buggy_semaphore = buggy_semaphore;
3076  if (xbox)
3077  chip->xbox = 1;
3078 
3079  chip->inside_vm = snd_intel8x0_inside_vm(pci);
3080 
3081  if (pci->vendor == PCI_VENDOR_ID_INTEL &&
3082  pci->device == PCI_DEVICE_ID_INTEL_440MX)
3083  chip->fix_nocache = 1; /* enable workaround */
3084 
3085  if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3086  kfree(chip);
3087  pci_disable_device(pci);
3088  return err;
3089  }
3090 
3091  if (device_type == DEVICE_ALI) {
3092  /* ALI5455 has no ac97 region */
3093  chip->bmaddr = pci_iomap(pci, 0, 0);
3094  goto port_inited;
3095  }
3096 
3097  if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3098  chip->addr = pci_iomap(pci, 2, 0);
3099  else
3100  chip->addr = pci_iomap(pci, 0, 0);
3101  if (!chip->addr) {
3102  snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
3103  snd_intel8x0_free(chip);
3104  return -EIO;
3105  }
3106  if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3107  chip->bmaddr = pci_iomap(pci, 3, 0);
3108  else
3109  chip->bmaddr = pci_iomap(pci, 1, 0);
3110  if (!chip->bmaddr) {
3111  snd_printk(KERN_ERR "Controller space ioremap problem\n");
3112  snd_intel8x0_free(chip);
3113  return -EIO;
3114  }
3115 
3116  port_inited:
3117  chip->bdbars_count = bdbars[device_type];
3118 
3119  /* initialize offsets */
3120  switch (device_type) {
3121  case DEVICE_NFORCE:
3122  tbl = nforce_regs;
3123  break;
3124  case DEVICE_ALI:
3125  tbl = ali_regs;
3126  break;
3127  default:
3128  tbl = intel_regs;
3129  break;
3130  }
3131  for (i = 0; i < chip->bdbars_count; i++) {
3132  ichdev = &chip->ichd[i];
3133  ichdev->ichd = i;
3134  ichdev->reg_offset = tbl[i].offset;
3135  ichdev->int_sta_mask = tbl[i].int_sta_mask;
3136  if (device_type == DEVICE_SIS) {
3137  /* SiS 7012 swaps the registers */
3138  ichdev->roff_sr = ICH_REG_OFF_PICB;
3139  ichdev->roff_picb = ICH_REG_OFF_SR;
3140  } else {
3141  ichdev->roff_sr = ICH_REG_OFF_SR;
3142  ichdev->roff_picb = ICH_REG_OFF_PICB;
3143  }
3144  if (device_type == DEVICE_ALI)
3145  ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3146  /* SIS7012 handles the pcm data in bytes, others are in samples */
3147  ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3148  }
3149 
3150  /* allocate buffer descriptor lists */
3151  /* the start of each lists must be aligned to 8 bytes */
3152  if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3153  chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3154  &chip->bdbars) < 0) {
3155  snd_intel8x0_free(chip);
3156  snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3157  return -ENOMEM;
3158  }
3159  /* tables must be aligned to 8 bytes here, but the kernel pages
3160  are much bigger, so we don't care (on i386) */
3161  /* workaround for 440MX */
3162  if (chip->fix_nocache)
3163  fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3164  int_sta_masks = 0;
3165  for (i = 0; i < chip->bdbars_count; i++) {
3166  ichdev = &chip->ichd[i];
3167  ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3168  (i * ICH_MAX_FRAGS * 2);
3169  ichdev->bdbar_addr = chip->bdbars.addr +
3170  (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3171  int_sta_masks |= ichdev->int_sta_mask;
3172  }
3173  chip->int_sta_reg = device_type == DEVICE_ALI ?
3174  ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3175  chip->int_sta_mask = int_sta_masks;
3176 
3177  pci_set_master(pci);
3178 
3179  switch(chip->device_type) {
3180  case DEVICE_INTEL_ICH4:
3181  /* ICH4 can have three codecs */
3182  chip->max_codecs = 3;
3183  chip->codec_bit = ich_codec_bits;
3184  chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3185  break;
3186  case DEVICE_SIS:
3187  /* recent SIS7012 can have three codecs */
3188  chip->max_codecs = 3;
3189  chip->codec_bit = sis_codec_bits;
3190  chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3191  break;
3192  default:
3193  /* others up to two codecs */
3194  chip->max_codecs = 2;
3195  chip->codec_bit = ich_codec_bits;
3196  chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3197  break;
3198  }
3199  for (i = 0; i < chip->max_codecs; i++)
3200  chip->codec_isr_bits |= chip->codec_bit[i];
3201 
3202  if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3203  snd_intel8x0_free(chip);
3204  return err;
3205  }
3206 
3207  /* request irq after initializaing int_sta_mask, etc */
3208  if (request_irq(pci->irq, snd_intel8x0_interrupt,
3209  IRQF_SHARED, KBUILD_MODNAME, chip)) {
3210  snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3211  snd_intel8x0_free(chip);
3212  return -EBUSY;
3213  }
3214  chip->irq = pci->irq;
3215 
3216  if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3217  snd_intel8x0_free(chip);
3218  return err;
3219  }
3220 
3221  snd_card_set_dev(card, &pci->dev);
3222 
3223  *r_intel8x0 = chip;
3224  return 0;
3225 }
3226 
3227 static struct shortname_table {
3228  unsigned int id;
3229  const char *s;
3230 } shortnames[] __devinitdata = {
3231  { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3232  { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3233  { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3234  { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3235  { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3236  { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3237  { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3238  { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3239  { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3240  { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3241  { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3242  { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3243  { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3244  { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3245  { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3246  { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3247  { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3248  { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3249  { 0x003a, "NVidia MCP04" },
3250  { 0x746d, "AMD AMD8111" },
3251  { 0x7445, "AMD AMD768" },
3252  { 0x5455, "ALi M5455" },
3253  { 0, NULL },
3254 };
3255 
3256 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3257  SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3258  { } /* end */
3259 };
3260 
3261 /* look up white/black list for SPDIF over ac-link */
3262 static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3263 {
3264  const struct snd_pci_quirk *w;
3265 
3266  w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3267  if (w) {
3268  if (w->value)
3269  snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3270  "AC-Link for %s\n", w->name);
3271  else
3272  snd_printdd(KERN_INFO "intel8x0: Using integrated "
3273  "SPDIF DMA for %s\n", w->name);
3274  return w->value;
3275  }
3276  return 0;
3277 }
3278 
3279 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3280  const struct pci_device_id *pci_id)
3281 {
3282  struct snd_card *card;
3283  struct intel8x0 *chip;
3284  int err;
3285  struct shortname_table *name;
3286 
3287  err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3288  if (err < 0)
3289  return err;
3290 
3291  if (spdif_aclink < 0)
3292  spdif_aclink = check_default_spdif_aclink(pci);
3293 
3294  strcpy(card->driver, "ICH");
3295  if (!spdif_aclink) {
3296  switch (pci_id->driver_data) {
3297  case DEVICE_NFORCE:
3298  strcpy(card->driver, "NFORCE");
3299  break;
3300  case DEVICE_INTEL_ICH4:
3301  strcpy(card->driver, "ICH4");
3302  }
3303  }
3304 
3305  strcpy(card->shortname, "Intel ICH");
3306  for (name = shortnames; name->id; name++) {
3307  if (pci->device == name->id) {
3308  strcpy(card->shortname, name->s);
3309  break;
3310  }
3311  }
3312 
3313  if (buggy_irq < 0) {
3314  /* some Nforce[2] and ICH boards have problems with IRQ handling.
3315  * Needs to return IRQ_HANDLED for unknown irqs.
3316  */
3317  if (pci_id->driver_data == DEVICE_NFORCE)
3318  buggy_irq = 1;
3319  else
3320  buggy_irq = 0;
3321  }
3322 
3323  if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3324  &chip)) < 0) {
3325  snd_card_free(card);
3326  return err;
3327  }
3328  card->private_data = chip;
3329 
3330  if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3331  snd_card_free(card);
3332  return err;
3333  }
3334  if ((err = snd_intel8x0_pcm(chip)) < 0) {
3335  snd_card_free(card);
3336  return err;
3337  }
3338 
3339  snd_intel8x0_proc_init(chip);
3340 
3341  snprintf(card->longname, sizeof(card->longname),
3342  "%s with %s at irq %i", card->shortname,
3343  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3344 
3345  if (ac97_clock == 0 || ac97_clock == 1) {
3346  if (ac97_clock == 0) {
3347  if (intel8x0_in_clock_list(chip) == 0)
3348  intel8x0_measure_ac97_clock(chip);
3349  } else {
3350  intel8x0_measure_ac97_clock(chip);
3351  }
3352  }
3353 
3354  if ((err = snd_card_register(card)) < 0) {
3355  snd_card_free(card);
3356  return err;
3357  }
3358  pci_set_drvdata(pci, card);
3359  return 0;
3360 }
3361 
3362 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3363 {
3364  snd_card_free(pci_get_drvdata(pci));
3365  pci_set_drvdata(pci, NULL);
3366 }
3367 
3368 static struct pci_driver intel8x0_driver = {
3369  .name = KBUILD_MODNAME,
3370  .id_table = snd_intel8x0_ids,
3371  .probe = snd_intel8x0_probe,
3372  .remove = __devexit_p(snd_intel8x0_remove),
3373  .driver = {
3374  .pm = INTEL8X0_PM_OPS,
3375  },
3376 };
3377 
3378 module_pci_driver(intel8x0_driver);
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