#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/seq_file.h>
#include <linux/string.h>
#include <linux/tick.h>
#include <linux/timer.h>
#include <linux/dmi.h>
#include <drm/i915_drm.h>
#include <asm/msr.h>
#include <asm/processor.h>
#include "intel_ips.h"
#include <asm-generic/io-64-nonatomic-lo-hi.h>

Data Structures
struct	ips_mcp_limits

struct	ips_driver

Macros
#define	PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32

#define	PLATFORM_INFO 0xce

#define	PLATFORM_TDP (1<<29)

#define	PLATFORM_RATIO (1<<28)

#define	IA32_MISC_ENABLE 0x1a0

#define	IA32_MISC_TURBO_EN (1ULL<<38)

#define	TURBO_POWER_CURRENT_LIMIT 0x1ac

#define	TURBO_TDC_OVR_EN (1UL<<31)

#define	TURBO_TDC_MASK (0x000000007fff0000UL)

#define	TURBO_TDC_SHIFT (16)

#define	TURBO_TDP_OVR_EN (1UL<<15)

#define	TURBO_TDP_MASK (0x0000000000003fffUL)

#define	IA32_PERF_CTL 0x199

#define	IA32_PERF_TURBO_DIS (1ULL<<32)

#define	THM_CFG_TBAR 0x10

#define	THM_CFG_TBAR_HI 0x14

#define	THM_TSIU 0x00

#define	THM_TSE 0x01

#define	TSE_EN 0xb8

#define	THM_TSS 0x02

#define	THM_TSTR 0x03

#define	THM_TSTTP 0x04

#define	THM_TSCO 0x08

#define	THM_TSES 0x0c

#define	THM_TSGPEN 0x0d

#define	TSGPEN_HOT_LOHI (1<<1)

#define	TSGPEN_CRIT_LOHI (1<<2)

#define	THM_TSPC 0x0e

#define	THM_PPEC 0x10

#define	THM_CTA 0x12

#define	THM_PTA 0x14

#define	PTA_SLOPE_MASK (0xff00)

#define	PTA_SLOPE_SHIFT 8

#define	PTA_OFFSET_MASK (0x00ff)

#define	THM_MGTA 0x16

#define	MGTA_SLOPE_MASK (0xff00)

#define	MGTA_SLOPE_SHIFT 8

#define	MGTA_OFFSET_MASK (0x00ff)

#define	THM_TRC 0x1a

#define	TRC_CORE2_EN (1<<15)

#define	TRC_THM_EN (1<<12)

#define	TRC_C6_WAR (1<<8)

#define	TRC_CORE1_EN (1<<7)

#define	TRC_CORE_PWR (1<<6)

#define	TRC_PCH_EN (1<<5)

#define	TRC_MCH_EN (1<<4)

#define	TRC_DIMM4 (1<<3)

#define	TRC_DIMM3 (1<<2)

#define	TRC_DIMM2 (1<<1)

#define	TRC_DIMM1 (1<<0)

#define	THM_TES 0x20

#define	THM_TEN 0x21

#define	TEN_UPDATE_EN 1

#define	THM_PSC 0x24

#define	PSC_NTG (1<<0) /* No GFX turbo support */

#define	PSC_NTPC (1<<1) /* No CPU turbo support */

#define	PSC_PP_DEF (0<<2) /* Perf policy up to driver */

#define	PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */

#define	PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */

#define	PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */

#define	PSP_PBRT (1<<4) /* BIOS run time support */

#define	THM_CTV1 0x30

#define	CTV_TEMP_ERROR (1<<15)

#define	CTV_TEMP_MASK 0x3f

#define	CTV_

#define	THM_CTV2 0x32

#define	THM_CEC 0x34 /* undocumented power accumulator in joules */

#define	THM_AE 0x3f

#define	THM_HTS 0x50 /* 32 bits */

#define	HTS_PCPL_MASK (0x7fe00000)

#define	HTS_PCPL_SHIFT 21

#define	HTS_GPL_MASK (0x001ff000)

#define	HTS_GPL_SHIFT 12

#define	HTS_PP_MASK (0x00000c00)

#define	HTS_PP_SHIFT 10

#define	HTS_PP_DEF 0

#define	HTS_PP_PROC 1

#define	HTS_PP_BAL 2

#define	HTS_PP_GFX 3

#define	HTS_PCTD_DIS (1<<9)

#define	HTS_GTD_DIS (1<<8)

#define	HTS_PTL_MASK (0x000000fe)

#define	HTS_PTL_SHIFT 1

#define	HTS_NVV (1<<0)

#define	THM_HTSHI 0x54 /* 16 bits */

#define	HTS2_PPL_MASK (0x03ff)

#define	HTS2_PRST_MASK (0x3c00)

#define	HTS2_PRST_SHIFT 10

#define	HTS2_PRST_UNLOADED 0

#define	HTS2_PRST_RUNNING 1

#define	HTS2_PRST_TDISOP 2 /* turbo disabled due to power */

#define	HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */

#define	HTS2_PRST_TDISUSR 4 /* user disabled turbo */

#define	HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */

#define	HTS2_PRST_TDISPM 6 /* power management disabled turbo */

#define	HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */

#define	THM_PTL 0x56

#define	THM_MGTV 0x58

#define	TV_MASK 0x000000000000ff00

#define	TV_SHIFT 8

#define	THM_PTV 0x60

#define	PTV_MASK 0x00ff

#define	THM_MMGPC 0x64

#define	THM_MPPC 0x66

#define	THM_MPCPC 0x68

#define	THM_TSPIEN 0x82

#define	TSPIEN_AUX_LOHI (1<<0)

#define	TSPIEN_HOT_LOHI (1<<1)

#define	TSPIEN_CRIT_LOHI (1<<2)

#define	TSPIEN_AUX2_LOHI (1<<3)

#define	THM_TSLOCK 0x83

#define	THM_ATR 0x84

#define	THM_TOF 0x87

#define	THM_STS 0x98

#define	STS_PCPL_MASK (0x7fe00000)

#define	STS_PCPL_SHIFT 21

#define	STS_GPL_MASK (0x001ff000)

#define	STS_GPL_SHIFT 12

#define	STS_PP_MASK (0x00000c00)

#define	STS_PP_SHIFT 10

#define	STS_PP_DEF 0

#define	STS_PP_PROC 1

#define	STS_PP_BAL 2

#define	STS_PP_GFX 3

#define	STS_PCTD_DIS (1<<9)

#define	STS_GTD_DIS (1<<8)

#define	STS_PTL_MASK (0x000000fe)

#define	STS_PTL_SHIFT 1

#define	STS_NVV (1<<0)

#define	THM_SEC 0x9c

#define	SEC_ACK (1<<0)

#define	THM_TC3 0xa4

#define	THM_TC1 0xa8

#define	STS_PPL_MASK (0x0003ff00)

#define	STS_PPL_SHIFT 16

#define	THM_TC2 0xac

#define	THM_DTV 0xb0

#define	THM_ITV 0xd8

#define	ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */

#define	ITV_ME_SEQNO_SHIFT (16)

#define	ITV_MCH_TEMP_MASK 0x0000ff00

#define	ITV_MCH_TEMP_SHIFT (8)

#define	ITV_PCH_TEMP_MASK 0x000000ff

#define	thm_readb(off) readb(ips->regmap + (off))

#define	thm_readw(off) readw(ips->regmap + (off))

#define	thm_readl(off) readl(ips->regmap + (off))

#define	thm_readq(off) readq(ips->regmap + (off))

#define	thm_writeb(off, val) writeb((val), ips->regmap + (off))

#define	thm_writew(off, val) writew((val), ips->regmap + (off))

#define	thm_writel(off, val) writel((val), ips->regmap + (off))

#define	IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)

Functions
void	ips_link_to_i915_driver (void)

	EXPORT_SYMBOL_GPL (ips_link_to_i915_driver)

	MODULE_DEVICE_TABLE (pci, ips_id_table)

	module_init (ips_init)

	module_exit (ips_exit)

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Jesse Barnes <[email protected]>")

	MODULE_DESCRIPTION ("Intelligent Power Sharing Driver")

Variables
struct ips_mcp_limits	ips_sv_limits

struct ips_mcp_limits	ips_lv_limits

struct ips_mcp_limits	ips_ulv_limits

Macro Definition Documentation

#define CTV_

Definition at line 162 of file intel_ips.c.

#define CTV_TEMP_ERROR (1<<15)

Definition at line 160 of file intel_ips.c.

#define CTV_TEMP_MASK 0x3f

Definition at line 161 of file intel_ips.c.

#define HTS2_PPL_MASK (0x03ff)

Definition at line 183 of file intel_ips.c.

#define HTS2_PRST_MASK (0x3c00)

Definition at line 184 of file intel_ips.c.

#define HTS2_PRST_RUNNING 1

Definition at line 187 of file intel_ips.c.

#define HTS2_PRST_SHIFT 10

Definition at line 185 of file intel_ips.c.

#define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */

Definition at line 193 of file intel_ips.c.

#define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */

Definition at line 189 of file intel_ips.c.

#define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */

Definition at line 188 of file intel_ips.c.

#define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */

Definition at line 191 of file intel_ips.c.

#define HTS2_PRST_TDISPM 6 /* power management disabled turbo */

Definition at line 192 of file intel_ips.c.

#define HTS2_PRST_TDISUSR 4 /* user disabled turbo */

Definition at line 190 of file intel_ips.c.

#define HTS2_PRST_UNLOADED 0

Definition at line 186 of file intel_ips.c.

#define HTS_GPL_MASK (0x001ff000)

Definition at line 169 of file intel_ips.c.

#define HTS_GPL_SHIFT 12

Definition at line 170 of file intel_ips.c.

#define HTS_GTD_DIS (1<<8)

Definition at line 178 of file intel_ips.c.

#define HTS_NVV (1<<0)

Definition at line 181 of file intel_ips.c.

#define HTS_PCPL_MASK (0x7fe00000)

Definition at line 167 of file intel_ips.c.

#define HTS_PCPL_SHIFT 21

Definition at line 168 of file intel_ips.c.

#define HTS_PCTD_DIS (1<<9)

Definition at line 177 of file intel_ips.c.

#define HTS_PP_BAL 2

Definition at line 175 of file intel_ips.c.

#define HTS_PP_DEF 0

Definition at line 173 of file intel_ips.c.

#define HTS_PP_GFX 3

Definition at line 176 of file intel_ips.c.

#define HTS_PP_MASK (0x00000c00)

Definition at line 171 of file intel_ips.c.

#define HTS_PP_PROC 1

Definition at line 174 of file intel_ips.c.

#define HTS_PP_SHIFT 10

Definition at line 172 of file intel_ips.c.

#define HTS_PTL_MASK (0x000000fe)

Definition at line 179 of file intel_ips.c.

#define HTS_PTL_SHIFT 1

Definition at line 180 of file intel_ips.c.

#define IA32_MISC_ENABLE 0x1a0

Definition at line 92 of file intel_ips.c.

#define IA32_MISC_TURBO_EN (1ULL<<38)

Definition at line 93 of file intel_ips.c.

#define IA32_PERF_CTL 0x199

Definition at line 105 of file intel_ips.c.

#define IA32_PERF_TURBO_DIS (1ULL<<32)

Definition at line 106 of file intel_ips.c.

#define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)

Definition at line 257 of file intel_ips.c.

#define ITV_MCH_TEMP_MASK 0x0000ff00

Definition at line 238 of file intel_ips.c.

#define ITV_MCH_TEMP_SHIFT (8)

Definition at line 239 of file intel_ips.c.

#define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */

Definition at line 236 of file intel_ips.c.

#define ITV_ME_SEQNO_SHIFT (16)

Definition at line 237 of file intel_ips.c.

#define ITV_PCH_TEMP_MASK 0x000000ff

Definition at line 240 of file intel_ips.c.

#define MGTA_OFFSET_MASK (0x00ff)

Definition at line 135 of file intel_ips.c.

#define MGTA_SLOPE_MASK (0xff00)

Definition at line 133 of file intel_ips.c.

#define MGTA_SLOPE_SHIFT 8

Definition at line 134 of file intel_ips.c.

#define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32

Definition at line 83 of file intel_ips.c.

#define PLATFORM_INFO 0xce

Definition at line 88 of file intel_ips.c.

#define PLATFORM_RATIO (1<<28)

Definition at line 90 of file intel_ips.c.

#define PLATFORM_TDP (1<<29)

Definition at line 89 of file intel_ips.c.

#define PSC_NTG (1<<0) /* No GFX turbo support */

Definition at line 152 of file intel_ips.c.

#define PSC_NTPC (1<<1) /* No CPU turbo support */

Definition at line 153 of file intel_ips.c.

#define PSC_PP_DEF (0<<2) /* Perf policy up to driver */

Definition at line 154 of file intel_ips.c.

#define PSP_PBRT (1<<4) /* BIOS run time support */

Definition at line 158 of file intel_ips.c.

#define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */

Definition at line 156 of file intel_ips.c.

#define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */

Definition at line 157 of file intel_ips.c.

#define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */

Definition at line 155 of file intel_ips.c.

#define PTA_OFFSET_MASK (0x00ff)

Definition at line 131 of file intel_ips.c.

#define PTA_SLOPE_MASK (0xff00)

Definition at line 129 of file intel_ips.c.

#define PTA_SLOPE_SHIFT 8

Definition at line 130 of file intel_ips.c.

#define PTV_MASK 0x00ff

Definition at line 199 of file intel_ips.c.

#define SEC_ACK (1<<0)

Definition at line 228 of file intel_ips.c.

#define STS_GPL_MASK (0x001ff000)

Definition at line 214 of file intel_ips.c.

#define STS_GPL_SHIFT 12

Definition at line 215 of file intel_ips.c.

#define STS_GTD_DIS (1<<8)

Definition at line 223 of file intel_ips.c.

#define STS_NVV (1<<0)

Definition at line 226 of file intel_ips.c.

#define STS_PCPL_MASK (0x7fe00000)

Definition at line 212 of file intel_ips.c.

#define STS_PCPL_SHIFT 21

Definition at line 213 of file intel_ips.c.

#define STS_PCTD_DIS (1<<9)

Definition at line 222 of file intel_ips.c.

#define STS_PP_BAL 2

Definition at line 220 of file intel_ips.c.

#define STS_PP_DEF 0

Definition at line 218 of file intel_ips.c.

#define STS_PP_GFX 3

Definition at line 221 of file intel_ips.c.

#define STS_PP_MASK (0x00000c00)

Definition at line 216 of file intel_ips.c.

#define STS_PP_PROC 1

Definition at line 219 of file intel_ips.c.

#define STS_PP_SHIFT 10

Definition at line 217 of file intel_ips.c.

#define STS_PPL_MASK (0x0003ff00)

Definition at line 231 of file intel_ips.c.

#define STS_PPL_SHIFT 16

Definition at line 232 of file intel_ips.c.

#define STS_PTL_MASK (0x000000fe)

Definition at line 224 of file intel_ips.c.

#define STS_PTL_SHIFT 1

Definition at line 225 of file intel_ips.c.

#define TEN_UPDATE_EN 1

Definition at line 150 of file intel_ips.c.

#define THM_AE 0x3f

Definition at line 165 of file intel_ips.c.

#define THM_ATR 0x84

Definition at line 209 of file intel_ips.c.

#define THM_CEC 0x34 /* undocumented power accumulator in joules */

Definition at line 164 of file intel_ips.c.

#define THM_CFG_TBAR 0x10

Definition at line 111 of file intel_ips.c.

#define THM_CFG_TBAR_HI 0x14

Definition at line 112 of file intel_ips.c.

#define THM_CTA 0x12

Definition at line 127 of file intel_ips.c.

#define THM_CTV1 0x30

Definition at line 159 of file intel_ips.c.

#define THM_CTV2 0x32

Definition at line 163 of file intel_ips.c.

#define THM_DTV 0xb0

Definition at line 234 of file intel_ips.c.

#define THM_HTS 0x50 /* 32 bits */

Definition at line 166 of file intel_ips.c.

#define THM_HTSHI 0x54 /* 16 bits */

Definition at line 182 of file intel_ips.c.

#define THM_ITV 0xd8

Definition at line 235 of file intel_ips.c.

#define THM_MGTA 0x16

Definition at line 132 of file intel_ips.c.

#define THM_MGTV 0x58

Definition at line 195 of file intel_ips.c.

#define THM_MMGPC 0x64

Definition at line 200 of file intel_ips.c.

#define THM_MPCPC 0x68

Definition at line 202 of file intel_ips.c.

#define THM_MPPC 0x66

Definition at line 201 of file intel_ips.c.

#define THM_PPEC 0x10

Definition at line 126 of file intel_ips.c.

#define THM_PSC 0x24

Definition at line 151 of file intel_ips.c.

#define THM_PTA 0x14

Definition at line 128 of file intel_ips.c.

#define THM_PTL 0x56

Definition at line 194 of file intel_ips.c.

#define THM_PTV 0x60

Definition at line 198 of file intel_ips.c.

#define thm_readb ( off ) readb(ips->regmap + (off))

Definition at line 242 of file intel_ips.c.

#define thm_readl ( off ) readl(ips->regmap + (off))

Definition at line 244 of file intel_ips.c.

#define thm_readq ( off ) readq(ips->regmap + (off))

Definition at line 245 of file intel_ips.c.

#define thm_readw ( off ) readw(ips->regmap + (off))

Definition at line 243 of file intel_ips.c.

#define THM_SEC 0x9c

Definition at line 227 of file intel_ips.c.

#define THM_STS 0x98

Definition at line 211 of file intel_ips.c.

#define THM_TC1 0xa8

Definition at line 230 of file intel_ips.c.

#define THM_TC2 0xac

Definition at line 233 of file intel_ips.c.

#define THM_TC3 0xa4

Definition at line 229 of file intel_ips.c.

#define THM_TEN 0x21

Definition at line 149 of file intel_ips.c.

#define THM_TES 0x20

Definition at line 148 of file intel_ips.c.

#define THM_TOF 0x87

Definition at line 210 of file intel_ips.c.

#define THM_TRC 0x1a

Definition at line 136 of file intel_ips.c.

#define THM_TSCO 0x08

Definition at line 120 of file intel_ips.c.

#define THM_TSE 0x01

Definition at line 115 of file intel_ips.c.

#define THM_TSES 0x0c

Definition at line 121 of file intel_ips.c.

#define THM_TSGPEN 0x0d

Definition at line 122 of file intel_ips.c.

#define THM_TSIU 0x00

Definition at line 114 of file intel_ips.c.

#define THM_TSLOCK 0x83

Definition at line 208 of file intel_ips.c.

#define THM_TSPC 0x0e

Definition at line 125 of file intel_ips.c.

#define THM_TSPIEN 0x82

Definition at line 203 of file intel_ips.c.

#define THM_TSS 0x02

Definition at line 117 of file intel_ips.c.

#define THM_TSTR 0x03

Definition at line 118 of file intel_ips.c.

#define THM_TSTTP 0x04

Definition at line 119 of file intel_ips.c.

#define thm_writeb	(	off,
		val
	)	writeb((val), ips->regmap + (off))

Definition at line 247 of file intel_ips.c.

#define thm_writel	(	off,
		val
	)	writel((val), ips->regmap + (off))

Definition at line 249 of file intel_ips.c.

#define thm_writew	(	off,
		val
	)	writew((val), ips->regmap + (off))

Definition at line 248 of file intel_ips.c.

#define TRC_C6_WAR (1<<8)

Definition at line 139 of file intel_ips.c.

#define TRC_CORE1_EN (1<<7)

Definition at line 140 of file intel_ips.c.

#define TRC_CORE2_EN (1<<15)

Definition at line 137 of file intel_ips.c.

#define TRC_CORE_PWR (1<<6)

Definition at line 141 of file intel_ips.c.

#define TRC_DIMM1 (1<<0)

Definition at line 147 of file intel_ips.c.

#define TRC_DIMM2 (1<<1)

Definition at line 146 of file intel_ips.c.

#define TRC_DIMM3 (1<<2)

Definition at line 145 of file intel_ips.c.

#define TRC_DIMM4 (1<<3)

Definition at line 144 of file intel_ips.c.

#define TRC_MCH_EN (1<<4)

Definition at line 143 of file intel_ips.c.

#define TRC_PCH_EN (1<<5)

Definition at line 142 of file intel_ips.c.

#define TRC_THM_EN (1<<12)

Definition at line 138 of file intel_ips.c.

#define TSE_EN 0xb8

Definition at line 116 of file intel_ips.c.

#define TSGPEN_CRIT_LOHI (1<<2)

Definition at line 124 of file intel_ips.c.

#define TSGPEN_HOT_LOHI (1<<1)

Definition at line 123 of file intel_ips.c.

#define TSPIEN_AUX2_LOHI (1<<3)

Definition at line 207 of file intel_ips.c.

#define TSPIEN_AUX_LOHI (1<<0)

Definition at line 204 of file intel_ips.c.

#define TSPIEN_CRIT_LOHI (1<<2)

Definition at line 206 of file intel_ips.c.

#define TSPIEN_HOT_LOHI (1<<1)

Definition at line 205 of file intel_ips.c.

#define TURBO_POWER_CURRENT_LIMIT 0x1ac

Definition at line 95 of file intel_ips.c.

#define TURBO_TDC_MASK (0x000000007fff0000UL)

Definition at line 97 of file intel_ips.c.

#define TURBO_TDC_OVR_EN (1UL<<31)

Definition at line 96 of file intel_ips.c.

#define TURBO_TDC_SHIFT (16)

Definition at line 98 of file intel_ips.c.

#define TURBO_TDP_MASK (0x0000000000003fffUL)

Definition at line 100 of file intel_ips.c.

#define TURBO_TDP_OVR_EN (1UL<<15)

Definition at line 99 of file intel_ips.c.

#define TV_MASK 0x000000000000ff00

Definition at line 196 of file intel_ips.c.

#define TV_SHIFT 8

Definition at line 197 of file intel_ips.c.

Function Documentation

EXPORT_SYMBOL_GPL ( ips_link_to_i915_driver )

void ips_link_to_i915_driver ( void )

Definition at line 1471 of file intel_ips.c.

MODULE_AUTHOR ( "Jesse Barnes <[email protected]>" )

MODULE_DESCRIPTION ( "Intelligent Power Sharing Driver" )

MODULE_DEVICE_TABLE	(	pci	,
		ips_id_table
	)

module_exit ( ips_exit )

module_init ( ips_init )

MODULE_LICENSE ( "GPL" )

Variable Documentation

struct ips_mcp_limits ips_lv_limits

Initial value:

= {
    .mcp_power_limit = 25000,
    .core_power_limit = 21000,
    .mch_power_limit = 13000,
    .core_temp_limit = 95,
    .mch_temp_limit = 90
}

Definition at line 280 of file intel_ips.c.

struct ips_mcp_limits ips_sv_limits

Initial value:

= {
    .mcp_power_limit = 35000,
    .core_power_limit = 29000,
    .mch_power_limit = 20000,
    .core_temp_limit = 95,
    .mch_temp_limit = 90
}

Definition at line 272 of file intel_ips.c.

struct ips_mcp_limits ips_ulv_limits

Initial value:

= {
    .mcp_power_limit = 18000,
    .core_power_limit = 14000,
    .mch_power_limit = 11000,
    .core_temp_limit = 95,
    .mch_temp_limit = 90
}

Definition at line 288 of file intel_ips.c.

Data Structures

Macros

Functions

Variables

Macro Definition Documentation

Function Documentation

Variable Documentation