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ixgbe_type.h
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1 /*******************************************************************************
2 
3  Intel 10 Gigabit PCI Express Linux driver
4  Copyright(c) 1999 - 2012 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
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12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
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25 
26 *******************************************************************************/
27 
28 #ifndef _IXGBE_TYPE_H_
29 #define _IXGBE_TYPE_H_
30 
31 #include <linux/types.h>
32 #include <linux/mdio.h>
33 #include <linux/netdevice.h>
34 
35 /* Device IDs */
36 #define IXGBE_DEV_ID_82598 0x10B6
37 #define IXGBE_DEV_ID_82598_BX 0x1508
38 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
39 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
40 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
41 #define IXGBE_DEV_ID_82598AT 0x10C8
42 #define IXGBE_DEV_ID_82598AT2 0x150B
43 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
44 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
45 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
46 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
47 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
48 #define IXGBE_DEV_ID_82599_KX4 0x10F7
49 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
50 #define IXGBE_DEV_ID_82599_KR 0x1517
51 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
52 #define IXGBE_DEV_ID_82599_CX4 0x10F9
53 #define IXGBE_DEV_ID_82599_SFP 0x10FB
54 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a
55 #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
56 #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
57 #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
58 #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
59 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507
60 #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
61 #define IXGBE_DEV_ID_82599EN_SFP 0x1557
62 #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
63 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
64 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
65 #define IXGBE_DEV_ID_82599_LS 0x154F
66 #define IXGBE_DEV_ID_X540T 0x1528
67 #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
68 #define IXGBE_DEV_ID_X540T1 0x1560
69 
70 /* VF Device IDs */
71 #define IXGBE_DEV_ID_82599_VF 0x10ED
72 #define IXGBE_DEV_ID_X540_VF 0x1515
73 
74 /* General Registers */
75 #define IXGBE_CTRL 0x00000
76 #define IXGBE_STATUS 0x00008
77 #define IXGBE_CTRL_EXT 0x00018
78 #define IXGBE_ESDP 0x00020
79 #define IXGBE_EODSDP 0x00028
80 #define IXGBE_I2CCTL 0x00028
81 #define IXGBE_LEDCTL 0x00200
82 #define IXGBE_FRTIMER 0x00048
83 #define IXGBE_TCPTIMER 0x0004C
84 #define IXGBE_CORESPARE 0x00600
85 #define IXGBE_EXVET 0x05078
86 
87 /* NVM Registers */
88 #define IXGBE_EEC 0x10010
89 #define IXGBE_EERD 0x10014
90 #define IXGBE_EEWR 0x10018
91 #define IXGBE_FLA 0x1001C
92 #define IXGBE_EEMNGCTL 0x10110
93 #define IXGBE_EEMNGDATA 0x10114
94 #define IXGBE_FLMNGCTL 0x10118
95 #define IXGBE_FLMNGDATA 0x1011C
96 #define IXGBE_FLMNGCNT 0x10120
97 #define IXGBE_FLOP 0x1013C
98 #define IXGBE_GRC 0x10200
99 
100 /* General Receive Control */
101 #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
102 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
103 
104 #define IXGBE_VPDDIAG0 0x10204
105 #define IXGBE_VPDDIAG1 0x10208
106 
107 /* I2CCTL Bit Masks */
108 #define IXGBE_I2C_CLK_IN 0x00000001
109 #define IXGBE_I2C_CLK_OUT 0x00000002
110 #define IXGBE_I2C_DATA_IN 0x00000004
111 #define IXGBE_I2C_DATA_OUT 0x00000008
112 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
113 
114 #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
115 #define IXGBE_EMC_INTERNAL_DATA 0x00
116 #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
117 #define IXGBE_EMC_DIODE1_DATA 0x01
118 #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
119 #define IXGBE_EMC_DIODE2_DATA 0x23
120 #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
121 
122 #define IXGBE_MAX_SENSORS 3
123 
124 struct ixgbe_thermal_diode_data {
125  u8 location;
126  u8 temp;
127  u8 caution_thresh;
128  u8 max_op_thresh;
129 };
130 
131 struct ixgbe_thermal_sensor_data {
132  struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
133 };
134 
135 /* Interrupt Registers */
136 #define IXGBE_EICR 0x00800
137 #define IXGBE_EICS 0x00808
138 #define IXGBE_EIMS 0x00880
139 #define IXGBE_EIMC 0x00888
140 #define IXGBE_EIAC 0x00810
141 #define IXGBE_EIAM 0x00890
142 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
143 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
144 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
145 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
146 /*
147  * 82598 EITR is 16 bits but set the limits based on the max
148  * supported by all ixgbe hardware. 82599 EITR is only 12 bits,
149  * with the lower 3 always zero.
150  */
151 #define IXGBE_MAX_INT_RATE 488281
152 #define IXGBE_MIN_INT_RATE 956
153 #define IXGBE_MAX_EITR 0x00000FF8
154 #define IXGBE_MIN_EITR 8
155 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
156  (0x012300 + (((_i) - 24) * 4)))
157 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
158 #define IXGBE_EITR_LLI_MOD 0x00008000
159 #define IXGBE_EITR_CNT_WDIS 0x80000000
160 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
161 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
162 #define IXGBE_EITRSEL 0x00894
163 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
164 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
165 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
166 #define IXGBE_GPIE 0x00898
167 
168 /* Flow Control Registers */
169 #define IXGBE_FCADBUL 0x03210
170 #define IXGBE_FCADBUH 0x03214
171 #define IXGBE_FCAMACL 0x04328
172 #define IXGBE_FCAMACH 0x0432C
173 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
174 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
175 #define IXGBE_PFCTOP 0x03008
176 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
177 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
178 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
179 #define IXGBE_FCRTV 0x032A0
180 #define IXGBE_FCCFG 0x03D00
181 #define IXGBE_TFCS 0x0CE00
182 
183 /* Receive DMA Registers */
184 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
185  (0x0D000 + (((_i) - 64) * 0x40)))
186 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
187  (0x0D004 + (((_i) - 64) * 0x40)))
188 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
189  (0x0D008 + (((_i) - 64) * 0x40)))
190 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
191  (0x0D010 + (((_i) - 64) * 0x40)))
192 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
193  (0x0D018 + (((_i) - 64) * 0x40)))
194 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
195  (0x0D028 + (((_i) - 64) * 0x40)))
196 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
197  (0x0D02C + (((_i) - 64) * 0x40)))
198 #define IXGBE_RSCDBU 0x03028
199 #define IXGBE_RDDCC 0x02F20
200 #define IXGBE_RXMEMWRAP 0x03190
201 #define IXGBE_STARCTRL 0x03024
202 /*
203  * Split and Replication Receive Control Registers
204  * 00-15 : 0x02100 + n*4
205  * 16-64 : 0x01014 + n*0x40
206  * 64-127: 0x0D014 + (n-64)*0x40
207  */
208 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
209  (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
210  (0x0D014 + (((_i) - 64) * 0x40))))
211 /*
212  * Rx DCA Control Register:
213  * 00-15 : 0x02200 + n*4
214  * 16-64 : 0x0100C + n*0x40
215  * 64-127: 0x0D00C + (n-64)*0x40
216  */
217 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
218  (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
219  (0x0D00C + (((_i) - 64) * 0x40))))
220 #define IXGBE_RDRXCTL 0x02F00
221 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
222  /* 8 of these 0x03C00 - 0x03C1C */
223 #define IXGBE_RXCTRL 0x03000
224 #define IXGBE_DROPEN 0x03D04
225 #define IXGBE_RXPBSIZE_SHIFT 10
226 
227 /* Receive Registers */
228 #define IXGBE_RXCSUM 0x05000
229 #define IXGBE_RFCTL 0x05008
230 #define IXGBE_DRECCCTL 0x02F08
231 #define IXGBE_DRECCCTL_DISABLE 0
232 /* Multicast Table Array - 128 entries */
233 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
234 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
235  (0x0A200 + ((_i) * 8)))
236 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
237  (0x0A204 + ((_i) * 8)))
238 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
239 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
240 /* Packet split receive type */
241 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
242  (0x0EA00 + ((_i) * 4)))
243 /* array of 4096 1-bit vlan filters */
244 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
245 /*array of 4096 4-bit vlan vmdq indices */
246 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
247 #define IXGBE_FCTRL 0x05080
248 #define IXGBE_VLNCTRL 0x05088
249 #define IXGBE_MCSTCTRL 0x05090
250 #define IXGBE_MRQC 0x05818
251 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
252 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
253 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
254 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
255 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
256 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
257 #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
258 #define IXGBE_RQTC 0x0EC70
259 #define IXGBE_MTQC 0x08120
260 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
261 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
262 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
263 #define IXGBE_VT_CTL 0x051B0
264 #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */
265 #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
266 #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */
267 #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */
268 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
269 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
270 #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
271 #define IXGBE_QDE 0x2F04
272 #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */
273 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
274 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
275 #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
276 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
277 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
278 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
279 #define IXGBE_RXFECCERR0 0x051B8
280 #define IXGBE_LLITHRESH 0x0EC90
281 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
282 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
283 #define IXGBE_IMIRVP 0x05AC0
284 #define IXGBE_VMD_CTL 0x0581C
285 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
286 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
287 
288 /* Flow Director registers */
289 #define IXGBE_FDIRCTRL 0x0EE00
290 #define IXGBE_FDIRHKEY 0x0EE68
291 #define IXGBE_FDIRSKEY 0x0EE6C
292 #define IXGBE_FDIRDIP4M 0x0EE3C
293 #define IXGBE_FDIRSIP4M 0x0EE40
294 #define IXGBE_FDIRTCPM 0x0EE44
295 #define IXGBE_FDIRUDPM 0x0EE48
296 #define IXGBE_FDIRIP6M 0x0EE74
297 #define IXGBE_FDIRM 0x0EE70
298 
299 /* Flow Director Stats registers */
300 #define IXGBE_FDIRFREE 0x0EE38
301 #define IXGBE_FDIRLEN 0x0EE4C
302 #define IXGBE_FDIRUSTAT 0x0EE50
303 #define IXGBE_FDIRFSTAT 0x0EE54
304 #define IXGBE_FDIRMATCH 0x0EE58
305 #define IXGBE_FDIRMISS 0x0EE5C
306 
307 /* Flow Director Programming registers */
308 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
309 #define IXGBE_FDIRIPSA 0x0EE18
310 #define IXGBE_FDIRIPDA 0x0EE1C
311 #define IXGBE_FDIRPORT 0x0EE20
312 #define IXGBE_FDIRVLAN 0x0EE24
313 #define IXGBE_FDIRHASH 0x0EE28
314 #define IXGBE_FDIRCMD 0x0EE2C
315 
316 /* Transmit DMA registers */
317 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
318 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
319 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
320 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
321 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
322 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
323 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
324 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
325 #define IXGBE_DTXCTL 0x07E00
326 
327 #define IXGBE_DMATXCTL 0x04A80
328 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
329 #define IXGBE_PFDTXGSWC 0x08220
330 #define IXGBE_DTXMXSZRQ 0x08100
331 #define IXGBE_DTXTCPFLGL 0x04A88
332 #define IXGBE_DTXTCPFLGH 0x04A8C
333 #define IXGBE_LBDRPEN 0x0CA00
334 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
335 
336 #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
337 #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
338 #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
339 #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
340 
341 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
342 
343 /* Anti-spoofing defines */
344 #define IXGBE_SPOOF_MACAS_MASK 0xFF
345 #define IXGBE_SPOOF_VLANAS_MASK 0xFF00
346 #define IXGBE_SPOOF_VLANAS_SHIFT 8
347 #define IXGBE_PFVFSPOOF_REG_COUNT 8
348 
349 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
350 /* Tx DCA Control register : 128 of these (0-127) */
351 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
352 #define IXGBE_TIPG 0x0CB00
353 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
354 #define IXGBE_MNGTXMAP 0x0CD10
355 #define IXGBE_TIPG_FIBER_DEFAULT 3
356 #define IXGBE_TXPBSIZE_SHIFT 10
357 
358 /* Wake up registers */
359 #define IXGBE_WUC 0x05800
360 #define IXGBE_WUFC 0x05808
361 #define IXGBE_WUS 0x05810
362 #define IXGBE_IPAV 0x05838
363 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
364 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
365 
366 #define IXGBE_WUPL 0x05900
367 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
368 #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
369 #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host
370  * Filter Table */
371 
372 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
373 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
374 
375 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
376 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
377 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
378 #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
379 
380 /* Definitions for power management and wakeup registers */
381 /* Wake Up Control */
382 #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
383 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
384 #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
385 
386 /* Wake Up Filter Control */
387 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
388 #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
389 #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
390 #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
391 #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
392 #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
393 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
394 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
395 #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
396 
397 #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
398 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
399 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
400 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
401 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
402 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
403 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
404 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
405 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
406 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
407 #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
408 
409 /* Wake Up Status */
410 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
411 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG
412 #define IXGBE_WUS_EX IXGBE_WUFC_EX
413 #define IXGBE_WUS_MC IXGBE_WUFC_MC
414 #define IXGBE_WUS_BC IXGBE_WUFC_BC
415 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP
416 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
417 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
418 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG
419 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
420 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
421 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
422 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
423 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
424 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
425 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
426 
427 /* Wake Up Packet Length */
428 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
429 
430 /* DCB registers */
431 #define MAX_TRAFFIC_CLASS 8
432 #define X540_TRAFFIC_CLASS 4
433 #define IXGBE_RMCS 0x03D00
434 #define IXGBE_DPMCS 0x07F40
435 #define IXGBE_PDPMCS 0x0CD00
436 #define IXGBE_RUPPBMR 0x050A0
437 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
438 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
439 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
440 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
441 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
442 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
443 
444 
445 /* Security Control Registers */
446 #define IXGBE_SECTXCTRL 0x08800
447 #define IXGBE_SECTXSTAT 0x08804
448 #define IXGBE_SECTXBUFFAF 0x08808
449 #define IXGBE_SECTXMINIFG 0x08810
450 #define IXGBE_SECRXCTRL 0x08D00
451 #define IXGBE_SECRXSTAT 0x08D04
452 
453 /* Security Bit Fields and Masks */
454 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
455 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002
456 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
457 
458 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
459 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
460 
461 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
462 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002
463 
464 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
465 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
466 
467 /* LinkSec (MacSec) Registers */
468 #define IXGBE_LSECTXCAP 0x08A00
469 #define IXGBE_LSECRXCAP 0x08F00
470 #define IXGBE_LSECTXCTRL 0x08A04
471 #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
472 #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
473 #define IXGBE_LSECTXSA 0x08A10
474 #define IXGBE_LSECTXPN0 0x08A14
475 #define IXGBE_LSECTXPN1 0x08A18
476 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
477 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
478 #define IXGBE_LSECRXCTRL 0x08F04
479 #define IXGBE_LSECRXSCL 0x08F08
480 #define IXGBE_LSECRXSCH 0x08F0C
481 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
482 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
483 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
484 #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
485 #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
486 #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
487 #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
488 #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
489 #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
490 #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
491 #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
492 #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
493 #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
494 #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
495 #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
496 #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
497 #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
498 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
499 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
500 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
501 #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
502 #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
503 
504 /* LinkSec (MacSec) Bit Fields and Masks */
505 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
506 #define IXGBE_LSECTXCAP_SUM_SHIFT 16
507 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
508 #define IXGBE_LSECRXCAP_SUM_SHIFT 16
509 
510 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
511 #define IXGBE_LSECTXCTRL_DISABLE 0x0
512 #define IXGBE_LSECTXCTRL_AUTH 0x1
513 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
514 #define IXGBE_LSECTXCTRL_AISCI 0x00000020
515 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
516 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
517 
518 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
519 #define IXGBE_LSECRXCTRL_EN_SHIFT 2
520 #define IXGBE_LSECRXCTRL_DISABLE 0x0
521 #define IXGBE_LSECRXCTRL_CHECK 0x1
522 #define IXGBE_LSECRXCTRL_STRICT 0x2
523 #define IXGBE_LSECRXCTRL_DROP 0x3
524 #define IXGBE_LSECRXCTRL_PLSH 0x00000040
525 #define IXGBE_LSECRXCTRL_RP 0x00000080
526 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
527 
528 /* IpSec Registers */
529 #define IXGBE_IPSTXIDX 0x08900
530 #define IXGBE_IPSTXSALT 0x08904
531 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
532 #define IXGBE_IPSRXIDX 0x08E00
533 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
534 #define IXGBE_IPSRXSPI 0x08E14
535 #define IXGBE_IPSRXIPIDX 0x08E18
536 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
537 #define IXGBE_IPSRXSALT 0x08E2C
538 #define IXGBE_IPSRXMOD 0x08E30
539 
540 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
541 
542 /* DCB registers */
543 #define IXGBE_RTRPCS 0x02430
544 #define IXGBE_RTTDCS 0x04900
545 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
546 #define IXGBE_RTTPCS 0x0CD00
547 #define IXGBE_RTRUP2TC 0x03020
548 #define IXGBE_RTTUP2TC 0x0C800
549 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
550 #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
551 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
552 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
553 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
554 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
555 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
556 #define IXGBE_RTTDQSEL 0x04904
557 #define IXGBE_RTTDT1C 0x04908
558 #define IXGBE_RTTDT1S 0x0490C
559 #define IXGBE_RTTDTECC 0x04990
560 #define IXGBE_RTTDTECC_NO_BCN 0x00000100
561 #define IXGBE_RTTBCNRC 0x04984
562 #define IXGBE_RTTBCNRC_RS_ENA 0x80000000
563 #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
564 #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
565 #define IXGBE_RTTBCNRC_RF_INT_MASK \
566  (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
567 #define IXGBE_RTTBCNRM 0x04980
568 
569 /* FCoE DMA Context Registers */
570 #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
571 #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
572 #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
573 #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
574 #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
575 #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
576 #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
577 #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
578 #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
579 #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
580 #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
581 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
582 #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
583 #define IXGBE_FCBUFF_OFFSET_SHIFT 16
584 #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
585 #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
586 #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
587 #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
588 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
589 
590 /* FCoE SOF/EOF */
591 #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
592 #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
593 #define IXGBE_REOFF 0x05158 /* Rx FC EOF */
594 #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
595 /* FCoE Filter Context Registers */
596 #define IXGBE_FCFLT 0x05108 /* FC FLT Context */
597 #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
598 #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
599 #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
600 #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
601 #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
602 #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
603 #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
604 #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
605 #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
606 /* FCoE Receive Control */
607 #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
608 #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
609 #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
610 #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
611 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
612 #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
613 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
614 #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
615 #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
616 #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
617 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
618 /* FCoE Redirection */
619 #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
620 #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
621 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
622 #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
623 #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
624 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
625 
626 /* Stats registers */
627 #define IXGBE_CRCERRS 0x04000
628 #define IXGBE_ILLERRC 0x04004
629 #define IXGBE_ERRBC 0x04008
630 #define IXGBE_MSPDC 0x04010
631 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
632 #define IXGBE_MLFC 0x04034
633 #define IXGBE_MRFC 0x04038
634 #define IXGBE_RLEC 0x04040
635 #define IXGBE_LXONTXC 0x03F60
636 #define IXGBE_LXONRXC 0x0CF60
637 #define IXGBE_LXOFFTXC 0x03F68
638 #define IXGBE_LXOFFRXC 0x0CF68
639 #define IXGBE_LXONRXCNT 0x041A4
640 #define IXGBE_LXOFFRXCNT 0x041A8
641 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
642 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
643 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
644 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
645 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
646 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
647 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
648 #define IXGBE_PRC64 0x0405C
649 #define IXGBE_PRC127 0x04060
650 #define IXGBE_PRC255 0x04064
651 #define IXGBE_PRC511 0x04068
652 #define IXGBE_PRC1023 0x0406C
653 #define IXGBE_PRC1522 0x04070
654 #define IXGBE_GPRC 0x04074
655 #define IXGBE_BPRC 0x04078
656 #define IXGBE_MPRC 0x0407C
657 #define IXGBE_GPTC 0x04080
658 #define IXGBE_GORCL 0x04088
659 #define IXGBE_GORCH 0x0408C
660 #define IXGBE_GOTCL 0x04090
661 #define IXGBE_GOTCH 0x04094
662 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
663 #define IXGBE_RUC 0x040A4
664 #define IXGBE_RFC 0x040A8
665 #define IXGBE_ROC 0x040AC
666 #define IXGBE_RJC 0x040B0
667 #define IXGBE_MNGPRC 0x040B4
668 #define IXGBE_MNGPDC 0x040B8
669 #define IXGBE_MNGPTC 0x0CF90
670 #define IXGBE_TORL 0x040C0
671 #define IXGBE_TORH 0x040C4
672 #define IXGBE_TPR 0x040D0
673 #define IXGBE_TPT 0x040D4
674 #define IXGBE_PTC64 0x040D8
675 #define IXGBE_PTC127 0x040DC
676 #define IXGBE_PTC255 0x040E0
677 #define IXGBE_PTC511 0x040E4
678 #define IXGBE_PTC1023 0x040E8
679 #define IXGBE_PTC1522 0x040EC
680 #define IXGBE_MPTC 0x040F0
681 #define IXGBE_BPTC 0x040F4
682 #define IXGBE_XEC 0x04120
683 #define IXGBE_SSVPC 0x08780
684 
685 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
686 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
687  (0x08600 + ((_i) * 4)))
688 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
689 
690 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
691 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
692 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
693 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
694 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
695 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
696 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
697 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
698 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
699 #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
700 #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
701 #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
702 #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
703 #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
704 #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
705 #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
706 #define IXGBE_O2BGPTC 0x041C4
707 #define IXGBE_O2BSPC 0x087B0
708 #define IXGBE_B2OSPC 0x041C0
709 #define IXGBE_B2OGPRC 0x02F90
710 #define IXGBE_PCRC8ECL 0x0E810
711 #define IXGBE_PCRC8ECH 0x0E811
712 #define IXGBE_PCRC8ECH_MASK 0x1F
713 #define IXGBE_LDPCECL 0x0E820
714 #define IXGBE_LDPCECH 0x0E821
715 
716 /* Management */
717 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
718 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
719 #define IXGBE_MANC 0x05820
720 #define IXGBE_MFVAL 0x05824
721 #define IXGBE_MANC2H 0x05860
722 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
723 #define IXGBE_MIPAF 0x058B0
724 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
725 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
726 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
727 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
728 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
729 #define IXGBE_LSWFW 0x15014
730 
731 /* ARC Subsystem registers */
732 #define IXGBE_HICR 0x15F00
733 #define IXGBE_FWSTS 0x15F0C
734 #define IXGBE_HSMC0R 0x15F04
735 #define IXGBE_HSMC1R 0x15F08
736 #define IXGBE_SWSR 0x15F10
737 #define IXGBE_HFDR 0x15FE8
738 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
739 
740 #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */
741 /* Driver sets this bit when done to put command in RAM */
742 #define IXGBE_HICR_C 0x02
743 #define IXGBE_HICR_SV 0x04 /* Status Validity */
744 #define IXGBE_HICR_FW_RESET_ENABLE 0x40
745 #define IXGBE_HICR_FW_RESET 0x80
746 
747 /* PCI-E registers */
748 #define IXGBE_GCR 0x11000
749 #define IXGBE_GTV 0x11004
750 #define IXGBE_FUNCTAG 0x11008
751 #define IXGBE_GLT 0x1100C
752 #define IXGBE_GSCL_1 0x11010
753 #define IXGBE_GSCL_2 0x11014
754 #define IXGBE_GSCL_3 0x11018
755 #define IXGBE_GSCL_4 0x1101C
756 #define IXGBE_GSCN_0 0x11020
757 #define IXGBE_GSCN_1 0x11024
758 #define IXGBE_GSCN_2 0x11028
759 #define IXGBE_GSCN_3 0x1102C
760 #define IXGBE_FACTPS 0x10150
761 #define IXGBE_PCIEANACTL 0x11040
762 #define IXGBE_SWSM 0x10140
763 #define IXGBE_FWSM 0x10148
764 #define IXGBE_GSSR 0x10160
765 #define IXGBE_MREVID 0x11064
766 #define IXGBE_DCA_ID 0x11070
767 #define IXGBE_DCA_CTRL 0x11074
768 #define IXGBE_SWFW_SYNC IXGBE_GSSR
769 
770 /* PCIe registers 82599-specific */
771 #define IXGBE_GCR_EXT 0x11050
772 #define IXGBE_GSCL_5_82599 0x11030
773 #define IXGBE_GSCL_6_82599 0x11034
774 #define IXGBE_GSCL_7_82599 0x11038
775 #define IXGBE_GSCL_8_82599 0x1103C
776 #define IXGBE_PHYADR_82599 0x11040
777 #define IXGBE_PHYDAT_82599 0x11044
778 #define IXGBE_PHYCTL_82599 0x11048
779 #define IXGBE_PBACLR_82599 0x11068
780 #define IXGBE_CIAA_82599 0x11088
781 #define IXGBE_CIAD_82599 0x1108C
782 #define IXGBE_PICAUSE 0x110B0
783 #define IXGBE_PIENA 0x110B8
784 #define IXGBE_CDQ_MBR_82599 0x110B4
785 #define IXGBE_PCIESPARE 0x110BC
786 #define IXGBE_MISC_REG_82599 0x110F0
787 #define IXGBE_ECC_CTRL_0_82599 0x11100
788 #define IXGBE_ECC_CTRL_1_82599 0x11104
789 #define IXGBE_ECC_STATUS_82599 0x110E0
790 #define IXGBE_BAR_CTRL_82599 0x110F4
791 
792 /* PCI Express Control */
793 #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
794 #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
795 #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
796 #define IXGBE_GCR_CAP_VER2 0x00040000
797 
798 #define IXGBE_GCR_EXT_MSIX_EN 0x80000000
799 #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
800 #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
801 #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
802 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
803 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
804  IXGBE_GCR_EXT_VT_MODE_64)
805 
806 /* Time Sync Registers */
807 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
808 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
809 #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
810 #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
811 #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
812 #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
813 #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
814 #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
815 #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
816 #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
817 #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
818 #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
819 #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
820 #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
821 #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
822 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
823 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
824 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
825 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
826 #define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */
827 #define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */
828 #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
829 #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
830 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
831 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
832 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
833 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
834 
835 /* Diagnostic Registers */
836 #define IXGBE_RDSTATCTL 0x02C20
837 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
838 #define IXGBE_RDHMPN 0x02F08
839 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
840 #define IXGBE_RDPROBE 0x02F20
841 #define IXGBE_RDMAM 0x02F30
842 #define IXGBE_RDMAD 0x02F34
843 #define IXGBE_TDSTATCTL 0x07C20
844 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
845 #define IXGBE_TDHMPN 0x07F08
846 #define IXGBE_TDHMPN2 0x082FC
847 #define IXGBE_TXDESCIC 0x082CC
848 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
849 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
850 #define IXGBE_TDPROBE 0x07F20
851 #define IXGBE_TXBUFCTRL 0x0C600
852 #define IXGBE_TXBUFDATA0 0x0C610
853 #define IXGBE_TXBUFDATA1 0x0C614
854 #define IXGBE_TXBUFDATA2 0x0C618
855 #define IXGBE_TXBUFDATA3 0x0C61C
856 #define IXGBE_RXBUFCTRL 0x03600
857 #define IXGBE_RXBUFDATA0 0x03610
858 #define IXGBE_RXBUFDATA1 0x03614
859 #define IXGBE_RXBUFDATA2 0x03618
860 #define IXGBE_RXBUFDATA3 0x0361C
861 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
862 #define IXGBE_RFVAL 0x050A4
863 #define IXGBE_MDFTC1 0x042B8
864 #define IXGBE_MDFTC2 0x042C0
865 #define IXGBE_MDFTFIFO1 0x042C4
866 #define IXGBE_MDFTFIFO2 0x042C8
867 #define IXGBE_MDFTS 0x042CC
868 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
869 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
870 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
871 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
872 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
873 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
874 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
875 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
876 #define IXGBE_PCIEECCCTL 0x1106C
877 #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
878 #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
879 #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
880 #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
881 #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
882 #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
883 #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
884 #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
885 #define IXGBE_PCIEECCCTL0 0x11100
886 #define IXGBE_PCIEECCCTL1 0x11104
887 #define IXGBE_RXDBUECC 0x03F70
888 #define IXGBE_TXDBUECC 0x0CF70
889 #define IXGBE_RXDBUEST 0x03F74
890 #define IXGBE_TXDBUEST 0x0CF74
891 #define IXGBE_PBTXECC 0x0C300
892 #define IXGBE_PBRXECC 0x03300
893 #define IXGBE_GHECCR 0x110B0
894 
895 /* MAC Registers */
896 #define IXGBE_PCS1GCFIG 0x04200
897 #define IXGBE_PCS1GLCTL 0x04208
898 #define IXGBE_PCS1GLSTA 0x0420C
899 #define IXGBE_PCS1GDBG0 0x04210
900 #define IXGBE_PCS1GDBG1 0x04214
901 #define IXGBE_PCS1GANA 0x04218
902 #define IXGBE_PCS1GANLP 0x0421C
903 #define IXGBE_PCS1GANNP 0x04220
904 #define IXGBE_PCS1GANLPNP 0x04224
905 #define IXGBE_HLREG0 0x04240
906 #define IXGBE_HLREG1 0x04244
907 #define IXGBE_PAP 0x04248
908 #define IXGBE_MACA 0x0424C
909 #define IXGBE_APAE 0x04250
910 #define IXGBE_ARD 0x04254
911 #define IXGBE_AIS 0x04258
912 #define IXGBE_MSCA 0x0425C
913 #define IXGBE_MSRWD 0x04260
914 #define IXGBE_MLADD 0x04264
915 #define IXGBE_MHADD 0x04268
916 #define IXGBE_MAXFRS 0x04268
917 #define IXGBE_TREG 0x0426C
918 #define IXGBE_PCSS1 0x04288
919 #define IXGBE_PCSS2 0x0428C
920 #define IXGBE_XPCSS 0x04290
921 #define IXGBE_MFLCN 0x04294
922 #define IXGBE_SERDESC 0x04298
923 #define IXGBE_MACS 0x0429C
924 #define IXGBE_AUTOC 0x042A0
925 #define IXGBE_LINKS 0x042A4
926 #define IXGBE_LINKS2 0x04324
927 #define IXGBE_AUTOC2 0x042A8
928 #define IXGBE_AUTOC3 0x042AC
929 #define IXGBE_ANLP1 0x042B0
930 #define IXGBE_ANLP2 0x042B4
931 #define IXGBE_MACC 0x04330
932 #define IXGBE_ATLASCTL 0x04800
933 #define IXGBE_MMNGC 0x042D0
934 #define IXGBE_ANLPNP1 0x042D4
935 #define IXGBE_ANLPNP2 0x042D8
936 #define IXGBE_KRPCSFC 0x042E0
937 #define IXGBE_KRPCSS 0x042E4
938 #define IXGBE_FECS1 0x042E8
939 #define IXGBE_FECS2 0x042EC
940 #define IXGBE_SMADARCTL 0x14F10
941 #define IXGBE_MPVC 0x04318
942 #define IXGBE_SGMIIC 0x04314
943 
944 /* Statistics Registers */
945 #define IXGBE_RXNFGPC 0x041B0
946 #define IXGBE_RXNFGBCL 0x041B4
947 #define IXGBE_RXNFGBCH 0x041B8
948 #define IXGBE_RXDGPC 0x02F50
949 #define IXGBE_RXDGBCL 0x02F54
950 #define IXGBE_RXDGBCH 0x02F58
951 #define IXGBE_RXDDGPC 0x02F5C
952 #define IXGBE_RXDDGBCL 0x02F60
953 #define IXGBE_RXDDGBCH 0x02F64
954 #define IXGBE_RXLPBKGPC 0x02F68
955 #define IXGBE_RXLPBKGBCL 0x02F6C
956 #define IXGBE_RXLPBKGBCH 0x02F70
957 #define IXGBE_RXDLPBKGPC 0x02F74
958 #define IXGBE_RXDLPBKGBCL 0x02F78
959 #define IXGBE_RXDLPBKGBCH 0x02F7C
960 #define IXGBE_TXDGPC 0x087A0
961 #define IXGBE_TXDGBCL 0x087A4
962 #define IXGBE_TXDGBCH 0x087A8
963 
964 #define IXGBE_RXDSTATCTRL 0x02F40
965 
966 /* Copper Pond 2 link timeout */
967 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
968 
969 /* Omer CORECTL */
970 #define IXGBE_CORECTL 0x014F00
971 /* BARCTRL */
972 #define IXGBE_BARCTRL 0x110F4
973 #define IXGBE_BARCTRL_FLSIZE 0x0700
974 #define IXGBE_BARCTRL_FLSIZE_SHIFT 8
975 #define IXGBE_BARCTRL_CSRSIZE 0x2000
976 
977 /* RSCCTL Bit Masks */
978 #define IXGBE_RSCCTL_RSCEN 0x01
979 #define IXGBE_RSCCTL_MAXDESC_1 0x00
980 #define IXGBE_RSCCTL_MAXDESC_4 0x04
981 #define IXGBE_RSCCTL_MAXDESC_8 0x08
982 #define IXGBE_RSCCTL_MAXDESC_16 0x0C
983 
984 /* RSCDBU Bit Masks */
985 #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
986 #define IXGBE_RSCDBU_RSCACKDIS 0x00000080
987 
988 /* RDRXCTL Bit Masks */
989 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
990 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
991 #define IXGBE_RDRXCTL_MVMEN 0x00000020
992 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
993 #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
994 #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
995 #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */
996 #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
997 #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
998 
999 /* RQTC Bit Masks and Shifts */
1000 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1001 #define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1002 #define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1003 #define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1004 #define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1005 #define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1006 #define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1007 #define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1008 #define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1009 
1010 /* PSRTYPE.RQPL Bit masks and shift */
1011 #define IXGBE_PSRTYPE_RQPL_MASK 0x7
1012 #define IXGBE_PSRTYPE_RQPL_SHIFT 29
1013 
1014 /* CTRL Bit Masks */
1015 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
1016 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
1017 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
1018 #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1019 
1020 /* FACTPS */
1021 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
1022 
1023 /* MHADD Bit Masks */
1024 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1025 #define IXGBE_MHADD_MFS_SHIFT 16
1026 
1027 /* Extended Device Control */
1028 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
1029 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
1030 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1031 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1032 
1033 /* Direct Cache Access (DCA) definitions */
1034 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
1035 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
1036 
1037 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
1038 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1039 
1040 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1041 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
1042 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1043 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
1044 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
1045 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
1046 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
1047 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
1048 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
1049 
1050 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1051 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
1052 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1053 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
1054 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
1055 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
1056 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
1057 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
1058 
1059 /* MSCA Bit Masks */
1060 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
1061 #define IXGBE_MSCA_NP_ADDR_SHIFT 0
1062 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
1063 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
1064 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
1065 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
1066 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
1067 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
1068 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
1069 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
1070 #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */
1071 #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/
1072 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
1073 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
1074 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
1075 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
1076 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
1077 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
1078 
1079 /* MSRWD bit masks */
1080 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
1081 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
1082 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
1083 #define IXGBE_MSRWD_READ_DATA_SHIFT 16
1084 
1085 /* Atlas registers */
1086 #define IXGBE_ATLAS_PDN_LPBK 0x24
1087 #define IXGBE_ATLAS_PDN_10G 0xB
1088 #define IXGBE_ATLAS_PDN_1G 0xC
1089 #define IXGBE_ATLAS_PDN_AN 0xD
1090 
1091 /* Atlas bit masks */
1092 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
1093 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
1094 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1095 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1096 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1097 
1098 /* Omer bit masks */
1099 #define IXGBE_CORECTL_WRITE_CMD 0x00010000
1100 
1101 /* MDIO definitions */
1102 
1103 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
1104 
1105 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
1106 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1107 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
1108 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1109 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1110 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1111 
1112 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1113 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1114 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1115 
1116 /* MII clause 22/28 definitions */
1117 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1118 #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
1119 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
1120 #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
1121 #define IXGBE_MII_AUTONEG_REG 0x0
1122 
1123 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1124 #define IXGBE_MAX_PHY_ADDR 32
1125 
1126 /* PHY IDs*/
1127 #define TN1010_PHY_ID 0x00A19410
1128 #define TNX_FW_REV 0xB
1129 #define X540_PHY_ID 0x01540200
1130 #define QT2022_PHY_ID 0x0043A400
1131 #define ATH_PHY_ID 0x03429050
1132 #define AQ_FW_REV 0x20
1133 
1134 /* PHY Types */
1135 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1136 
1137 /* Special PHY Init Routine */
1138 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1139 #define IXGBE_PHY_INIT_END_NL 0xFFFF
1140 #define IXGBE_CONTROL_MASK_NL 0xF000
1141 #define IXGBE_DATA_MASK_NL 0x0FFF
1142 #define IXGBE_CONTROL_SHIFT_NL 12
1143 #define IXGBE_DELAY_NL 0
1144 #define IXGBE_DATA_NL 1
1145 #define IXGBE_CONTROL_NL 0x000F
1146 #define IXGBE_CONTROL_EOL_NL 0x0FFF
1147 #define IXGBE_CONTROL_SOL_NL 0x0000
1148 
1149 /* General purpose Interrupt Enable */
1150 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
1151 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
1152 #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
1153 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1154 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1155 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1156 #define IXGBE_GPIE_EIAME 0x40000000
1157 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1158 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1159 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
1160 #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
1161 #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
1162 #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
1163 
1164 /* Packet Buffer Initialization */
1165 #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */
1166 #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
1167 #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
1168 #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
1169 #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
1170 #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
1171 #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/
1172 #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/
1173 
1174 #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
1175 #define IXGBE_MAX_PB 8
1176 
1177 /* Packet buffer allocation strategies */
1178 enum {
1179  PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
1180 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
1181  PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */
1182 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
1183 };
1184 
1185 /* Transmit Flow Control status */
1186 #define IXGBE_TFCS_TXOFF 0x00000001
1187 #define IXGBE_TFCS_TXOFF0 0x00000100
1188 #define IXGBE_TFCS_TXOFF1 0x00000200
1189 #define IXGBE_TFCS_TXOFF2 0x00000400
1190 #define IXGBE_TFCS_TXOFF3 0x00000800
1191 #define IXGBE_TFCS_TXOFF4 0x00001000
1192 #define IXGBE_TFCS_TXOFF5 0x00002000
1193 #define IXGBE_TFCS_TXOFF6 0x00004000
1194 #define IXGBE_TFCS_TXOFF7 0x00008000
1195 
1196 /* TCP Timer */
1197 #define IXGBE_TCPTIMER_KS 0x00000100
1198 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1199 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1200 #define IXGBE_TCPTIMER_LOOP 0x00000800
1201 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1202 
1203 /* HLREG0 Bit Masks */
1204 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
1205 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
1206 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
1207 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
1208 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
1209 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
1210 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
1211 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
1212 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
1213 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
1214 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
1215 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
1216 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
1217 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
1218 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
1219 
1220 /* VMD_CTL bitmasks */
1221 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1222 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1223 
1224 /* VT_CTL bitmasks */
1225 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1226 #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1227 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
1228 #define IXGBE_VT_CTL_POOL_SHIFT 7
1229 #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1230 
1231 /* VMOLR bitmasks */
1232 #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1233 #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1234 #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1235 #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1236 #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1237 
1238 /* VFRE bitmask */
1239 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1240 
1241 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
1242 
1243 /* RDHMPN and TDHMPN bitmasks */
1244 #define IXGBE_RDHMPN_RDICADDR 0x007FF800
1245 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1246 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1247 #define IXGBE_TDHMPN_TDICADDR 0x003FF800
1248 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1249 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1250 
1251 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1252 #define IXGBE_RDMAM_DWORD_SHIFT 9
1253 #define IXGBE_RDMAM_DESC_COMP_FIFO 1
1254 #define IXGBE_RDMAM_DFC_CMD_FIFO 2
1255 #define IXGBE_RDMAM_TCN_STATUS_RAM 4
1256 #define IXGBE_RDMAM_WB_COLL_FIFO 5
1257 #define IXGBE_RDMAM_QSC_CNT_RAM 6
1258 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1259 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1260 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1261 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1262 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1263 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1264 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1265 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1266 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1267 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1268 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1269 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1270 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1271 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1272 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1273 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1274 
1275 #define IXGBE_TXDESCIC_READY 0x80000000
1276 
1277 /* Receive Checksum Control */
1278 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1279 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1280 
1281 /* FCRTL Bit Masks */
1282 #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1283 #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
1284 
1285 /* PAP bit masks*/
1286 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1287 
1288 /* RMCS Bit Masks */
1289 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
1290 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1291 #define IXGBE_RMCS_RAC 0x00000004
1292 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1293 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1294 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
1295 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1296 
1297 /* FCCFG Bit Masks */
1298 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1299 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
1300 
1301 /* Interrupt register bitmasks */
1302 
1303 /* Extended Interrupt Cause Read */
1304 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
1305 #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1306 #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1307 #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1308 #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
1309 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1310 #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
1311 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1312 #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
1313 #define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */
1314 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1315 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1316 #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1317 #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
1318 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1319 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1320 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1321 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1322 
1323 /* Extended Interrupt Cause Set */
1324 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1325 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1326 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1327 #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1328 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1329 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1330 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1331 #define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1332 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1333 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1334 #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1335 #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
1336 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1337 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
1338 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1339 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1340 
1341 /* Extended Interrupt Mask Set */
1342 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1343 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1344 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1345 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1346 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1347 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1348 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1349 #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */
1350 #define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1351 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1352 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1353 #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1354 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
1355 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1356 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1357 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1358 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1359 
1360 /* Extended Interrupt Mask Clear */
1361 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1362 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1363 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1364 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1365 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1366 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1367 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1368 #define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1369 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1370 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1371 #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1372 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
1373 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1374 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
1375 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1376 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1377 
1378 #define IXGBE_EIMS_ENABLE_MASK ( \
1379  IXGBE_EIMS_RTX_QUEUE | \
1380  IXGBE_EIMS_LSC | \
1381  IXGBE_EIMS_TCP_TIMER | \
1382  IXGBE_EIMS_OTHER)
1383 
1384 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1385 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1386 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1387 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1388 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1389 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1390 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1391 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1392 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1393 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1394 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
1395 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1396 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1397 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1398 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1399 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1400 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1401 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1402 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1403 #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1404 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1405 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1406 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1407 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1408 
1409 #define IXGBE_MAX_FTQF_FILTERS 128
1410 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1411 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1412 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1413 #define IXGBE_FTQF_PROTOCOL_SCTP 2
1414 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1415 #define IXGBE_FTQF_PRIORITY_SHIFT 2
1416 #define IXGBE_FTQF_POOL_MASK 0x0000003F
1417 #define IXGBE_FTQF_POOL_SHIFT 8
1418 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1419 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1420 #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
1421 #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
1422 #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
1423 #define IXGBE_FTQF_DEST_PORT_MASK 0x17
1424 #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
1425 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1426 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1427 
1428 /* Interrupt clear mask */
1429 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1430 
1431 /* Interrupt Vector Allocation Registers */
1432 #define IXGBE_IVAR_REG_NUM 25
1433 #define IXGBE_IVAR_REG_NUM_82599 64
1434 #define IXGBE_IVAR_TXRX_ENTRY 96
1435 #define IXGBE_IVAR_RX_ENTRY 64
1436 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1437 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1438 #define IXGBE_IVAR_TX_ENTRY 32
1439 
1440 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
1441 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
1442 
1443 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1444 
1445 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
1446 
1447 /* ETYPE Queue Filter/Select Bit Masks */
1448 #define IXGBE_MAX_ETQF_FILTERS 8
1449 #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
1450 #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1451 #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1452 #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1453 #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1454 #define IXGBE_ETQF_POOL_SHIFT 20
1455 
1456 #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1457 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1458 #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1459 #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1460 
1461 /*
1462  * ETQF filter list: one static filter per filter consumer. This is
1463  * to avoid filter collisions later. Add new filters
1464  * here!!
1465  *
1466  * Current filters:
1467  * EAPOL 802.1x (0x888e): Filter 0
1468  * FCoE (0x8906): Filter 2
1469  * 1588 (0x88f7): Filter 3
1470  * FIP (0x8914): Filter 4
1471  */
1472 #define IXGBE_ETQF_FILTER_EAPOL 0
1473 #define IXGBE_ETQF_FILTER_FCOE 2
1474 #define IXGBE_ETQF_FILTER_1588 3
1475 #define IXGBE_ETQF_FILTER_FIP 4
1476 /* VLAN Control Bit Masks */
1477 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1478 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
1479 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1480 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1481 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1482 
1483 /* VLAN pool filtering masks */
1484 #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1485 #define IXGBE_VLVF_ENTRIES 64
1486 #define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1487 
1488 /* Per VF Port VLAN insertion rules */
1489 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1490 #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
1491 
1492 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1493 
1494 /* STATUS Bit Masks */
1495 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1496 #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1497 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
1498 
1499 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
1500 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
1501 
1502 /* ESDP Bit Masks */
1503 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1504 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1505 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1506 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1507 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1508 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1509 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1510 #define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */
1511 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
1512 #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1513 #define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 Native Function */
1514 
1515 /* LEDCTL Bit Masks */
1516 #define IXGBE_LED_IVRT_BASE 0x00000040
1517 #define IXGBE_LED_BLINK_BASE 0x00000080
1518 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1519 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1520 #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
1521 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1522 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1523 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1524 
1525 /* LED modes */
1526 #define IXGBE_LED_LINK_UP 0x0
1527 #define IXGBE_LED_LINK_10G 0x1
1528 #define IXGBE_LED_MAC 0x2
1529 #define IXGBE_LED_FILTER 0x3
1530 #define IXGBE_LED_LINK_ACTIVE 0x4
1531 #define IXGBE_LED_LINK_1G 0x5
1532 #define IXGBE_LED_ON 0xE
1533 #define IXGBE_LED_OFF 0xF
1534 
1535 /* AUTOC Bit Masks */
1536 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1537 #define IXGBE_AUTOC_KX4_SUPP 0x80000000
1538 #define IXGBE_AUTOC_KX_SUPP 0x40000000
1539 #define IXGBE_AUTOC_PAUSE 0x30000000
1540 #define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1541 #define IXGBE_AUTOC_SYM_PAUSE 0x10000000
1542 #define IXGBE_AUTOC_RF 0x08000000
1543 #define IXGBE_AUTOC_PD_TMR 0x06000000
1544 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1545 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1546 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1547 #define IXGBE_AUTOC_FECA 0x00040000
1548 #define IXGBE_AUTOC_FECR 0x00020000
1549 #define IXGBE_AUTOC_KR_SUPP 0x00010000
1550 #define IXGBE_AUTOC_AN_RESTART 0x00001000
1551 #define IXGBE_AUTOC_FLU 0x00000001
1552 #define IXGBE_AUTOC_LMS_SHIFT 13
1553 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1554 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1555 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1556 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1557 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1558 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1559 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1560 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1561 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1562 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1563 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1564 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1565 
1566 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1567 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1568 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1569 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1570 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1571 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1572 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1573 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1574 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1575 #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1576 #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1577 
1578 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1579 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1580 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1581 #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1582 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1583 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1584 
1585 #define IXGBE_MACC_FLU 0x00000001
1586 #define IXGBE_MACC_FSV_10G 0x00030000
1587 #define IXGBE_MACC_FS 0x00040000
1588 #define IXGBE_MAC_RX2TX_LPBK 0x00000002
1589 
1590 /* LINKS Bit Masks */
1591 #define IXGBE_LINKS_KX_AN_COMP 0x80000000
1592 #define IXGBE_LINKS_UP 0x40000000
1593 #define IXGBE_LINKS_SPEED 0x20000000
1594 #define IXGBE_LINKS_MODE 0x18000000
1595 #define IXGBE_LINKS_RX_MODE 0x06000000
1596 #define IXGBE_LINKS_TX_MODE 0x01800000
1597 #define IXGBE_LINKS_XGXS_EN 0x00400000
1598 #define IXGBE_LINKS_SGMII_EN 0x02000000
1599 #define IXGBE_LINKS_PCS_1G_EN 0x00200000
1600 #define IXGBE_LINKS_1G_AN_EN 0x00100000
1601 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1602 #define IXGBE_LINKS_1G_SYNC 0x00040000
1603 #define IXGBE_LINKS_10G_ALIGN 0x00020000
1604 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1605 #define IXGBE_LINKS_TL_FAULT 0x00001000
1606 #define IXGBE_LINKS_SIGNAL 0x00000F00
1607 
1608 #define IXGBE_LINKS_SPEED_82599 0x30000000
1609 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1610 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1611 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1612 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
1613 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1614 
1615 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1616 
1617 /* PCS1GLSTA Bit Masks */
1618 #define IXGBE_PCS1GLSTA_LINK_OK 1
1619 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1620 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1621 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1622 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1623 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1624 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1625 
1626 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1627 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1628 
1629 /* PCS1GLCTL Bit Masks */
1630 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1631 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1632 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1633 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1634 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1635 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1636 
1637 /* ANLP1 Bit Masks */
1638 #define IXGBE_ANLP1_PAUSE 0x0C00
1639 #define IXGBE_ANLP1_SYM_PAUSE 0x0400
1640 #define IXGBE_ANLP1_ASM_PAUSE 0x0800
1641 #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1642 
1643 /* SW Semaphore Register bitmasks */
1644 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1645 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1646 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1647 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1648 
1649 /* SW_FW_SYNC/GSSR definitions */
1650 #define IXGBE_GSSR_EEP_SM 0x0001
1651 #define IXGBE_GSSR_PHY0_SM 0x0002
1652 #define IXGBE_GSSR_PHY1_SM 0x0004
1653 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
1654 #define IXGBE_GSSR_FLASH_SM 0x0010
1655 #define IXGBE_GSSR_SW_MNG_SM 0x0400
1656 
1657 /* FW Status register bitmask */
1658 #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
1659 
1660 /* EEC Register */
1661 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
1662 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
1663 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
1664 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
1665 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
1666 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1667 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1668 #define IXGBE_EEC_FWE_SHIFT 4
1669 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1670 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1671 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1672 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1673 #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
1674 #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
1675 #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
1676 /* EEPROM Addressing bits based on type (0-small, 1-large) */
1677 #define IXGBE_EEC_ADDR_SIZE 0x00000400
1678 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1679 #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
1680 
1681 #define IXGBE_EEC_SIZE_SHIFT 11
1682 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1683 #define IXGBE_EEPROM_OPCODE_BITS 8
1684 
1685 /* Part Number String Length */
1686 #define IXGBE_PBANUM_LENGTH 11
1687 
1688 /* Checksum and EEPROM pointers */
1689 #define IXGBE_PBANUM_PTR_GUARD 0xFAFA
1690 #define IXGBE_EEPROM_CHECKSUM 0x3F
1691 #define IXGBE_EEPROM_SUM 0xBABA
1692 #define IXGBE_PCIE_ANALOG_PTR 0x03
1693 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
1694 #define IXGBE_PHY_PTR 0x04
1695 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
1696 #define IXGBE_OPTION_ROM_PTR 0x05
1697 #define IXGBE_PCIE_GENERAL_PTR 0x06
1698 #define IXGBE_PCIE_CONFIG0_PTR 0x07
1699 #define IXGBE_PCIE_CONFIG1_PTR 0x08
1700 #define IXGBE_CORE0_PTR 0x09
1701 #define IXGBE_CORE1_PTR 0x0A
1702 #define IXGBE_MAC0_PTR 0x0B
1703 #define IXGBE_MAC1_PTR 0x0C
1704 #define IXGBE_CSR0_CONFIG_PTR 0x0D
1705 #define IXGBE_CSR1_CONFIG_PTR 0x0E
1706 #define IXGBE_FW_PTR 0x0F
1707 #define IXGBE_PBANUM0_PTR 0x15
1708 #define IXGBE_PBANUM1_PTR 0x16
1709 #define IXGBE_FREE_SPACE_PTR 0X3E
1710 
1711 /* External Thermal Sensor Config */
1712 #define IXGBE_ETS_CFG 0x26
1713 #define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0
1714 #define IXGBE_ETS_LTHRES_DELTA_SHIFT 6
1715 #define IXGBE_ETS_TYPE_MASK 0x0038
1716 #define IXGBE_ETS_TYPE_SHIFT 3
1717 #define IXGBE_ETS_TYPE_EMC 0x000
1718 #define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000
1719 #define IXGBE_ETS_NUM_SENSORS_MASK 0x0007
1720 #define IXGBE_ETS_DATA_LOC_MASK 0x3C00
1721 #define IXGBE_ETS_DATA_LOC_SHIFT 10
1722 #define IXGBE_ETS_DATA_INDEX_MASK 0x0300
1723 #define IXGBE_ETS_DATA_INDEX_SHIFT 8
1724 #define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF
1725 
1726 #define IXGBE_SAN_MAC_ADDR_PTR 0x28
1727 #define IXGBE_DEVICE_CAPS 0x2C
1728 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
1729 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1730 #define IXGBE_MAX_MSIX_VECTORS_82599 0x40
1731 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1732 #define IXGBE_MAX_MSIX_VECTORS_82598 0x13
1733 
1734 /* MSI-X capability fields masks */
1735 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1736 
1737 /* Legacy EEPROM word offsets */
1738 #define IXGBE_ISCSI_BOOT_CAPS 0x0033
1739 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1740 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1741 
1742 /* EEPROM Commands - SPI */
1743 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
1744 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1745 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1746 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1747 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
1748 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
1749 /* EEPROM reset Write Enable latch */
1750 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1751 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
1752 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
1753 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1754 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1755 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1756 
1757 /* EEPROM Read Register */
1758 #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
1759 #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
1760 #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1761 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1762 #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1763 #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
1764 
1765 #define IXGBE_EEPROM_PAGE_SIZE_MAX 128
1766 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
1767 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
1768 
1769 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1770 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1771 #endif
1772 
1773 #ifndef IXGBE_EERD_EEWR_ATTEMPTS
1774 /* Number of 5 microseconds we wait for EERD read and
1775  * EERW write to complete */
1776 #define IXGBE_EERD_EEWR_ATTEMPTS 100000
1777 #endif
1778 
1779 #ifndef IXGBE_FLUDONE_ATTEMPTS
1780 /* # attempts we wait for flush update to complete */
1781 #define IXGBE_FLUDONE_ATTEMPTS 20000
1782 #endif
1783 
1784 #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
1785 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
1786 #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
1787 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
1788 
1789 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1790 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
1791 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
1792 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
1793 #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
1794 #define IXGBE_FW_LESM_STATE_1 0x1
1795 #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
1796 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
1797 #define IXGBE_FW_PATCH_VERSION_4 0x7
1798 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
1799 #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
1800 #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
1801 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
1802 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
1803 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
1804 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
1805 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1806 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1807 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
1808 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
1809 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
1810 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1811 
1812 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */
1813 #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */
1814 #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */
1815 
1816 /* PCI Bus Info */
1817 #define IXGBE_PCI_DEVICE_STATUS 0xAA
1818 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
1819 #define IXGBE_PCI_LINK_STATUS 0xB2
1820 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1821 #define IXGBE_PCI_LINK_WIDTH 0x3F0
1822 #define IXGBE_PCI_LINK_WIDTH_1 0x10
1823 #define IXGBE_PCI_LINK_WIDTH_2 0x20
1824 #define IXGBE_PCI_LINK_WIDTH_4 0x40
1825 #define IXGBE_PCI_LINK_WIDTH_8 0x80
1826 #define IXGBE_PCI_LINK_SPEED 0xF
1827 #define IXGBE_PCI_LINK_SPEED_2500 0x1
1828 #define IXGBE_PCI_LINK_SPEED_5000 0x2
1829 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1830 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1831 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
1832 
1833 /* Number of 100 microseconds we wait for PCI Express master disable */
1834 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1835 
1836 /* Check whether address is multicast. This is little-endian specific check.*/
1837 #define IXGBE_IS_MULTICAST(Address) \
1838  (bool)(((u8 *)(Address))[0] & ((u8)0x01))
1839 
1840 /* Check whether an address is broadcast. */
1841 #define IXGBE_IS_BROADCAST(Address) \
1842  ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1843  (((u8 *)(Address))[1] == ((u8)0xff)))
1844 
1845 /* RAH */
1846 #define IXGBE_RAH_VIND_MASK 0x003C0000
1847 #define IXGBE_RAH_VIND_SHIFT 18
1848 #define IXGBE_RAH_AV 0x80000000
1849 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
1850 
1851 /* Header split receive */
1852 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1853 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1854 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1855 #define IXGBE_RFCTL_NFSW_DIS 0x00000040
1856 #define IXGBE_RFCTL_NFSR_DIS 0x00000080
1857 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1858 #define IXGBE_RFCTL_NFS_VER_SHIFT 8
1859 #define IXGBE_RFCTL_NFS_VER_2 0
1860 #define IXGBE_RFCTL_NFS_VER_3 1
1861 #define IXGBE_RFCTL_NFS_VER_4 2
1862 #define IXGBE_RFCTL_IPV6_DIS 0x00000400
1863 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1864 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1865 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1866 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1867 
1868 /* Transmit Config masks */
1869 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
1870 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
1871 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
1872 /* Enable short packet padding to 64 bytes */
1873 #define IXGBE_TX_PAD_ENABLE 0x00000400
1874 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
1875 /* This allows for 16K packets + 4k for vlan */
1876 #define IXGBE_MAX_FRAME_SZ 0x40040000
1877 
1878 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
1879 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
1880 
1881 /* Receive Config masks */
1882 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1883 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
1884 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
1885 #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */
1886 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */
1887 #define IXGBE_RXDCTL_RLPML_EN 0x00008000
1888 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
1889 
1890 #define IXGBE_TSAUXC_EN_CLK 0x00000004
1891 #define IXGBE_TSAUXC_SYNCLK 0x00000008
1892 #define IXGBE_TSAUXC_SDP0_INT 0x00000040
1893 
1894 #define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
1895 #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
1896 
1897 #define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
1898 #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
1899 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
1900 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
1901 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
1902 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
1903 #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */
1904 
1905 #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
1906 #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
1907 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
1908 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
1909 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
1910 #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
1911 
1912 #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
1913 #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
1914 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
1915 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
1916 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
1917 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
1918 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
1919 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
1920 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
1921 #define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00
1922 #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
1923 
1924 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1925 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1926 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1927 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1928 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1929 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
1930 /* Receive Priority Flow Control Enable */
1931 #define IXGBE_FCTRL_RPFCE 0x00004000
1932 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
1933 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1934 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1935 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1936 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
1937 #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Receive FC Mask */
1938 
1939 #define IXGBE_MFLCN_RPFCE_SHIFT 4
1940 
1941 /* Multiple Receive Queue Control */
1942 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
1943 #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1944 #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1945 #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1946 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
1947 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
1948 #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
1949 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
1950 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
1951 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
1952 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
1953 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
1954 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1955 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
1956 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1957 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1958 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
1959 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1960 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1961 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1962 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
1963 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000
1964 
1965 /* Queue Drop Enable */
1966 #define IXGBE_QDE_ENABLE 0x00000001
1967 #define IXGBE_QDE_IDX_MASK 0x00007F00
1968 #define IXGBE_QDE_IDX_SHIFT 8
1969 
1970 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
1971 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
1972 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
1973 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1974 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
1975 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
1976 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
1977 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
1978 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
1979 
1980 #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
1981 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
1982 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
1983 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
1984 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
1985 /* Multiple Transmit Queue Command Register */
1986 #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
1987 #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
1988 #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
1989 #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
1990 #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
1991 #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
1992 #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */
1993 
1994 /* Receive Descriptor bit definitions */
1995 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
1996 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
1997 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
1998 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
1999 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
2000 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
2001 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
2002 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
2003 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
2004 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
2005 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
2006 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
2007 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
2008 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
2009 #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
2010 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
2011 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
2012 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
2013 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
2014 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
2015 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
2016 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
2017 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
2018 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
2019 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
2020 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
2021 #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
2022 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
2023 #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
2024 #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
2025 #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
2026 #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
2027 #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
2028 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
2029 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
2030 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
2031 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
2032 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
2033 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
2034 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
2035 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
2036 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
2037 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2038 #define IXGBE_RXD_PRI_SHIFT 13
2039 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
2040 #define IXGBE_RXD_CFI_SHIFT 12
2041 
2042 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
2043 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
2044 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
2045 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
2046 #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
2047 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
2048 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
2049 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2050 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
2051 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2052 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
2053 #define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE 1588 Time Stamp */
2054 
2055 /* PSRTYPE bit definitions */
2056 #define IXGBE_PSRTYPE_TCPHDR 0x00000010
2057 #define IXGBE_PSRTYPE_UDPHDR 0x00000020
2058 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100
2059 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200
2060 #define IXGBE_PSRTYPE_L2HDR 0x00001000
2061 
2062 /* SRRCTL bit definitions */
2063 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
2064 #define IXGBE_SRRCTL_RDMTS_SHIFT 22
2065 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
2066 #define IXGBE_SRRCTL_DROP_EN 0x10000000
2067 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
2068 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
2069 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
2070 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2071 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2072 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2073 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2074 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
2075 
2076 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
2077 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2078 
2079 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
2080 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
2081 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
2082 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
2083 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
2084 #define IXGBE_RXDADV_RSCCNT_SHIFT 17
2085 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
2086 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
2087 #define IXGBE_RXDADV_SPH 0x8000
2088 
2089 /* RSS Hash results */
2090 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
2091 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
2092 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
2093 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
2094 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
2095 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
2096 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2097 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
2098 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
2099 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2100 
2101 /* RSS Packet Types as indicated in the receive descriptor. */
2102 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
2103 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
2104 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
2105 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
2106 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
2107 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
2108 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
2109 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
2110 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
2111 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
2112 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
2113 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
2114 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
2115 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
2116 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
2117 
2118 /* Security Processing bit Indication */
2119 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
2120 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
2121 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
2122 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
2123 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
2124 
2125 /* Masks to determine if packets should be dropped due to frame errors */
2126 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2127  IXGBE_RXD_ERR_CE | \
2128  IXGBE_RXD_ERR_LE | \
2129  IXGBE_RXD_ERR_PE | \
2130  IXGBE_RXD_ERR_OSE | \
2131  IXGBE_RXD_ERR_USE)
2132 
2133 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2134  IXGBE_RXDADV_ERR_CE | \
2135  IXGBE_RXDADV_ERR_LE | \
2136  IXGBE_RXDADV_ERR_PE | \
2137  IXGBE_RXDADV_ERR_OSE | \
2138  IXGBE_RXDADV_ERR_USE)
2139 
2140 /* Multicast bit mask */
2141 #define IXGBE_MCSTCTRL_MFE 0x4
2142 
2143 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2144 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
2145 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
2146 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
2147 
2148 /* Vlan-specific macros */
2149 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
2150 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
2151 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2152 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2153 
2154 /* SR-IOV specific macros */
2155 #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
2156 #define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))
2157 #define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600))
2158 #define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))
2159 
2160 enum ixgbe_fdir_pballoc_type {
2161  IXGBE_FDIR_PBALLOC_NONE = 0,
2162  IXGBE_FDIR_PBALLOC_64K = 1,
2163  IXGBE_FDIR_PBALLOC_128K = 2,
2164  IXGBE_FDIR_PBALLOC_256K = 3,
2165 };
2166 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
2167 
2168 /* Flow Director register values */
2169 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2170 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2171 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2172 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2173 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
2174 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
2175 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
2176 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
2177 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16
2178 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
2179 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
2180 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
2181 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
2182 
2183 #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
2184 #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
2185 #define IXGBE_FDIRIP6M_DIPM_SHIFT 16
2186 #define IXGBE_FDIRM_VLANID 0x00000001
2187 #define IXGBE_FDIRM_VLANP 0x00000002
2188 #define IXGBE_FDIRM_POOL 0x00000004
2189 #define IXGBE_FDIRM_L4P 0x00000008
2190 #define IXGBE_FDIRM_FLEX 0x00000010
2191 #define IXGBE_FDIRM_DIPv6 0x00000020
2192 
2193 #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
2194 #define IXGBE_FDIRFREE_FREE_SHIFT 0
2195 #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
2196 #define IXGBE_FDIRFREE_COLL_SHIFT 16
2197 #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
2198 #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
2199 #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
2200 #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
2201 #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
2202 #define IXGBE_FDIRUSTAT_ADD_SHIFT 0
2203 #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
2204 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
2205 #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2206 #define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2207 #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2208 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2209 #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2210 #define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2211 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2212 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2213 
2214 #define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2215 #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2216 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2217 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2218 #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
2219 #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2220 #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2221 #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2222 #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2223 #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2224 #define IXGBE_FDIRCMD_IPV6 0x00000080
2225 #define IXGBE_FDIRCMD_CLEARHT 0x00000100
2226 #define IXGBE_FDIRCMD_DROP 0x00000200
2227 #define IXGBE_FDIRCMD_INT 0x00000400
2228 #define IXGBE_FDIRCMD_LAST 0x00000800
2229 #define IXGBE_FDIRCMD_COLLISION 0x00001000
2230 #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
2231 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2232 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2233 #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2234 #define IXGBE_FDIR_INIT_DONE_POLL 10
2235 #define IXGBE_FDIRCMD_CMD_POLL 10
2236 
2237 #define IXGBE_FDIR_DROP_QUEUE 127
2238 
2239 /* Manageablility Host Interface defines */
2240 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
2241 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
2242 #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
2243 
2244 /* CEM Support */
2245 #define FW_CEM_HDR_LEN 0x4
2246 #define FW_CEM_CMD_DRIVER_INFO 0xDD
2247 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
2248 #define FW_CEM_CMD_RESERVED 0x0
2249 #define FW_CEM_UNUSED_VER 0x0
2250 #define FW_CEM_MAX_RETRIES 3
2251 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
2252 
2253 /* Host Interface Command Structures */
2254 struct ixgbe_hic_hdr {
2255  u8 cmd;
2256  u8 buf_len;
2257  union {
2258  u8 cmd_resv;
2259  u8 ret_status;
2260  } cmd_or_resp;
2261  u8 checksum;
2262 };
2263 
2264 struct ixgbe_hic_drv_info {
2265  struct ixgbe_hic_hdr hdr;
2266  u8 port_num;
2267  u8 ver_sub;
2268  u8 ver_build;
2269  u8 ver_min;
2270  u8 ver_maj;
2271  u8 pad; /* end spacing to ensure length is mult. of dword */
2272  u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2273 };
2274 
2275 /* Transmit Descriptor - Advanced */
2276 union ixgbe_adv_tx_desc {
2277  struct {
2278  __le64 buffer_addr; /* Address of descriptor's data buf */
2279  __le32 cmd_type_len;
2280  __le32 olinfo_status;
2281  } read;
2282  struct {
2283  __le64 rsvd; /* Reserved */
2284  __le32 nxtseq_seed;
2285  __le32 status;
2286  } wb;
2287 };
2288 
2289 /* Receive Descriptor - Advanced */
2290 union ixgbe_adv_rx_desc {
2291  struct {
2292  __le64 pkt_addr; /* Packet buffer address */
2293  __le64 hdr_addr; /* Header buffer address */
2294  } read;
2295  struct {
2296  struct {
2297  union {
2298  __le32 data;
2299  struct {
2300  __le16 pkt_info; /* RSS, Pkt type */
2301  __le16 hdr_info; /* Splithdr, hdrlen */
2302  } hs_rss;
2303  } lo_dword;
2304  union {
2305  __le32 rss; /* RSS Hash */
2306  struct {
2307  __le16 ip_id; /* IP id */
2308  __le16 csum; /* Packet Checksum */
2309  } csum_ip;
2310  } hi_dword;
2311  } lower;
2312  struct {
2313  __le32 status_error; /* ext status/error */
2314  __le16 length; /* Packet length */
2315  __le16 vlan; /* VLAN tag */
2316  } upper;
2317  } wb; /* writeback */
2318 };
2319 
2320 /* Context descriptors */
2321 struct ixgbe_adv_tx_context_desc {
2322  __le32 vlan_macip_lens;
2323  __le32 seqnum_seed;
2324  __le32 type_tucmd_mlhl;
2325  __le32 mss_l4len_idx;
2326 };
2327 
2328 /* Adv Transmit Descriptor Config Masks */
2329 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
2330 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
2331 #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE 1588 Time Stamp */
2332 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
2333 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
2334 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
2335 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
2336 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
2337 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
2338 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
2339 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
2340 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
2341 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2342 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
2343 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
2344 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
2345 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
2346 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
2347 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
2348 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
2349 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
2350 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2351  IXGBE_ADVTXD_POPTS_SHIFT)
2352 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2353  IXGBE_ADVTXD_POPTS_SHIFT)
2354 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
2355 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
2356 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2357 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2358 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
2359 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
2360 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
2361 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
2362 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
2363 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
2364 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
2365 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
2366 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
2367 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
2368 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
2369 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2370 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2371 #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
2372 #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
2373 #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
2374 #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
2375 #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
2376 #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
2377 #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
2378 #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
2379 #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
2380 #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
2381 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
2382 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
2383 
2384 /* Autonegotiation advertised speeds */
2385 typedef u32 ixgbe_autoneg_advertised;
2386 /* Link speed */
2387 typedef u32 ixgbe_link_speed;
2388 #define IXGBE_LINK_SPEED_UNKNOWN 0
2389 #define IXGBE_LINK_SPEED_100_FULL 0x0008
2390 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2391 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2392 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2393  IXGBE_LINK_SPEED_10GB_FULL)
2394 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2395  IXGBE_LINK_SPEED_1GB_FULL | \
2396  IXGBE_LINK_SPEED_10GB_FULL)
2397 
2398 
2399 /* Physical layer type */
2400 typedef u32 ixgbe_physical_layer;
2401 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
2402 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
2403 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
2404 #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
2405 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
2406 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
2407 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
2408 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
2409 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2410 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2411 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2412 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2413 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2414 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2415 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2416 
2417 /* Flow Control Data Sheet defined values
2418  * Calculation and defines taken from 802.1bb Annex O
2419  */
2420 
2421 /* BitTimes (BT) conversion */
2422 #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
2423 #define IXGBE_B2BT(BT) (BT * 8)
2424 
2425 /* Calculate Delay to respond to PFC */
2426 #define IXGBE_PFC_D 672
2427 
2428 /* Calculate Cable Delay */
2429 #define IXGBE_CABLE_DC 5556 /* Delay Copper */
2430 #define IXGBE_CABLE_DO 5000 /* Delay Optical */
2431 
2432 /* Calculate Interface Delay X540 */
2433 #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */
2434 #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */
2435 #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */
2436 
2437 #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2438 
2439 /* Calculate Interface Delay 82598, 82599 */
2440 #define IXGBE_PHY_D 12800
2441 #define IXGBE_MAC_D 4096
2442 #define IXGBE_XAUI_D (2 * 1024)
2443 
2444 #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
2445 
2446 /* Calculate Delay incurred from higher layer */
2447 #define IXGBE_HD 6144
2448 
2449 /* Calculate PCI Bus delay for low thresholds */
2450 #define IXGBE_PCI_DELAY 10000
2451 
2452 /* Calculate X540 delay value in bit times */
2453 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
2454  ((36 * \
2455  (IXGBE_B2BT(_max_frame_link) + \
2456  IXGBE_PFC_D + \
2457  (2 * IXGBE_CABLE_DC) + \
2458  (2 * IXGBE_ID_X540) + \
2459  IXGBE_HD) / 25 + 1) + \
2460  2 * IXGBE_B2BT(_max_frame_tc))
2461 
2462 /* Calculate 82599, 82598 delay value in bit times */
2463 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
2464  ((36 * \
2465  (IXGBE_B2BT(_max_frame_link) + \
2466  IXGBE_PFC_D + \
2467  (2 * IXGBE_CABLE_DC) + \
2468  (2 * IXGBE_ID) + \
2469  IXGBE_HD) / 25 + 1) + \
2470  2 * IXGBE_B2BT(_max_frame_tc))
2471 
2472 /* Calculate low threshold delay values */
2473 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
2474  (2 * IXGBE_B2BT(_max_frame_tc) + \
2475  (36 * IXGBE_PCI_DELAY / 25) + 1)
2476 #define IXGBE_LOW_DV(_max_frame_tc) \
2477  (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
2478 
2479 /* Software ATR hash keys */
2480 #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2481 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2482 
2483 /* Software ATR input stream values and masks */
2484 #define IXGBE_ATR_HASH_MASK 0x7fff
2485 #define IXGBE_ATR_L4TYPE_MASK 0x3
2486 #define IXGBE_ATR_L4TYPE_UDP 0x1
2487 #define IXGBE_ATR_L4TYPE_TCP 0x2
2488 #define IXGBE_ATR_L4TYPE_SCTP 0x3
2489 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2490 enum ixgbe_atr_flow_type {
2491  IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
2492  IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
2493  IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
2494  IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2495  IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
2496  IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
2497  IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
2498  IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2499 };
2500 
2501 /* Flow Director ATR input struct. */
2502 union ixgbe_atr_input {
2503  /*
2504  * Byte layout in order, all values with MSB first:
2505  *
2506  * vm_pool - 1 byte
2507  * flow_type - 1 byte
2508  * vlan_id - 2 bytes
2509  * src_ip - 16 bytes
2510  * dst_ip - 16 bytes
2511  * src_port - 2 bytes
2512  * dst_port - 2 bytes
2513  * flex_bytes - 2 bytes
2514  * bkt_hash - 2 bytes
2515  */
2516  struct {
2517  u8 vm_pool;
2518  u8 flow_type;
2519  __be16 vlan_id;
2520  __be32 dst_ip[4];
2521  __be32 src_ip[4];
2522  __be16 src_port;
2523  __be16 dst_port;
2524  __be16 flex_bytes;
2525  __be16 bkt_hash;
2526  } formatted;
2527  __be32 dword_stream[11];
2528 };
2529 
2530 /* Flow Director compressed ATR hash input struct */
2531 union ixgbe_atr_hash_dword {
2532  struct {
2533  u8 vm_pool;
2534  u8 flow_type;
2535  __be16 vlan_id;
2536  } formatted;
2537  __be32 ip;
2538  struct {
2539  __be16 src;
2540  __be16 dst;
2541  } port;
2542  __be16 flex_bytes;
2543  __be32 dword;
2544 };
2545 
2546 enum ixgbe_eeprom_type {
2547  ixgbe_eeprom_uninitialized = 0,
2548  ixgbe_eeprom_spi,
2549  ixgbe_flash,
2550  ixgbe_eeprom_none /* No NVM support */
2551 };
2552 
2553 enum ixgbe_mac_type {
2554  ixgbe_mac_unknown = 0,
2555  ixgbe_mac_82598EB,
2556  ixgbe_mac_82599EB,
2557  ixgbe_mac_X540,
2558  ixgbe_num_macs
2559 };
2560 
2561 enum ixgbe_phy_type {
2562  ixgbe_phy_unknown = 0,
2563  ixgbe_phy_none,
2564  ixgbe_phy_tn,
2565  ixgbe_phy_aq,
2566  ixgbe_phy_cu_unknown,
2567  ixgbe_phy_qt,
2568  ixgbe_phy_xaui,
2569  ixgbe_phy_nl,
2570  ixgbe_phy_sfp_passive_tyco,
2571  ixgbe_phy_sfp_passive_unknown,
2572  ixgbe_phy_sfp_active_unknown,
2573  ixgbe_phy_sfp_avago,
2574  ixgbe_phy_sfp_ftl,
2575  ixgbe_phy_sfp_ftl_active,
2576  ixgbe_phy_sfp_unknown,
2577  ixgbe_phy_sfp_intel,
2578  ixgbe_phy_sfp_unsupported,
2579  ixgbe_phy_generic
2580 };
2581 
2582 /*
2583  * SFP+ module type IDs:
2584  *
2585  * ID Module Type
2586  * =============
2587  * 0 SFP_DA_CU
2588  * 1 SFP_SR
2589  * 2 SFP_LR
2590  * 3 SFP_DA_CU_CORE0 - 82599-specific
2591  * 4 SFP_DA_CU_CORE1 - 82599-specific
2592  * 5 SFP_SR/LR_CORE0 - 82599-specific
2593  * 6 SFP_SR/LR_CORE1 - 82599-specific
2594  */
2595 enum ixgbe_sfp_type {
2596  ixgbe_sfp_type_da_cu = 0,
2597  ixgbe_sfp_type_sr = 1,
2598  ixgbe_sfp_type_lr = 2,
2599  ixgbe_sfp_type_da_cu_core0 = 3,
2600  ixgbe_sfp_type_da_cu_core1 = 4,
2601  ixgbe_sfp_type_srlr_core0 = 5,
2602  ixgbe_sfp_type_srlr_core1 = 6,
2603  ixgbe_sfp_type_da_act_lmt_core0 = 7,
2604  ixgbe_sfp_type_da_act_lmt_core1 = 8,
2605  ixgbe_sfp_type_1g_cu_core0 = 9,
2606  ixgbe_sfp_type_1g_cu_core1 = 10,
2607  ixgbe_sfp_type_1g_sx_core0 = 11,
2608  ixgbe_sfp_type_1g_sx_core1 = 12,
2609  ixgbe_sfp_type_not_present = 0xFFFE,
2610  ixgbe_sfp_type_unknown = 0xFFFF
2611 };
2612 
2613 enum ixgbe_media_type {
2614  ixgbe_media_type_unknown = 0,
2615  ixgbe_media_type_fiber,
2616  ixgbe_media_type_fiber_lco,
2617  ixgbe_media_type_copper,
2618  ixgbe_media_type_backplane,
2619  ixgbe_media_type_cx4,
2620  ixgbe_media_type_virtual
2621 };
2622 
2623 /* Flow Control Settings */
2624 enum ixgbe_fc_mode {
2625  ixgbe_fc_none = 0,
2626  ixgbe_fc_rx_pause,
2627  ixgbe_fc_tx_pause,
2628  ixgbe_fc_full,
2629  ixgbe_fc_default
2630 };
2631 
2632 /* Smart Speed Settings */
2633 #define IXGBE_SMARTSPEED_MAX_RETRIES 3
2634 enum ixgbe_smart_speed {
2635  ixgbe_smart_speed_auto = 0,
2636  ixgbe_smart_speed_on,
2637  ixgbe_smart_speed_off
2638 };
2639 
2640 /* PCI bus types */
2641 enum ixgbe_bus_type {
2642  ixgbe_bus_type_unknown = 0,
2643  ixgbe_bus_type_pci,
2644  ixgbe_bus_type_pcix,
2645  ixgbe_bus_type_pci_express,
2646  ixgbe_bus_type_reserved
2647 };
2648 
2649 /* PCI bus speeds */
2650 enum ixgbe_bus_speed {
2651  ixgbe_bus_speed_unknown = 0,
2652  ixgbe_bus_speed_33 = 33,
2653  ixgbe_bus_speed_66 = 66,
2654  ixgbe_bus_speed_100 = 100,
2655  ixgbe_bus_speed_120 = 120,
2656  ixgbe_bus_speed_133 = 133,
2657  ixgbe_bus_speed_2500 = 2500,
2658  ixgbe_bus_speed_5000 = 5000,
2659  ixgbe_bus_speed_reserved
2660 };
2661 
2662 /* PCI bus widths */
2663 enum ixgbe_bus_width {
2664  ixgbe_bus_width_unknown = 0,
2665  ixgbe_bus_width_pcie_x1 = 1,
2666  ixgbe_bus_width_pcie_x2 = 2,
2667  ixgbe_bus_width_pcie_x4 = 4,
2668  ixgbe_bus_width_pcie_x8 = 8,
2669  ixgbe_bus_width_32 = 32,
2670  ixgbe_bus_width_64 = 64,
2671  ixgbe_bus_width_reserved
2672 };
2673 
2674 struct ixgbe_addr_filter_info {
2675  u32 num_mc_addrs;
2676  u32 rar_used_count;
2677  u32 mta_in_use;
2678  u32 overflow_promisc;
2679  bool uc_set_promisc;
2680  bool user_set_promisc;
2681 };
2682 
2683 /* Bus parameters */
2684 struct ixgbe_bus_info {
2685  enum ixgbe_bus_speed speed;
2686  enum ixgbe_bus_width width;
2687  enum ixgbe_bus_type type;
2688 
2689  u16 func;
2690  u16 lan_id;
2691 };
2692 
2693 /* Flow control parameters */
2694 struct ixgbe_fc_info {
2695  u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */
2696  u32 low_water; /* Flow Control Low-water */
2697  u16 pause_time; /* Flow Control Pause timer */
2698  bool send_xon; /* Flow control send XON */
2699  bool strict_ieee; /* Strict IEEE mode */
2700  bool disable_fc_autoneg; /* Do not autonegotiate FC */
2701  bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
2702  enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2703  enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2704 };
2705 
2706 /* Statistics counters collected by the MAC */
2707 struct ixgbe_hw_stats {
2708  u64 crcerrs;
2709  u64 illerrc;
2710  u64 errbc;
2711  u64 mspdc;
2712  u64 mpctotal;
2713  u64 mpc[8];
2714  u64 mlfc;
2715  u64 mrfc;
2716  u64 rlec;
2717  u64 lxontxc;
2718  u64 lxonrxc;
2719  u64 lxofftxc;
2720  u64 lxoffrxc;
2721  u64 pxontxc[8];
2722  u64 pxonrxc[8];
2723  u64 pxofftxc[8];
2724  u64 pxoffrxc[8];
2725  u64 prc64;
2726  u64 prc127;
2727  u64 prc255;
2728  u64 prc511;
2729  u64 prc1023;
2730  u64 prc1522;
2731  u64 gprc;
2732  u64 bprc;
2733  u64 mprc;
2734  u64 gptc;
2735  u64 gorc;
2736  u64 gotc;
2737  u64 rnbc[8];
2738  u64 ruc;
2739  u64 rfc;
2740  u64 roc;
2741  u64 rjc;
2742  u64 mngprc;
2743  u64 mngpdc;
2744  u64 mngptc;
2745  u64 tor;
2746  u64 tpr;
2747  u64 tpt;
2748  u64 ptc64;
2749  u64 ptc127;
2750  u64 ptc255;
2751  u64 ptc511;
2752  u64 ptc1023;
2753  u64 ptc1522;
2754  u64 mptc;
2755  u64 bptc;
2756  u64 xec;
2757  u64 rqsmr[16];
2758  u64 tqsmr[8];
2759  u64 qprc[16];
2760  u64 qptc[16];
2761  u64 qbrc[16];
2762  u64 qbtc[16];
2763  u64 qprdc[16];
2764  u64 pxon2offc[8];
2765  u64 fdirustat_add;
2766  u64 fdirustat_remove;
2767  u64 fdirfstat_fadd;
2768  u64 fdirfstat_fremove;
2769  u64 fdirmatch;
2770  u64 fdirmiss;
2771  u64 fccrc;
2772  u64 fcoerpdc;
2773  u64 fcoeprc;
2774  u64 fcoeptc;
2775  u64 fcoedwrc;
2776  u64 fcoedwtc;
2777  u64 fcoe_noddp;
2778  u64 fcoe_noddp_ext_buff;
2779  u64 b2ospc;
2780  u64 b2ogprc;
2781  u64 o2bgptc;
2782  u64 o2bspc;
2783 };
2784 
2785 /* forward declaration */
2786 struct ixgbe_hw;
2787 
2788 /* iterator type for walking multicast address lists */
2789 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2790  u32 *vmdq);
2791 
2792 /* Function pointer table */
2793 struct ixgbe_eeprom_operations {
2794  s32 (*init_params)(struct ixgbe_hw *);
2795  s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2796  s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2797  s32 (*write)(struct ixgbe_hw *, u16, u16);
2798  s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2799  s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2800  s32 (*update_checksum)(struct ixgbe_hw *);
2801  u16 (*calc_checksum)(struct ixgbe_hw *);
2802 };
2803 
2804 struct ixgbe_mac_operations {
2805  s32 (*init_hw)(struct ixgbe_hw *);
2806  s32 (*reset_hw)(struct ixgbe_hw *);
2807  s32 (*start_hw)(struct ixgbe_hw *);
2808  s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2809  enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2810  u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2811  s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2812  s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2813  s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2814  s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2815  s32 (*stop_adapter)(struct ixgbe_hw *);
2816  s32 (*get_bus_info)(struct ixgbe_hw *);
2817  void (*set_lan_id)(struct ixgbe_hw *);
2818  s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2819  s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2820  s32 (*setup_sfp)(struct ixgbe_hw *);
2821  s32 (*disable_rx_buff)(struct ixgbe_hw *);
2822  s32 (*enable_rx_buff)(struct ixgbe_hw *);
2823  s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2824  s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2825  void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2826 
2827  /* Link */
2828  void (*disable_tx_laser)(struct ixgbe_hw *);
2829  void (*enable_tx_laser)(struct ixgbe_hw *);
2830  void (*flap_tx_laser)(struct ixgbe_hw *);
2831  s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
2832  s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2833  s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2834  bool *);
2835 
2836  /* Packet Buffer Manipulation */
2837  void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
2838 
2839  /* LED */
2840  s32 (*led_on)(struct ixgbe_hw *, u32);
2841  s32 (*led_off)(struct ixgbe_hw *, u32);
2842  s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2843  s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2844 
2845  /* RAR, Multicast, VLAN */
2846  s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2847  s32 (*clear_rar)(struct ixgbe_hw *, u32);
2848  s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2849  s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
2850  s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2851  s32 (*init_rx_addrs)(struct ixgbe_hw *);
2852  s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
2853  s32 (*enable_mc)(struct ixgbe_hw *);
2854  s32 (*disable_mc)(struct ixgbe_hw *);
2855  s32 (*clear_vfta)(struct ixgbe_hw *);
2856  s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2857  s32 (*init_uta_tables)(struct ixgbe_hw *);
2858  void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
2859  void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
2860 
2861  /* Flow Control */
2862  s32 (*fc_enable)(struct ixgbe_hw *);
2863 
2864  /* Manageability interface */
2865  s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
2866  s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
2867  s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
2868 };
2869 
2870 struct ixgbe_phy_operations {
2871  s32 (*identify)(struct ixgbe_hw *);
2872  s32 (*identify_sfp)(struct ixgbe_hw *);
2873  s32 (*init)(struct ixgbe_hw *);
2874  s32 (*reset)(struct ixgbe_hw *);
2875  s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2876  s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
2877  s32 (*setup_link)(struct ixgbe_hw *);
2878  s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2879  bool);
2880  s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2881  s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2882  s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2883  s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2884  s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2885  s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2886  s32 (*check_overtemp)(struct ixgbe_hw *);
2887 };
2888 
2889 struct ixgbe_eeprom_info {
2890  struct ixgbe_eeprom_operations ops;
2891  enum ixgbe_eeprom_type type;
2892  u32 semaphore_delay;
2893  u16 word_size;
2894  u16 address_bits;
2895  u16 word_page_size;
2896 };
2897 
2898 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
2899 struct ixgbe_mac_info {
2900  struct ixgbe_mac_operations ops;
2901  enum ixgbe_mac_type type;
2902  u8 addr[ETH_ALEN];
2903  u8 perm_addr[ETH_ALEN];
2904  u8 san_addr[ETH_ALEN];
2905  /* prefix for World Wide Node Name (WWNN) */
2906  u16 wwnn_prefix;
2907  /* prefix for World Wide Port Name (WWPN) */
2908  u16 wwpn_prefix;
2909  u16 max_msix_vectors;
2910 #define IXGBE_MAX_MTA 128
2911  u32 mta_shadow[IXGBE_MAX_MTA];
2912  s32 mc_filter_type;
2913  u32 mcft_size;
2914  u32 vft_size;
2915  u32 num_rar_entries;
2916  u32 rar_highwater;
2917  u32 rx_pb_size;
2918  u32 max_tx_queues;
2919  u32 max_rx_queues;
2920  u32 orig_autoc;
2921  u32 orig_autoc2;
2922  bool orig_link_settings_stored;
2923  bool autotry_restart;
2924  u8 flags;
2925  u8 san_mac_rar_index;
2926  struct ixgbe_thermal_sensor_data thermal_sensor_data;
2927 };
2928 
2929 struct ixgbe_phy_info {
2930  struct ixgbe_phy_operations ops;
2931  struct mdio_if_info mdio;
2932  enum ixgbe_phy_type type;
2933  u32 id;
2934  enum ixgbe_sfp_type sfp_type;
2935  bool sfp_setup_needed;
2936  u32 revision;
2937  enum ixgbe_media_type media_type;
2938  bool reset_disable;
2939  ixgbe_autoneg_advertised autoneg_advertised;
2940  enum ixgbe_smart_speed smart_speed;
2941  bool smart_speed_active;
2942  bool multispeed_fiber;
2943  bool reset_if_overtemp;
2944 };
2945 
2946 #include "ixgbe_mbx.h"
2947 
2948 struct ixgbe_mbx_operations {
2949  s32 (*init_params)(struct ixgbe_hw *hw);
2950  s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
2951  s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
2952  s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2953  s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2954  s32 (*check_for_msg)(struct ixgbe_hw *, u16);
2955  s32 (*check_for_ack)(struct ixgbe_hw *, u16);
2956  s32 (*check_for_rst)(struct ixgbe_hw *, u16);
2957 };
2958 
2959 struct ixgbe_mbx_stats {
2960  u32 msgs_tx;
2961  u32 msgs_rx;
2962 
2963  u32 acks;
2964  u32 reqs;
2965  u32 rsts;
2966 };
2967 
2968 struct ixgbe_mbx_info {
2969  struct ixgbe_mbx_operations ops;
2970  struct ixgbe_mbx_stats stats;
2971  u32 timeout;
2972  u32 usec_delay;
2973  u32 v2p_mailbox;
2974  u16 size;
2975 };
2976 
2977 struct ixgbe_hw {
2978  u8 __iomem *hw_addr;
2979  void *back;
2980  struct ixgbe_mac_info mac;
2981  struct ixgbe_addr_filter_info addr_ctrl;
2982  struct ixgbe_fc_info fc;
2983  struct ixgbe_phy_info phy;
2984  struct ixgbe_eeprom_info eeprom;
2985  struct ixgbe_bus_info bus;
2986  struct ixgbe_mbx_info mbx;
2987  u16 device_id;
2988  u16 vendor_id;
2989  u16 subsystem_device_id;
2990  u16 subsystem_vendor_id;
2991  u8 revision_id;
2992  bool adapter_stopped;
2993  bool force_full_reset;
2994  bool allow_unsupported_sfp;
2995 };
2996 
2997 struct ixgbe_info {
2998  enum ixgbe_mac_type mac;
2999  s32 (*get_invariants)(struct ixgbe_hw *);
3000  struct ixgbe_mac_operations *mac_ops;
3001  struct ixgbe_eeprom_operations *eeprom_ops;
3002  struct ixgbe_phy_operations *phy_ops;
3003  struct ixgbe_mbx_operations *mbx_ops;
3004 };
3005 
3006 
3007 /* Error Codes */
3008 #define IXGBE_ERR_EEPROM -1
3009 #define IXGBE_ERR_EEPROM_CHECKSUM -2
3010 #define IXGBE_ERR_PHY -3
3011 #define IXGBE_ERR_CONFIG -4
3012 #define IXGBE_ERR_PARAM -5
3013 #define IXGBE_ERR_MAC_TYPE -6
3014 #define IXGBE_ERR_UNKNOWN_PHY -7
3015 #define IXGBE_ERR_LINK_SETUP -8
3016 #define IXGBE_ERR_ADAPTER_STOPPED -9
3017 #define IXGBE_ERR_INVALID_MAC_ADDR -10
3018 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
3019 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
3020 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
3021 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
3022 #define IXGBE_ERR_RESET_FAILED -15
3023 #define IXGBE_ERR_SWFW_SYNC -16
3024 #define IXGBE_ERR_PHY_ADDR_INVALID -17
3025 #define IXGBE_ERR_I2C -18
3026 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
3027 #define IXGBE_ERR_SFP_NOT_PRESENT -20
3028 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
3029 #define IXGBE_ERR_NO_SAN_ADDR_PTR -22
3030 #define IXGBE_ERR_FDIR_REINIT_FAILED -23
3031 #define IXGBE_ERR_EEPROM_VERSION -24
3032 #define IXGBE_ERR_NO_SPACE -25
3033 #define IXGBE_ERR_OVERTEMP -26
3034 #define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3035 #define IXGBE_ERR_FC_NOT_SUPPORTED -28
3036 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3037 #define IXGBE_ERR_PBA_SECTION -31
3038 #define IXGBE_ERR_INVALID_ARGUMENT -32
3039 #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3040 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3041 
3042 #endif /* _IXGBE_TYPE_H_ */
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