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ixj.c
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1 /****************************************************************************
2  * ixj.c
3  *
4  * Device Driver for Quicknet Technologies, Inc.'s Telephony cards
5  * including the Internet PhoneJACK, Internet PhoneJACK Lite,
6  * Internet PhoneJACK PCI, Internet LineJACK, Internet PhoneCARD and
7  * SmartCABLE
8  *
9  * (c) Copyright 1999-2001 Quicknet Technologies, Inc.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version
14  * 2 of the License, or (at your option) any later version.
15  *
16  * Author: Ed Okerson, <[email protected]>
17  *
18  * Contributors: Greg Herlein, <[email protected]>
19  * David W. Erhart, <[email protected]>
20  * John Sellers, <[email protected]>
21  * Mike Preston, <[email protected]>
22  *
23  * Fixes: David Huggins-Daines, <[email protected]>
24  * Fabio Ferrari, <[email protected]>
25  * Artis Kugevics, <[email protected]>
26  * Daniele Bellucci, <[email protected]>
27  *
28  * More information about the hardware related to this driver can be found
29  * at our website: http://www.quicknet.net
30  *
31  * IN NO EVENT SHALL QUICKNET TECHNOLOGIES, INC. BE LIABLE TO ANY PARTY FOR
32  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
33  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF QUICKNET
34  * TECHNOLOGIES, INC. HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  * QUICKNET TECHNOLOGIES, INC. SPECIFICALLY DISCLAIMS ANY WARRANTIES,
37  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
38  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
39  * ON AN "AS IS" BASIS, AND QUICKNET TECHNOLOGIES, INC. HAS NO OBLIGATION
40  * TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
41  *
42  ***************************************************************************/
43 
44 /*
45  * Revision 4.8 2003/07/09 19:39:00 Daniele Bellucci
46  * Audit some copy_*_user and minor cleanup.
47  *
48  * Revision 4.7 2001/08/13 06:19:33 craigs
49  * Added additional changes from Alan Cox and John Anderson for
50  * 2.2 to 2.4 cleanup and bounds checking
51  *
52  * Revision 4.6 2001/08/13 01:05:05 craigs
53  * Really fixed PHONE_QUERY_CODEC problem this time
54  *
55  * Revision 4.5 2001/08/13 00:11:03 craigs
56  * Fixed problem in handling of PHONE_QUERY_CODEC, thanks to Shane Anderson
57  *
58  * Revision 4.4 2001/08/07 07:58:12 craigs
59  * Changed back to three digit version numbers
60  * Added tagbuild target to allow automatic and easy tagging of versions
61  *
62  * Revision 4.3 2001/08/07 07:24:47 craigs
63  * Added ixj-ver.h to allow easy configuration management of driver
64  * Added display of version number in /prox/ixj
65  *
66  * Revision 4.2 2001/08/06 07:07:19 craigs
67  * Reverted IXJCTL_DSP_TYPE and IXJCTL_DSP_VERSION files to original
68  * behaviour of returning int rather than short *
69  *
70  * Revision 4.1 2001/08/05 00:17:37 craigs
71  * More changes for correct PCMCIA installation
72  * Start of changes for backward Linux compatibility
73  *
74  * Revision 4.0 2001/08/04 12:33:12 craigs
75  * New version using GNU autoconf
76  *
77  * Revision 3.105 2001/07/20 23:14:32 eokerson
78  * More work on CallerID generation when using ring cadences.
79  *
80  * Revision 3.104 2001/07/06 01:33:55 eokerson
81  * Some bugfixes from Robert Vojta <[email protected]> and a few mods to the Makefile.
82  *
83  * Revision 3.103 2001/07/05 19:20:16 eokerson
84  * Updated HOWTO
85  * Changed mic gain to 30dB on Internet LineJACK mic/speaker port.
86  *
87  * Revision 3.102 2001/07/03 23:51:21 eokerson
88  * Un-mute mic on Internet LineJACK when in speakerphone mode.
89  *
90  * Revision 3.101 2001/07/02 19:26:56 eokerson
91  * Removed initialiazation of ixjdebug and ixj_convert_loaded so they will go in the .bss instead of the .data
92  *
93  * Revision 3.100 2001/07/02 19:18:27 eokerson
94  * Changed driver to make dynamic allocation possible. We now pass IXJ * between functions instead of array indexes.
95  * Fixed the way the POTS and PSTN ports interact during a PSTN call to allow local answering.
96  * Fixed speaker mode on Internet LineJACK.
97  *
98  * Revision 3.99 2001/05/09 14:11:16 eokerson
99  * Fixed kmalloc error in ixj_build_filter_cadence. Thanks David Chan <[email protected]>.
100  *
101  * Revision 3.98 2001/05/08 19:55:33 eokerson
102  * Fixed POTS hookstate detection while it is connected to PSTN port.
103  *
104  * Revision 3.97 2001/05/08 00:01:04 eokerson
105  * Fixed kernel oops when sending caller ID data.
106  *
107  * Revision 3.96 2001/05/04 23:09:30 eokerson
108  * Now uses one kernel timer for each card, instead of one for the entire driver.
109  *
110  * Revision 3.95 2001/04/25 22:06:47 eokerson
111  * Fixed squawking at beginning of some G.723.1 calls.
112  *
113  * Revision 3.94 2001/04/03 23:42:00 eokerson
114  * Added linear volume ioctls
115  * Added raw filter load ioctl
116  *
117  * Revision 3.93 2001/02/27 01:00:06 eokerson
118  * Fixed blocking in CallerID.
119  * Reduced size of ixj structure for smaller driver footprint.
120  *
121  * Revision 3.92 2001/02/20 22:02:59 eokerson
122  * Fixed isapnp and pcmcia module compatibility for 2.4.x kernels.
123  * Improved PSTN ring detection.
124  * Fixed wink generation on POTS ports.
125  *
126  * Revision 3.91 2001/02/13 00:55:44 eokerson
127  * Turn AEC back on after changing frame sizes.
128  *
129  * Revision 3.90 2001/02/12 16:42:00 eokerson
130  * Added ALAW codec, thanks to Fabio Ferrari for the table based converters to make ALAW from ULAW.
131  *
132  * Revision 3.89 2001/02/12 15:41:16 eokerson
133  * Fix from Artis Kugevics - Tone gains were not being set correctly.
134  *
135  * Revision 3.88 2001/02/05 23:25:42 eokerson
136  * Fixed lockup bugs with deregister.
137  *
138  * Revision 3.87 2001/01/29 21:00:39 eokerson
139  * Fix from Fabio Ferrari <[email protected]> to properly handle EAGAIN and EINTR during non-blocking write.
140  * Updated copyright date.
141  *
142  * Revision 3.86 2001/01/23 23:53:46 eokerson
143  * Fixes to G.729 compatibility.
144  *
145  * Revision 3.85 2001/01/23 21:30:36 eokerson
146  * Added verbage about cards supported.
147  * Removed commands that put the card in low power mode at some times that it should not be in low power mode.
148  *
149  * Revision 3.84 2001/01/22 23:32:10 eokerson
150  * Some bugfixes from David Huggins-Daines, <[email protected]> and other cleanups.
151  *
152  * Revision 3.83 2001/01/19 14:51:41 eokerson
153  * Fixed ixj_WriteDSPCommand to decrement usage counter when command fails.
154  *
155  * Revision 3.82 2001/01/19 00:34:49 eokerson
156  * Added verbosity to write overlap errors.
157  *
158  * Revision 3.81 2001/01/18 23:56:54 eokerson
159  * Fixed PSTN line test functions.
160  *
161  * Revision 3.80 2001/01/18 22:29:27 eokerson
162  * Updated AEC/AGC values for different cards.
163  *
164  * Revision 3.79 2001/01/17 02:58:54 eokerson
165  * Fixed AEC reset after Caller ID.
166  * Fixed Codec lockup after Caller ID on Call Waiting when not using 30ms frames.
167  *
168  * Revision 3.78 2001/01/16 19:43:09 eokerson
169  * Added support for Linux 2.4.x kernels.
170  *
171  * Revision 3.77 2001/01/09 04:00:52 eokerson
172  * Linetest will now test the line, even if it has previously succeeded.
173  *
174  * Revision 3.76 2001/01/08 19:27:00 eokerson
175  * Fixed problem with standard cable on Internet PhoneCARD.
176  *
177  * Revision 3.75 2000/12/22 16:52:14 eokerson
178  * Modified to allow hookstate detection on the POTS port when the PSTN port is selected.
179  *
180  * Revision 3.74 2000/12/08 22:41:50 eokerson
181  * Added capability for G729B.
182  *
183  * Revision 3.73 2000/12/07 23:35:16 eokerson
184  * Added capability to have different ring pattern before CallerID data.
185  * Added hookstate checks in CallerID routines to stop FSK.
186  *
187  * Revision 3.72 2000/12/06 19:31:31 eokerson
188  * Modified signal behavior to only send one signal per event.
189  *
190  * Revision 3.71 2000/12/06 03:23:08 eokerson
191  * Fixed CallerID on Call Waiting.
192  *
193  * Revision 3.70 2000/12/04 21:29:37 eokerson
194  * Added checking to Smart Cable gain functions.
195  *
196  * Revision 3.69 2000/12/04 21:05:20 eokerson
197  * Changed ixjdebug levels.
198  * Added ioctls to change gains in Internet Phone CARD Smart Cable.
199  *
200  * Revision 3.68 2000/12/04 00:17:21 craigs
201  * Changed mixer voice gain to +6dB rather than 0dB
202  *
203  * Revision 3.67 2000/11/30 21:25:51 eokerson
204  * Fixed write signal errors.
205  *
206  * Revision 3.66 2000/11/29 22:42:44 eokerson
207  * Fixed PSTN ring detect problems.
208  *
209  * Revision 3.65 2000/11/29 07:31:55 craigs
210  * Added new 425Hz filter co-efficients
211  * Added card-specific DTMF prescaler initialisation
212  *
213  * Revision 3.64 2000/11/28 14:03:32 craigs
214  * Changed certain mixer initialisations to be 0dB rather than 12dB
215  * Added additional information to /proc/ixj
216  *
217  * Revision 3.63 2000/11/28 11:38:41 craigs
218  * Added display of AEC modes in AUTO and AGC mode
219  *
220  * Revision 3.62 2000/11/28 04:05:44 eokerson
221  * Improved PSTN ring detection routine.
222  *
223  * Revision 3.61 2000/11/27 21:53:12 eokerson
224  * Fixed flash detection.
225  *
226  * Revision 3.60 2000/11/27 15:57:29 eokerson
227  * More work on G.729 load routines.
228  *
229  * Revision 3.59 2000/11/25 21:55:12 eokerson
230  * Fixed errors in G.729 load routine.
231  *
232  * Revision 3.58 2000/11/25 04:08:29 eokerson
233  * Added board locks around G.729 and TS85 load routines.
234  *
235  * Revision 3.57 2000/11/24 05:35:17 craigs
236  * Added ability to retrieve mixer values on LineJACK
237  * Added complete initialisation of all mixer values at startup
238  * Fixed spelling mistake
239  *
240  * Revision 3.56 2000/11/23 02:52:11 robertj
241  * Added cvs change log keyword.
242  * Fixed bug in capabilities list when using G.729 module.
243  *
244  */
245 
246 #include "ixj-ver.h"
247 
248 #define PERFMON_STATS
249 #define IXJDEBUG 0
250 #define MAXRINGS 5
251 
252 #include <linux/module.h>
253 
254 #include <linux/init.h>
255 #include <linux/sched.h>
256 #include <linux/kernel.h> /* printk() */
257 #include <linux/fs.h> /* everything... */
258 #include <linux/errno.h> /* error codes */
259 #include <linux/slab.h>
260 #include <linux/mutex.h>
261 #include <linux/mm.h>
262 #include <linux/ioport.h>
263 #include <linux/interrupt.h>
264 #include <linux/proc_fs.h>
265 #include <linux/poll.h>
266 #include <linux/timer.h>
267 #include <linux/delay.h>
268 #include <linux/pci.h>
269 
270 #include <asm/io.h>
271 #include <asm/uaccess.h>
272 
273 #include <linux/isapnp.h>
274 
275 #include "ixj.h"
276 
277 #define TYPE(inode) (iminor(inode) >> 4)
278 #define NUM(inode) (iminor(inode) & 0xf)
279 
280 static DEFINE_MUTEX(ixj_mutex);
281 static int ixjdebug;
282 static int hertz = HZ;
283 static int samplerate = 100;
284 
285 module_param(ixjdebug, int, 0);
286 
287 static DEFINE_PCI_DEVICE_TABLE(ixj_pci_tbl) = {
289  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
290  { }
291 };
292 MODULE_DEVICE_TABLE(pci, ixj_pci_tbl);
293 
294 /************************************************************************
295 *
296 * ixjdebug meanings are now bit mapped instead of level based
297 * Values can be or'ed together to turn on multiple messages
298 *
299 * bit 0 (0x0001) = any failure
300 * bit 1 (0x0002) = general messages
301 * bit 2 (0x0004) = POTS ringing related
302 * bit 3 (0x0008) = PSTN events
303 * bit 4 (0x0010) = PSTN Cadence state details
304 * bit 5 (0x0020) = Tone detection triggers
305 * bit 6 (0x0040) = Tone detection cadence details
306 * bit 7 (0x0080) = ioctl tracking
307 * bit 8 (0x0100) = signal tracking
308 * bit 9 (0x0200) = CallerID generation details
309 *
310 ************************************************************************/
311 
312 #ifdef IXJ_DYN_ALLOC
313 
314 static IXJ *ixj[IXJMAX];
315 #define get_ixj(b) ixj[(b)]
316 
317 /*
318  * Allocate a free IXJ device
319  */
320 
321 static IXJ *ixj_alloc()
322 {
323  for(cnt=0; cnt<IXJMAX; cnt++)
324  {
325  if(ixj[cnt] == NULL || !ixj[cnt]->DSPbase)
326  {
327  j = kmalloc(sizeof(IXJ), GFP_KERNEL);
328  if (j == NULL)
329  return NULL;
330  ixj[cnt] = j;
331  return j;
332  }
333  }
334  return NULL;
335 }
336 
337 static void ixj_fsk_free(IXJ *j)
338 {
339  kfree(j->fskdata);
340  j->fskdata = NULL;
341 }
342 
343 static void ixj_fsk_alloc(IXJ *j)
344 {
345  if(!j->fskdata) {
346  j->fskdata = kmalloc(8000, GFP_KERNEL);
347  if (!j->fskdata) {
348  if(ixjdebug & 0x0200) {
349  printk("IXJ phone%d - allocate failed\n", j->board);
350  }
351  return;
352  } else {
353  j->fsksize = 8000;
354  if(ixjdebug & 0x0200) {
355  printk("IXJ phone%d - allocate succeeded\n", j->board);
356  }
357  }
358  }
359 }
360 
361 #else
362 
363 static IXJ ixj[IXJMAX];
364 #define get_ixj(b) (&ixj[(b)])
365 
366 /*
367  * Allocate a free IXJ device
368  */
369 
370 static IXJ *ixj_alloc(void)
371 {
372  int cnt;
373  for(cnt=0; cnt<IXJMAX; cnt++) {
374  if(!ixj[cnt].DSPbase)
375  return &ixj[cnt];
376  }
377  return NULL;
378 }
379 
380 static inline void ixj_fsk_free(IXJ *j) {;}
381 
382 static inline void ixj_fsk_alloc(IXJ *j)
383 {
384  j->fsksize = 8000;
385 }
386 
387 #endif
388 
389 #ifdef PERFMON_STATS
390 #define ixj_perfmon(x) ((x)++)
391 #else
392 #define ixj_perfmon(x) do { } while(0)
393 #endif
394 
395 static int ixj_convert_loaded;
396 
397 static int ixj_WriteDSPCommand(unsigned short, IXJ *j);
398 
399 /************************************************************************
400 *
401 * These are function definitions to allow external modules to register
402 * enhanced functionality call backs.
403 *
404 ************************************************************************/
405 
406 static int Stub(IXJ * J, unsigned long arg)
407 {
408  return 0;
409 }
410 
411 static IXJ_REGFUNC ixj_PreRead = &Stub;
412 static IXJ_REGFUNC ixj_PostRead = &Stub;
413 static IXJ_REGFUNC ixj_PreWrite = &Stub;
414 static IXJ_REGFUNC ixj_PostWrite = &Stub;
415 
416 static void ixj_read_frame(IXJ *j);
417 static void ixj_write_frame(IXJ *j);
418 static void ixj_init_timer(IXJ *j);
419 static void ixj_add_timer(IXJ * j);
420 static void ixj_timeout(unsigned long ptr);
421 static int read_filters(IXJ *j);
422 static int LineMonitor(IXJ *j);
423 static int ixj_fasync(int fd, struct file *, int mode);
424 static int ixj_set_port(IXJ *j, int arg);
425 static int ixj_set_pots(IXJ *j, int arg);
426 static int ixj_hookstate(IXJ *j);
427 static int ixj_record_start(IXJ *j);
428 static void ixj_record_stop(IXJ *j);
429 static void set_rec_volume(IXJ *j, int volume);
430 static int get_rec_volume(IXJ *j);
431 static int set_rec_codec(IXJ *j, int rate);
432 static void ixj_vad(IXJ *j, int arg);
433 static int ixj_play_start(IXJ *j);
434 static void ixj_play_stop(IXJ *j);
435 static int ixj_set_tone_on(unsigned short arg, IXJ *j);
436 static int ixj_set_tone_off(unsigned short, IXJ *j);
437 static int ixj_play_tone(IXJ *j, char tone);
438 static void ixj_aec_start(IXJ *j, int level);
439 static int idle(IXJ *j);
440 static void ixj_ring_on(IXJ *j);
441 static void ixj_ring_off(IXJ *j);
442 static void aec_stop(IXJ *j);
443 static void ixj_ringback(IXJ *j);
444 static void ixj_busytone(IXJ *j);
445 static void ixj_dialtone(IXJ *j);
446 static void ixj_cpt_stop(IXJ *j);
447 static char daa_int_read(IXJ *j);
448 static char daa_CR_read(IXJ *j, int cr);
449 static int daa_set_mode(IXJ *j, int mode);
450 static int ixj_linetest(IXJ *j);
451 static int ixj_daa_write(IXJ *j);
452 static int ixj_daa_cid_read(IXJ *j);
453 static void DAA_Coeff_US(IXJ *j);
454 static void DAA_Coeff_UK(IXJ *j);
455 static void DAA_Coeff_France(IXJ *j);
456 static void DAA_Coeff_Germany(IXJ *j);
457 static void DAA_Coeff_Australia(IXJ *j);
458 static void DAA_Coeff_Japan(IXJ *j);
459 static int ixj_init_filter(IXJ *j, IXJ_FILTER * jf);
460 static int ixj_init_filter_raw(IXJ *j, IXJ_FILTER_RAW * jfr);
461 static int ixj_init_tone(IXJ *j, IXJ_TONE * ti);
462 static int ixj_build_cadence(IXJ *j, IXJ_CADENCE __user * cp);
463 static int ixj_build_filter_cadence(IXJ *j, IXJ_FILTER_CADENCE __user * cp);
464 /* Serial Control Interface funtions */
465 static int SCI_Control(IXJ *j, int control);
466 static int SCI_Prepare(IXJ *j);
467 static int SCI_WaitHighSCI(IXJ *j);
468 static int SCI_WaitLowSCI(IXJ *j);
469 static DWORD PCIEE_GetSerialNumber(WORD wAddress);
470 static int ixj_PCcontrol_wait(IXJ *j);
471 static void ixj_pre_cid(IXJ *j);
472 static void ixj_write_cid(IXJ *j);
473 static void ixj_write_cid_bit(IXJ *j, int bit);
474 static int set_base_frame(IXJ *j, int size);
475 static int set_play_codec(IXJ *j, int rate);
476 static void set_rec_depth(IXJ *j, int depth);
477 static int ixj_mixer(long val, IXJ *j);
478 
479 /************************************************************************
480 CT8020/CT8021 Host Programmers Model
481 Host address Function Access
482 DSPbase +
483 0-1 Aux Software Status Register (reserved) Read Only
484 2-3 Software Status Register Read Only
485 4-5 Aux Software Control Register (reserved) Read Write
486 6-7 Software Control Register Read Write
487 8-9 Hardware Status Register Read Only
488 A-B Hardware Control Register Read Write
489 C-D Host Transmit (Write) Data Buffer Access Port (buffer input)Write Only
490 E-F Host Receive (Read) Data Buffer Access Port (buffer input) Read Only
491 ************************************************************************/
492 
493 static inline void ixj_read_HSR(IXJ *j)
494 {
495  j->hsr.bytes.low = inb_p(j->DSPbase + 8);
496  j->hsr.bytes.high = inb_p(j->DSPbase + 9);
497 }
498 
499 static inline int IsControlReady(IXJ *j)
500 {
501  ixj_read_HSR(j);
502  return j->hsr.bits.controlrdy ? 1 : 0;
503 }
504 
505 static inline int IsPCControlReady(IXJ *j)
506 {
507  j->pccr1.byte = inb_p(j->XILINXbase + 3);
508  return j->pccr1.bits.crr ? 1 : 0;
509 }
510 
511 static inline int IsStatusReady(IXJ *j)
512 {
513  ixj_read_HSR(j);
514  return j->hsr.bits.statusrdy ? 1 : 0;
515 }
516 
517 static inline int IsRxReady(IXJ *j)
518 {
519  ixj_read_HSR(j);
521  return j->hsr.bits.rxrdy ? 1 : 0;
522 }
523 
524 static inline int IsTxReady(IXJ *j)
525 {
526  ixj_read_HSR(j);
528  return j->hsr.bits.txrdy ? 1 : 0;
529 }
530 
531 static inline void set_play_volume(IXJ *j, int volume)
532 {
533  if (ixjdebug & 0x0002)
534  printk(KERN_INFO "IXJ: /dev/phone%d Setting Play Volume to 0x%4.4x\n", j->board, volume);
535  ixj_WriteDSPCommand(0xCF02, j);
536  ixj_WriteDSPCommand(volume, j);
537 }
538 
539 static int set_play_volume_linear(IXJ *j, int volume)
540 {
541  int newvolume, dspplaymax;
542 
543  if (ixjdebug & 0x0002)
544  printk(KERN_INFO "IXJ: /dev/phone %d Setting Linear Play Volume to 0x%4.4x\n", j->board, volume);
545  if(volume > 100 || volume < 0) {
546  return -1;
547  }
548 
549  /* This should normalize the perceived volumes between the different cards caused by differences in the hardware */
550  switch (j->cardtype) {
551  case QTI_PHONEJACK:
552  dspplaymax = 0x380;
553  break;
554  case QTI_LINEJACK:
555  if(j->port == PORT_PSTN) {
556  dspplaymax = 0x48;
557  } else {
558  dspplaymax = 0x100;
559  }
560  break;
561  case QTI_PHONEJACK_LITE:
562  dspplaymax = 0x380;
563  break;
564  case QTI_PHONEJACK_PCI:
565  dspplaymax = 0x6C;
566  break;
567  case QTI_PHONECARD:
568  dspplaymax = 0x50;
569  break;
570  default:
571  return -1;
572  }
573  newvolume = (dspplaymax * volume) / 100;
574  set_play_volume(j, newvolume);
575  return 0;
576 }
577 
578 static inline void set_play_depth(IXJ *j, int depth)
579 {
580  if (depth > 60)
581  depth = 60;
582  if (depth < 0)
583  depth = 0;
584  ixj_WriteDSPCommand(0x5280 + depth, j);
585 }
586 
587 static inline int get_play_volume(IXJ *j)
588 {
589  ixj_WriteDSPCommand(0xCF00, j);
590  return j->ssr.high << 8 | j->ssr.low;
591 }
592 
593 static int get_play_volume_linear(IXJ *j)
594 {
595  int volume, newvolume, dspplaymax;
596 
597  /* This should normalize the perceived volumes between the different cards caused by differences in the hardware */
598  switch (j->cardtype) {
599  case QTI_PHONEJACK:
600  dspplaymax = 0x380;
601  break;
602  case QTI_LINEJACK:
603  if(j->port == PORT_PSTN) {
604  dspplaymax = 0x48;
605  } else {
606  dspplaymax = 0x100;
607  }
608  break;
609  case QTI_PHONEJACK_LITE:
610  dspplaymax = 0x380;
611  break;
612  case QTI_PHONEJACK_PCI:
613  dspplaymax = 0x6C;
614  break;
615  case QTI_PHONECARD:
616  dspplaymax = 100;
617  break;
618  default:
619  return -1;
620  }
621  volume = get_play_volume(j);
622  newvolume = (volume * 100) / dspplaymax;
623  if(newvolume > 100)
624  newvolume = 100;
625  return newvolume;
626 }
627 
628 static inline BYTE SLIC_GetState(IXJ *j)
629 {
630  if (j->cardtype == QTI_PHONECARD) {
631  j->pccr1.byte = 0;
632  j->psccr.bits.dev = 3;
633  j->psccr.bits.rw = 1;
634  outw_p(j->psccr.byte << 8, j->XILINXbase + 0x00);
635  ixj_PCcontrol_wait(j);
636  j->pslic.byte = inw_p(j->XILINXbase + 0x00) & 0xFF;
637  ixj_PCcontrol_wait(j);
638  if (j->pslic.bits.powerdown)
639  return PLD_SLIC_STATE_OC;
640  else if (!j->pslic.bits.ring0 && !j->pslic.bits.ring1)
641  return PLD_SLIC_STATE_ACTIVE;
642  else
643  return PLD_SLIC_STATE_RINGING;
644  } else {
645  j->pld_slicr.byte = inb_p(j->XILINXbase + 0x01);
646  }
647  return j->pld_slicr.bits.state;
648 }
649 
650 static bool SLIC_SetState(BYTE byState, IXJ *j)
651 {
652  bool fRetVal = false;
653 
654  if (j->cardtype == QTI_PHONECARD) {
655  if (j->flags.pcmciasct) {
656  switch (byState) {
658  case PLD_SLIC_STATE_OC:
659  j->pslic.bits.powerdown = 1;
660  j->pslic.bits.ring0 = j->pslic.bits.ring1 = 0;
661  fRetVal = true;
662  break;
664  if (j->readers || j->writers) {
665  j->pslic.bits.powerdown = 0;
666  j->pslic.bits.ring0 = 1;
667  j->pslic.bits.ring1 = 0;
668  fRetVal = true;
669  }
670  break;
671  case PLD_SLIC_STATE_OHT: /* On-hook transmit */
672 
675  if (j->readers || j->writers) {
676  j->pslic.bits.powerdown = 0;
677  } else {
678  j->pslic.bits.powerdown = 1;
679  }
680  j->pslic.bits.ring0 = j->pslic.bits.ring1 = 0;
681  fRetVal = true;
682  break;
683  case PLD_SLIC_STATE_APR: /* Active polarity reversal */
684 
685  case PLD_SLIC_STATE_OHTPR: /* OHT polarity reversal */
686 
687  default:
688  fRetVal = false;
689  break;
690  }
691  j->psccr.bits.dev = 3;
692  j->psccr.bits.rw = 0;
693  outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
694  ixj_PCcontrol_wait(j);
695  }
696  } else {
697  /* Set the C1, C2, C3 & B2EN signals. */
698  switch (byState) {
699  case PLD_SLIC_STATE_OC:
700  j->pld_slicw.bits.c1 = 0;
701  j->pld_slicw.bits.c2 = 0;
702  j->pld_slicw.bits.c3 = 0;
703  j->pld_slicw.bits.b2en = 0;
704  outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
705  fRetVal = true;
706  break;
708  j->pld_slicw.bits.c1 = 1;
709  j->pld_slicw.bits.c2 = 0;
710  j->pld_slicw.bits.c3 = 0;
711  j->pld_slicw.bits.b2en = 1;
712  outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
713  fRetVal = true;
714  break;
716  j->pld_slicw.bits.c1 = 0;
717  j->pld_slicw.bits.c2 = 1;
718  j->pld_slicw.bits.c3 = 0;
719  j->pld_slicw.bits.b2en = 0;
720  outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
721  fRetVal = true;
722  break;
723  case PLD_SLIC_STATE_OHT: /* On-hook transmit */
724 
725  j->pld_slicw.bits.c1 = 1;
726  j->pld_slicw.bits.c2 = 1;
727  j->pld_slicw.bits.c3 = 0;
728  j->pld_slicw.bits.b2en = 0;
729  outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
730  fRetVal = true;
731  break;
733  j->pld_slicw.bits.c1 = 0;
734  j->pld_slicw.bits.c2 = 0;
735  j->pld_slicw.bits.c3 = 1;
736  j->pld_slicw.bits.b2en = 0;
737  outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
738  fRetVal = true;
739  break;
741  j->pld_slicw.bits.c1 = 1;
742  j->pld_slicw.bits.c2 = 0;
743  j->pld_slicw.bits.c3 = 1;
744  j->pld_slicw.bits.b2en = 1;
745  outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
746  fRetVal = true;
747  break;
748  case PLD_SLIC_STATE_APR: /* Active polarity reversal */
749 
750  j->pld_slicw.bits.c1 = 0;
751  j->pld_slicw.bits.c2 = 1;
752  j->pld_slicw.bits.c3 = 1;
753  j->pld_slicw.bits.b2en = 0;
754  outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
755  fRetVal = true;
756  break;
757  case PLD_SLIC_STATE_OHTPR: /* OHT polarity reversal */
758 
759  j->pld_slicw.bits.c1 = 1;
760  j->pld_slicw.bits.c2 = 1;
761  j->pld_slicw.bits.c3 = 1;
762  j->pld_slicw.bits.b2en = 0;
763  outb_p(j->pld_slicw.byte, j->XILINXbase + 0x01);
764  fRetVal = true;
765  break;
766  default:
767  fRetVal = false;
768  break;
769  }
770  }
771 
772  return fRetVal;
773 }
774 
775 static int ixj_wink(IXJ *j)
776 {
777  BYTE slicnow;
778 
779  slicnow = SLIC_GetState(j);
780 
781  j->pots_winkstart = jiffies;
782  SLIC_SetState(PLD_SLIC_STATE_OC, j);
783 
785 
786  SLIC_SetState(slicnow, j);
787  return 0;
788 }
789 
790 static void ixj_init_timer(IXJ *j)
791 {
792  init_timer(&j->timer);
793  j->timer.function = ixj_timeout;
794  j->timer.data = (unsigned long)j;
795 }
796 
797 static void ixj_add_timer(IXJ *j)
798 {
799  j->timer.expires = jiffies + (hertz / samplerate);
800  add_timer(&j->timer);
801 }
802 
803 static void ixj_tone_timeout(IXJ *j)
804 {
805  IXJ_TONE ti;
806 
807  j->tone_state++;
808  if (j->tone_state == 3) {
809  j->tone_state = 0;
810  if (j->cadence_t) {
811  j->tone_cadence_state++;
813  switch (j->cadence_t->termination) {
814  case PLAY_ONCE:
815  ixj_cpt_stop(j);
816  break;
817  case REPEAT_LAST_ELEMENT:
818  j->tone_cadence_state--;
819  ixj_play_tone(j, j->cadence_t->ce[j->tone_cadence_state].index);
820  break;
821  case REPEAT_ALL:
822  j->tone_cadence_state = 0;
823  if (j->cadence_t->ce[j->tone_cadence_state].freq0) {
829  ixj_init_tone(j, &ti);
830  }
831  ixj_set_tone_on(j->cadence_t->ce[0].tone_on_time, j);
832  ixj_set_tone_off(j->cadence_t->ce[0].tone_off_time, j);
833  ixj_play_tone(j, j->cadence_t->ce[0].index);
834  break;
835  }
836  } else {
837  if (j->cadence_t->ce[j->tone_cadence_state].gain0) {
843  ixj_init_tone(j, &ti);
844  }
845  ixj_set_tone_on(j->cadence_t->ce[j->tone_cadence_state].tone_on_time, j);
846  ixj_set_tone_off(j->cadence_t->ce[j->tone_cadence_state].tone_off_time, j);
847  ixj_play_tone(j, j->cadence_t->ce[j->tone_cadence_state].index);
848  }
849  }
850  }
851 }
852 
853 static inline void ixj_kill_fasync(IXJ *j, IXJ_SIGEVENT event, int dir)
854 {
855  if(j->ixj_signals[event]) {
856  if(ixjdebug & 0x0100)
857  printk("Sending signal for event %d\n", event);
858  /* Send apps notice of change */
859  /* see config.h for macro definition */
860  kill_fasync(&(j->async_queue), j->ixj_signals[event], dir);
861  }
862 }
863 
864 static void ixj_pstn_state(IXJ *j)
865 {
866  int var;
867  union XOPXR0 XR0, daaint;
868 
869  var = 10;
870 
871  XR0.reg = j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.reg;
872  daaint.reg = 0;
873  XR0.bitreg.RMR = j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR;
874 
875  j->pld_scrr.byte = inb_p(j->XILINXbase);
876  if (j->pld_scrr.bits.daaflag) {
877  daa_int_read(j);
878  if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.RING) {
879  if(time_after(jiffies, j->pstn_sleeptil) && !(j->flags.pots_pstn && j->hookstate)) {
880  daaint.bitreg.RING = 1;
881  if(ixjdebug & 0x0008) {
882  printk(KERN_INFO "IXJ DAA Ring Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
883  }
884  } else {
885  daa_set_mode(j, SOP_PU_RESET);
886  }
887  }
888  if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.Caller_ID) {
889  daaint.bitreg.Caller_ID = 1;
890  j->pstn_cid_intr = 1;
892  if(ixjdebug & 0x0008) {
893  printk(KERN_INFO "IXJ DAA Caller_ID Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
894  }
895  }
896  if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.Cadence) {
897  daaint.bitreg.Cadence = 1;
898  if(ixjdebug & 0x0008) {
899  printk(KERN_INFO "IXJ DAA Cadence Interrupt /dev/phone%d at %ld\n", j->board, jiffies);
900  }
901  }
902  if(j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.VDD_OK != XR0.bitreg.VDD_OK) {
903  daaint.bitreg.VDD_OK = 1;
904  daaint.bitreg.SI_0 = j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.bitreg.VDD_OK;
905  }
906  }
907  daa_CR_read(j, 1);
908  if(j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR != XR0.bitreg.RMR && time_after(jiffies, j->pstn_sleeptil) && !(j->flags.pots_pstn && j->hookstate)) {
909  daaint.bitreg.RMR = 1;
910  daaint.bitreg.SI_1 = j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.bitreg.RMR;
911  if(ixjdebug & 0x0008) {
912  printk(KERN_INFO "IXJ DAA RMR /dev/phone%d was %s for %ld\n", j->board, XR0.bitreg.RMR?"on":"off", jiffies - j->pstn_last_rmr);
913  }
915  j->pstn_last_rmr = jiffies;
916  }
917  switch(j->daa_mode) {
918  case SOP_PU_SLEEP:
919  if (daaint.bitreg.RING) {
920  if (!j->flags.pstn_ringing) {
921  if (j->daa_mode != SOP_PU_RINGING) {
922  j->pstn_ring_int = jiffies;
923  daa_set_mode(j, SOP_PU_RINGING);
924  }
925  }
926  }
927  break;
928  case SOP_PU_RINGING:
929  if (daaint.bitreg.RMR) {
930  if (ixjdebug & 0x0008) {
931  printk(KERN_INFO "IXJ Ring Cadence a state = %d /dev/phone%d at %ld\n", j->cadence_f[4].state, j->board, jiffies);
932  }
933  if (daaint.bitreg.SI_1) { /* Rising edge of RMR */
934  j->flags.pstn_rmr = 1;
936  j->pstn_ring_stop = 0;
937  j->ex.bits.pstn_ring = 0;
938  if (j->cadence_f[4].state == 0) {
939  j->cadence_f[4].state = 1;
940  j->cadence_f[4].on1min = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100 - var)) / 10000);
941  j->cadence_f[4].on1dot = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100)) / 10000);
942  j->cadence_f[4].on1max = jiffies + (long)((j->cadence_f[4].on1 * hertz * (100 + var)) / 10000);
943  } else if (j->cadence_f[4].state == 2) {
944  if((time_after(jiffies, j->cadence_f[4].off1min) &&
945  time_before(jiffies, j->cadence_f[4].off1max))) {
946  if (j->cadence_f[4].on2) {
947  j->cadence_f[4].state = 3;
948  j->cadence_f[4].on2min = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100 - var)) / 10000));
949  j->cadence_f[4].on2dot = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100)) / 10000));
950  j->cadence_f[4].on2max = jiffies + (long)((j->cadence_f[4].on2 * (hertz * (100 + var)) / 10000));
951  } else {
952  j->cadence_f[4].state = 7;
953  }
954  } else {
955  if (ixjdebug & 0x0008) {
956  printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
957  j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
958  j->cadence_f[4].off1);
959  }
960  j->cadence_f[4].state = 0;
961  }
962  } else if (j->cadence_f[4].state == 4) {
963  if((time_after(jiffies, j->cadence_f[4].off2min) &&
964  time_before(jiffies, j->cadence_f[4].off2max))) {
965  if (j->cadence_f[4].on3) {
966  j->cadence_f[4].state = 5;
967  j->cadence_f[4].on3min = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100 - var)) / 10000));
968  j->cadence_f[4].on3dot = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100)) / 10000));
969  j->cadence_f[4].on3max = jiffies + (long)((j->cadence_f[4].on3 * (hertz * (100 + var)) / 10000));
970  } else {
971  j->cadence_f[4].state = 7;
972  }
973  } else {
974  if (ixjdebug & 0x0008) {
975  printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
976  j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
977  j->cadence_f[4].off2);
978  }
979  j->cadence_f[4].state = 0;
980  }
981  } else if (j->cadence_f[4].state == 6) {
982  if((time_after(jiffies, j->cadence_f[4].off3min) &&
983  time_before(jiffies, j->cadence_f[4].off3max))) {
984  j->cadence_f[4].state = 7;
985  } else {
986  if (ixjdebug & 0x0008) {
987  printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
988  j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
989  j->cadence_f[4].off3);
990  }
991  j->cadence_f[4].state = 0;
992  }
993  } else {
994  j->cadence_f[4].state = 0;
995  }
996  } else { /* Falling edge of RMR */
997  j->pstn_ring_start = 0;
998  j->pstn_ring_stop = jiffies;
999  if (j->cadence_f[4].state == 1) {
1000  if(!j->cadence_f[4].on1) {
1001  j->cadence_f[4].state = 7;
1002  } else if((time_after(jiffies, j->cadence_f[4].on1min) &&
1003  time_before(jiffies, j->cadence_f[4].on1max))) {
1004  if (j->cadence_f[4].off1) {
1005  j->cadence_f[4].state = 2;
1006  j->cadence_f[4].off1min = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100 - var)) / 10000));
1007  j->cadence_f[4].off1dot = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100)) / 10000));
1008  j->cadence_f[4].off1max = jiffies + (long)((j->cadence_f[4].off1 * (hertz * (100 + var)) / 10000));
1009  } else {
1010  j->cadence_f[4].state = 7;
1011  }
1012  } else {
1013  if (ixjdebug & 0x0008) {
1014  printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1015  j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1016  j->cadence_f[4].on1);
1017  }
1018  j->cadence_f[4].state = 0;
1019  }
1020  } else if (j->cadence_f[4].state == 3) {
1021  if((time_after(jiffies, j->cadence_f[4].on2min) &&
1022  time_before(jiffies, j->cadence_f[4].on2max))) {
1023  if (j->cadence_f[4].off2) {
1024  j->cadence_f[4].state = 4;
1025  j->cadence_f[4].off2min = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100 - var)) / 10000));
1026  j->cadence_f[4].off2dot = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100)) / 10000));
1027  j->cadence_f[4].off2max = jiffies + (long)((j->cadence_f[4].off2 * (hertz * (100 + var)) / 10000));
1028  } else {
1029  j->cadence_f[4].state = 7;
1030  }
1031  } else {
1032  if (ixjdebug & 0x0008) {
1033  printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1034  j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1035  j->cadence_f[4].on2);
1036  }
1037  j->cadence_f[4].state = 0;
1038  }
1039  } else if (j->cadence_f[4].state == 5) {
1040  if((time_after(jiffies, j->cadence_f[4].on3min) &&
1041  time_before(jiffies, j->cadence_f[4].on3max))) {
1042  if (j->cadence_f[4].off3) {
1043  j->cadence_f[4].state = 6;
1044  j->cadence_f[4].off3min = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100 - var)) / 10000));
1045  j->cadence_f[4].off3dot = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100)) / 10000));
1046  j->cadence_f[4].off3max = jiffies + (long)((j->cadence_f[4].off3 * (hertz * (100 + var)) / 10000));
1047  } else {
1048  j->cadence_f[4].state = 7;
1049  }
1050  } else {
1051  j->cadence_f[4].state = 0;
1052  }
1053  } else {
1054  if (ixjdebug & 0x0008) {
1055  printk(KERN_INFO "IXJ Ring Cadence fail state = %d /dev/phone%d at %ld should be %d\n",
1056  j->cadence_f[4].state, j->board, jiffies - j->pstn_prev_rmr,
1057  j->cadence_f[4].on3);
1058  }
1059  j->cadence_f[4].state = 0;
1060  }
1061  }
1062  if (ixjdebug & 0x0010) {
1063  printk(KERN_INFO "IXJ Ring Cadence b state = %d /dev/phone%d at %ld\n", j->cadence_f[4].state, j->board, jiffies);
1064  }
1065  if (ixjdebug & 0x0010) {
1066  switch(j->cadence_f[4].state) {
1067  case 1:
1068  printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1069  j->cadence_f[4].on1, j->cadence_f[4].on1min, j->cadence_f[4].on1dot, j->cadence_f[4].on1max);
1070  break;
1071  case 2:
1072  printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1073  j->cadence_f[4].off1, j->cadence_f[4].off1min, j->cadence_f[4].off1dot, j->cadence_f[4].off1max);
1074  break;
1075  case 3:
1076  printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1077  j->cadence_f[4].on2, j->cadence_f[4].on2min, j->cadence_f[4].on2dot, j->cadence_f[4].on2max);
1078  break;
1079  case 4:
1080  printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1081  j->cadence_f[4].off2, j->cadence_f[4].off2min, j->cadence_f[4].off2dot, j->cadence_f[4].off2max);
1082  break;
1083  case 5:
1084  printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1085  j->cadence_f[4].on3, j->cadence_f[4].on3min, j->cadence_f[4].on3dot, j->cadence_f[4].on3max);
1086  break;
1087  case 6:
1088  printk(KERN_INFO "IXJ /dev/phone%d Next Ring Cadence state at %u min %ld - %ld - max %ld\n", j->board,
1089  j->cadence_f[4].off3, j->cadence_f[4].off3min, j->cadence_f[4].off3dot, j->cadence_f[4].off3max);
1090  break;
1091  }
1092  }
1093  }
1094  if (j->cadence_f[4].state == 7) {
1095  j->cadence_f[4].state = 0;
1096  j->pstn_ring_stop = jiffies;
1097  j->ex.bits.pstn_ring = 1;
1098  ixj_kill_fasync(j, SIG_PSTN_RING, POLL_IN);
1099  if(ixjdebug & 0x0008) {
1100  printk(KERN_INFO "IXJ Ring int set /dev/phone%d at %ld\n", j->board, jiffies);
1101  }
1102  }
1103  if((j->pstn_ring_int != 0 && time_after(jiffies, j->pstn_ring_int + (hertz * 5)) && !j->flags.pstn_rmr) ||
1104  (j->pstn_ring_stop != 0 && time_after(jiffies, j->pstn_ring_stop + (hertz * 5)))) {
1105  if(ixjdebug & 0x0008) {
1106  printk("IXJ DAA no ring in 5 seconds /dev/phone%d at %ld\n", j->board, jiffies);
1107  printk("IXJ DAA pstn ring int /dev/phone%d at %ld\n", j->board, j->pstn_ring_int);
1108  printk("IXJ DAA pstn ring stop /dev/phone%d at %ld\n", j->board, j->pstn_ring_stop);
1109  }
1110  j->pstn_ring_stop = j->pstn_ring_int = 0;
1111  daa_set_mode(j, SOP_PU_SLEEP);
1112  }
1113  outb_p(j->pld_scrw.byte, j->XILINXbase);
1114  if (j->pstn_cid_intr && time_after(jiffies, j->pstn_cid_received + hertz)) {
1115  ixj_daa_cid_read(j);
1116  j->ex.bits.caller_id = 1;
1117  ixj_kill_fasync(j, SIG_CALLER_ID, POLL_IN);
1118  j->pstn_cid_intr = 0;
1119  }
1120  if (daaint.bitreg.Cadence) {
1121  if(ixjdebug & 0x0008) {
1122  printk("IXJ DAA Cadence interrupt going to sleep /dev/phone%d\n", j->board);
1123  }
1124  daa_set_mode(j, SOP_PU_SLEEP);
1125  j->ex.bits.pstn_ring = 0;
1126  }
1127  break;
1128  case SOP_PU_CONVERSATION:
1129  if (daaint.bitreg.VDD_OK) {
1130  if(!daaint.bitreg.SI_0) {
1131  if (!j->pstn_winkstart) {
1132  if(ixjdebug & 0x0008) {
1133  printk("IXJ DAA possible wink /dev/phone%d %ld\n", j->board, jiffies);
1134  }
1135  j->pstn_winkstart = jiffies;
1136  }
1137  } else {
1138  if (j->pstn_winkstart) {
1139  if(ixjdebug & 0x0008) {
1140  printk("IXJ DAA possible wink end /dev/phone%d %ld\n", j->board, jiffies);
1141  }
1142  j->pstn_winkstart = 0;
1143  }
1144  }
1145  }
1146  if (j->pstn_winkstart && time_after(jiffies, j->pstn_winkstart + ((hertz * j->winktime) / 1000))) {
1147  if(ixjdebug & 0x0008) {
1148  printk("IXJ DAA wink detected going to sleep /dev/phone%d %ld\n", j->board, jiffies);
1149  }
1150  daa_set_mode(j, SOP_PU_SLEEP);
1151  j->pstn_winkstart = 0;
1152  j->ex.bits.pstn_wink = 1;
1153  ixj_kill_fasync(j, SIG_PSTN_WINK, POLL_IN);
1154  }
1155  break;
1156  }
1157 }
1158 
1159 static void ixj_timeout(unsigned long ptr)
1160 {
1161  int board;
1162  unsigned long jifon;
1163  IXJ *j = (IXJ *)ptr;
1164  board = j->board;
1165 
1166  if (j->DSPbase && atomic_read(&j->DSPWrite) == 0 && test_and_set_bit(board, (void *)&j->busyflags) == 0) {
1168  j->hookstate = ixj_hookstate(j);
1169  if (j->tone_state) {
1170  if (!(j->hookstate)) {
1171  ixj_cpt_stop(j);
1172  if (j->m_hook) {
1173  j->m_hook = 0;
1174  j->ex.bits.hookstate = 1;
1175  ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1176  }
1177  clear_bit(board, &j->busyflags);
1178  ixj_add_timer(j);
1179  return;
1180  }
1181  if (j->tone_state == 1)
1182  jifon = ((hertz * j->tone_on_time) * 25 / 100000);
1183  else
1184  jifon = ((hertz * j->tone_on_time) * 25 / 100000) + ((hertz * j->tone_off_time) * 25 / 100000);
1185  if (time_before(jiffies, j->tone_start_jif + jifon)) {
1186  if (j->tone_state == 1) {
1187  ixj_play_tone(j, j->tone_index);
1188  if (j->dsp.low == 0x20) {
1189  clear_bit(board, &j->busyflags);
1190  ixj_add_timer(j);
1191  return;
1192  }
1193  } else {
1194  ixj_play_tone(j, 0);
1195  if (j->dsp.low == 0x20) {
1196  clear_bit(board, &j->busyflags);
1197  ixj_add_timer(j);
1198  return;
1199  }
1200  }
1201  } else {
1202  ixj_tone_timeout(j);
1203  if (j->flags.dialtone) {
1204  ixj_dialtone(j);
1205  }
1206  if (j->flags.busytone) {
1207  ixj_busytone(j);
1208  if (j->dsp.low == 0x20) {
1209  clear_bit(board, &j->busyflags);
1210  ixj_add_timer(j);
1211  return;
1212  }
1213  }
1214  if (j->flags.ringback) {
1215  ixj_ringback(j);
1216  if (j->dsp.low == 0x20) {
1217  clear_bit(board, &j->busyflags);
1218  ixj_add_timer(j);
1219  return;
1220  }
1221  }
1222  if (!j->tone_state) {
1223  ixj_cpt_stop(j);
1224  }
1225  }
1226  }
1227  if (!(j->tone_state && j->dsp.low == 0x20)) {
1228  if (IsRxReady(j)) {
1229  ixj_read_frame(j);
1230  }
1231  if (IsTxReady(j)) {
1232  ixj_write_frame(j);
1233  }
1234  }
1235  if (j->flags.cringing) {
1236  if (j->hookstate & 1) {
1237  j->flags.cringing = 0;
1238  ixj_ring_off(j);
1239  } else if(j->cadence_f[5].enable && ((!j->cadence_f[5].en_filter) || (j->cadence_f[5].en_filter && j->flags.firstring))) {
1240  switch(j->cadence_f[5].state) {
1241  case 0:
1242  j->cadence_f[5].on1dot = jiffies + (long)((j->cadence_f[5].on1 * (hertz * 100) / 10000));
1243  if (time_before(jiffies, j->cadence_f[5].on1dot)) {
1244  if(ixjdebug & 0x0004) {
1245  printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1246  }
1247  ixj_ring_on(j);
1248  }
1249  j->cadence_f[5].state = 1;
1250  break;
1251  case 1:
1252  if (time_after(jiffies, j->cadence_f[5].on1dot)) {
1253  j->cadence_f[5].off1dot = jiffies + (long)((j->cadence_f[5].off1 * (hertz * 100) / 10000));
1254  if(ixjdebug & 0x0004) {
1255  printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1256  }
1257  ixj_ring_off(j);
1258  j->cadence_f[5].state = 2;
1259  }
1260  break;
1261  case 2:
1262  if (time_after(jiffies, j->cadence_f[5].off1dot)) {
1263  if(ixjdebug & 0x0004) {
1264  printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1265  }
1266  ixj_ring_on(j);
1267  if (j->cadence_f[5].on2) {
1268  j->cadence_f[5].on2dot = jiffies + (long)((j->cadence_f[5].on2 * (hertz * 100) / 10000));
1269  j->cadence_f[5].state = 3;
1270  } else {
1271  j->cadence_f[5].state = 7;
1272  }
1273  }
1274  break;
1275  case 3:
1276  if (time_after(jiffies, j->cadence_f[5].on2dot)) {
1277  if(ixjdebug & 0x0004) {
1278  printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1279  }
1280  ixj_ring_off(j);
1281  if (j->cadence_f[5].off2) {
1282  j->cadence_f[5].off2dot = jiffies + (long)((j->cadence_f[5].off2 * (hertz * 100) / 10000));
1283  j->cadence_f[5].state = 4;
1284  } else {
1285  j->cadence_f[5].state = 7;
1286  }
1287  }
1288  break;
1289  case 4:
1290  if (time_after(jiffies, j->cadence_f[5].off2dot)) {
1291  if(ixjdebug & 0x0004) {
1292  printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1293  }
1294  ixj_ring_on(j);
1295  if (j->cadence_f[5].on3) {
1296  j->cadence_f[5].on3dot = jiffies + (long)((j->cadence_f[5].on3 * (hertz * 100) / 10000));
1297  j->cadence_f[5].state = 5;
1298  } else {
1299  j->cadence_f[5].state = 7;
1300  }
1301  }
1302  break;
1303  case 5:
1304  if (time_after(jiffies, j->cadence_f[5].on3dot)) {
1305  if(ixjdebug & 0x0004) {
1306  printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1307  }
1308  ixj_ring_off(j);
1309  if (j->cadence_f[5].off3) {
1310  j->cadence_f[5].off3dot = jiffies + (long)((j->cadence_f[5].off3 * (hertz * 100) / 10000));
1311  j->cadence_f[5].state = 6;
1312  } else {
1313  j->cadence_f[5].state = 7;
1314  }
1315  }
1316  break;
1317  case 6:
1318  if (time_after(jiffies, j->cadence_f[5].off3dot)) {
1319  if(ixjdebug & 0x0004) {
1320  printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1321  }
1322  j->cadence_f[5].state = 7;
1323  }
1324  break;
1325  case 7:
1326  if(ixjdebug & 0x0004) {
1327  printk("Ringing cadence state = %d - %ld\n", j->cadence_f[5].state, jiffies);
1328  }
1329  j->flags.cidring = 1;
1330  j->cadence_f[5].state = 0;
1331  break;
1332  }
1333  if (j->flags.cidring && !j->flags.cidsent) {
1334  j->flags.cidsent = 1;
1335  if(j->fskdcnt) {
1336  SLIC_SetState(PLD_SLIC_STATE_OHT, j);
1337  ixj_pre_cid(j);
1338  }
1339  j->flags.cidring = 0;
1340  }
1341  clear_bit(board, &j->busyflags);
1342  ixj_add_timer(j);
1343  return;
1344  } else {
1345  if (time_after(jiffies, j->ring_cadence_jif + (hertz / 2))) {
1346  if (j->flags.cidring && !j->flags.cidsent) {
1347  j->flags.cidsent = 1;
1348  if(j->fskdcnt) {
1349  SLIC_SetState(PLD_SLIC_STATE_OHT, j);
1350  ixj_pre_cid(j);
1351  }
1352  j->flags.cidring = 0;
1353  }
1354  j->ring_cadence_t--;
1355  if (j->ring_cadence_t == -1)
1356  j->ring_cadence_t = 15;
1358 
1359  if (j->ring_cadence & 1 << j->ring_cadence_t) {
1360  if(j->flags.cidsent && j->cadence_f[5].en_filter)
1361  j->flags.firstring = 1;
1362  else
1363  ixj_ring_on(j);
1364  } else {
1365  ixj_ring_off(j);
1366  if(!j->flags.cidsent)
1367  j->flags.cidring = 1;
1368  }
1369  }
1370  clear_bit(board, &j->busyflags);
1371  ixj_add_timer(j);
1372  return;
1373  }
1374  }
1375  if (!j->flags.ringing) {
1376  if (j->hookstate) { /* & 1) { */
1377  if (j->dsp.low != 0x20 &&
1378  SLIC_GetState(j) != PLD_SLIC_STATE_ACTIVE) {
1379  SLIC_SetState(PLD_SLIC_STATE_ACTIVE, j);
1380  }
1381  LineMonitor(j);
1382  read_filters(j);
1383  ixj_WriteDSPCommand(0x511B, j);
1384  j->proc_load = j->ssr.high << 8 | j->ssr.low;
1385  if (!j->m_hook && (j->hookstate & 1)) {
1386  j->m_hook = j->ex.bits.hookstate = 1;
1387  ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1388  }
1389  } else {
1390  if (j->ex.bits.dtmf_ready) {
1391  j->dtmf_wp = j->dtmf_rp = j->ex.bits.dtmf_ready = 0;
1392  }
1393  if (j->m_hook) {
1394  j->m_hook = 0;
1395  j->ex.bits.hookstate = 1;
1396  ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1397  }
1398  }
1399  }
1400  if (j->cardtype == QTI_LINEJACK && !j->flags.pstncheck && j->flags.pstn_present) {
1401  ixj_pstn_state(j);
1402  }
1403  if (j->ex.bytes) {
1404  wake_up_interruptible(&j->poll_q); /* Wake any blocked selects */
1405  }
1406  clear_bit(board, &j->busyflags);
1407  }
1408  ixj_add_timer(j);
1409 }
1410 
1411 static int ixj_status_wait(IXJ *j)
1412 {
1413  unsigned long jif;
1414 
1415  jif = jiffies + ((60 * hertz) / 100);
1416  while (!IsStatusReady(j)) {
1417  ixj_perfmon(j->statuswait);
1418  if (time_after(jiffies, jif)) {
1420  return -1;
1421  }
1422  }
1423  return 0;
1424 }
1425 
1426 static int ixj_PCcontrol_wait(IXJ *j)
1427 {
1428  unsigned long jif;
1429 
1430  jif = jiffies + ((60 * hertz) / 100);
1431  while (!IsPCControlReady(j)) {
1433  if (time_after(jiffies, jif)) {
1435  return -1;
1436  }
1437  }
1438  return 0;
1439 }
1440 
1441 static int ixj_WriteDSPCommand(unsigned short cmd, IXJ *j)
1442 {
1443  BYTES bytes;
1444  unsigned long jif;
1445 
1446  atomic_inc(&j->DSPWrite);
1447  if(atomic_read(&j->DSPWrite) > 1) {
1448  printk("IXJ %d DSP write overlap attempting command 0x%4.4x\n", j->board, cmd);
1449  return -1;
1450  }
1451  bytes.high = (cmd & 0xFF00) >> 8;
1452  bytes.low = cmd & 0x00FF;
1453  jif = jiffies + ((60 * hertz) / 100);
1454  while (!IsControlReady(j)) {
1456  if (time_after(jiffies, jif)) {
1458  atomic_dec(&j->DSPWrite);
1459  if(atomic_read(&j->DSPWrite) > 0) {
1460  printk("IXJ %d DSP overlaped command 0x%4.4x during control ready failure.\n", j->board, cmd);
1461  while(atomic_read(&j->DSPWrite) > 0) {
1462  atomic_dec(&j->DSPWrite);
1463  }
1464  }
1465  return -1;
1466  }
1467  }
1468  outb(bytes.low, j->DSPbase + 6);
1469  outb(bytes.high, j->DSPbase + 7);
1470 
1471  if (ixj_status_wait(j)) {
1472  j->ssr.low = 0xFF;
1473  j->ssr.high = 0xFF;
1474  atomic_dec(&j->DSPWrite);
1475  if(atomic_read(&j->DSPWrite) > 0) {
1476  printk("IXJ %d DSP overlaped command 0x%4.4x during status wait failure.\n", j->board, cmd);
1477  while(atomic_read(&j->DSPWrite) > 0) {
1478  atomic_dec(&j->DSPWrite);
1479  }
1480  }
1481  return -1;
1482  }
1483 /* Read Software Status Register */
1484  j->ssr.low = inb_p(j->DSPbase + 2);
1485  j->ssr.high = inb_p(j->DSPbase + 3);
1486  atomic_dec(&j->DSPWrite);
1487  if(atomic_read(&j->DSPWrite) > 0) {
1488  printk("IXJ %d DSP overlaped command 0x%4.4x\n", j->board, cmd);
1489  while(atomic_read(&j->DSPWrite) > 0) {
1490  atomic_dec(&j->DSPWrite);
1491  }
1492  }
1493  return 0;
1494 }
1495 
1496 /***************************************************************************
1497 *
1498 * General Purpose IO Register read routine
1499 *
1500 ***************************************************************************/
1501 static inline int ixj_gpio_read(IXJ *j)
1502 {
1503  if (ixj_WriteDSPCommand(0x5143, j))
1504  return -1;
1505 
1506  j->gpio.bytes.low = j->ssr.low;
1507  j->gpio.bytes.high = j->ssr.high;
1508 
1509  return 0;
1510 }
1511 
1512 static inline void LED_SetState(int state, IXJ *j)
1513 {
1514  if (j->cardtype == QTI_LINEJACK) {
1515  j->pld_scrw.bits.led1 = state & 0x1 ? 1 : 0;
1516  j->pld_scrw.bits.led2 = state & 0x2 ? 1 : 0;
1517  j->pld_scrw.bits.led3 = state & 0x4 ? 1 : 0;
1518  j->pld_scrw.bits.led4 = state & 0x8 ? 1 : 0;
1519 
1520  outb(j->pld_scrw.byte, j->XILINXbase);
1521  }
1522 }
1523 
1524 /*********************************************************************
1525 * GPIO Pins are configured as follows on the Quicknet Internet
1526 * PhoneJACK Telephony Cards
1527 *
1528 * POTS Select GPIO_6=0 GPIO_7=0
1529 * Mic/Speaker Select GPIO_6=0 GPIO_7=1
1530 * Handset Select GPIO_6=1 GPIO_7=0
1531 *
1532 * SLIC Active GPIO_1=0 GPIO_2=1 GPIO_5=0
1533 * SLIC Ringing GPIO_1=1 GPIO_2=1 GPIO_5=0
1534 * SLIC Open Circuit GPIO_1=0 GPIO_2=0 GPIO_5=0
1535 *
1536 * Hook Switch changes reported on GPIO_3
1537 *********************************************************************/
1538 static int ixj_set_port(IXJ *j, int arg)
1539 {
1540  if (j->cardtype == QTI_PHONEJACK_LITE) {
1541  if (arg != PORT_POTS)
1542  return 10;
1543  else
1544  return 0;
1545  }
1546  switch (arg) {
1547  case PORT_POTS:
1548  j->port = PORT_POTS;
1549  switch (j->cardtype) {
1550  case QTI_PHONECARD:
1551  if (j->flags.pcmciasct == 1)
1552  SLIC_SetState(PLD_SLIC_STATE_ACTIVE, j);
1553  else
1554  return 11;
1555  break;
1556  case QTI_PHONEJACK_PCI:
1557  j->pld_slicw.pcib.mic = 0;
1558  j->pld_slicw.pcib.spk = 0;
1559  outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1560  break;
1561  case QTI_LINEJACK:
1562  ixj_set_pots(j, 0); /* Disconnect POTS/PSTN relay */
1563  if (ixj_WriteDSPCommand(0xC528, j)) /* Write CODEC config to
1564  Software Control Register */
1565  return 2;
1566  j->pld_scrw.bits.daafsyncen = 0; /* Turn off DAA Frame Sync */
1567 
1568  outb(j->pld_scrw.byte, j->XILINXbase);
1569  j->pld_clock.byte = 0;
1570  outb(j->pld_clock.byte, j->XILINXbase + 0x04);
1571  j->pld_slicw.bits.rly1 = 1;
1572  j->pld_slicw.bits.spken = 0;
1573  outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1574  ixj_mixer(0x1200, j); /* Turn Off MIC switch on mixer left */
1575  ixj_mixer(0x1401, j); /* Turn On Mono1 switch on mixer left */
1576  ixj_mixer(0x1300, j); /* Turn Off MIC switch on mixer right */
1577  ixj_mixer(0x1501, j); /* Turn On Mono1 switch on mixer right */
1578  ixj_mixer(0x0E80, j); /*Mic mute */
1579  ixj_mixer(0x0F00, j); /* Set mono out (SLIC) to 0dB */
1580  ixj_mixer(0x0080, j); /* Mute Master Left volume */
1581  ixj_mixer(0x0180, j); /* Mute Master Right volume */
1582  SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
1583 /* SLIC_SetState(PLD_SLIC_STATE_ACTIVE, j); */
1584  break;
1585  case QTI_PHONEJACK:
1586  j->gpio.bytes.high = 0x0B;
1587  j->gpio.bits.gpio6 = 0;
1588  j->gpio.bits.gpio7 = 0;
1589  ixj_WriteDSPCommand(j->gpio.word, j);
1590  break;
1591  }
1592  break;
1593  case PORT_PSTN:
1594  if (j->cardtype == QTI_LINEJACK) {
1595  ixj_WriteDSPCommand(0xC534, j); /* Write CODEC config to Software Control Register */
1596 
1597  j->pld_slicw.bits.rly3 = 0;
1598  j->pld_slicw.bits.rly1 = 1;
1599  j->pld_slicw.bits.spken = 0;
1600  outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1601  j->port = PORT_PSTN;
1602  } else {
1603  return 4;
1604  }
1605  break;
1606  case PORT_SPEAKER:
1607  j->port = PORT_SPEAKER;
1608  switch (j->cardtype) {
1609  case QTI_PHONECARD:
1610  if (j->flags.pcmciasct) {
1611  SLIC_SetState(PLD_SLIC_STATE_OC, j);
1612  }
1613  break;
1614  case QTI_PHONEJACK_PCI:
1615  j->pld_slicw.pcib.mic = 1;
1616  j->pld_slicw.pcib.spk = 1;
1617  outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1618  break;
1619  case QTI_LINEJACK:
1620  ixj_set_pots(j, 0); /* Disconnect POTS/PSTN relay */
1621  if (ixj_WriteDSPCommand(0xC528, j)) /* Write CODEC config to
1622  Software Control Register */
1623  return 2;
1624  j->pld_scrw.bits.daafsyncen = 0; /* Turn off DAA Frame Sync */
1625 
1626  outb(j->pld_scrw.byte, j->XILINXbase);
1627  j->pld_clock.byte = 0;
1628  outb(j->pld_clock.byte, j->XILINXbase + 0x04);
1629  j->pld_slicw.bits.rly1 = 1;
1630  j->pld_slicw.bits.spken = 1;
1631  outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1632  ixj_mixer(0x1201, j); /* Turn On MIC switch on mixer left */
1633  ixj_mixer(0x1400, j); /* Turn Off Mono1 switch on mixer left */
1634  ixj_mixer(0x1301, j); /* Turn On MIC switch on mixer right */
1635  ixj_mixer(0x1500, j); /* Turn Off Mono1 switch on mixer right */
1636  ixj_mixer(0x0E06, j); /*Mic un-mute 0dB */
1637  ixj_mixer(0x0F80, j); /* Mute mono out (SLIC) */
1638  ixj_mixer(0x0000, j); /* Set Master Left volume to 0dB */
1639  ixj_mixer(0x0100, j); /* Set Master Right volume to 0dB */
1640  break;
1641  case QTI_PHONEJACK:
1642  j->gpio.bytes.high = 0x0B;
1643  j->gpio.bits.gpio6 = 0;
1644  j->gpio.bits.gpio7 = 1;
1645  ixj_WriteDSPCommand(j->gpio.word, j);
1646  break;
1647  }
1648  break;
1649  case PORT_HANDSET:
1650  if (j->cardtype != QTI_PHONEJACK) {
1651  return 5;
1652  } else {
1653  j->gpio.bytes.high = 0x0B;
1654  j->gpio.bits.gpio6 = 1;
1655  j->gpio.bits.gpio7 = 0;
1656  ixj_WriteDSPCommand(j->gpio.word, j);
1657  j->port = PORT_HANDSET;
1658  }
1659  break;
1660  default:
1661  return 6;
1662  break;
1663  }
1664  return 0;
1665 }
1666 
1667 static int ixj_set_pots(IXJ *j, int arg)
1668 {
1669  if (j->cardtype == QTI_LINEJACK) {
1670  if (arg) {
1671  if (j->port == PORT_PSTN) {
1672  j->pld_slicw.bits.rly1 = 0;
1673  outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1674  j->flags.pots_pstn = 1;
1675  return 1;
1676  } else {
1677  j->flags.pots_pstn = 0;
1678  return 0;
1679  }
1680  } else {
1681  j->pld_slicw.bits.rly1 = 1;
1682  outb(j->pld_slicw.byte, j->XILINXbase + 0x01);
1683  j->flags.pots_pstn = 0;
1684  return 1;
1685  }
1686  } else {
1687  return 0;
1688  }
1689 }
1690 
1691 static void ixj_ring_on(IXJ *j)
1692 {
1693  if (j->dsp.low == 0x20) /* Internet PhoneJACK */
1694  {
1695  if (ixjdebug & 0x0004)
1696  printk(KERN_INFO "IXJ Ring On /dev/phone%d\n", j->board);
1697 
1698  j->gpio.bytes.high = 0x0B;
1699  j->gpio.bytes.low = 0x00;
1700  j->gpio.bits.gpio1 = 1;
1701  j->gpio.bits.gpio2 = 1;
1702  j->gpio.bits.gpio5 = 0;
1703  ixj_WriteDSPCommand(j->gpio.word, j); /* send the ring signal */
1704  } else /* Internet LineJACK, Internet PhoneJACK Lite or Internet PhoneJACK PCI */
1705  {
1706  if (ixjdebug & 0x0004)
1707  printk(KERN_INFO "IXJ Ring On /dev/phone%d\n", j->board);
1708 
1709  SLIC_SetState(PLD_SLIC_STATE_RINGING, j);
1710  }
1711 }
1712 
1713 static int ixj_siadc(IXJ *j, int val)
1714 {
1715  if(j->cardtype == QTI_PHONECARD){
1716  if(j->flags.pcmciascp){
1717  if(val == -1)
1718  return j->siadc.bits.rxg;
1719 
1720  if(val < 0 || val > 0x1F)
1721  return -1;
1722 
1723  j->siadc.bits.hom = 0; /* Handset Out Mute */
1724  j->siadc.bits.lom = 0; /* Line Out Mute */
1725  j->siadc.bits.rxg = val; /*(0xC000 - 0x41C8) / 0x4EF; RX PGA Gain */
1726  j->psccr.bits.addr = 6; /* R/W Smart Cable Register Address */
1727  j->psccr.bits.rw = 0; /* Read / Write flag */
1728  j->psccr.bits.dev = 0;
1729  outb(j->siadc.byte, j->XILINXbase + 0x00);
1730  outb(j->psccr.byte, j->XILINXbase + 0x01);
1731  ixj_PCcontrol_wait(j);
1732  return j->siadc.bits.rxg;
1733  }
1734  }
1735  return -1;
1736 }
1737 
1738 static int ixj_sidac(IXJ *j, int val)
1739 {
1740  if(j->cardtype == QTI_PHONECARD){
1741  if(j->flags.pcmciascp){
1742  if(val == -1)
1743  return j->sidac.bits.txg;
1744 
1745  if(val < 0 || val > 0x1F)
1746  return -1;
1747 
1748  j->sidac.bits.srm = 1; /* Speaker Right Mute */
1749  j->sidac.bits.slm = 1; /* Speaker Left Mute */
1750  j->sidac.bits.txg = val; /* (0xC000 - 0x45E4) / 0x5D3; TX PGA Gain */
1751  j->psccr.bits.addr = 7; /* R/W Smart Cable Register Address */
1752  j->psccr.bits.rw = 0; /* Read / Write flag */
1753  j->psccr.bits.dev = 0;
1754  outb(j->sidac.byte, j->XILINXbase + 0x00);
1755  outb(j->psccr.byte, j->XILINXbase + 0x01);
1756  ixj_PCcontrol_wait(j);
1757  return j->sidac.bits.txg;
1758  }
1759  }
1760  return -1;
1761 }
1762 
1763 static int ixj_pcmcia_cable_check(IXJ *j)
1764 {
1765  j->pccr1.byte = inb_p(j->XILINXbase + 0x03);
1766  if (!j->flags.pcmciastate) {
1767  j->pccr2.byte = inb_p(j->XILINXbase + 0x02);
1768  if (j->pccr1.bits.drf || j->pccr2.bits.rstc) {
1769  j->flags.pcmciastate = 4;
1770  return 0;
1771  }
1772  if (j->pccr1.bits.ed) {
1773  j->pccr1.bits.ed = 0;
1774  j->psccr.bits.dev = 3;
1775  j->psccr.bits.rw = 1;
1776  outw_p(j->psccr.byte << 8, j->XILINXbase + 0x00);
1777  ixj_PCcontrol_wait(j);
1778  j->pslic.byte = inw_p(j->XILINXbase + 0x00) & 0xFF;
1779  j->pslic.bits.led2 = j->pslic.bits.det ? 1 : 0;
1780  j->psccr.bits.dev = 3;
1781  j->psccr.bits.rw = 0;
1782  outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
1783  ixj_PCcontrol_wait(j);
1784  return j->pslic.bits.led2 ? 1 : 0;
1785  } else if (j->flags.pcmciasct) {
1786  return j->r_hook;
1787  } else {
1788  return 1;
1789  }
1790  } else if (j->flags.pcmciastate == 4) {
1791  if (!j->pccr1.bits.drf) {
1792  j->flags.pcmciastate = 3;
1793  }
1794  return 0;
1795  } else if (j->flags.pcmciastate == 3) {
1796  j->pccr2.bits.pwr = 0;
1797  j->pccr2.bits.rstc = 1;
1798  outb(j->pccr2.byte, j->XILINXbase + 0x02);
1799  j->checkwait = jiffies + (hertz * 2);
1800  j->flags.incheck = 1;
1801  j->flags.pcmciastate = 2;
1802  return 0;
1803  } else if (j->flags.pcmciastate == 2) {
1804  if (j->flags.incheck) {
1805  if (time_before(jiffies, j->checkwait)) {
1806  return 0;
1807  } else {
1808  j->flags.incheck = 0;
1809  }
1810  }
1811  j->pccr2.bits.pwr = 0;
1812  j->pccr2.bits.rstc = 0;
1813  outb_p(j->pccr2.byte, j->XILINXbase + 0x02);
1814  j->flags.pcmciastate = 1;
1815  return 0;
1816  } else if (j->flags.pcmciastate == 1) {
1817  j->flags.pcmciastate = 0;
1818  if (!j->pccr1.bits.drf) {
1819  j->psccr.bits.dev = 3;
1820  j->psccr.bits.rw = 1;
1821  outb_p(j->psccr.byte, j->XILINXbase + 0x01);
1822  ixj_PCcontrol_wait(j);
1823  j->flags.pcmciascp = 1; /* Set Cable Present Flag */
1824 
1825  j->flags.pcmciasct = (inw_p(j->XILINXbase + 0x00) >> 8) & 0x03; /* Get Cable Type */
1826 
1827  if (j->flags.pcmciasct == 3) {
1828  j->flags.pcmciastate = 4;
1829  return 0;
1830  } else if (j->flags.pcmciasct == 0) {
1831  j->pccr2.bits.pwr = 1;
1832  j->pccr2.bits.rstc = 0;
1833  outb_p(j->pccr2.byte, j->XILINXbase + 0x02);
1834  j->port = PORT_SPEAKER;
1835  } else {
1836  j->port = PORT_POTS;
1837  }
1838  j->sic1.bits.cpd = 0; /* Chip Power Down */
1839  j->sic1.bits.mpd = 0; /* MIC Bias Power Down */
1840  j->sic1.bits.hpd = 0; /* Handset Bias Power Down */
1841  j->sic1.bits.lpd = 0; /* Line Bias Power Down */
1842  j->sic1.bits.spd = 1; /* Speaker Drive Power Down */
1843  j->psccr.bits.addr = 1; /* R/W Smart Cable Register Address */
1844  j->psccr.bits.rw = 0; /* Read / Write flag */
1845  j->psccr.bits.dev = 0;
1846  outb(j->sic1.byte, j->XILINXbase + 0x00);
1847  outb(j->psccr.byte, j->XILINXbase + 0x01);
1848  ixj_PCcontrol_wait(j);
1849 
1850  j->sic2.bits.al = 0; /* Analog Loopback DAC analog -> ADC analog */
1851  j->sic2.bits.dl2 = 0; /* Digital Loopback DAC -> ADC one bit */
1852  j->sic2.bits.dl1 = 0; /* Digital Loopback ADC -> DAC one bit */
1853  j->sic2.bits.pll = 0; /* 1 = div 10, 0 = div 5 */
1854  j->sic2.bits.hpd = 0; /* HPF disable */
1855  j->psccr.bits.addr = 2; /* R/W Smart Cable Register Address */
1856  j->psccr.bits.rw = 0; /* Read / Write flag */
1857  j->psccr.bits.dev = 0;
1858  outb(j->sic2.byte, j->XILINXbase + 0x00);
1859  outb(j->psccr.byte, j->XILINXbase + 0x01);
1860  ixj_PCcontrol_wait(j);
1861 
1862  j->psccr.bits.addr = 3; /* R/W Smart Cable Register Address */
1863  j->psccr.bits.rw = 0; /* Read / Write flag */
1864  j->psccr.bits.dev = 0;
1865  outb(0x00, j->XILINXbase + 0x00); /* PLL Divide N1 */
1866  outb(j->psccr.byte, j->XILINXbase + 0x01);
1867  ixj_PCcontrol_wait(j);
1868 
1869  j->psccr.bits.addr = 4; /* R/W Smart Cable Register Address */
1870  j->psccr.bits.rw = 0; /* Read / Write flag */
1871  j->psccr.bits.dev = 0;
1872  outb(0x09, j->XILINXbase + 0x00); /* PLL Multiply M1 */
1873  outb(j->psccr.byte, j->XILINXbase + 0x01);
1874  ixj_PCcontrol_wait(j);
1875 
1876  j->sirxg.bits.lig = 1; /* Line In Gain */
1877  j->sirxg.bits.lim = 1; /* Line In Mute */
1878  j->sirxg.bits.mcg = 0; /* MIC In Gain was 3 */
1879  j->sirxg.bits.mcm = 0; /* MIC In Mute */
1880  j->sirxg.bits.him = 0; /* Handset In Mute */
1881  j->sirxg.bits.iir = 1; /* IIR */
1882  j->psccr.bits.addr = 5; /* R/W Smart Cable Register Address */
1883  j->psccr.bits.rw = 0; /* Read / Write flag */
1884  j->psccr.bits.dev = 0;
1885  outb(j->sirxg.byte, j->XILINXbase + 0x00);
1886  outb(j->psccr.byte, j->XILINXbase + 0x01);
1887  ixj_PCcontrol_wait(j);
1888 
1889  ixj_siadc(j, 0x17);
1890  ixj_sidac(j, 0x1D);
1891 
1892  j->siaatt.bits.sot = 0;
1893  j->psccr.bits.addr = 9; /* R/W Smart Cable Register Address */
1894  j->psccr.bits.rw = 0; /* Read / Write flag */
1895  j->psccr.bits.dev = 0;
1896  outb(j->siaatt.byte, j->XILINXbase + 0x00);
1897  outb(j->psccr.byte, j->XILINXbase + 0x01);
1898  ixj_PCcontrol_wait(j);
1899 
1900  if (j->flags.pcmciasct == 1 && !j->readers && !j->writers) {
1901  j->psccr.byte = j->pslic.byte = 0;
1902  j->pslic.bits.powerdown = 1;
1903  j->psccr.bits.dev = 3;
1904  j->psccr.bits.rw = 0;
1905  outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
1906  ixj_PCcontrol_wait(j);
1907  }
1908  }
1909  return 0;
1910  } else {
1911  j->flags.pcmciascp = 0;
1912  return 0;
1913  }
1914  return 0;
1915 }
1916 
1917 static int ixj_hookstate(IXJ *j)
1918 {
1919  int fOffHook = 0;
1920 
1921  switch (j->cardtype) {
1922  case QTI_PHONEJACK:
1923  ixj_gpio_read(j);
1924  fOffHook = j->gpio.bits.gpio3read ? 1 : 0;
1925  break;
1926  case QTI_LINEJACK:
1927  case QTI_PHONEJACK_LITE:
1928  case QTI_PHONEJACK_PCI:
1929  SLIC_GetState(j);
1930  if(j->cardtype == QTI_LINEJACK && j->flags.pots_pstn == 1 && (j->readers || j->writers)) {
1931  fOffHook = j->pld_slicr.bits.potspstn ? 1 : 0;
1932  if(fOffHook != j->p_hook) {
1933  if(!j->checkwait) {
1934  j->checkwait = jiffies;
1935  }
1936  if(time_before(jiffies, j->checkwait + 2)) {
1937  fOffHook ^= 1;
1938  } else {
1939  j->checkwait = 0;
1940  }
1941  j->p_hook = fOffHook;
1942  printk("IXJ : /dev/phone%d pots-pstn hookstate check %d at %ld\n", j->board, fOffHook, jiffies);
1943  }
1944  } else {
1947  if (j->flags.ringing || j->flags.cringing) {
1948  if (!in_interrupt()) {
1949  msleep(20);
1950  }
1951  SLIC_GetState(j);
1953  ixj_ring_on(j);
1954  }
1955  }
1956  if (j->cardtype == QTI_PHONEJACK_PCI) {
1957  j->pld_scrr.byte = inb_p(j->XILINXbase);
1958  fOffHook = j->pld_scrr.pcib.det ? 1 : 0;
1959  } else
1960  fOffHook = j->pld_slicr.bits.det ? 1 : 0;
1961  }
1962  }
1963  break;
1964  case QTI_PHONECARD:
1965  fOffHook = ixj_pcmcia_cable_check(j);
1966  break;
1967  }
1968  if (j->r_hook != fOffHook) {
1969  j->r_hook = fOffHook;
1970  if (j->port == PORT_SPEAKER || j->port == PORT_HANDSET) { // || (j->port == PORT_PSTN && j->flags.pots_pstn == 0)) {
1971  j->ex.bits.hookstate = 1;
1972  ixj_kill_fasync(j, SIG_HOOKSTATE, POLL_IN);
1973  } else if (!fOffHook) {
1974  j->flash_end = jiffies + ((60 * hertz) / 100);
1975  }
1976  }
1977  if (fOffHook) {
1978  if(time_before(jiffies, j->flash_end)) {
1979  j->ex.bits.flash = 1;
1980  j->flash_end = 0;
1981  ixj_kill_fasync(j, SIG_FLASH, POLL_IN);
1982  }
1983  } else {
1984  if(time_before(jiffies, j->flash_end)) {
1985  fOffHook = 1;
1986  }
1987  }
1988 
1989  if (j->port == PORT_PSTN && j->daa_mode == SOP_PU_CONVERSATION)
1990  fOffHook |= 2;
1991 
1992  if (j->port == PORT_SPEAKER) {
1993  if(j->cardtype == QTI_PHONECARD) {
1994  if(j->flags.pcmciascp && j->flags.pcmciasct) {
1995  fOffHook |= 2;
1996  }
1997  } else {
1998  fOffHook |= 2;
1999  }
2000  }
2001 
2002  if (j->port == PORT_HANDSET)
2003  fOffHook |= 2;
2004 
2005  return fOffHook;
2006 }
2007 
2008 static void ixj_ring_off(IXJ *j)
2009 {
2010  if (j->dsp.low == 0x20) /* Internet PhoneJACK */
2011  {
2012  if (ixjdebug & 0x0004)
2013  printk(KERN_INFO "IXJ Ring Off\n");
2014  j->gpio.bytes.high = 0x0B;
2015  j->gpio.bytes.low = 0x00;
2016  j->gpio.bits.gpio1 = 0;
2017  j->gpio.bits.gpio2 = 1;
2018  j->gpio.bits.gpio5 = 0;
2019  ixj_WriteDSPCommand(j->gpio.word, j);
2020  } else /* Internet LineJACK */
2021  {
2022  if (ixjdebug & 0x0004)
2023  printk(KERN_INFO "IXJ Ring Off\n");
2024 
2025  if(!j->flags.cidplay)
2026  SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
2027 
2028  SLIC_GetState(j);
2029  }
2030 }
2031 
2032 static void ixj_ring_start(IXJ *j)
2033 {
2034  j->flags.cringing = 1;
2035  if (ixjdebug & 0x0004)
2036  printk(KERN_INFO "IXJ Cadence Ringing Start /dev/phone%d\n", j->board);
2037  if (ixj_hookstate(j) & 1) {
2038  if (j->port == PORT_POTS)
2039  ixj_ring_off(j);
2040  j->flags.cringing = 0;
2041  if (ixjdebug & 0x0004)
2042  printk(KERN_INFO "IXJ Cadence Ringing Stopped /dev/phone%d off hook\n", j->board);
2043  } else if(j->cadence_f[5].enable && (!j->cadence_f[5].en_filter)) {
2045  j->flags.cidsent = j->flags.cidring = 0;
2046  j->cadence_f[5].state = 0;
2047  if(j->cadence_f[5].on1)
2048  ixj_ring_on(j);
2049  } else {
2051  j->ring_cadence_t = 15;
2052  if (j->ring_cadence & 1 << j->ring_cadence_t) {
2053  ixj_ring_on(j);
2054  } else {
2055  ixj_ring_off(j);
2056  }
2057  j->flags.cidsent = j->flags.cidring = j->flags.firstring = 0;
2058  }
2059 }
2060 
2061 static int ixj_ring(IXJ *j)
2062 {
2063  char cntr;
2064  unsigned long jif;
2065 
2066  j->flags.ringing = 1;
2067  if (ixj_hookstate(j) & 1) {
2068  ixj_ring_off(j);
2069  j->flags.ringing = 0;
2070  return 1;
2071  }
2072  for (cntr = 0; cntr < j->maxrings; cntr++) {
2073  jif = jiffies + (1 * hertz);
2074  ixj_ring_on(j);
2075  while (time_before(jiffies, jif)) {
2076  if (ixj_hookstate(j) & 1) {
2077  ixj_ring_off(j);
2078  j->flags.ringing = 0;
2079  return 1;
2080  }
2082  if (signal_pending(current))
2083  break;
2084  }
2085  jif = jiffies + (3 * hertz);
2086  ixj_ring_off(j);
2087  while (time_before(jiffies, jif)) {
2088  if (ixj_hookstate(j) & 1) {
2089  msleep(10);
2090  if (ixj_hookstate(j) & 1) {
2091  j->flags.ringing = 0;
2092  return 1;
2093  }
2094  }
2096  if (signal_pending(current))
2097  break;
2098  }
2099  }
2100  ixj_ring_off(j);
2101  j->flags.ringing = 0;
2102  return 0;
2103 }
2104 
2105 static int ixj_open(struct phone_device *p, struct file *file_p)
2106 {
2107  IXJ *j = get_ixj(p->board);
2108  file_p->private_data = j;
2109 
2110  if (!j->DSPbase)
2111  return -ENODEV;
2112 
2113  if (file_p->f_mode & FMODE_READ) {
2114  if(!j->readers) {
2115  j->readers++;
2116  } else {
2117  return -EBUSY;
2118  }
2119  }
2120 
2121  if (file_p->f_mode & FMODE_WRITE) {
2122  if(!j->writers) {
2123  j->writers++;
2124  } else {
2125  if (file_p->f_mode & FMODE_READ){
2126  j->readers--;
2127  }
2128  return -EBUSY;
2129  }
2130  }
2131 
2132  if (j->cardtype == QTI_PHONECARD) {
2133  j->pslic.bits.powerdown = 0;
2134  j->psccr.bits.dev = 3;
2135  j->psccr.bits.rw = 0;
2136  outw_p(j->psccr.byte << 8 | j->pslic.byte, j->XILINXbase + 0x00);
2137  ixj_PCcontrol_wait(j);
2138  }
2139 
2140  j->flags.cidplay = 0;
2141  j->flags.cidcw_ack = 0;
2142 
2143  if (ixjdebug & 0x0002)
2144  printk(KERN_INFO "Opening board %d\n", p->board);
2145 
2146  j->framesread = j->frameswritten = 0;
2147  return 0;
2148 }
2149 
2150 static int ixj_release(struct inode *inode, struct file *file_p)
2151 {
2152  IXJ_TONE ti;
2153  int cnt;
2154  IXJ *j = file_p->private_data;
2155  int board = j->p.board;
2156 
2157  /*
2158  * Set up locks to ensure that only one process is talking to the DSP at a time.
2159  * This is necessary to keep the DSP from locking up.
2160  */
2161  while(test_and_set_bit(board, (void *)&j->busyflags) != 0)
2163  if (ixjdebug & 0x0002)
2164  printk(KERN_INFO "Closing board %d\n", NUM(inode));
2165 
2166  if (j->cardtype == QTI_PHONECARD)
2167  ixj_set_port(j, PORT_SPEAKER);
2168  else
2169  ixj_set_port(j, PORT_POTS);
2170 
2171  aec_stop(j);
2172  ixj_play_stop(j);
2173  ixj_record_stop(j);
2174  set_play_volume(j, 0x100);
2175  set_rec_volume(j, 0x100);
2176  ixj_ring_off(j);
2177 
2178  /* Restore the tone table to default settings. */
2179  ti.tone_index = 10;
2180  ti.gain0 = 1;
2181  ti.freq0 = hz941;
2182  ti.gain1 = 0;
2183  ti.freq1 = hz1209;
2184  ixj_init_tone(j, &ti);
2185  ti.tone_index = 11;
2186  ti.gain0 = 1;
2187  ti.freq0 = hz941;
2188  ti.gain1 = 0;
2189  ti.freq1 = hz1336;
2190  ixj_init_tone(j, &ti);
2191  ti.tone_index = 12;
2192  ti.gain0 = 1;
2193  ti.freq0 = hz941;
2194  ti.gain1 = 0;
2195  ti.freq1 = hz1477;
2196  ixj_init_tone(j, &ti);
2197  ti.tone_index = 13;
2198  ti.gain0 = 1;
2199  ti.freq0 = hz800;
2200  ti.gain1 = 0;
2201  ti.freq1 = 0;
2202  ixj_init_tone(j, &ti);
2203  ti.tone_index = 14;
2204  ti.gain0 = 1;
2205  ti.freq0 = hz1000;
2206  ti.gain1 = 0;
2207  ti.freq1 = 0;
2208  ixj_init_tone(j, &ti);
2209  ti.tone_index = 15;
2210  ti.gain0 = 1;
2211  ti.freq0 = hz1250;
2212  ti.gain1 = 0;
2213  ti.freq1 = 0;
2214  ixj_init_tone(j, &ti);
2215  ti.tone_index = 16;
2216  ti.gain0 = 1;
2217  ti.freq0 = hz950;
2218  ti.gain1 = 0;
2219  ti.freq1 = 0;
2220  ixj_init_tone(j, &ti);
2221  ti.tone_index = 17;
2222  ti.gain0 = 1;
2223  ti.freq0 = hz1100;
2224  ti.gain1 = 0;
2225  ti.freq1 = 0;
2226  ixj_init_tone(j, &ti);
2227  ti.tone_index = 18;
2228  ti.gain0 = 1;
2229  ti.freq0 = hz1400;
2230  ti.gain1 = 0;
2231  ti.freq1 = 0;
2232  ixj_init_tone(j, &ti);
2233  ti.tone_index = 19;
2234  ti.gain0 = 1;
2235  ti.freq0 = hz1500;
2236  ti.gain1 = 0;
2237  ti.freq1 = 0;
2238  ixj_init_tone(j, &ti);
2239  ti.tone_index = 20;
2240  ti.gain0 = 1;
2241  ti.freq0 = hz1600;
2242  ti.gain1 = 0;
2243  ti.freq1 = 0;
2244  ixj_init_tone(j, &ti);
2245  ti.tone_index = 21;
2246  ti.gain0 = 1;
2247  ti.freq0 = hz1800;
2248  ti.gain1 = 0;
2249  ti.freq1 = 0;
2250  ixj_init_tone(j, &ti);
2251  ti.tone_index = 22;
2252  ti.gain0 = 1;
2253  ti.freq0 = hz2100;
2254  ti.gain1 = 0;
2255  ti.freq1 = 0;
2256  ixj_init_tone(j, &ti);
2257  ti.tone_index = 23;
2258  ti.gain0 = 1;
2259  ti.freq0 = hz1300;
2260  ti.gain1 = 0;
2261  ti.freq1 = 0;
2262  ixj_init_tone(j, &ti);
2263  ti.tone_index = 24;
2264  ti.gain0 = 1;
2265  ti.freq0 = hz2450;
2266  ti.gain1 = 0;
2267  ti.freq1 = 0;
2268  ixj_init_tone(j, &ti);
2269  ti.tone_index = 25;
2270  ti.gain0 = 1;
2271  ti.freq0 = hz350;
2272  ti.gain1 = 0;
2273  ti.freq1 = hz440;
2274  ixj_init_tone(j, &ti);
2275  ti.tone_index = 26;
2276  ti.gain0 = 1;
2277  ti.freq0 = hz440;
2278  ti.gain1 = 0;
2279  ti.freq1 = hz480;
2280  ixj_init_tone(j, &ti);
2281  ti.tone_index = 27;
2282  ti.gain0 = 1;
2283  ti.freq0 = hz480;
2284  ti.gain1 = 0;
2285  ti.freq1 = hz620;
2286  ixj_init_tone(j, &ti);
2287 
2288  set_rec_depth(j, 2); /* Set Record Channel Limit to 2 frames */
2289 
2290  set_play_depth(j, 2); /* Set Playback Channel Limit to 2 frames */
2291 
2292  j->ex.bits.dtmf_ready = 0;
2293  j->dtmf_state = 0;
2294  j->dtmf_wp = j->dtmf_rp = 0;
2295  j->rec_mode = j->play_mode = -1;
2296  j->flags.ringing = 0;
2297  j->maxrings = MAXRINGS;
2299  if(j->cadence_f[5].enable) {
2300  j->cadence_f[5].enable = j->cadence_f[5].en_filter = j->cadence_f[5].state = 0;
2301  }
2302  j->drybuffer = 0;
2303  j->winktime = 320;
2304  j->flags.dtmf_oob = 0;
2305  for (cnt = 0; cnt < 4; cnt++)
2306  j->cadence_f[cnt].enable = 0;
2307 
2308  idle(j);
2309 
2310  if(j->cardtype == QTI_PHONECARD) {
2311  SLIC_SetState(PLD_SLIC_STATE_OC, j);
2312  }
2313 
2314  if (file_p->f_mode & FMODE_READ)
2315  j->readers--;
2316  if (file_p->f_mode & FMODE_WRITE)
2317  j->writers--;
2318 
2319  if (j->read_buffer && !j->readers) {
2320  kfree(j->read_buffer);
2321  j->read_buffer = NULL;
2322  j->read_buffer_size = 0;
2323  }
2324  if (j->write_buffer && !j->writers) {
2325  kfree(j->write_buffer);
2326  j->write_buffer = NULL;
2327  j->write_buffer_size = 0;
2328  }
2329  j->rec_codec = j->play_codec = 0;
2330  j->rec_frame_size = j->play_frame_size = 0;
2331  j->flags.cidsent = j->flags.cidring = 0;
2332 
2333  if(j->cardtype == QTI_LINEJACK && !j->readers && !j->writers) {
2334  ixj_set_port(j, PORT_PSTN);
2335  daa_set_mode(j, SOP_PU_SLEEP);
2336  ixj_set_pots(j, 1);
2337  }
2338  ixj_WriteDSPCommand(0x0FE3, j); /* Put the DSP in 1/5 power mode. */
2339 
2340  /* Set up the default signals for events */
2341  for (cnt = 0; cnt < 35; cnt++)
2342  j->ixj_signals[cnt] = SIGIO;
2343 
2344  /* Set the excetion signal enable flags */
2345  j->ex_sig.bits.dtmf_ready = j->ex_sig.bits.hookstate = j->ex_sig.bits.flash = j->ex_sig.bits.pstn_ring =
2346  j->ex_sig.bits.caller_id = j->ex_sig.bits.pstn_wink = j->ex_sig.bits.f0 = j->ex_sig.bits.f1 = j->ex_sig.bits.f2 =
2347  j->ex_sig.bits.f3 = j->ex_sig.bits.fc0 = j->ex_sig.bits.fc1 = j->ex_sig.bits.fc2 = j->ex_sig.bits.fc3 = 1;
2348 
2349  file_p->private_data = NULL;
2350  clear_bit(board, &j->busyflags);
2351  return 0;
2352 }
2353 
2354 static int read_filters(IXJ *j)
2355 {
2356  unsigned short fc, cnt, trg;
2357  int var;
2358 
2359  trg = 0;
2360  if (ixj_WriteDSPCommand(0x5144, j)) {
2361  if(ixjdebug & 0x0001) {
2362  printk(KERN_INFO "Read Frame Counter failed!\n");
2363  }
2364  return -1;
2365  }
2366  fc = j->ssr.high << 8 | j->ssr.low;
2367  if (fc == j->frame_count)
2368  return 1;
2369 
2370  j->frame_count = fc;
2371 
2372  if (j->dtmf_proc)
2373  return 1;
2374 
2375  var = 10;
2376 
2377  for (cnt = 0; cnt < 4; cnt++) {
2378  if (ixj_WriteDSPCommand(0x5154 + cnt, j)) {
2379  if(ixjdebug & 0x0001) {
2380  printk(KERN_INFO "Select Filter %d failed!\n", cnt);
2381  }
2382  return -1;
2383  }
2384  if (ixj_WriteDSPCommand(0x515C, j)) {
2385  if(ixjdebug & 0x0001) {
2386  printk(KERN_INFO "Read Filter History %d failed!\n", cnt);
2387  }
2388  return -1;
2389  }
2390  j->filter_hist[cnt] = j->ssr.high << 8 | j->ssr.low;
2391 
2392  if (j->cadence_f[cnt].enable) {
2393  if (j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12)) {
2394  if (j->cadence_f[cnt].state == 0) {
2395  j->cadence_f[cnt].state = 1;
2396  j->cadence_f[cnt].on1min = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100 - var)) / 10000));
2397  j->cadence_f[cnt].on1dot = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100)) / 10000));
2398  j->cadence_f[cnt].on1max = jiffies + (long)((j->cadence_f[cnt].on1 * (hertz * (100 + var)) / 10000));
2399  } else if (j->cadence_f[cnt].state == 2 &&
2400  (time_after(jiffies, j->cadence_f[cnt].off1min) &&
2401  time_before(jiffies, j->cadence_f[cnt].off1max))) {
2402  if (j->cadence_f[cnt].on2) {
2403  j->cadence_f[cnt].state = 3;
2404  j->cadence_f[cnt].on2min = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100 - var)) / 10000));
2405  j->cadence_f[cnt].on2dot = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100)) / 10000));
2406  j->cadence_f[cnt].on2max = jiffies + (long)((j->cadence_f[cnt].on2 * (hertz * (100 + var)) / 10000));
2407  } else {
2408  j->cadence_f[cnt].state = 7;
2409  }
2410  } else if (j->cadence_f[cnt].state == 4 &&
2411  (time_after(jiffies, j->cadence_f[cnt].off2min) &&
2412  time_before(jiffies, j->cadence_f[cnt].off2max))) {
2413  if (j->cadence_f[cnt].on3) {
2414  j->cadence_f[cnt].state = 5;
2415  j->cadence_f[cnt].on3min = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100 - var)) / 10000));
2416  j->cadence_f[cnt].on3dot = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100)) / 10000));
2417  j->cadence_f[cnt].on3max = jiffies + (long)((j->cadence_f[cnt].on3 * (hertz * (100 + var)) / 10000));
2418  } else {
2419  j->cadence_f[cnt].state = 7;
2420  }
2421  } else {
2422  j->cadence_f[cnt].state = 0;
2423  }
2424  } else if (j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3)) {
2425  if (j->cadence_f[cnt].state == 1) {
2426  if(!j->cadence_f[cnt].on1) {
2427  j->cadence_f[cnt].state = 7;
2428  } else if((time_after(jiffies, j->cadence_f[cnt].on1min) &&
2429  time_before(jiffies, j->cadence_f[cnt].on1max))) {
2430  if(j->cadence_f[cnt].off1) {
2431  j->cadence_f[cnt].state = 2;
2432  j->cadence_f[cnt].off1min = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100 - var)) / 10000));
2433  j->cadence_f[cnt].off1dot = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100)) / 10000));
2434  j->cadence_f[cnt].off1max = jiffies + (long)((j->cadence_f[cnt].off1 * (hertz * (100 + var)) / 10000));
2435  } else {
2436  j->cadence_f[cnt].state = 7;
2437  }
2438  } else {
2439  j->cadence_f[cnt].state = 0;
2440  }
2441  } else if (j->cadence_f[cnt].state == 3) {
2442  if((time_after(jiffies, j->cadence_f[cnt].on2min) &&
2443  time_before(jiffies, j->cadence_f[cnt].on2max))) {
2444  if(j->cadence_f[cnt].off2) {
2445  j->cadence_f[cnt].state = 4;
2446  j->cadence_f[cnt].off2min = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100 - var)) / 10000));
2447  j->cadence_f[cnt].off2dot = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100)) / 10000));
2448  j->cadence_f[cnt].off2max = jiffies + (long)((j->cadence_f[cnt].off2 * (hertz * (100 + var)) / 10000));
2449  } else {
2450  j->cadence_f[cnt].state = 7;
2451  }
2452  } else {
2453  j->cadence_f[cnt].state = 0;
2454  }
2455  } else if (j->cadence_f[cnt].state == 5) {
2456  if ((time_after(jiffies, j->cadence_f[cnt].on3min) &&
2457  time_before(jiffies, j->cadence_f[cnt].on3max))) {
2458  if(j->cadence_f[cnt].off3) {
2459  j->cadence_f[cnt].state = 6;
2460  j->cadence_f[cnt].off3min = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100 - var)) / 10000));
2461  j->cadence_f[cnt].off3dot = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100)) / 10000));
2462  j->cadence_f[cnt].off3max = jiffies + (long)((j->cadence_f[cnt].off3 * (hertz * (100 + var)) / 10000));
2463  } else {
2464  j->cadence_f[cnt].state = 7;
2465  }
2466  } else {
2467  j->cadence_f[cnt].state = 0;
2468  }
2469  } else {
2470  j->cadence_f[cnt].state = 0;
2471  }
2472  } else {
2473  switch(j->cadence_f[cnt].state) {
2474  case 1:
2475  if(time_after(jiffies, j->cadence_f[cnt].on1dot) &&
2476  !j->cadence_f[cnt].off1 &&
2477  !j->cadence_f[cnt].on2 && !j->cadence_f[cnt].off2 &&
2478  !j->cadence_f[cnt].on3 && !j->cadence_f[cnt].off3) {
2479  j->cadence_f[cnt].state = 7;
2480  }
2481  break;
2482  case 3:
2483  if(time_after(jiffies, j->cadence_f[cnt].on2dot) &&
2484  !j->cadence_f[cnt].off2 &&
2485  !j->cadence_f[cnt].on3 && !j->cadence_f[cnt].off3) {
2486  j->cadence_f[cnt].state = 7;
2487  }
2488  break;
2489  case 5:
2490  if(time_after(jiffies, j->cadence_f[cnt].on3dot) &&
2491  !j->cadence_f[cnt].off3) {
2492  j->cadence_f[cnt].state = 7;
2493  }
2494  break;
2495  }
2496  }
2497 
2498  if (ixjdebug & 0x0040) {
2499  printk(KERN_INFO "IXJ Tone Cadence state = %d /dev/phone%d at %ld\n", j->cadence_f[cnt].state, j->board, jiffies);
2500  switch(j->cadence_f[cnt].state) {
2501  case 0:
2502  printk(KERN_INFO "IXJ /dev/phone%d No Tone detected\n", j->board);
2503  break;
2504  case 1:
2505  printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %u %ld - %ld - %ld\n", j->board,
2506  j->cadence_f[cnt].on1, j->cadence_f[cnt].on1min, j->cadence_f[cnt].on1dot, j->cadence_f[cnt].on1max);
2507  break;
2508  case 2:
2509  printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off1min,
2510  j->cadence_f[cnt].off1max);
2511  break;
2512  case 3:
2513  printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].on2min,
2514  j->cadence_f[cnt].on2max);
2515  break;
2516  case 4:
2517  printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off2min,
2518  j->cadence_f[cnt].off2max);
2519  break;
2520  case 5:
2521  printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].on3min,
2522  j->cadence_f[cnt].on3max);
2523  break;
2524  case 6:
2525  printk(KERN_INFO "IXJ /dev/phone%d Next Tone Cadence state at %ld - %ld\n", j->board, j->cadence_f[cnt].off3min,
2526  j->cadence_f[cnt].off3max);
2527  break;
2528  }
2529  }
2530  }
2531  if (j->cadence_f[cnt].state == 7) {
2532  j->cadence_f[cnt].state = 0;
2533  if (j->cadence_f[cnt].enable == 1)
2534  j->cadence_f[cnt].enable = 0;
2535  switch (cnt) {
2536  case 0:
2537  if(ixjdebug & 0x0020) {
2538  printk(KERN_INFO "Filter Cadence 0 triggered %ld\n", jiffies);
2539  }
2540  j->ex.bits.fc0 = 1;
2541  ixj_kill_fasync(j, SIG_FC0, POLL_IN);
2542  break;
2543  case 1:
2544  if(ixjdebug & 0x0020) {
2545  printk(KERN_INFO "Filter Cadence 1 triggered %ld\n", jiffies);
2546  }
2547  j->ex.bits.fc1 = 1;
2548  ixj_kill_fasync(j, SIG_FC1, POLL_IN);
2549  break;
2550  case 2:
2551  if(ixjdebug & 0x0020) {
2552  printk(KERN_INFO "Filter Cadence 2 triggered %ld\n", jiffies);
2553  }
2554  j->ex.bits.fc2 = 1;
2555  ixj_kill_fasync(j, SIG_FC2, POLL_IN);
2556  break;
2557  case 3:
2558  if(ixjdebug & 0x0020) {
2559  printk(KERN_INFO "Filter Cadence 3 triggered %ld\n", jiffies);
2560  }
2561  j->ex.bits.fc3 = 1;
2562  ixj_kill_fasync(j, SIG_FC3, POLL_IN);
2563  break;
2564  }
2565  }
2566  if (j->filter_en[cnt] && ((j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12)) ||
2567  (j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3)))) {
2568  if((j->filter_hist[cnt] & 3 && !(j->filter_hist[cnt] & 12))) {
2569  trg = 1;
2570  } else if((j->filter_hist[cnt] & 12 && !(j->filter_hist[cnt] & 3))) {
2571  trg = 0;
2572  }
2573  switch (cnt) {
2574  case 0:
2575  if(ixjdebug & 0x0020) {
2576  printk(KERN_INFO "Filter 0 triggered %d at %ld\n", trg, jiffies);
2577  }
2578  j->ex.bits.f0 = 1;
2579  ixj_kill_fasync(j, SIG_F0, POLL_IN);
2580  break;
2581  case 1:
2582  if(ixjdebug & 0x0020) {
2583  printk(KERN_INFO "Filter 1 triggered %d at %ld\n", trg, jiffies);
2584  }
2585  j->ex.bits.f1 = 1;
2586  ixj_kill_fasync(j, SIG_F1, POLL_IN);
2587  break;
2588  case 2:
2589  if(ixjdebug & 0x0020) {
2590  printk(KERN_INFO "Filter 2 triggered %d at %ld\n", trg, jiffies);
2591  }
2592  j->ex.bits.f2 = 1;
2593  ixj_kill_fasync(j, SIG_F2, POLL_IN);
2594  break;
2595  case 3:
2596  if(ixjdebug & 0x0020) {
2597  printk(KERN_INFO "Filter 3 triggered %d at %ld\n", trg, jiffies);
2598  }
2599  j->ex.bits.f3 = 1;
2600  ixj_kill_fasync(j, SIG_F3, POLL_IN);
2601  break;
2602  }
2603  }
2604  }
2605  return 0;
2606 }
2607 
2608 static int LineMonitor(IXJ *j)
2609 {
2610  if (j->dtmf_proc) {
2611  return -1;
2612  }
2613  j->dtmf_proc = 1;
2614 
2615  if (ixj_WriteDSPCommand(0x7000, j)) /* Line Monitor */
2616  return -1;
2617 
2618  j->dtmf.bytes.high = j->ssr.high;
2619  j->dtmf.bytes.low = j->ssr.low;
2620  if (!j->dtmf_state && j->dtmf.bits.dtmf_valid) {
2621  j->dtmf_state = 1;
2622  j->dtmf_current = j->dtmf.bits.digit;
2623  }
2624  if (j->dtmf_state && !j->dtmf.bits.dtmf_valid) /* && j->dtmf_wp != j->dtmf_rp) */
2625  {
2626  if(!j->cidcw_wait) {
2627  j->dtmfbuffer[j->dtmf_wp] = j->dtmf_current;
2628  j->dtmf_wp++;
2629  if (j->dtmf_wp == 79)
2630  j->dtmf_wp = 0;
2631  j->ex.bits.dtmf_ready = 1;
2632  if(j->ex_sig.bits.dtmf_ready) {
2633  ixj_kill_fasync(j, SIG_DTMF_READY, POLL_IN);
2634  }
2635  }
2636  else if(j->dtmf_current == 0x00 || j->dtmf_current == 0x0D) {
2637  if(ixjdebug & 0x0020) {
2638  printk("IXJ phone%d saw CIDCW Ack DTMF %d from display at %ld\n", j->board, j->dtmf_current, jiffies);
2639  }
2640  j->flags.cidcw_ack = 1;
2641  }
2642  j->dtmf_state = 0;
2643  }
2644  j->dtmf_proc = 0;
2645 
2646  return 0;
2647 }
2648 
2649 /************************************************************************
2650 *
2651 * Functions to allow alaw <-> ulaw conversions.
2652 *
2653 ************************************************************************/
2654 
2655 static void ulaw2alaw(unsigned char *buff, unsigned long len)
2656 {
2657  static unsigned char table_ulaw2alaw[] =
2658  {
2659  0x2A, 0x2B, 0x28, 0x29, 0x2E, 0x2F, 0x2C, 0x2D,
2660  0x22, 0x23, 0x20, 0x21, 0x26, 0x27, 0x24, 0x25,
2661  0x3A, 0x3B, 0x38, 0x39, 0x3E, 0x3F, 0x3C, 0x3D,
2662  0x32, 0x33, 0x30, 0x31, 0x36, 0x37, 0x34, 0x35,
2663  0x0B, 0x08, 0x09, 0x0E, 0x0F, 0x0C, 0x0D, 0x02,
2664  0x03, 0x00, 0x01, 0x06, 0x07, 0x04, 0x05, 0x1A,
2665  0x1B, 0x18, 0x19, 0x1E, 0x1F, 0x1C, 0x1D, 0x12,
2666  0x13, 0x10, 0x11, 0x16, 0x17, 0x14, 0x15, 0x6B,
2667  0x68, 0x69, 0x6E, 0x6F, 0x6C, 0x6D, 0x62, 0x63,
2668  0x60, 0x61, 0x66, 0x67, 0x64, 0x65, 0x7B, 0x79,
2669  0x7E, 0x7F, 0x7C, 0x7D, 0x72, 0x73, 0x70, 0x71,
2670  0x76, 0x77, 0x74, 0x75, 0x4B, 0x49, 0x4F, 0x4D,
2671  0x42, 0x43, 0x40, 0x41, 0x46, 0x47, 0x44, 0x45,
2672  0x5A, 0x5B, 0x58, 0x59, 0x5E, 0x5F, 0x5C, 0x5D,
2673  0x52, 0x52, 0x53, 0x53, 0x50, 0x50, 0x51, 0x51,
2674  0x56, 0x56, 0x57, 0x57, 0x54, 0x54, 0x55, 0xD5,
2675  0xAA, 0xAB, 0xA8, 0xA9, 0xAE, 0xAF, 0xAC, 0xAD,
2676  0xA2, 0xA3, 0xA0, 0xA1, 0xA6, 0xA7, 0xA4, 0xA5,
2677  0xBA, 0xBB, 0xB8, 0xB9, 0xBE, 0xBF, 0xBC, 0xBD,
2678  0xB2, 0xB3, 0xB0, 0xB1, 0xB6, 0xB7, 0xB4, 0xB5,
2679  0x8B, 0x88, 0x89, 0x8E, 0x8F, 0x8C, 0x8D, 0x82,
2680  0x83, 0x80, 0x81, 0x86, 0x87, 0x84, 0x85, 0x9A,
2681  0x9B, 0x98, 0x99, 0x9E, 0x9F, 0x9C, 0x9D, 0x92,
2682  0x93, 0x90, 0x91, 0x96, 0x97, 0x94, 0x95, 0xEB,
2683  0xE8, 0xE9, 0xEE, 0xEF, 0xEC, 0xED, 0xE2, 0xE3,
2684  0xE0, 0xE1, 0xE6, 0xE7, 0xE4, 0xE5, 0xFB, 0xF9,
2685  0xFE, 0xFF, 0xFC, 0xFD, 0xF2, 0xF3, 0xF0, 0xF1,
2686  0xF6, 0xF7, 0xF4, 0xF5, 0xCB, 0xC9, 0xCF, 0xCD,
2687  0xC2, 0xC3, 0xC0, 0xC1, 0xC6, 0xC7, 0xC4, 0xC5,
2688  0xDA, 0xDB, 0xD8, 0xD9, 0xDE, 0xDF, 0xDC, 0xDD,
2689  0xD2, 0xD2, 0xD3, 0xD3, 0xD0, 0xD0, 0xD1, 0xD1,
2690  0xD6, 0xD6, 0xD7, 0xD7, 0xD4, 0xD4, 0xD5, 0xD5
2691  };
2692 
2693  while (len--)
2694  {
2695  *buff = table_ulaw2alaw[*(unsigned char *)buff];
2696  buff++;
2697  }
2698 }
2699 
2700 static void alaw2ulaw(unsigned char *buff, unsigned long len)
2701 {
2702  static unsigned char table_alaw2ulaw[] =
2703  {
2704  0x29, 0x2A, 0x27, 0x28, 0x2D, 0x2E, 0x2B, 0x2C,
2705  0x21, 0x22, 0x1F, 0x20, 0x25, 0x26, 0x23, 0x24,
2706  0x39, 0x3A, 0x37, 0x38, 0x3D, 0x3E, 0x3B, 0x3C,
2707  0x31, 0x32, 0x2F, 0x30, 0x35, 0x36, 0x33, 0x34,
2708  0x0A, 0x0B, 0x08, 0x09, 0x0E, 0x0F, 0x0C, 0x0D,
2709  0x02, 0x03, 0x00, 0x01, 0x06, 0x07, 0x04, 0x05,
2710  0x1A, 0x1B, 0x18, 0x19, 0x1E, 0x1F, 0x1C, 0x1D,
2711  0x12, 0x13, 0x10, 0x11, 0x16, 0x17, 0x14, 0x15,
2712  0x62, 0x63, 0x60, 0x61, 0x66, 0x67, 0x64, 0x65,
2713  0x5D, 0x5D, 0x5C, 0x5C, 0x5F, 0x5F, 0x5E, 0x5E,
2714  0x74, 0x76, 0x70, 0x72, 0x7C, 0x7E, 0x78, 0x7A,
2715  0x6A, 0x6B, 0x68, 0x69, 0x6E, 0x6F, 0x6C, 0x6D,
2716  0x48, 0x49, 0x46, 0x47, 0x4C, 0x4D, 0x4A, 0x4B,
2717  0x40, 0x41, 0x3F, 0x3F, 0x44, 0x45, 0x42, 0x43,
2718  0x56, 0x57, 0x54, 0x55, 0x5A, 0x5B, 0x58, 0x59,
2719  0x4F, 0x4F, 0x4E, 0x4E, 0x52, 0x53, 0x50, 0x51,
2720  0xA9, 0xAA, 0xA7, 0xA8, 0xAD, 0xAE, 0xAB, 0xAC,
2721  0xA1, 0xA2, 0x9F, 0xA0, 0xA5, 0xA6, 0xA3, 0xA4,
2722  0xB9, 0xBA, 0xB7, 0xB8, 0xBD, 0xBE, 0xBB, 0xBC,
2723  0xB1, 0xB2, 0xAF, 0xB0, 0xB5, 0xB6, 0xB3, 0xB4,
2724  0x8A, 0x8B, 0x88, 0x89, 0x8E, 0x8F, 0x8C, 0x8D,
2725  0x82, 0x83, 0x80, 0x81, 0x86, 0x87, 0x84, 0x85,
2726  0x9A, 0x9B, 0x98, 0x99, 0x9E, 0x9F, 0x9C, 0x9D,
2727  0x92, 0x93, 0x90, 0x91, 0x96, 0x97, 0x94, 0x95,
2728  0xE2, 0xE3, 0xE0, 0xE1, 0xE6, 0xE7, 0xE4, 0xE5,
2729  0xDD, 0xDD, 0xDC, 0xDC, 0xDF, 0xDF, 0xDE, 0xDE,
2730  0xF4, 0xF6, 0xF0, 0xF2, 0xFC, 0xFE, 0xF8, 0xFA,
2731  0xEA, 0xEB, 0xE8, 0xE9, 0xEE, 0xEF, 0xEC, 0xED,
2732  0xC8, 0xC9, 0xC6, 0xC7, 0xCC, 0xCD, 0xCA, 0xCB,
2733  0xC0, 0xC1, 0xBF, 0xBF, 0xC4, 0xC5, 0xC2, 0xC3,
2734  0xD6, 0xD7, 0xD4, 0xD5, 0xDA, 0xDB, 0xD8, 0xD9,
2735  0xCF, 0xCF, 0xCE, 0xCE, 0xD2, 0xD3, 0xD0, 0xD1
2736  };
2737 
2738  while (len--)
2739  {
2740  *buff = table_alaw2ulaw[*(unsigned char *)buff];
2741  buff++;
2742  }
2743 }
2744 
2745 static ssize_t ixj_read(struct file * file_p, char __user *buf, size_t length, loff_t * ppos)
2746 {
2747  unsigned long i = *ppos;
2748  IXJ * j = get_ixj(NUM(file_p->f_path.dentry->d_inode));
2749 
2751 
2752  if (j->flags.inread)
2753  return -EALREADY;
2754 
2755  j->flags.inread = 1;
2756 
2757  add_wait_queue(&j->read_q, &wait);
2759  mb();
2760 
2761  while (!j->read_buffer_ready || (j->dtmf_state && j->flags.dtmf_oob)) {
2762  ++j->read_wait;
2763  if (file_p->f_flags & O_NONBLOCK) {
2765  remove_wait_queue(&j->read_q, &wait);
2766  j->flags.inread = 0;
2767  return -EAGAIN;
2768  }
2769  if (!ixj_hookstate(j)) {
2771  remove_wait_queue(&j->read_q, &wait);
2772  j->flags.inread = 0;
2773  return 0;
2774  }
2776  if (signal_pending(current)) {
2778  remove_wait_queue(&j->read_q, &wait);
2779  j->flags.inread = 0;
2780  return -EINTR;
2781  }
2782  }
2783 
2784  remove_wait_queue(&j->read_q, &wait);
2786  /* Don't ever copy more than the user asks */
2787  if(j->rec_codec == ALAW)
2788  ulaw2alaw(j->read_buffer, min(length, j->read_buffer_size));
2789  i = copy_to_user(buf, j->read_buffer, min(length, j->read_buffer_size));
2790  j->read_buffer_ready = 0;
2791  if (i) {
2792  j->flags.inread = 0;
2793  return -EFAULT;
2794  } else {
2795  j->flags.inread = 0;
2796  return min(length, j->read_buffer_size);
2797  }
2798 }
2799 
2800 static ssize_t ixj_enhanced_read(struct file * file_p, char __user *buf, size_t length,
2801  loff_t * ppos)
2802 {
2803  int pre_retval;
2804  ssize_t read_retval = 0;
2805  IXJ *j = get_ixj(NUM(file_p->f_path.dentry->d_inode));
2806 
2807  pre_retval = ixj_PreRead(j, 0L);
2808  switch (pre_retval) {
2809  case NORMAL:
2810  read_retval = ixj_read(file_p, buf, length, ppos);
2811  ixj_PostRead(j, 0L);
2812  break;
2813  case NOPOST:
2814  read_retval = ixj_read(file_p, buf, length, ppos);
2815  break;
2816  case POSTONLY:
2817  ixj_PostRead(j, 0L);
2818  break;
2819  default:
2820  read_retval = pre_retval;
2821  }
2822  return read_retval;
2823 }
2824 
2825 static ssize_t ixj_write(struct file *file_p, const char __user *buf, size_t count, loff_t * ppos)
2826 {
2827  unsigned long i = *ppos;
2828  IXJ *j = file_p->private_data;
2829 
2831 
2832  if (j->flags.inwrite)
2833  return -EALREADY;
2834 
2835  j->flags.inwrite = 1;
2836 
2837  add_wait_queue(&j->write_q, &wait);
2839  mb();
2840 
2841 
2842  while (!j->write_buffers_empty) {
2843  ++j->write_wait;
2844  if (file_p->f_flags & O_NONBLOCK) {
2847  j->flags.inwrite = 0;
2848  return -EAGAIN;
2849  }
2850  if (!ixj_hookstate(j)) {
2853  j->flags.inwrite = 0;
2854  return 0;
2855  }
2857  if (signal_pending(current)) {
2860  j->flags.inwrite = 0;
2861  return -EINTR;
2862  }
2863  }
2866  if (j->write_buffer_wp + count >= j->write_buffer_end)
2867  j->write_buffer_wp = j->write_buffer;
2868  i = copy_from_user(j->write_buffer_wp, buf, min(count, j->write_buffer_size));
2869  if (i) {
2870  j->flags.inwrite = 0;
2871  return -EFAULT;
2872  }
2873  if(j->play_codec == ALAW)
2874  alaw2ulaw(j->write_buffer_wp, min(count, j->write_buffer_size));
2875  j->flags.inwrite = 0;
2876  return min(count, j->write_buffer_size);
2877 }
2878 
2879 static ssize_t ixj_enhanced_write(struct file * file_p, const char __user *buf, size_t count, loff_t * ppos)
2880 {
2881  int pre_retval;
2882  ssize_t write_retval = 0;
2883 
2884  IXJ *j = get_ixj(NUM(file_p->f_path.dentry->d_inode));
2885 
2886  pre_retval = ixj_PreWrite(j, 0L);
2887  switch (pre_retval) {
2888  case NORMAL:
2889  write_retval = ixj_write(file_p, buf, count, ppos);
2890  if (write_retval > 0) {
2891  ixj_PostWrite(j, 0L);
2892  j->write_buffer_wp += write_retval;
2893  j->write_buffers_empty--;
2894  }
2895  break;
2896  case NOPOST:
2897  write_retval = ixj_write(file_p, buf, count, ppos);
2898  if (write_retval > 0) {
2899  j->write_buffer_wp += write_retval;
2900  j->write_buffers_empty--;
2901  }
2902  break;
2903  case POSTONLY:
2904  ixj_PostWrite(j, 0L);
2905  break;
2906  default:
2907  write_retval = pre_retval;
2908  }
2909  return write_retval;
2910 }
2911 
2912 static void ixj_read_frame(IXJ *j)
2913 {
2914  int cnt, dly;
2915 
2916  if (j->read_buffer) {
2917  for (cnt = 0; cnt < j->rec_frame_size * 2; cnt += 2) {
2918  if (!(cnt % 16) && !IsRxReady(j)) {
2919  dly = 0;
2920  while (!IsRxReady(j)) {
2921  if (dly++ > 5) {
2922  dly = 0;
2923  break;
2924  }
2925  udelay(10);
2926  }
2927  }
2928  /* Throw away word 0 of the 8021 compressed format to get standard G.729. */
2929  if (j->rec_codec == G729 && (cnt == 0 || cnt == 10 || cnt == 20)) {
2930  inb_p(j->DSPbase + 0x0E);
2931  inb_p(j->DSPbase + 0x0F);
2932  }
2933  *(j->read_buffer + cnt) = inb_p(j->DSPbase + 0x0E);
2934  *(j->read_buffer + cnt + 1) = inb_p(j->DSPbase + 0x0F);
2935  }
2936  ++j->framesread;
2937  if (j->intercom != -1) {
2938  if (IsTxReady(get_ixj(j->intercom))) {
2939  for (cnt = 0; cnt < j->rec_frame_size * 2; cnt += 2) {
2940  if (!(cnt % 16) && !IsTxReady(j)) {
2941  dly = 0;
2942  while (!IsTxReady(j)) {
2943  if (dly++ > 5) {
2944  dly = 0;
2945  break;
2946  }
2947  udelay(10);
2948  }
2949  }
2950  outb_p(*(j->read_buffer + cnt), get_ixj(j->intercom)->DSPbase + 0x0C);
2951  outb_p(*(j->read_buffer + cnt + 1), get_ixj(j->intercom)->DSPbase + 0x0D);
2952  }
2953  get_ixj(j->intercom)->frameswritten++;
2954  }
2955  } else {
2956  j->read_buffer_ready = 1;
2957  wake_up_interruptible(&j->read_q); /* Wake any blocked readers */
2958 
2959  wake_up_interruptible(&j->poll_q); /* Wake any blocked selects */
2960 
2961  if(j->ixj_signals[SIG_READ_READY])
2962  ixj_kill_fasync(j, SIG_READ_READY, POLL_OUT);
2963  }
2964  }
2965 }
2966 
2967 static short fsk[][6][20] =
2968 {
2969  {
2970  {
2971  0, 17846, 29934, 32364, 24351, 8481, -10126, -25465, -32587, -29196,
2972  -16384, 1715, 19260, 30591, 32051, 23170, 6813, -11743, -26509, -32722
2973  },
2974  {
2975  -28377, -14876, 3425, 20621, 31163, 31650, 21925, 5126, -13328, -27481,
2976  -32767, -27481, -13328, 5126, 21925, 31650, 31163, 20621, 3425, -14876
2977  },
2978  {
2979  -28377, -32722, -26509, -11743, 6813, 23170, 32051, 30591, 19260, 1715,
2980  -16384, -29196, -32587, -25465, -10126, 8481, 24351, 32364, 29934, 17846
2981  },
2982  {
2983  0, -17846, -29934, -32364, -24351, -8481, 10126, 25465, 32587, 29196,
2984  16384, -1715, -19260, -30591, -32051, -23170, -6813, 11743, 26509, 32722
2985  },
2986  {
2987  28377, 14876, -3425, -20621, -31163, -31650, -21925, -5126, 13328, 27481,
2988  32767, 27481, 13328, -5126, -21925, -31650, -31163, -20621, -3425, 14876
2989  },
2990  {
2991  28377, 32722, 26509, 11743, -6813, -23170, -32051, -30591, -19260, -1715,
2992  16384, 29196, 32587, 25465, 10126, -8481, -24351, -32364, -29934, -17846
2993  }
2994  },
2995  {
2996  {
2997  0, 10126, 19260, 26509, 31163, 32767, 31163, 26509, 19260, 10126,
2998  0, -10126, -19260, -26509, -31163, -32767, -31163, -26509, -19260, -10126
2999  },
3000  {
3001  -28377, -21925, -13328, -3425, 6813, 16384, 24351, 29934, 32587, 32051,
3002  28377, 21925, 13328, 3425, -6813, -16384, -24351, -29934, -32587, -32051
3003  },
3004  {
3005  -28377, -32051, -32587, -29934, -24351, -16384, -6813, 3425, 13328, 21925,
3006  28377, 32051, 32587, 29934, 24351, 16384, 6813, -3425, -13328, -21925
3007  },
3008  {
3009  0, -10126, -19260, -26509, -31163, -32767, -31163, -26509, -19260, -10126,
3010  0, 10126, 19260, 26509, 31163, 32767, 31163, 26509, 19260, 10126
3011  },
3012  {
3013  28377, 21925, 13328, 3425, -6813, -16383, -24351, -29934, -32587, -32051,
3014  -28377, -21925, -13328, -3425, 6813, 16383, 24351, 29934, 32587, 32051
3015  },
3016  {
3017  28377, 32051, 32587, 29934, 24351, 16384, 6813, -3425, -13328, -21925,
3018  -28377, -32051, -32587, -29934, -24351, -16384, -6813, 3425, 13328, 21925
3019  }
3020  }
3021 };
3022 
3023 
3024 static void ixj_write_cid_bit(IXJ *j, int bit)
3025 {
3026  while (j->fskcnt < 20) {
3027  if(j->fskdcnt < (j->fsksize - 1))
3028  j->fskdata[j->fskdcnt++] = fsk[bit][j->fskz][j->fskcnt];
3029 
3030  j->fskcnt += 3;
3031  }
3032  j->fskcnt %= 20;
3033 
3034  if (!bit)
3035  j->fskz++;
3036  if (j->fskz >= 6)
3037  j->fskz = 0;
3038 
3039 }
3040 
3041 static void ixj_write_cid_byte(IXJ *j, char byte)
3042 {
3043  IXJ_CBYTE cb;
3044 
3045  cb.cbyte = byte;
3046  ixj_write_cid_bit(j, 0);
3047  ixj_write_cid_bit(j, cb.cbits.b0 ? 1 : 0);
3048  ixj_write_cid_bit(j, cb.cbits.b1 ? 1 : 0);
3049  ixj_write_cid_bit(j, cb.cbits.b2 ? 1 : 0);
3050  ixj_write_cid_bit(j, cb.cbits.b3 ? 1 : 0);
3051  ixj_write_cid_bit(j, cb.cbits.b4 ? 1 : 0);
3052  ixj_write_cid_bit(j, cb.cbits.b5 ? 1 : 0);
3053  ixj_write_cid_bit(j, cb.cbits.b6 ? 1 : 0);
3054  ixj_write_cid_bit(j, cb.cbits.b7 ? 1 : 0);
3055  ixj_write_cid_bit(j, 1);
3056 }
3057 
3058 static void ixj_write_cid_seize(IXJ *j)
3059 {
3060  int cnt;
3061 
3062  for (cnt = 0; cnt < 150; cnt++) {
3063  ixj_write_cid_bit(j, 0);
3064  ixj_write_cid_bit(j, 1);
3065  }
3066  for (cnt = 0; cnt < 180; cnt++) {
3067  ixj_write_cid_bit(j, 1);
3068  }
3069 }
3070 
3071 static void ixj_write_cidcw_seize(IXJ *j)
3072 {
3073  int cnt;
3074 
3075  for (cnt = 0; cnt < 80; cnt++) {
3076  ixj_write_cid_bit(j, 1);
3077  }
3078 }
3079 
3080 static int ixj_write_cid_string(IXJ *j, char *s, int checksum)
3081 {
3082  int cnt;
3083 
3084  for (cnt = 0; cnt < strlen(s); cnt++) {
3085  ixj_write_cid_byte(j, s[cnt]);
3086  checksum = (checksum + s[cnt]);
3087  }
3088  return checksum;
3089 }
3090 
3091 static void ixj_pad_fsk(IXJ *j, int pad)
3092 {
3093  int cnt;
3094 
3095  for (cnt = 0; cnt < pad; cnt++) {
3096  if(j->fskdcnt < (j->fsksize - 1))
3097  j->fskdata[j->fskdcnt++] = 0x0000;
3098  }
3099  for (cnt = 0; cnt < 720; cnt++) {
3100  if(j->fskdcnt < (j->fsksize - 1))
3101  j->fskdata[j->fskdcnt++] = 0x0000;
3102  }
3103 }
3104 
3105 static void ixj_pre_cid(IXJ *j)
3106 {
3107  j->cid_play_codec = j->play_codec;
3109  j->cid_play_volume = get_play_volume(j);
3110  j->cid_play_flag = j->flags.playing;
3111 
3112  j->cid_rec_codec = j->rec_codec;
3113  j->cid_rec_volume = get_rec_volume(j);
3114  j->cid_rec_flag = j->flags.recording;
3115 
3116  j->cid_play_aec_level = j->aec_level;
3117 
3118  switch(j->baseframe.low) {
3119  case 0xA0:
3120  j->cid_base_frame_size = 20;
3121  break;
3122  case 0x50:
3123  j->cid_base_frame_size = 10;
3124  break;
3125  case 0xF0:
3126  j->cid_base_frame_size = 30;
3127  break;
3128  }
3129 
3130  ixj_play_stop(j);
3131  ixj_cpt_stop(j);
3132 
3133  j->flags.cidplay = 1;
3134 
3135  set_base_frame(j, 30);
3136  set_play_codec(j, LINEAR16);
3137  set_play_volume(j, 0x1B);
3138  ixj_play_start(j);
3139 }
3140 
3141 static void ixj_post_cid(IXJ *j)
3142 {
3143  ixj_play_stop(j);
3144 
3145  if(j->cidsize > 5000) {
3146  SLIC_SetState(PLD_SLIC_STATE_STANDBY, j);
3147  }
3148  j->flags.cidplay = 0;
3149  if(ixjdebug & 0x0200) {
3150  printk("IXJ phone%d Finished Playing CallerID data %ld\n", j->board, jiffies);
3151  }
3152 
3153  ixj_fsk_free(j);
3154 
3155  j->fskdcnt = 0;
3156  set_base_frame(j, j->cid_base_frame_size);
3157  set_play_codec(j, j->cid_play_codec);
3158  ixj_aec_start(j, j->cid_play_aec_level);
3159  set_play_volume(j, j->cid_play_volume);
3160 
3161  set_rec_codec(j, j->cid_rec_codec);
3162  set_rec_volume(j, j->cid_rec_volume);
3163 
3164  if(j->cid_rec_flag)
3165  ixj_record_start(j);
3166 
3167  if(j->cid_play_flag)
3168  ixj_play_start(j);
3169 
3170  if(j->cid_play_flag) {
3171  wake_up_interruptible(&j->write_q); /* Wake any blocked writers */
3172  }
3173 }
3174 
3175 static void ixj_write_cid(IXJ *j)
3176 {
3177  char sdmf1[50];
3178  char sdmf2[50];
3179  char sdmf3[80];
3180  char mdmflen, len1, len2, len3;
3181  int pad;
3182 
3183  int checksum = 0;
3184 
3185  if (j->dsp.low == 0x20 || j->flags.cidplay)
3186  return;
3187 
3188  j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3189  j->cidsize = j->cidcnt = 0;
3190 
3191  ixj_fsk_alloc(j);
3192 
3193  strlcpy(sdmf1, j->cid_send.month, sizeof(sdmf1));
3194  strlcat(sdmf1, j->cid_send.day, sizeof(sdmf1));
3195  strlcat(sdmf1, j->cid_send.hour, sizeof(sdmf1));
3196  strlcat(sdmf1, j->cid_send.min, sizeof(sdmf1));
3197  strlcpy(sdmf2, j->cid_send.number, sizeof(sdmf2));
3198  strlcpy(sdmf3, j->cid_send.name, sizeof(sdmf3));
3199 
3200  len1 = strlen(sdmf1);
3201  len2 = strlen(sdmf2);
3202  len3 = strlen(sdmf3);
3203  mdmflen = len1 + len2 + len3 + 6;
3204 
3205  while(1){
3206  ixj_write_cid_seize(j);
3207 
3208  ixj_write_cid_byte(j, 0x80);
3209  checksum = 0x80;
3210  ixj_write_cid_byte(j, mdmflen);
3211  checksum = checksum + mdmflen;
3212 
3213  ixj_write_cid_byte(j, 0x01);
3214  checksum = checksum + 0x01;
3215  ixj_write_cid_byte(j, len1);
3216  checksum = checksum + len1;
3217  checksum = ixj_write_cid_string(j, sdmf1, checksum);
3218  if(ixj_hookstate(j) & 1)
3219  break;
3220 
3221  ixj_write_cid_byte(j, 0x02);
3222  checksum = checksum + 0x02;
3223  ixj_write_cid_byte(j, len2);
3224  checksum = checksum + len2;
3225  checksum = ixj_write_cid_string(j, sdmf2, checksum);
3226  if(ixj_hookstate(j) & 1)
3227  break;
3228 
3229  ixj_write_cid_byte(j, 0x07);
3230  checksum = checksum + 0x07;
3231  ixj_write_cid_byte(j, len3);
3232  checksum = checksum + len3;
3233  checksum = ixj_write_cid_string(j, sdmf3, checksum);
3234  if(ixj_hookstate(j) & 1)
3235  break;
3236 
3237  checksum %= 256;
3238  checksum ^= 0xFF;
3239  checksum += 1;
3240 
3241  ixj_write_cid_byte(j, (char) checksum);
3242 
3243  pad = j->fskdcnt % 240;
3244  if (pad) {
3245  pad = 240 - pad;
3246  }
3247  ixj_pad_fsk(j, pad);
3248  break;
3249  }
3250 
3251  ixj_write_frame(j);
3252 }
3253 
3254 static void ixj_write_cidcw(IXJ *j)
3255 {
3256  IXJ_TONE ti;
3257 
3258  char sdmf1[50];
3259  char sdmf2[50];
3260  char sdmf3[80];
3261  char mdmflen, len1, len2, len3;
3262  int pad;
3263 
3264  int checksum = 0;
3265 
3266  if (j->dsp.low == 0x20 || j->flags.cidplay)
3267  return;
3268 
3269  j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3270  j->cidsize = j->cidcnt = 0;
3271 
3272  ixj_fsk_alloc(j);
3273 
3274  j->flags.cidcw_ack = 0;
3275 
3276  ti.tone_index = 23;
3277  ti.gain0 = 1;
3278  ti.freq0 = hz440;
3279  ti.gain1 = 0;
3280  ti.freq1 = 0;
3281  ixj_init_tone(j, &ti);
3282 
3283  ixj_set_tone_on(1500, j);
3284  ixj_set_tone_off(32, j);
3285  if(ixjdebug & 0x0200) {
3286  printk("IXJ cidcw phone%d first tone start at %ld\n", j->board, jiffies);
3287  }
3288  ixj_play_tone(j, 23);
3289 
3290  clear_bit(j->board, &j->busyflags);
3291  while(j->tone_state)
3293  while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0)
3295  if(ixjdebug & 0x0200) {
3296  printk("IXJ cidcw phone%d first tone end at %ld\n", j->board, jiffies);
3297  }
3298 
3299  ti.tone_index = 24;
3300  ti.gain0 = 1;
3301  ti.freq0 = hz2130;
3302  ti.gain1 = 0;
3303  ti.freq1 = hz2750;
3304  ixj_init_tone(j, &ti);
3305 
3306  ixj_set_tone_off(10, j);
3307  ixj_set_tone_on(600, j);
3308  if(ixjdebug & 0x0200) {
3309  printk("IXJ cidcw phone%d second tone start at %ld\n", j->board, jiffies);
3310  }
3311  ixj_play_tone(j, 24);
3312 
3313  clear_bit(j->board, &j->busyflags);
3314  while(j->tone_state)
3316  while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0)
3318  if(ixjdebug & 0x0200) {
3319  printk("IXJ cidcw phone%d sent second tone at %ld\n", j->board, jiffies);
3320  }
3321 
3322  j->cidcw_wait = jiffies + ((50 * hertz) / 100);
3323 
3324  clear_bit(j->board, &j->busyflags);
3325  while(!j->flags.cidcw_ack && time_before(jiffies, j->cidcw_wait))
3327  while(test_and_set_bit(j->board, (void *)&j->busyflags) != 0)
3329  j->cidcw_wait = 0;
3330  if(!j->flags.cidcw_ack) {
3331  if(ixjdebug & 0x0200) {
3332  printk("IXJ cidcw phone%d did not receive ACK from display %ld\n", j->board, jiffies);
3333  }
3334  ixj_post_cid(j);
3335  if(j->cid_play_flag) {
3336  wake_up_interruptible(&j->write_q); /* Wake any blocked readers */
3337  }
3338  return;
3339  } else {
3340  ixj_pre_cid(j);
3341  }
3342  j->flags.cidcw_ack = 0;
3343  strlcpy(sdmf1, j->cid_send.month, sizeof(sdmf1));
3344  strlcat(sdmf1, j->cid_send.day, sizeof(sdmf1));
3345  strlcat(sdmf1, j->cid_send.hour, sizeof(sdmf1));
3346  strlcat(sdmf1, j->cid_send.min, sizeof(sdmf1));
3347  strlcpy(sdmf2, j->cid_send.number, sizeof(sdmf2));
3348  strlcpy(sdmf3, j->cid_send.name, sizeof(sdmf3));
3349 
3350  len1 = strlen(sdmf1);
3351  len2 = strlen(sdmf2);
3352  len3 = strlen(sdmf3);
3353  mdmflen = len1 + len2 + len3 + 6;
3354 
3355  ixj_write_cidcw_seize(j);
3356 
3357  ixj_write_cid_byte(j, 0x80);
3358  checksum = 0x80;
3359  ixj_write_cid_byte(j, mdmflen);
3360  checksum = checksum + mdmflen;
3361 
3362  ixj_write_cid_byte(j, 0x01);
3363  checksum = checksum + 0x01;
3364  ixj_write_cid_byte(j, len1);
3365  checksum = checksum + len1;
3366  checksum = ixj_write_cid_string(j, sdmf1, checksum);
3367 
3368  ixj_write_cid_byte(j, 0x02);
3369  checksum = checksum + 0x02;
3370  ixj_write_cid_byte(j, len2);
3371  checksum = checksum + len2;
3372  checksum = ixj_write_cid_string(j, sdmf2, checksum);
3373 
3374  ixj_write_cid_byte(j, 0x07);
3375  checksum = checksum + 0x07;
3376  ixj_write_cid_byte(j, len3);
3377  checksum = checksum + len3;
3378  checksum = ixj_write_cid_string(j, sdmf3, checksum);
3379 
3380  checksum %= 256;
3381  checksum ^= 0xFF;
3382  checksum += 1;
3383 
3384  ixj_write_cid_byte(j, (char) checksum);
3385 
3386  pad = j->fskdcnt % 240;
3387  if (pad) {
3388  pad = 240 - pad;
3389  }
3390  ixj_pad_fsk(j, pad);
3391  if(ixjdebug & 0x0200) {
3392  printk("IXJ cidcw phone%d sent FSK data at %ld\n", j->board, jiffies);
3393  }
3394 }
3395 
3396 static void ixj_write_vmwi(IXJ *j, int msg)
3397 {
3398  char mdmflen;
3399  int pad;
3400 
3401  int checksum = 0;
3402 
3403  if (j->dsp.low == 0x20 || j->flags.cidplay)
3404  return;
3405 
3406  j->fskz = j->fskphase = j->fskcnt = j->fskdcnt = 0;
3407  j->cidsize = j->cidcnt = 0;
3408 
3409  ixj_fsk_alloc(j);
3410 
3411  mdmflen = 3;
3412 
3413  if (j->port == PORT_POTS)
3414  SLIC_SetState(PLD_SLIC_STATE_OHT, j);
3415 
3416  ixj_write_cid_seize(j);
3417 
3418  ixj_write_cid_byte(j, 0x82);
3419  checksum = 0x82;
3420  ixj_write_cid_byte(j, mdmflen);
3421  checksum = checksum + mdmflen;
3422 
3423  ixj_write_cid_byte(j, 0x0B);
3424  checksum = checksum + 0x0B;
3425  ixj_write_cid_byte(j, 1);
3426  checksum = checksum + 1;
3427 
3428  if(msg) {
3429  ixj_write_cid_byte(j, 0xFF);
3430  checksum = checksum + 0xFF;
3431  }
3432  else {
3433  ixj_write_cid_byte(j, 0x00);
3434  checksum = checksum + 0x00;
3435  }
3436 
3437  checksum %= 256;
3438  checksum ^= 0xFF;
3439  checksum += 1;
3440 
3441  ixj_write_cid_byte(j, (char) checksum);
3442 
3443  pad = j->fskdcnt % 240;
3444  if (pad) {
3445  pad = 240 - pad;
3446  }
3447  ixj_pad_fsk(j, pad);
3448 }
3449 
3450 static void ixj_write_frame(IXJ *j)
3451 {
3452  int cnt, frame_count, dly;
3453  IXJ_WORD dat;
3454 
3455  frame_count = 0;
3456  if(j->flags.cidplay) {
3457  for(cnt = 0; cnt < 480; cnt++) {
3458  if (!(cnt % 16) && !IsTxReady(j)) {
3459  dly = 0;
3460  while (!IsTxReady(j)) {
3461  if (dly++ > 5) {
3462  dly = 0;
3463  break;
3464  }
3465  udelay(10);
3466  }
3467  }
3468  dat.word = j->fskdata[j->cidcnt++];
3469  outb_p(dat.bytes.low, j->DSPbase + 0x0C);
3470  outb_p(dat.bytes.high, j->DSPbase + 0x0D);
3471  cnt++;
3472  }
3473  if(j->cidcnt >= j->fskdcnt) {
3474  ixj_post_cid(j);
3475  }
3476  /* This may seem rude, but if we just played one frame of FSK data for CallerID
3477  and there is real audio data in the buffer, we need to throw it away because
3478  we just used it's time slot */
3479  if (j->write_buffer_rp > j->write_buffer_wp) {
3480  j->write_buffer_rp += j->cid_play_frame_size * 2;
3481  if (j->write_buffer_rp >= j->write_buffer_end) {
3482  j->write_buffer_rp = j->write_buffer;
3483  }
3484  j->write_buffers_empty++;
3485  wake_up_interruptible(&j->write_q); /* Wake any blocked writers */
3486 
3487  wake_up_interruptible(&j->poll_q); /* Wake any blocked selects */
3488  }
3489  } else if (j->write_buffer && j->write_buffers_empty < 1) {
3490  if (j->write_buffer_wp > j->write_buffer_rp) {
3491  frame_count =
3492  (j->write_buffer_wp - j->write_buffer_rp) / (j->play_frame_size * 2);
3493  }
3494  if (j->write_buffer_rp > j->write_buffer_wp) {
3495  frame_count =
3496  (j->write_buffer_wp - j->write_buffer) / (j->play_frame_size * 2) +
3497  (j->write_buffer_end - j->write_buffer_rp) / (j->play_frame_size * 2);
3498  }
3499  if (frame_count >= 1) {
3500  if (j->ver.low == 0x12 && j->play_mode && j->flags.play_first_frame) {
3501  BYTES blankword;
3502 
3503  switch (j->play_mode) {
3504  case PLAYBACK_MODE_ULAW:
3505  case PLAYBACK_MODE_ALAW:
3506  blankword.low = blankword.high = 0xFF;
3507  break;
3508  case PLAYBACK_MODE_8LINEAR:
3510  default:
3511  blankword.low = blankword.high = 0x00;
3512  break;
3514  blankword.low = blankword.high = 0x80;
3515  break;
3516  }
3517  for (cnt = 0; cnt < 16; cnt++) {
3518  if (!(cnt % 16) && !IsTxReady(j)) {
3519  dly = 0;
3520  while (!IsTxReady(j)) {
3521  if (dly++ > 5) {
3522  dly = 0;
3523  break;
3524  }
3525  udelay(10);
3526  }
3527  }
3528  outb_p((blankword.low), j->DSPbase + 0x0C);
3529  outb_p((blankword.high), j->DSPbase + 0x0D);
3530  }
3531  j->flags.play_first_frame = 0;
3532  } else if (j->play_codec == G723_63 && j->flags.play_first_frame) {
3533  for (cnt = 0; cnt < 24; cnt++) {
3534  BYTES blankword;
3535 
3536  if(cnt == 12) {
3537  blankword.low = 0x02;
3538  blankword.high = 0x00;
3539  }
3540  else {
3541  blankword.low = blankword.high = 0x00;
3542  }
3543  if (!(cnt % 16) && !IsTxReady(j)) {
3544  dly = 0;
3545  while (!IsTxReady(j)) {
3546  if (dly++ > 5) {
3547  dly = 0;
3548  break;
3549  }
3550  udelay(10);
3551  }
3552  }
3553  outb_p((blankword.low), j->DSPbase + 0x0C);
3554  outb_p((blankword.high), j->DSPbase + 0x0D);
3555  }
3556  j->flags.play_first_frame = 0;
3557  }
3558  for (cnt = 0; cnt < j->play_frame_size * 2; cnt += 2) {
3559  if (!(cnt % 16) && !IsTxReady(j)) {
3560  dly = 0;
3561  while (!IsTxReady(j)) {
3562  if (dly++ > 5) {
3563  dly = 0;
3564  break;
3565  }
3566  udelay(10);
3567  }
3568  }
3569  /* Add word 0 to G.729 frames for the 8021. Right now we don't do VAD/CNG */
3570  if (j->play_codec == G729 && (cnt == 0 || cnt == 10 || cnt == 20)) {
3571  if (j->write_buffer_rp[cnt] == 0 &&
3572  j->write_buffer_rp[cnt + 1] == 0 &&
3573  j->write_buffer_rp[cnt + 2] == 0 &&
3574  j->write_buffer_rp[cnt + 3] == 0 &&
3575  j->write_buffer_rp[cnt + 4] == 0 &&
3576  j->write_buffer_rp[cnt + 5] == 0 &&
3577  j->write_buffer_rp[cnt + 6] == 0 &&
3578  j->write_buffer_rp[cnt + 7] == 0 &&
3579  j->write_buffer_rp[cnt + 8] == 0 &&
3580  j->write_buffer_rp[cnt + 9] == 0) {
3581  /* someone is trying to write silence lets make this a type 0 frame. */
3582  outb_p(0x00, j->DSPbase + 0x0C);
3583  outb_p(0x00, j->DSPbase + 0x0D);
3584  } else {
3585  /* so all other frames are type 1. */
3586  outb_p(0x01, j->DSPbase + 0x0C);
3587  outb_p(0x00, j->DSPbase + 0x0D);
3588  }
3589  }
3590  outb_p(*(j->write_buffer_rp + cnt), j->DSPbase + 0x0C);
3591  outb_p(*(j->write_buffer_rp + cnt + 1), j->DSPbase + 0x0D);
3592  *(j->write_buffer_rp + cnt) = 0;
3593  *(j->write_buffer_rp + cnt + 1) = 0;
3594  }
3595  j->write_buffer_rp += j->play_frame_size * 2;
3596  if (j->write_buffer_rp >= j->write_buffer_end) {
3597  j->write_buffer_rp = j->write_buffer;
3598  }
3599  j->write_buffers_empty++;
3600  wake_up_interruptible(&j->write_q); /* Wake any blocked writers */
3601 
3602  wake_up_interruptible(&j->poll_q); /* Wake any blocked selects */
3603 
3604  ++j->frameswritten;
3605  }
3606  } else {
3607  j->drybuffer++;
3608  }
3609  if(j->ixj_signals[SIG_WRITE_READY]) {
3610  ixj_kill_fasync(j, SIG_WRITE_READY, POLL_OUT);
3611  }
3612 }
3613 
3614 static int idle(IXJ *j)
3615 {
3616  if (ixj_WriteDSPCommand(0x0000, j)) /* DSP Idle */
3617 
3618  return 0;
3619 
3620  if (j->ssr.high || j->ssr.low) {
3621  return 0;
3622  } else {
3623  j->play_mode = -1;
3624  j->flags.playing = 0;
3625  j->rec_mode = -1;
3626  j->flags.recording = 0;
3627  return 1;
3628  }
3629 }
3630 
3631 static int set_base_frame(IXJ *j, int size)
3632 {
3633  unsigned short cmd;
3634  int cnt;
3635 
3636  idle(j);
3637  j->cid_play_aec_level = j->aec_level;
3638  aec_stop(j);
3639  for (cnt = 0; cnt < 10; cnt++) {
3640  if (idle(j))
3641  break;
3642  }
3643  if (j->ssr.high || j->ssr.low)
3644  return -1;
3645  if (j->dsp.low != 0x20) {
3646  switch (size) {
3647  case 30:
3648  cmd = 0x07F0;
3649  /* Set Base Frame Size to 240 pg9-10 8021 */
3650  break;
3651  case 20:
3652  cmd = 0x07A0;
3653  /* Set Base Frame Size to 160 pg9-10 8021 */
3654  break;
3655  case 10:
3656  cmd = 0x0750;
3657  /* Set Base Frame Size to 80 pg9-10 8021 */
3658  break;
3659  default:
3660  return -1;
3661  }
3662  } else {
3663  if (size == 30)
3664  return size;
3665  else
3666  return -1;
3667  }
3668  if (ixj_WriteDSPCommand(cmd, j)) {
3669  j->baseframe.high = j->baseframe.low = 0xFF;
3670  return -1;
3671  } else {
3672  j->baseframe.high = j->ssr.high;
3673  j->baseframe.low = j->ssr.low;
3674  /* If the status returned is 0x0000 (pg9-9 8021) the call failed */
3675  if(j->baseframe.high == 0x00 && j->baseframe.low == 0x00) {
3676  return -1;
3677  }
3678  }
3679  ixj_aec_start(j, j->cid_play_aec_level);
3680  return size;
3681 }
3682 
3683 static int set_rec_codec(IXJ *j, int rate)
3684 {
3685  int retval = 0;
3686 
3687  j->rec_codec = rate;
3688 
3689  switch (rate) {
3690  case G723_63:
3691  if (j->ver.low != 0x12 || ixj_convert_loaded) {
3692  j->rec_frame_size = 12;
3693  j->rec_mode = 0;
3694  } else {
3695  retval = 1;
3696  }
3697  break;
3698  case G723_53:
3699  if (j->ver.low != 0x12 || ixj_convert_loaded) {
3700  j->rec_frame_size = 10;
3701  j->rec_mode = 0;
3702  } else {
3703  retval = 1;
3704  }
3705  break;
3706  case TS85:
3707  if (j->dsp.low == 0x20 || j->flags.ts85_loaded) {
3708  j->rec_frame_size = 16;
3709  j->rec_mode = 0;
3710  } else {
3711  retval = 1;
3712  }
3713  break;
3714  case TS48:
3715  if (j->ver.low != 0x12 || ixj_convert_loaded) {
3716  j->rec_frame_size = 9;
3717  j->rec_mode = 0;
3718  } else {
3719  retval = 1;
3720  }
3721  break;
3722  case TS41:
3723  if (j->ver.low != 0x12 || ixj_convert_loaded) {
3724  j->rec_frame_size = 8;
3725  j->rec_mode = 0;
3726  } else {
3727  retval = 1;
3728  }
3729  break;
3730  case G728:
3731  if (j->dsp.low != 0x20) {
3732  j->rec_frame_size = 48;
3733  j->rec_mode = 0;
3734  } else {
3735  retval = 1;
3736  }
3737  break;
3738  case G729:
3739  if (j->dsp.low != 0x20) {
3740  if (!j->flags.g729_loaded) {
3741  retval = 1;
3742  break;
3743  }
3744  switch (j->baseframe.low) {
3745  case 0xA0:
3746  j->rec_frame_size = 10;
3747  break;
3748  case 0x50:
3749  j->rec_frame_size = 5;
3750  break;
3751  default:
3752  j->rec_frame_size = 15;
3753  break;
3754  }
3755  j->rec_mode = 0;
3756  } else {
3757  retval = 1;
3758  }
3759  break;
3760  case G729B:
3761  if (j->dsp.low != 0x20) {
3762  if (!j->flags.g729_loaded) {
3763  retval = 1;
3764  break;
3765  }
3766  switch (j->baseframe.low) {
3767  case 0xA0:
3768  j->rec_frame_size = 12;
3769  break;
3770  case 0x50:
3771  j->rec_frame_size = 6;
3772  break;
3773  default:
3774  j->rec_frame_size = 18;
3775  break;
3776  }
3777  j->rec_mode = 0;
3778  } else {
3779  retval = 1;
3780  }
3781  break;
3782  case ULAW:
3783  switch (j->baseframe.low) {
3784  case 0xA0:
3785  j->rec_frame_size = 80;
3786  break;
3787  case 0x50:
3788  j->rec_frame_size = 40;
3789  break;
3790  default:
3791  j->rec_frame_size = 120;
3792  break;
3793  }
3794  j->rec_mode = 4;
3795  break;
3796  case ALAW:
3797  switch (j->baseframe.low) {
3798  case 0xA0:
3799  j->rec_frame_size = 80;
3800  break;
3801  case 0x50:
3802  j->rec_frame_size = 40;
3803  break;
3804  default:
3805  j->rec_frame_size = 120;
3806  break;
3807  }
3808  j->rec_mode = 4;
3809  break;
3810  case LINEAR16:
3811  switch (j->baseframe.low) {
3812  case 0xA0:
3813  j->rec_frame_size = 160;
3814  break;
3815  case 0x50:
3816  j->rec_frame_size = 80;
3817  break;
3818  default:
3819  j->rec_frame_size = 240;
3820  break;
3821  }
3822  j->rec_mode = 5;
3823  break;
3824  case LINEAR8:
3825  switch (j->baseframe.low) {
3826  case 0xA0:
3827  j->rec_frame_size = 80;
3828  break;
3829  case 0x50:
3830  j->rec_frame_size = 40;
3831  break;
3832  default:
3833  j->rec_frame_size = 120;
3834  break;
3835  }
3836  j->rec_mode = 6;
3837  break;
3838  case WSS:
3839  switch (j->baseframe.low) {
3840  case 0xA0:
3841  j->rec_frame_size = 80;
3842  break;
3843  case 0x50:
3844  j->rec_frame_size = 40;
3845  break;
3846  default:
3847  j->rec_frame_size = 120;
3848  break;
3849  }
3850  j->rec_mode = 7;
3851  break;
3852  default:
3853  kfree(j->read_buffer);
3854  j->rec_frame_size = 0;
3855  j->rec_mode = -1;
3856  j->read_buffer = NULL;
3857  j->read_buffer_size = 0;
3858  retval = 1;
3859  break;
3860  }
3861  return retval;
3862 }
3863 
3864 static int ixj_record_start(IXJ *j)
3865 {
3866  unsigned short cmd = 0x0000;
3867 
3868  if (j->read_buffer) {
3869  ixj_record_stop(j);
3870  }
3871  j->flags.recording = 1;
3872  ixj_WriteDSPCommand(0x0FE0, j); /* Put the DSP in full power mode. */
3873 
3874  if(ixjdebug & 0x0002)
3875  printk("IXJ %d Starting Record Codec %d at %ld\n", j->board, j->rec_codec, jiffies);
3876 
3877  if (!j->rec_mode) {
3878  switch (j->rec_codec) {
3879  case G723_63:
3880  cmd = 0x5131;
3881  break;
3882  case G723_53:
3883  cmd = 0x5132;
3884  break;
3885  case TS85:
3886  cmd = 0x5130; /* TrueSpeech 8.5 */
3887 
3888  break;
3889  case TS48:
3890  cmd = 0x5133; /* TrueSpeech 4.8 */
3891 
3892  break;
3893  case TS41:
3894  cmd = 0x5134; /* TrueSpeech 4.1 */
3895 
3896  break;
3897  case G728:
3898  cmd = 0x5135;
3899  break;
3900  case G729:
3901  case G729B:
3902  cmd = 0x5136;
3903  break;
3904  default:
3905  return 1;
3906  }
3907  if (ixj_WriteDSPCommand(cmd, j))
3908  return -1;
3909  }
3910  if (!j->read_buffer) {
3911  if (!j->read_buffer)
3913  if (!j->read_buffer) {
3914  printk("Read buffer allocation for ixj board %d failed!\n", j->board);
3915  return -ENOMEM;
3916  }
3917  }
3918  j->read_buffer_size = j->rec_frame_size * 2;
3919 
3920  if (ixj_WriteDSPCommand(0x5102, j)) /* Set Poll sync mode */
3921 
3922  return -1;
3923 
3924  switch (j->rec_mode) {
3925  case 0:
3926  cmd = 0x1C03; /* Record C1 */
3927 
3928  break;
3929  case 4:
3930  if (j->ver.low == 0x12) {
3931  cmd = 0x1E03; /* Record C1 */
3932 
3933  } else {
3934  cmd = 0x1E01; /* Record C1 */
3935 
3936  }
3937  break;
3938  case 5:
3939  if (j->ver.low == 0x12) {
3940  cmd = 0x1E83; /* Record C1 */
3941 
3942  } else {
3943  cmd = 0x1E81; /* Record C1 */
3944 
3945  }
3946  break;
3947  case 6:
3948  if (j->ver.low == 0x12) {
3949  cmd = 0x1F03; /* Record C1 */
3950 
3951  } else {
3952  cmd = 0x1F01; /* Record C1 */
3953 
3954  }
3955  break;
3956  case 7:
3957  if (j->ver.low == 0x12) {
3958  cmd = 0x1F83; /* Record C1 */
3959  } else {
3960  cmd = 0x1F81; /* Record C1 */
3961  }
3962  break;
3963  }
3964  if (ixj_WriteDSPCommand(cmd, j))
3965  return -1;
3966 
3967  if (j->flags.playing) {
3968  ixj_aec_start(j, j->aec_level);
3969  }
3970  return 0;
3971 }
3972 
3973 static void ixj_record_stop(IXJ *j)
3974 {
3975  if (ixjdebug & 0x0002)
3976  printk("IXJ %d Stopping Record Codec %d at %ld\n", j->board, j->rec_codec, jiffies);
3977 
3978  kfree(j->read_buffer);
3979  j->read_buffer = NULL;
3980  j->read_buffer_size = 0;
3981  if (j->rec_mode > -1) {
3982  ixj_WriteDSPCommand(0x5120, j);
3983  j->rec_mode = -1;
3984  }
3985  j->flags.recording = 0;
3986 }
3987 static void ixj_vad(IXJ *j, int arg)
3988 {
3989  if (arg)
3990  ixj_WriteDSPCommand(0x513F, j);
3991  else
3992  ixj_WriteDSPCommand(0x513E, j);
3993 }
3994 
3995 static void set_rec_depth(IXJ *j, int depth)
3996 {
3997  if (depth > 60)
3998  depth = 60;
3999  if (depth < 0)
4000  depth = 0;
4001  ixj_WriteDSPCommand(0x5180 + depth, j);
4002 }
4003 
4004 static void set_dtmf_prescale(IXJ *j, int volume)
4005 {
4006  ixj_WriteDSPCommand(0xCF07, j);
4007  ixj_WriteDSPCommand(volume, j);
4008 }
4009 
4010 static int get_dtmf_prescale(IXJ *j)
4011 {
4012  ixj_WriteDSPCommand(0xCF05, j);
4013  return j->ssr.high << 8 | j->ssr.low;
4014 }
4015 
4016 static void set_rec_volume(IXJ *j, int volume)
4017 {
4018  if(j->aec_level == AEC_AGC) {
4019  if (ixjdebug & 0x0002)
4020  printk(KERN_INFO "IXJ: /dev/phone%d Setting AGC Threshold to 0x%4.4x\n", j->board, volume);
4021  ixj_WriteDSPCommand(0xCF96, j);
4022  ixj_WriteDSPCommand(volume, j);
4023  } else {
4024  if (ixjdebug & 0x0002)
4025  printk(KERN_INFO "IXJ: /dev/phone %d Setting Record Volume to 0x%4.4x\n", j->board, volume);
4026  ixj_WriteDSPCommand(0xCF03, j);
4027  ixj_WriteDSPCommand(volume, j);
4028  }
4029 }
4030 
4031 static int set_rec_volume_linear(IXJ *j, int volume)
4032 {
4033  int newvolume, dsprecmax;
4034 
4035  if (ixjdebug & 0x0002)
4036  printk(KERN_INFO "IXJ: /dev/phone %d Setting Linear Record Volume to 0x%4.4x\n", j->board, volume);
4037  if(volume > 100 || volume < 0) {
4038  return -1;
4039  }
4040 
4041  /* This should normalize the perceived volumes between the different cards caused by differences in the hardware */
4042  switch (j->cardtype) {
4043  case QTI_PHONEJACK:
4044  dsprecmax = 0x440;
4045  break;
4046  case QTI_LINEJACK:
4047  dsprecmax = 0x180;
4048  ixj_mixer(0x0203, j); /*Voice Left Volume unmute 6db */
4049  ixj_mixer(0x0303, j); /*Voice Right Volume unmute 6db */
4050  ixj_mixer(0x0C00, j); /*Mono1 unmute 12db */
4051  break;
4052  case QTI_PHONEJACK_LITE:
4053  dsprecmax = 0x4C0;
4054  break;
4055  case QTI_PHONEJACK_PCI:
4056  dsprecmax = 0x100;
4057  break;
4058  case QTI_PHONECARD:
4059  dsprecmax = 0x400;
4060  break;
4061  default:
4062  return -1;
4063  }
4064  newvolume = (dsprecmax * volume) / 100;
4065  set_rec_volume(j, newvolume);
4066  return 0;
4067 }
4068 
4069 static int get_rec_volume(IXJ *j)
4070 {
4071  if(j->aec_level == AEC_AGC) {
4072  if (ixjdebug & 0x0002)
4073  printk(KERN_INFO "Getting AGC Threshold\n");
4074  ixj_WriteDSPCommand(0xCF86, j);
4075  if (ixjdebug & 0x0002)
4076  printk(KERN_INFO "AGC Threshold is 0x%2.2x%2.2x\n", j->ssr.high, j->ssr.low);
4077  return j->ssr.high << 8 | j->ssr.low;
4078  } else {
4079  if (ixjdebug & 0x0002)
4080  printk(KERN_INFO "Getting Record Volume\n");
4081  ixj_WriteDSPCommand(0xCF01, j);
4082  return j->ssr.high << 8 | j->ssr.low;
4083  }
4084 }
4085 
4086 static int get_rec_volume_linear(IXJ *j)
4087 {
4088  int volume, newvolume, dsprecmax;
4089 
4090  switch (j->cardtype) {
4091  case QTI_PHONEJACK:
4092  dsprecmax = 0x440;
4093  break;
4094  case QTI_LINEJACK:
4095  dsprecmax = 0x180;
4096  break;
4097  case QTI_PHONEJACK_LITE:
4098  dsprecmax = 0x4C0;
4099  break;
4100  case QTI_PHONEJACK_PCI:
4101  dsprecmax = 0x100;
4102  break;
4103  case QTI_PHONECARD:
4104  dsprecmax = 0x400;
4105  break;
4106  default:
4107  return -1;
4108  }
4109  volume = get_rec_volume(j);
4110  newvolume = (volume * 100) / dsprecmax;
4111  if(newvolume > 100)
4112  newvolume = 100;
4113  return newvolume;
4114 }
4115 
4116 static int get_rec_level(IXJ *j)
4117 {
4118  int retval;
4119 
4120  ixj_WriteDSPCommand(0xCF88, j);
4121 
4122  retval = j->ssr.high << 8 | j->ssr.low;
4123  retval = (retval * 256) / 240;
4124  return retval;
4125 }
4126 
4127 static void ixj_aec_start(IXJ *j, int level)
4128 {
4129  j->aec_level = level;
4130  if (ixjdebug & 0x0002)
4131  printk(KERN_INFO "AGC set = 0x%2.2x\n", j->aec_level);
4132  if (!level) {
4133  aec_stop(j);
4134  } else {
4135  if (j->rec_codec == G729 || j->play_codec == G729 || j->rec_codec == G729B || j->play_codec == G729B) {
4136  ixj_WriteDSPCommand(0xE022, j); /* Move AEC filter buffer */
4137 
4138  ixj_WriteDSPCommand(0x0300, j);
4139  }
4140  ixj_WriteDSPCommand(0xB001, j); /* AEC On */
4141 
4142  ixj_WriteDSPCommand(0xE013, j); /* Advanced AEC C1 */
4143 
4144  switch (level) {
4145  case AEC_LOW:
4146  ixj_WriteDSPCommand(0x0000, j); /* Advanced AEC C2 = off */
4147 
4148  ixj_WriteDSPCommand(0xE011, j);
4149  ixj_WriteDSPCommand(0xFFFF, j);
4150 
4151  ixj_WriteDSPCommand(0xCF97, j); /* Set AGC Enable */
4152  ixj_WriteDSPCommand(0x0000, j); /* to off */
4153 
4154  break;
4155 
4156  case AEC_MED:
4157  ixj_WriteDSPCommand(0x0600, j); /* Advanced AEC C2 = on medium */
4158 
4159  ixj_WriteDSPCommand(0xE011, j);
4160  ixj_WriteDSPCommand(0x0080, j);
4161 
4162  ixj_WriteDSPCommand(0xCF97, j); /* Set AGC Enable */
4163  ixj_WriteDSPCommand(0x0000, j); /* to off */
4164 
4165  break;
4166 
4167  case AEC_HIGH:
4168  ixj_WriteDSPCommand(0x0C00, j); /* Advanced AEC C2 = on high */
4169 
4170  ixj_WriteDSPCommand(0xE011, j);
4171  ixj_WriteDSPCommand(0x0080, j);
4172 
4173  ixj_WriteDSPCommand(0xCF97, j); /* Set AGC Enable */
4174  ixj_WriteDSPCommand(0x0000, j); /* to off */
4175 
4176  break;
4177 
4178  case AEC_AGC:
4179  /* First we have to put the AEC into advance auto mode so that AGC will not conflict with it */
4180  ixj_WriteDSPCommand(0x0002, j); /* Attenuation scaling factor of 2 */
4181 
4182  ixj_WriteDSPCommand(0xE011, j);
4183  ixj_WriteDSPCommand(0x0100, j); /* Higher Threshold Floor */
4184 
4185  ixj_WriteDSPCommand(0xE012, j); /* Set Train and Lock */
4186 
4187  if(j->cardtype == QTI_LINEJACK || j->cardtype == QTI_PHONECARD)
4188  ixj_WriteDSPCommand(0x0224, j);
4189  else
4190  ixj_WriteDSPCommand(0x1224, j);
4191 
4192  ixj_WriteDSPCommand(0xE014, j);
4193  ixj_WriteDSPCommand(0x0003, j); /* Lock threshold at 3dB */
4194 
4195  ixj_WriteDSPCommand(0xE338, j); /* Set Echo Suppresser Attenuation to 0dB */
4196 
4197  /* Now we can set the AGC initial parameters and turn it on */
4198  ixj_WriteDSPCommand(0xCF90, j); /* Set AGC Minimum gain */
4199  ixj_WriteDSPCommand(0x0020, j); /* to 0.125 (-18dB) */
4200 
4201  ixj_WriteDSPCommand(0xCF91, j); /* Set AGC Maximum gain */
4202  ixj_WriteDSPCommand(0x1000, j); /* to 16 (24dB) */
4203 
4204  ixj_WriteDSPCommand(0xCF92, j); /* Set AGC start gain */
4205  ixj_WriteDSPCommand(0x0800, j); /* to 8 (+18dB) */
4206 
4207  ixj_WriteDSPCommand(0xCF93, j); /* Set AGC hold time */
4208  ixj_WriteDSPCommand(0x1F40, j); /* to 2 seconds (units are 250us) */
4209 
4210  ixj_WriteDSPCommand(0xCF94, j); /* Set AGC Attack Time Constant */
4211  ixj_WriteDSPCommand(0x0005, j); /* to 8ms */
4212 
4213  ixj_WriteDSPCommand(0xCF95, j); /* Set AGC Decay Time Constant */
4214  ixj_WriteDSPCommand(0x000D, j); /* to 4096ms */
4215 
4216  ixj_WriteDSPCommand(0xCF96, j); /* Set AGC Attack Threshold */
4217  ixj_WriteDSPCommand(0x1200, j); /* to 25% */
4218 
4219  ixj_WriteDSPCommand(0xCF97, j); /* Set AGC Enable */
4220  ixj_WriteDSPCommand(0x0001, j); /* to on */
4221 
4222  break;
4223 
4224  case AEC_AUTO:
4225  ixj_WriteDSPCommand(0x0002, j); /* Attenuation scaling factor of 2 */
4226 
4227  ixj_WriteDSPCommand(0xE011, j);
4228  ixj_WriteDSPCommand(0x0100, j); /* Higher Threshold Floor */
4229 
4230  ixj_WriteDSPCommand(0xE012, j); /* Set Train and Lock */
4231 
4232  if(j->cardtype == QTI_LINEJACK || j->cardtype == QTI_PHONECARD)
4233  ixj_WriteDSPCommand(0x0224, j);
4234  else
4235  ixj_WriteDSPCommand(0x1224, j);
4236 
4237  ixj_WriteDSPCommand(0xE014, j);
4238  ixj_WriteDSPCommand(0x0003, j); /* Lock threshold at 3dB */
4239 
4240  ixj_WriteDSPCommand(0xE338, j); /* Set Echo Suppresser Attenuation to 0dB */
4241 
4242  break;
4243  }
4244  }
4245 }
4246 
4247 static void aec_stop(IXJ *j)
4248 {
4249  j->aec_level = AEC_OFF;
4250  if (j->rec_codec == G729 || j->play_codec == G729 || j->rec_codec == G729B || j->play_codec == G729B) {
4251  ixj_WriteDSPCommand(0xE022, j); /* Move AEC filter buffer back */
4252 
4253  ixj_WriteDSPCommand(0x0700, j);
4254  }
4255  if (j->play_mode != -1 && j->rec_mode != -1)
4256  {
4257  ixj_WriteDSPCommand(0xB002, j); /* AEC Stop */
4258  }
4259 }
4260 
4261 static int set_play_codec(IXJ *j, int rate)
4262 {
4263  int retval = 0;
4264 
4265  j->play_codec = rate;
4266 
4267  switch (rate) {
4268  case G723_63:
4269  if (j->ver.low != 0x12 || ixj_convert_loaded) {
4270  j->play_frame_size = 12;
4271  j->play_mode = 0;
4272  } else {
4273  retval = 1;
4274  }
4275  break;
4276  case G723_53:
4277  if (j->ver.low != 0x12 || ixj_convert_loaded) {
4278  j->play_frame_size = 10;
4279  j->play_mode = 0;
4280  } else {
4281  retval = 1;
4282  }
4283  break;
4284  case TS85:
4285  if (j->dsp.low == 0x20 || j->flags.ts85_loaded) {
4286  j->play_frame_size = 16;
4287  j->play_mode = 0;
4288  } else {
4289  retval = 1;
4290  }
4291  break;
4292  case TS48:
4293  if (j->ver.low != 0x12 || ixj_convert_loaded) {
4294  j->play_frame_size = 9;
4295  j->play_mode = 0;
4296  } else {
4297  retval = 1;
4298  }
4299  break;
4300  case TS41:
4301  if (j->ver.low != 0x12 || ixj_convert_loaded) {
4302  j->play_frame_size = 8;
4303  j->play_mode = 0;
4304  } else {
4305  retval = 1;
4306  }
4307  break;
4308  case G728:
4309  if (j->dsp.low != 0x20) {
4310  j->play_frame_size = 48;
4311  j->play_mode = 0;
4312  } else {
4313  retval = 1;
4314  }
4315  break;
4316  case G729:
4317  if (j->dsp.low != 0x20) {
4318  if (!j->flags.g729_loaded) {
4319  retval = 1;
4320  break;
4321  }
4322  switch (j->baseframe.low) {
4323  case 0xA0:
4324  j->play_frame_size = 10;
4325  break;
4326  case 0x50:
4327  j->play_frame_size = 5;
4328  break;
4329  default:
4330  j->play_frame_size = 15;
4331  break;
4332  }
4333  j->play_mode = 0;
4334  } else {
4335  retval = 1;
4336  }
4337  break;
4338  case G729B:
4339  if (j->dsp.low != 0x20) {
4340  if (!j->flags.g729_loaded) {
4341  retval = 1;
4342  break;
4343  }
4344  switch (j->baseframe.low) {
4345  case 0xA0:
4346  j->play_frame_size = 12;
4347  break;
4348  case 0x50:
4349  j->play_frame_size = 6;
4350  break;
4351  default:
4352  j->play_frame_size = 18;
4353  break;
4354  }
4355  j->play_mode = 0;
4356  } else {
4357  retval = 1;
4358  }
4359  break;
4360  case ULAW:
4361  switch (j->baseframe.low) {
4362  case 0xA0:
4363  j->play_frame_size = 80;
4364  break;
4365  case 0x50:
4366  j->play_frame_size = 40;
4367  break;
4368  default:
4369  j->play_frame_size = 120;
4370  break;
4371  }
4372  j->play_mode = 2;
4373  break;
4374  case ALAW:
4375  switch (j->baseframe.low) {
4376  case 0xA0:
4377  j->play_frame_size = 80;
4378  break;
4379  case 0x50:
4380  j->play_frame_size = 40;
4381  break;
4382  default:
4383  j->play_frame_size = 120;
4384  break;
4385  }
4386  j->play_mode = 2;
4387  break;
4388  case LINEAR16:
4389  switch (j->baseframe.low) {
4390  case 0xA0:
4391  j->play_frame_size = 160;
4392  break;
4393  case 0x50:
4394  j->play_frame_size = 80;
4395  break;
4396  default:
4397  j->play_frame_size = 240;
4398  break;
4399  }
4400  j->play_mode = 6;
4401  break;
4402  case LINEAR8:
4403  switch (j->baseframe.low) {
4404  case 0xA0:
4405  j->play_frame_size = 80;
4406  break;
4407  case 0x50:
4408  j->play_frame_size = 40;
4409  break;
4410  default:
4411  j->play_frame_size = 120;
4412  break;
4413  }
4414  j->play_mode = 4;
4415  break;
4416  case WSS:
4417  switch (j->baseframe.low) {
4418  case 0xA0:
4419  j->play_frame_size = 80;
4420  break;
4421  case 0x50:
4422  j->play_frame_size = 40;
4423  break;
4424  default:
4425  j->play_frame_size = 120;
4426  break;
4427  }
4428  j->play_mode = 5;
4429  break;
4430  default:
4431  kfree(j->write_buffer);
4432  j->play_frame_size = 0;
4433  j->play_mode = -1;
4434  j->write_buffer = NULL;
4435  j->write_buffer_size = 0;
4436  retval = 1;
4437  break;
4438  }
4439  return retval;
4440 }
4441 
4442 static int ixj_play_start(IXJ *j)
4443 {
4444  unsigned short cmd = 0x0000;
4445 
4446  if (j->write_buffer) {
4447  ixj_play_stop(j);
4448  }
4449 
4450  if(ixjdebug & 0x0002)
4451  printk("IXJ %d Starting Play Codec %d at %ld\n", j->board, j->play_codec, jiffies);
4452 
4453  j->flags.playing = 1;
4454  ixj_WriteDSPCommand(0x0FE0, j); /* Put the DSP in full power mode. */
4455 
4456  j->flags.play_first_frame = 1;
4457  j->drybuffer = 0;
4458 
4459  if (!j->play_mode) {
4460  switch (j->play_codec) {
4461  case G723_63:
4462  cmd = 0x5231;
4463  break;
4464  case G723_53:
4465  cmd = 0x5232;
4466  break;
4467  case TS85:
4468  cmd = 0x5230; /* TrueSpeech 8.5 */
4469 
4470  break;
4471  case TS48:
4472  cmd = 0x5233; /* TrueSpeech 4.8 */
4473 
4474  break;
4475  case TS41:
4476  cmd = 0x5234; /* TrueSpeech 4.1 */
4477 
4478  break;
4479  case G728:
4480  cmd = 0x5235;
4481  break;
4482  case G729:
4483  case G729B:
4484  cmd = 0x5236;
4485  break;
4486  default:
4487  return 1;
4488  }
4489  if (ixj_WriteDSPCommand(cmd, j))
4490  return -1;
4491  }
4493  if (!j->write_buffer) {
4494  printk("Write buffer allocation for ixj board %d failed!\n", j->board);
4495  return -ENOMEM;
4496  }
4497 /* j->write_buffers_empty = 2; */
4498  j->write_buffers_empty = 1;
4499  j->write_buffer_size = j->play_frame_size * 2;
4502 
4503  if (ixj_WriteDSPCommand(0x5202, j)) /* Set Poll sync mode */
4504 
4505  return -1;
4506 
4507  switch (j->play_mode) {
4508  case 0:
4509  cmd = 0x2C03;
4510  break;
4511  case 2:
4512  if (j->ver.low == 0x12) {
4513  cmd = 0x2C23;
4514  } else {
4515  cmd = 0x2C21;
4516  }
4517  break;
4518  case 4:
4519  if (j->ver.low == 0x12) {
4520  cmd = 0x2C43;
4521  } else {
4522  cmd = 0x2C41;
4523  }
4524  break;
4525  case 5:
4526  if (j->ver.low == 0x12) {
4527  cmd = 0x2C53;
4528  } else {
4529  cmd = 0x2C51;
4530  }
4531  break;
4532  case 6:
4533  if (j->ver.low == 0x12) {
4534  cmd = 0x2C63;
4535  } else {
4536  cmd = 0x2C61;
4537  }
4538  break;
4539  }
4540  if (ixj_WriteDSPCommand(cmd, j))
4541  return -1;
4542 
4543  if (ixj_WriteDSPCommand(0x2000, j)) /* Playback C2 */
4544  return -1;
4545 
4546  if (ixj_WriteDSPCommand(0x2000 + j->play_frame_size, j)) /* Playback C3 */
4547  return -1;
4548 
4549  if (j->flags.recording) {
4550  ixj_aec_start(j, j->aec_level);
4551  }
4552 
4553  return 0;
4554 }
4555 
4556 static void ixj_play_stop(IXJ *j)
4557 {
4558  if (ixjdebug & 0x0002)
4559  printk("IXJ %d Stopping Play Codec %d at %ld\n", j->board, j->play_codec, jiffies);
4560 
4561  kfree(j->write_buffer);
4562  j->write_buffer = NULL;
4563  j->write_buffer_size = 0;
4564  if (j->play_mode > -1) {
4565  ixj_WriteDSPCommand(0x5221, j); /* Stop playback and flush buffers. 8022 reference page 9-40 */
4566 
4567  j->play_mode = -1;
4568  }
4569  j->flags.playing = 0;
4570 }
4571 
4572 static inline int get_play_level(IXJ *j)
4573 {
4574  int retval;
4575 
4576  ixj_WriteDSPCommand(0xCF8F, j); /* 8022 Reference page 9-38 */
4577  return j->ssr.high << 8 | j->ssr.low;
4578  retval = j->ssr.high << 8 | j->ssr.low;
4579  retval = (retval * 256) / 240;
4580  return retval;
4581 }
4582 
4583 static unsigned int ixj_poll(struct file *file_p, poll_table * wait)
4584 {
4585  unsigned int mask = 0;
4586 
4587  IXJ *j = get_ixj(NUM(file_p->f_path.dentry->d_inode));
4588 
4589  poll_wait(file_p, &(j->poll_q), wait);
4590  if (j->read_buffer_ready > 0)
4591  mask |= POLLIN | POLLRDNORM; /* readable */
4592  if (j->write_buffers_empty > 0)
4593  mask |= POLLOUT | POLLWRNORM; /* writable */
4594  if (j->ex.bytes)
4595  mask |= POLLPRI;
4596  return mask;
4597 }
4598 
4599 static int ixj_play_tone(IXJ *j, char tone)
4600 {
4601  if (!j->tone_state) {
4602  if(ixjdebug & 0x0002) {
4603  printk("IXJ %d starting tone %d at %ld\n", j->board, tone, jiffies);
4604  }
4605  if (j->dsp.low == 0x20) {
4606  idle(j);
4607  }
4608  j->tone_start_jif = jiffies;
4609 
4610  j->tone_state = 1;
4611  }
4612 
4613  j->tone_index = tone;
4614  if (ixj_WriteDSPCommand(0x6000 + j->tone_index, j))
4615  return -1;
4616 
4617  return 0;
4618 }
4619 
4620 static int ixj_set_tone_on(unsigned short arg, IXJ *j)
4621 {
4622  j->tone_on_time = arg;
4623 
4624  if (ixj_WriteDSPCommand(0x6E04, j)) /* Set Tone On Period */
4625 
4626  return -1;
4627 
4628  if (ixj_WriteDSPCommand(arg, j))
4629  return -1;
4630 
4631  return 0;
4632 }
4633 
4634 static int SCI_WaitHighSCI(IXJ *j)
4635 {
4636  int cnt;
4637 
4638  j->pld_scrr.byte = inb_p(j->XILINXbase);
4639  if (!j->pld_scrr.bits.sci) {
4640  for (cnt = 0; cnt < 10; cnt++) {
4641  udelay(32);
4642  j->pld_scrr.byte = inb_p(j->XILINXbase);
4643 
4644  if ((j->pld_scrr.bits.sci))
4645  return 1;
4646  }
4647  if (ixjdebug & 0x0001)
4648  printk(KERN_INFO "SCI Wait High failed %x\n", j->pld_scrr.byte);
4649  return 0;
4650  } else
4651  return 1;
4652 }
4653 
4654 static int SCI_WaitLowSCI(IXJ *j)
4655 {
4656  int cnt;
4657 
4658  j->pld_scrr.byte = inb_p(j->XILINXbase);
4659  if (j->pld_scrr.bits.sci) {
4660  for (cnt = 0; cnt < 10; cnt++) {
4661  udelay(32);
4662  j->pld_scrr.byte = inb_p(j->XILINXbase);
4663 
4664  if (!(j->pld_scrr.bits.sci))
4665  return 1;
4666  }
4667  if (ixjdebug & 0x0001)
4668  printk(KERN_INFO "SCI Wait Low failed %x\n", j->pld_scrr.byte);
4669  return 0;
4670  } else
4671  return 1;
4672 }
4673 
4674 static int SCI_Control(IXJ *j, int control)
4675 {
4676  switch (control) {
4677  case SCI_End:
4678  j->pld_scrw.bits.c0 = 0; /* Set PLD Serial control interface */
4679 
4680  j->pld_scrw.bits.c1 = 0; /* to no selection */
4681 
4682  break;
4683  case SCI_Enable_DAA:
4684  j->pld_scrw.bits.c0 = 1; /* Set PLD Serial control interface */
4685 
4686  j->pld_scrw.bits.c1 = 0; /* to write to DAA */
4687 
4688  break;
4689  case SCI_Enable_Mixer:
4690  j->pld_scrw.bits.c0 = 0; /* Set PLD Serial control interface */
4691 
4692  j->pld_scrw.bits.c1 = 1; /* to write to mixer */
4693 
4694  break;
4695  case SCI_Enable_EEPROM:
4696  j->pld_scrw.bits.c0 = 1; /* Set PLD Serial control interface */
4697 
4698  j->pld_scrw.bits.c1 = 1; /* to write to EEPROM */
4699 
4700  break;
4701  default:
4702  return 0;
4703  break;
4704  }
4705  outb_p(j->pld_scrw.byte, j->XILINXbase);
4706 
4707  switch (control) {
4708  case SCI_End:
4709  return 1;
4710  break;
4711  case SCI_Enable_DAA:
4712  case SCI_Enable_Mixer:
4713  case SCI_Enable_EEPROM:
4714  if (!SCI_WaitHighSCI(j))
4715  return 0;
4716  break;
4717  default:
4718  return 0;
4719  break;
4720  }
4721  return 1;
4722 }
4723 
4724 static int SCI_Prepare(IXJ *j)
4725 {
4726  if (!SCI_Control(j, SCI_End))
4727  return 0;
4728 
4729  if (!SCI_WaitLowSCI(j))
4730  return 0;
4731 
4732  return 1;
4733 }
4734 
4735 static int ixj_get_mixer(long val, IXJ *j)
4736 {
4737  int reg = (val & 0x1F00) >> 8;
4738  return j->mix.vol[reg];
4739 }
4740 
4741 static int ixj_mixer(long val, IXJ *j)
4742 {
4743  BYTES bytes;
4744 
4745  bytes.high = (val & 0x1F00) >> 8;
4746  bytes.low = val & 0x00FF;
4747 
4748  /* save mixer value so we can get back later on */
4749  j->mix.vol[bytes.high] = bytes.low;
4750 
4751  outb_p(bytes.high & 0x1F, j->XILINXbase + 0x03); /* Load Mixer Address */
4752 
4753  outb_p(bytes.low, j->XILINXbase + 0x02); /* Load Mixer Data */
4754 
4755  SCI_Control(j, SCI_Enable_Mixer);
4756 
4757  SCI_Control(j, SCI_End);
4758 
4759  return 0;
4760 }
4761 
4762 static int daa_load(BYTES * p_bytes, IXJ *j)
4763 {
4764  outb_p(p_bytes->high, j->XILINXbase + 0x03);
4765  outb_p(p_bytes->low, j->XILINXbase + 0x02);
4766  if (!SCI_Control(j, SCI_Enable_DAA))
4767  return 0;
4768  else
4769  return 1;
4770 }
4771 
4772 static int ixj_daa_cr4(IXJ *j, char reg)
4773 {
4774  BYTES bytes;
4775 
4776  switch (j->daa_mode) {
4777  case SOP_PU_SLEEP:
4778  bytes.high = 0x14;
4779  break;
4780  case SOP_PU_RINGING:
4781  bytes.high = 0x54;
4782  break;
4783  case SOP_PU_CONVERSATION:
4784  bytes.high = 0x94;
4785  break;
4786  case SOP_PU_PULSEDIALING:
4787  bytes.high = 0xD4;
4788  break;
4789  }
4790 
4791  j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.reg = reg;
4792 
4793  switch (j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGX) {
4794  case 0:
4795  j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 0;
4796  break;
4797  case 1:
4798  j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 2;
4799  break;
4800  case 2:
4801  j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 1;
4802  break;
4803  case 3:
4804  j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.bitreg.AGR_Z = 3;
4805  break;
4806  }
4807 
4808  bytes.low = j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.reg;
4809 
4810  if (!daa_load(&bytes, j))
4811  return 0;
4812 
4813  if (!SCI_Prepare(j))
4814  return 0;
4815 
4816  return 1;
4817 }
4818 
4819 static char daa_int_read(IXJ *j)
4820 {
4821  BYTES bytes;
4822 
4823  if (!SCI_Prepare(j))
4824  return 0;
4825 
4826  bytes.high = 0x38;
4827  bytes.low = 0x00;
4828  outb_p(bytes.high, j->XILINXbase + 0x03);
4829  outb_p(bytes.low, j->XILINXbase + 0x02);
4830 
4831  if (!SCI_Control(j, SCI_Enable_DAA))
4832  return 0;
4833 
4834  bytes.high = inb_p(j->XILINXbase + 0x03);
4835  bytes.low = inb_p(j->XILINXbase + 0x02);
4836  if (bytes.low != ALISDAA_ID_BYTE) {
4837  if (ixjdebug & 0x0001)
4838  printk("Cannot read DAA ID Byte high = %d low = %d\n", bytes.high, bytes.low);
4839  return 0;
4840  }
4841  if (!SCI_Control(j, SCI_Enable_DAA))
4842  return 0;
4843  if (!SCI_Control(j, SCI_End))
4844  return 0;
4845 
4846  bytes.high = inb_p(j->XILINXbase + 0x03);
4847  bytes.low = inb_p(j->XILINXbase + 0x02);
4848 
4849  j->m_DAAShadowRegs.XOP_REGS.XOP.xr0.reg = bytes.high;
4850 
4851  return 1;
4852 }
4853 
4854 static char daa_CR_read(IXJ *j, int cr)
4855 {
4856  IXJ_WORD wdata;
4857  BYTES bytes;
4858 
4859  if (!SCI_Prepare(j))
4860  return 0;
4861 
4862  switch (j->daa_mode) {
4863  case SOP_PU_SLEEP:
4864  bytes.high = 0x30 + cr;
4865  break;
4866  case SOP_PU_RINGING:
4867  bytes.high = 0x70 + cr;
4868  break;
4869  case SOP_PU_CONVERSATION:
4870  bytes.high = 0xB0 + cr;
4871  break;
4872  case SOP_PU_PULSEDIALING:
4873  default:
4874  bytes.high = 0xF0 + cr;
4875  break;
4876  }
4877 
4878  bytes.low = 0x00;
4879 
4880  outb_p(bytes.high, j->XILINXbase + 0x03);
4881  outb_p(bytes.low, j->XILINXbase + 0x02);
4882 
4883  if (!SCI_Control(j, SCI_Enable_DAA))
4884  return 0;
4885 
4886  bytes.high = inb_p(j->XILINXbase + 0x03);
4887  bytes.low = inb_p(j->XILINXbase + 0x02);
4888  if (bytes.low != ALISDAA_ID_BYTE) {
4889  if (ixjdebug & 0x0001)
4890  printk("Cannot read DAA ID Byte high = %d low = %d\n", bytes.high, bytes.low);
4891  return 0;
4892  }
4893  if (!SCI_Control(j, SCI_Enable_DAA))
4894  return 0;
4895  if (!SCI_Control(j, SCI_End))
4896  return 0;
4897 
4898  wdata.word = inw_p(j->XILINXbase + 0x02);
4899 
4900  switch(cr){
4901  case 5:
4902  j->m_DAAShadowRegs.SOP_REGS.SOP.cr5.reg = wdata.bytes.high;
4903  break;
4904  case 4:
4905  j->m_DAAShadowRegs.SOP_REGS.SOP.cr4.reg = wdata.bytes.high;
4906  break;
4907  case 3:
4908  j->m_DAAShadowRegs.SOP_REGS.SOP.cr3.reg = wdata.bytes.high;
4909  break;
4910  case 2:
4911  j->m_DAAShadowRegs.SOP_REGS.SOP.cr2.reg = wdata.bytes.high;
4912  break;
4913  case 1:
4914  j->m_DAAShadowRegs.SOP_REGS.SOP.cr1.reg = wdata.bytes.high;
4915  break;
4916  case 0:
4917  j->m_DAAShadowRegs.SOP_REGS.SOP.cr0.reg = wdata.bytes.high;
4918  break;
4919  default:
4920  return 0;
4921  }
4922  return 1;
4923 }
4924 
4925 static int ixj_daa_cid_reset(IXJ *j)
4926 {
4927  int i;
4928  BYTES bytes;
4929 
4930  if (ixjdebug & 0x0002)
4931  printk("DAA Clearing CID ram\n");
4932 
4933  if (!SCI_Prepare(j))
4934  return 0;
4935 
4936  bytes.high = 0x58;
4937  bytes.low = 0x00;
4938  outb_p(bytes.high, j->XILINXbase + 0x03);
4939  outb_p(bytes.low, j->XILINXbase + 0x02);
4940 
4941  if (!SCI_Control(j, SCI_Enable_DAA))
4942  return 0;