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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/module.h>#include <linux/device.h>#include <linux/serial_core.h>#include <linux/serial.h>#include <linux/tty.h>#include <linux/tty_flip.h>#include <linux/regmap.h>#include <linux/gpio.h>#include <linux/spi/spi.h>#include <linux/platform_data/max310x.h>Go to the source code of this file.
Data Structures | |
| struct | max310x_port |
Macros | |
| #define | MAX310X_MAJOR 204 |
| #define | MAX310X_MINOR 209 |
| #define | MAX310X_RHR_REG (0x00) /* RX FIFO */ |
| #define | MAX310X_THR_REG (0x00) /* TX FIFO */ |
| #define | MAX310X_IRQEN_REG (0x01) /* IRQ enable */ |
| #define | MAX310X_IRQSTS_REG (0x02) /* IRQ status */ |
| #define | MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ |
| #define | MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ |
| #define | MAX310X_SPCHR_IRQEN_REG (0x05) /* Special char IRQ enable */ |
| #define | MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ |
| #define | MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ |
| #define | MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ |
| #define | MAX310X_MODE1_REG (0x09) /* MODE1 */ |
| #define | MAX310X_MODE2_REG (0x0a) /* MODE2 */ |
| #define | MAX310X_LCR_REG (0x0b) /* LCR */ |
| #define | MAX310X_RXTO_REG (0x0c) /* RX timeout */ |
| #define | MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ |
| #define | MAX310X_IRDA_REG (0x0e) /* IRDA settings */ |
| #define | MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ |
| #define | MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ |
| #define | MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ |
| #define | MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ |
| #define | MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ |
| #define | MAX310X_XON1_REG (0x14) /* XON1 character */ |
| #define | MAX310X_XON2_REG (0x15) /* XON2 character */ |
| #define | MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ |
| #define | MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ |
| #define | MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ |
| #define | MAX310X_GPIODATA_REG (0x19) /* GPIO data */ |
| #define | MAX310X_PLLCFG_REG (0x1a) /* PLL config */ |
| #define | MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ |
| #define | MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ |
| #define | MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ |
| #define | MAX310X_CLKSRC_REG (0x1e) /* Clock source */ |
| #define | MAX3107_REVID_REG (0x1f) /* Revision identification */ |
| #define | MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ |
| #define | MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ |
| #define | MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ |
| #define | MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ |
| #define | MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ |
| #define | MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ |
| #define | MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ |
| #define | MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ |
| #define | MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ |
| #define | MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ |
| #define | MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ |
| #define | MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ |
| #define | MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ |
| #define | MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ |
| #define | MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ |
| #define | MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ |
| #define | MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ |
| #define | MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ |
| #define | MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ |
| #define | MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ |
| #define | MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ |
| #define | MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ |
| #define | MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ |
| #define | MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ |
| #define | MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ |
| #define | MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ |
| #define | MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ |
| #define | MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ |
| #define | MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ |
| #define | MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ |
| #define | MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ |
| #define | MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ |
| #define | MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ |
| #define | MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ |
| #define | MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ |
| #define | MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ |
| #define | MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ |
| #define | MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ |
| #define | MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ |
| #define | MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ |
| #define | MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ |
| #define | MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ |
| #define | MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ |
| #define | MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ |
| #define | MAX310X_LCR_LENGTH1_BIT |
| #define | MAX310X_LCR_STOPLEN_BIT |
| #define | MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ |
| #define | MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ |
| #define | MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ |
| #define | MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ |
| #define | MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ |
| #define | MAX310X_LCR_WORD_LEN_5 (0x00) |
| #define | MAX310X_LCR_WORD_LEN_6 (0x01) |
| #define | MAX310X_LCR_WORD_LEN_7 (0x02) |
| #define | MAX310X_LCR_WORD_LEN_8 (0x03) |
| #define | MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ |
| #define | MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ |
| #define | MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */ |
| #define | MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */ |
| #define | MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */ |
| #define | MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */ |
| #define | MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ |
| #define | MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ |
| #define | MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) |
| #define | MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) |
| #define | MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ |
| #define | MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ |
| #define | MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) |
| #define | MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) |
| #define | MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ |
| #define | MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ |
| #define | MAX310X_FLOWCTRL_GPIADDR_BIT |
| #define | MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ |
| #define | MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ |
| #define | MAX310X_FLOWCTRL_SWFLOW1_BIT |
| #define | MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ |
| #define | MAX310X_FLOWCTRL_SWFLOW3_BIT |
| #define | MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */ |
| #define | MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */ |
| #define | MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */ |
| #define | MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */ |
| #define | MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */ |
| #define | MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */ |
| #define | MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */ |
| #define | MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */ |
| #define | MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */ |
| #define | MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */ |
| #define | MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */ |
| #define | MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */ |
| #define | MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */ |
| #define | MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */ |
| #define | MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */ |
| #define | MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */ |
| #define | MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ |
| #define | MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ |
| #define | MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ |
| #define | MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ |
| #define | MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ |
| #define | MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ |
| #define | MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ |
| #define | MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ |
| #define | MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ |
| #define | MAX310X_FIFO_SIZE (128) |
| #define | MAX3107_REV_ID (0xa0) |
| #define | MAX3107_REV_MASK (0xfe) |
| #define | MAX310X_IRQ_TX |
| #define | MAX310X_IRQ_RX |
Enumerations | |
| enum | { MAX310X_TYPE_MAX3107 = 3107, MAX310X_TYPE_MAX3108 = 3108 } |
Functions | |
| MODULE_DEVICE_TABLE (spi, max310x_id_table) | |
| module_spi_driver (max310x_driver) | |
| MODULE_LICENSE ("GPL v2") | |
| MODULE_AUTHOR ("Alexander Shiyan <[email protected]>") | |
| MODULE_DESCRIPTION ("MAX310X serial driver") | |
| #define MAX3107_REVID_REG (0x1f) /* Revision identification */ |
| #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ |
| #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ |
| #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ |
| #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ |
| #define MAX310X_FIFOTRIGLVL_RX | ( | words | ) | (((words / 8) & 0x0f) << 4) |
| #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ |
| #define MAX310X_FIFOTRIGLVL_TX | ( | words | ) | ((words / 8) & 0x0f) |
| #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ |
| #define MAX310X_FLOWCTRL_GPIADDR_BIT |
| #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ |
| #define MAX310X_FLOWCTRL_SWFLOW1_BIT |
| #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ |
| #define MAX310X_FLOWCTRL_SWFLOW3_BIT |
| #define MAX310X_FLOWLVL_HALT | ( | words | ) | ((words / 8) & 0x0f) |
| #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ |
| #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ |
| #define MAX310X_FLOWLVL_RES | ( | words | ) | (((words / 8) & 0x0f) << 4) |
| #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ |
| #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ |
| #define MAX310X_IRQ_RX |
| #define MAX310X_IRQ_TX |
| #define MAX310X_LCR_LENGTH1_BIT |
| #define MAX310X_LCR_STOPLEN_BIT |
| #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ |
| #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ |
| #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ |
| #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ |
| #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ |
| #define MAX310X_SPCHR_IRQEN_REG (0x05) /* Special char IRQ enable */ |
| #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ |
| #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ |
| #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ |
| #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ |
| anonymous enum |
| MODULE_AUTHOR | ( | "Alexander Shiyan <[email protected]>" | ) |
| MODULE_DEVICE_TABLE | ( | spi | , |
| max310x_id_table | |||
| ) |
| MODULE_LICENSE | ( | "GPL v2" | ) |
| module_spi_driver | ( | max310x_driver | ) |
1.8.2