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me4000.c
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1 /*
2  comedi/drivers/me4000.c
3  Source code for the Meilhaus ME-4000 board family.
4 
5  COMEDI - Linux Control and Measurement Device Interface
6  Copyright (C) 2000 David A. Schleef <[email protected]>
7 
8  This program is free software; you can redistribute it and/or modify
9  it under the terms of the GNU General Public License as published by
10  the Free Software Foundation; either version 2 of the License, or
11  (at your option) any later version.
12 
13  This program is distributed in the hope that it will be useful,
14  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  GNU General Public License for more details.
17 
18  You should have received a copy of the GNU General Public License
19  along with this program; if not, write to the Free Software
20  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 
22  */
23 /*
24 Driver: me4000
25 Description: Meilhaus ME-4000 series boards
26 Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is
27 Author: gg (Guenter Gebhardt <[email protected]>)
28 Updated: Mon, 18 Mar 2002 15:34:01 -0800
29 Status: broken (no support for loading firmware)
30 
31 Supports:
32 
33  - Analog Input
34  - Analog Output
35  - Digital I/O
36  - Counter
37 
38 Configuration Options: not applicable, uses PCI auto config
39 
40 The firmware required by these boards is available in the
41 comedi_nonfree_firmware tarball available from
42 http://www.comedi.org. However, the driver's support for
43 loading the firmware through comedi_config is currently
44 broken.
45 
46  */
47 
48 #include <linux/interrupt.h>
49 #include "../comedidev.h"
50 
51 #include <linux/delay.h>
52 #include <linux/list.h>
53 #include <linux/spinlock.h>
54 
55 #include "comedi_fc.h"
56 #include "8253.h"
57 
58 #if 0
59 /* file removed due to GPL incompatibility */
60 #include "me4000_fw.h"
61 #endif
62 
63 #define PCI_VENDOR_ID_MEILHAUS 0x1402
64 
65 #define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650
66 #define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660
67 #define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661
68 #define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662
69 #define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663
70 #define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670
71 #define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671
72 #define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672
73 #define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673
74 #define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680
75 #define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681
76 #define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682
77 #define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683
78 
79 /*
80  * ME4000 Register map and bit defines
81  */
82 #define ME4000_AO_CHAN(x) ((x) * 0x18)
83 
84 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
85 #define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
86 #define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
87 #define ME4000_AO_CTRL_MASK_MODE (3 << 0)
88 #define ME4000_AO_CTRL_BIT_STOP (1 << 2)
89 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
90 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
91 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
92 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
93 #define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
94 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
95 #define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
96 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
97 #define ME4000_AO_STATUS_BIT_FSM (1 << 0)
98 #define ME4000_AO_STATUS_BIT_FF (1 << 1)
99 #define ME4000_AO_STATUS_BIT_HF (1 << 2)
100 #define ME4000_AO_STATUS_BIT_EF (1 << 3)
101 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
102 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
103 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
104 #define ME4000_AI_CTRL_REG 0x74
105 #define ME4000_AI_STATUS_REG 0x74
106 #define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
107 #define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
108 #define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
109 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
110 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
111 #define ME4000_AI_CTRL_BIT_STOP (1 << 5)
112 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
113 #define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
114 #define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
115 #define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
116 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
117 #define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
118 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
119 #define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
120 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
121 #define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
122 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
123 #define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
124 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
125 #define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
126 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
127 #define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
128 #define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
129 #define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
130 #define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
131 #define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
132 #define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
133 #define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
134 #define ME4000_AI_STATUS_BIT_LE (1 << 28)
135 #define ME4000_AI_STATUS_BIT_FSM (1 << 29)
136 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
137 #define ME4000_AI_CHANNEL_LIST_REG 0x78
138 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED (0 << 5)
139 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL (1 << 5)
140 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 (0 << 6)
141 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 (1 << 6)
142 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 (2 << 6)
143 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 (3 << 6)
144 #define ME4000_AI_LIST_LAST_ENTRY (1 << 8)
145 #define ME4000_AI_DATA_REG 0x7c
146 #define ME4000_AI_CHAN_TIMER_REG 0x80
147 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
148 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
149 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
150 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
151 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
152 #define ME4000_AI_START_REG 0x98
153 #define ME4000_IRQ_STATUS_REG 0x9c
154 #define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
155 #define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
156 #define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
157 #define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
158 #define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
159 #define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
160 #define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
161 #define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
162 #define ME4000_DIO_PORT_0_REG 0xa0
163 #define ME4000_DIO_PORT_1_REG 0xa4
164 #define ME4000_DIO_PORT_2_REG 0xa8
165 #define ME4000_DIO_PORT_3_REG 0xac
166 #define ME4000_DIO_DIR_REG 0xb0
167 #define ME4000_AO_LOADSETREG_XX 0xb4
168 #define ME4000_DIO_CTRL_REG 0xb8
169 #define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
170 #define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
171 #define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
172 #define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
173 #define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
174 #define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
175 #define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
176 #define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
177 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
178 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
179 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
180 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
181 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
182 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
183 #define ME4000_AO_DEMUX_ADJUST_REG 0xbc
184 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
185 #define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
186 
187 /*
188  * PLX Register map and bit defines
189  */
190 #define PLX_INTCSR 0x4c
191 #define PLX_INTCSR_LOCAL_INT1_EN (1 << 0)
192 #define PLX_INTCSR_LOCAL_INT1_POL (1 << 1)
193 #define PLX_INTCSR_LOCAL_INT1_STATE (1 << 2)
194 #define PLX_INTCSR_LOCAL_INT2_EN (1 << 3)
195 #define PLX_INTCSR_LOCAL_INT2_POL (1 << 4)
196 #define PLX_INTCSR_LOCAL_INT2_STATE (1 << 5)
197 #define PLX_INTCSR_PCI_INT_EN (1 << 6)
198 #define PLX_INTCSR_SOFT_INT (1 << 7)
199 #define PLX_ICR 0x50
200 #define PLX_ICR_BIT_EEPROM_CLOCK_SET (1 << 24)
201 #define PLX_ICR_BIT_EEPROM_CHIP_SELECT (1 << 25)
202 #define PLX_ICR_BIT_EEPROM_WRITE (1 << 26)
203 #define PLX_ICR_BIT_EEPROM_READ (1 << 27)
204 #define PLX_ICR_BIT_EEPROM_VALID (1 << 28)
205 #define PLX_ICR_MASK_EEPROM (0x1f << 24)
206 
207 #define EEPROM_DELAY 1
208 
209 #define ME4000_AI_FIFO_COUNT 2048
210 
211 #define ME4000_AI_MIN_TICKS 66
212 #define ME4000_AI_MIN_SAMPLE_TIME 2000
213 #define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
214 
215 #define ME4000_AI_CHANNEL_LIST_COUNT 1024
216 
217 struct me4000_info {
218  unsigned long plx_regbase;
219  unsigned long timer_regbase;
220 
221  unsigned int ao_readback[4];
222 };
223 
224 struct me4000_board {
225  const char *name;
226  unsigned short device_id;
227  int ao_nchan;
228  int ao_fifo;
229  int ai_nchan;
230  int ai_diff_nchan;
231  int ai_sh_nchan;
232  int ex_trig_analog;
233  int dio_nchan;
234  int has_counter;
235 };
236 
237 static const struct me4000_board me4000_boards[] = {
238  {
239  .name = "ME-4650",
240  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4650,
241  .ai_nchan = 16,
242  .dio_nchan = 32,
243  }, {
244  .name = "ME-4660",
245  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660,
246  .ai_nchan = 32,
247  .ai_diff_nchan = 16,
248  .dio_nchan = 32,
249  .has_counter = 1,
250  }, {
251  .name = "ME-4660i",
252  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660I,
253  .ai_nchan = 32,
254  .ai_diff_nchan = 16,
255  .dio_nchan = 32,
256  .has_counter = 1,
257  }, {
258  .name = "ME-4660s",
259  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660S,
260  .ai_nchan = 32,
261  .ai_diff_nchan = 16,
262  .ai_sh_nchan = 8,
263  .dio_nchan = 32,
264  .has_counter = 1,
265  }, {
266  .name = "ME-4660is",
267  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660IS,
268  .ai_nchan = 32,
269  .ai_diff_nchan = 16,
270  .ai_sh_nchan = 8,
271  .dio_nchan = 32,
272  .has_counter = 1,
273  }, {
274  .name = "ME-4670",
275  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670,
276  .ao_nchan = 4,
277  .ai_nchan = 32,
278  .ai_diff_nchan = 16,
279  .ex_trig_analog = 1,
280  .dio_nchan = 32,
281  .has_counter = 1,
282  }, {
283  .name = "ME-4670i",
284  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670I,
285  .ao_nchan = 4,
286  .ai_nchan = 32,
287  .ai_diff_nchan = 16,
288  .ex_trig_analog = 1,
289  .dio_nchan = 32,
290  .has_counter = 1,
291  }, {
292  .name = "ME-4670s",
293  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670S,
294  .ao_nchan = 4,
295  .ai_nchan = 32,
296  .ai_diff_nchan = 16,
297  .ai_sh_nchan = 8,
298  .ex_trig_analog = 1,
299  .dio_nchan = 32,
300  .has_counter = 1,
301  }, {
302  .name = "ME-4670is",
303  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670IS,
304  .ao_nchan = 4,
305  .ai_nchan = 32,
306  .ai_diff_nchan = 16,
307  .ai_sh_nchan = 8,
308  .ex_trig_analog = 1,
309  .dio_nchan = 32,
310  .has_counter = 1,
311  }, {
312  .name = "ME-4680",
313  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680,
314  .ao_nchan = 4,
315  .ao_fifo = 4,
316  .ai_nchan = 32,
317  .ai_diff_nchan = 16,
318  .ex_trig_analog = 1,
319  .dio_nchan = 32,
320  .has_counter = 1,
321  }, {
322  .name = "ME-4680i",
323  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680I,
324  .ao_nchan = 4,
325  .ao_fifo = 4,
326  .ai_nchan = 32,
327  .ai_diff_nchan = 16,
328  .ex_trig_analog = 1,
329  .dio_nchan = 32,
330  .has_counter = 1,
331  }, {
332  .name = "ME-4680s",
333  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680S,
334  .ao_nchan = 4,
335  .ao_fifo = 4,
336  .ai_nchan = 32,
337  .ai_diff_nchan = 16,
338  .ai_sh_nchan = 8,
339  .ex_trig_analog = 1,
340  .dio_nchan = 32,
341  .has_counter = 1,
342  }, {
343  .name = "ME-4680is",
344  .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680IS,
345  .ao_nchan = 4,
346  .ao_fifo = 4,
347  .ai_nchan = 32,
348  .ai_diff_nchan = 16,
349  .ai_sh_nchan = 8,
350  .ex_trig_analog = 1,
351  .dio_nchan = 32,
352  .has_counter = 1,
353  },
354 };
355 
356 static const struct comedi_lrange me4000_ai_range = {
357  4,
358  {
359  UNI_RANGE(2.5),
360  UNI_RANGE(10),
361  BIP_RANGE(2.5),
362  BIP_RANGE(10),
363  }
364 };
365 
366 #define FIRMWARE_NOT_AVAILABLE 1
367 #if FIRMWARE_NOT_AVAILABLE
368 extern unsigned char *xilinx_firm;
369 #endif
370 
371 static int xilinx_download(struct comedi_device *dev)
372 {
373  struct pci_dev *pcidev = comedi_to_pci_dev(dev);
374  struct me4000_info *info = dev->private;
375  unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
376  u32 value = 0;
377  wait_queue_head_t queue;
378  int idx = 0;
379  int size = 0;
380 
381  if (!xilinx_iobase)
382  return -ENODEV;
383 
384  init_waitqueue_head(&queue);
385 
386  /*
387  * Set PLX local interrupt 2 polarity to high.
388  * Interrupt is thrown by init pin of xilinx.
389  */
390  outl(0x10, info->plx_regbase + PLX_INTCSR);
391 
392  /* Set /CS and /WRITE of the Xilinx */
393  value = inl(info->plx_regbase + PLX_ICR);
394  value |= 0x100;
395  outl(value, info->plx_regbase + PLX_ICR);
396 
397  /* Init Xilinx with CS1 */
398  inb(xilinx_iobase + 0xC8);
399 
400  /* Wait until /INIT pin is set */
401  udelay(20);
402  if (!(inl(info->plx_regbase + PLX_INTCSR) & 0x20)) {
403  dev_err(dev->class_dev, "Can't init Xilinx\n");
404  return -EIO;
405  }
406 
407  /* Reset /CS and /WRITE of the Xilinx */
408  value = inl(info->plx_regbase + PLX_ICR);
409  value &= ~0x100;
410  outl(value, info->plx_regbase + PLX_ICR);
411  if (FIRMWARE_NOT_AVAILABLE) {
412  dev_err(dev->class_dev,
413  "xilinx firmware unavailable due to licensing, aborting");
414  return -EIO;
415  } else {
416  /* Download Xilinx firmware */
417  size = (xilinx_firm[0] << 24) + (xilinx_firm[1] << 16) +
418  (xilinx_firm[2] << 8) + xilinx_firm[3];
419  udelay(10);
420 
421  for (idx = 0; idx < size; idx++) {
422  outb(xilinx_firm[16 + idx], xilinx_iobase);
423  udelay(10);
424 
425  /* Check if BUSY flag is low */
426  if (inl(info->plx_regbase + PLX_ICR) & 0x20) {
427  dev_err(dev->class_dev,
428  "Xilinx is still busy (idx = %d)\n",
429  idx);
430  return -EIO;
431  }
432  }
433  }
434 
435  /* If done flag is high download was successful */
436  if (inl(info->plx_regbase + PLX_ICR) & 0x4) {
437  } else {
438  dev_err(dev->class_dev, "DONE flag is not set\n");
439  dev_err(dev->class_dev, "Download not successful\n");
440  return -EIO;
441  }
442 
443  /* Set /CS and /WRITE */
444  value = inl(info->plx_regbase + PLX_ICR);
445  value |= 0x100;
446  outl(value, info->plx_regbase + PLX_ICR);
447 
448  return 0;
449 }
450 
451 static void me4000_reset(struct comedi_device *dev)
452 {
453  struct me4000_info *info = dev->private;
454  unsigned long val;
455  int chan;
456 
457  /* Make a hardware reset */
458  val = inl(info->plx_regbase + PLX_ICR);
459  val |= 0x40000000;
460  outl(val, info->plx_regbase + PLX_ICR);
461  val &= ~0x40000000;
462  outl(val , info->plx_regbase + PLX_ICR);
463 
464  /* 0x8000 to the DACs means an output voltage of 0V */
465  for (chan = 0; chan < 4; chan++)
466  outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
467 
468  /* Set both stop bits in the analog input control register */
469  outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
470  dev->iobase + ME4000_AI_CTRL_REG);
471 
472  /* Set both stop bits in the analog output control register */
473  val = ME4000_AO_CTRL_BIT_IMMEDIATE_STOP | ME4000_AO_CTRL_BIT_STOP;
474  for (chan = 0; chan < 4; chan++)
475  outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
476 
477  /* Enable interrupts on the PLX */
478  outl(0x43, info->plx_regbase + PLX_INTCSR);
479 
480  /* Set the adustment register for AO demux */
481  outl(ME4000_AO_DEMUX_ADJUST_VALUE,
482  dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
483 
484  /*
485  * Set digital I/O direction for port 0
486  * to output on isolated versions
487  */
488  if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
489  outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
490 }
491 
492 /*=============================================================================
493  Analog input section
494  ===========================================================================*/
495 
496 static int me4000_ai_insn_read(struct comedi_device *dev,
497  struct comedi_subdevice *subdevice,
498  struct comedi_insn *insn, unsigned int *data)
499 {
500  const struct me4000_board *thisboard = comedi_board(dev);
501  int chan = CR_CHAN(insn->chanspec);
502  int rang = CR_RANGE(insn->chanspec);
503  int aref = CR_AREF(insn->chanspec);
504 
505  unsigned long entry = 0;
506  unsigned long tmp;
507  long lval;
508 
509  if (insn->n == 0) {
510  return 0;
511  } else if (insn->n > 1) {
512  dev_err(dev->class_dev, "Invalid instruction length %d\n",
513  insn->n);
514  return -EINVAL;
515  }
516 
517  switch (rang) {
518  case 0:
519  entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
520  break;
521  case 1:
522  entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
523  break;
524  case 2:
525  entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
526  break;
527  case 3:
528  entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
529  break;
530  default:
531  dev_err(dev->class_dev, "Invalid range specified\n");
532  return -EINVAL;
533  }
534 
535  switch (aref) {
536  case AREF_GROUND:
537  case AREF_COMMON:
538  if (chan >= thisboard->ai_nchan) {
539  dev_err(dev->class_dev,
540  "Analog input is not available\n");
541  return -EINVAL;
542  }
543  entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED | chan;
544  break;
545 
546  case AREF_DIFF:
547  if (rang == 0 || rang == 1) {
548  dev_err(dev->class_dev,
549  "Range must be bipolar when aref = diff\n");
550  return -EINVAL;
551  }
552 
553  if (chan >= thisboard->ai_diff_nchan) {
554  dev_err(dev->class_dev,
555  "Analog input is not available\n");
556  return -EINVAL;
557  }
558  entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL | chan;
559  break;
560  default:
561  dev_err(dev->class_dev, "Invalid aref specified\n");
562  return -EINVAL;
563  }
564 
565  entry |= ME4000_AI_LIST_LAST_ENTRY;
566 
567  /* Clear channel list, data fifo and both stop bits */
568  tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
569  tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
570  ME4000_AI_CTRL_BIT_DATA_FIFO |
571  ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
572  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
573 
574  /* Set the acquisition mode to single */
575  tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
576  ME4000_AI_CTRL_BIT_MODE_2);
577  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
578 
579  /* Enable channel list and data fifo */
580  tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
581  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
582 
583  /* Generate channel list entry */
584  outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
585 
586  /* Set the timer to maximum sample rate */
587  outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
588  outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
589 
590  /* Start conversion by dummy read */
591  inl(dev->iobase + ME4000_AI_START_REG);
592 
593  /* Wait until ready */
594  udelay(10);
595  if (!(inl(dev->iobase + ME4000_AI_STATUS_REG) &
596  ME4000_AI_STATUS_BIT_EF_DATA)) {
597  dev_err(dev->class_dev, "Value not available after wait\n");
598  return -EIO;
599  }
600 
601  /* Read value from data fifo */
602  lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
603  data[0] = lval ^ 0x8000;
604 
605  return 1;
606 }
607 
608 static int me4000_ai_cancel(struct comedi_device *dev,
609  struct comedi_subdevice *s)
610 {
611  unsigned long tmp;
612 
613  /* Stop any running conversion */
614  tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
615  tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
616  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
617 
618  /* Clear the control register */
619  outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
620 
621  return 0;
622 }
623 
624 static int ai_check_chanlist(struct comedi_device *dev,
625  struct comedi_subdevice *s, struct comedi_cmd *cmd)
626 {
627  const struct me4000_board *thisboard = comedi_board(dev);
628  int aref;
629  int i;
630 
631  /* Check whether a channel list is available */
632  if (!cmd->chanlist_len) {
633  dev_err(dev->class_dev, "No channel list available\n");
634  return -EINVAL;
635  }
636 
637  /* Check the channel list size */
638  if (cmd->chanlist_len > ME4000_AI_CHANNEL_LIST_COUNT) {
639  dev_err(dev->class_dev, "Channel list is to large\n");
640  return -EINVAL;
641  }
642 
643  /* Check the pointer */
644  if (!cmd->chanlist) {
645  dev_err(dev->class_dev, "NULL pointer to channel list\n");
646  return -EFAULT;
647  }
648 
649  /* Check whether aref is equal for all entries */
650  aref = CR_AREF(cmd->chanlist[0]);
651  for (i = 0; i < cmd->chanlist_len; i++) {
652  if (CR_AREF(cmd->chanlist[i]) != aref) {
653  dev_err(dev->class_dev,
654  "Mode is not equal for all entries\n");
655  return -EINVAL;
656  }
657  }
658 
659  /* Check whether channels are available for this ending */
660  if (aref == SDF_DIFF) {
661  for (i = 0; i < cmd->chanlist_len; i++) {
662  if (CR_CHAN(cmd->chanlist[i]) >=
663  thisboard->ai_diff_nchan) {
664  dev_err(dev->class_dev,
665  "Channel number to high\n");
666  return -EINVAL;
667  }
668  }
669  } else {
670  for (i = 0; i < cmd->chanlist_len; i++) {
671  if (CR_CHAN(cmd->chanlist[i]) >= thisboard->ai_nchan) {
672  dev_err(dev->class_dev,
673  "Channel number to high\n");
674  return -EINVAL;
675  }
676  }
677  }
678 
679  /* Check if bipolar is set for all entries when in differential mode */
680  if (aref == SDF_DIFF) {
681  for (i = 0; i < cmd->chanlist_len; i++) {
682  if (CR_RANGE(cmd->chanlist[i]) != 1 &&
683  CR_RANGE(cmd->chanlist[i]) != 2) {
684  dev_err(dev->class_dev,
685  "Bipolar is not selected in differential mode\n");
686  return -EINVAL;
687  }
688  }
689  }
690 
691  return 0;
692 }
693 
694 static int ai_round_cmd_args(struct comedi_device *dev,
695  struct comedi_subdevice *s,
696  struct comedi_cmd *cmd,
697  unsigned int *init_ticks,
698  unsigned int *scan_ticks, unsigned int *chan_ticks)
699 {
700 
701  int rest;
702 
703  *init_ticks = 0;
704  *scan_ticks = 0;
705  *chan_ticks = 0;
706 
707  if (cmd->start_arg) {
708  *init_ticks = (cmd->start_arg * 33) / 1000;
709  rest = (cmd->start_arg * 33) % 1000;
710 
711  if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
712  if (rest > 33)
713  (*init_ticks)++;
714  } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
715  if (rest)
716  (*init_ticks)++;
717  }
718  }
719 
720  if (cmd->scan_begin_arg) {
721  *scan_ticks = (cmd->scan_begin_arg * 33) / 1000;
722  rest = (cmd->scan_begin_arg * 33) % 1000;
723 
724  if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
725  if (rest > 33)
726  (*scan_ticks)++;
727  } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
728  if (rest)
729  (*scan_ticks)++;
730  }
731  }
732 
733  if (cmd->convert_arg) {
734  *chan_ticks = (cmd->convert_arg * 33) / 1000;
735  rest = (cmd->convert_arg * 33) % 1000;
736 
737  if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
738  if (rest > 33)
739  (*chan_ticks)++;
740  } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
741  if (rest)
742  (*chan_ticks)++;
743  }
744  }
745 
746  return 0;
747 }
748 
749 static void ai_write_timer(struct comedi_device *dev,
750  unsigned int init_ticks,
751  unsigned int scan_ticks, unsigned int chan_ticks)
752 {
753  outl(init_ticks - 1, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG);
754  outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);
755 
756  if (scan_ticks) {
757  outl(scan_ticks - 1, dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG);
758  outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);
759  }
760 
761  outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
762  outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
763 }
764 
765 static int ai_write_chanlist(struct comedi_device *dev,
766  struct comedi_subdevice *s, struct comedi_cmd *cmd)
767 {
768  unsigned int entry;
769  unsigned int chan;
770  unsigned int rang;
771  unsigned int aref;
772  int i;
773 
774  for (i = 0; i < cmd->chanlist_len; i++) {
775  chan = CR_CHAN(cmd->chanlist[i]);
776  rang = CR_RANGE(cmd->chanlist[i]);
777  aref = CR_AREF(cmd->chanlist[i]);
778 
779  entry = chan;
780 
781  if (rang == 0)
782  entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
783  else if (rang == 1)
784  entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
785  else if (rang == 2)
786  entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
787  else
788  entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
789 
790  if (aref == SDF_DIFF)
791  entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
792  else
793  entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED;
794 
795  outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
796  }
797 
798  return 0;
799 }
800 
801 static int ai_prepare(struct comedi_device *dev,
802  struct comedi_subdevice *s,
803  struct comedi_cmd *cmd,
804  unsigned int init_ticks,
805  unsigned int scan_ticks, unsigned int chan_ticks)
806 {
807 
808  unsigned long tmp = 0;
809 
810  /* Write timer arguments */
811  ai_write_timer(dev, init_ticks, scan_ticks, chan_ticks);
812 
813  /* Reset control register */
814  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
815 
816  /* Start sources */
817  if ((cmd->start_src == TRIG_EXT &&
818  cmd->scan_begin_src == TRIG_TIMER &&
819  cmd->convert_src == TRIG_TIMER) ||
820  (cmd->start_src == TRIG_EXT &&
821  cmd->scan_begin_src == TRIG_FOLLOW &&
822  cmd->convert_src == TRIG_TIMER)) {
823  tmp = ME4000_AI_CTRL_BIT_MODE_1 |
824  ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
825  ME4000_AI_CTRL_BIT_DATA_FIFO;
826  } else if (cmd->start_src == TRIG_EXT &&
827  cmd->scan_begin_src == TRIG_EXT &&
828  cmd->convert_src == TRIG_TIMER) {
829  tmp = ME4000_AI_CTRL_BIT_MODE_2 |
830  ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
831  ME4000_AI_CTRL_BIT_DATA_FIFO;
832  } else if (cmd->start_src == TRIG_EXT &&
833  cmd->scan_begin_src == TRIG_EXT &&
834  cmd->convert_src == TRIG_EXT) {
835  tmp = ME4000_AI_CTRL_BIT_MODE_0 |
836  ME4000_AI_CTRL_BIT_MODE_1 |
837  ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
838  ME4000_AI_CTRL_BIT_DATA_FIFO;
839  } else {
840  tmp = ME4000_AI_CTRL_BIT_MODE_0 |
841  ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
842  ME4000_AI_CTRL_BIT_DATA_FIFO;
843  }
844 
845  /* Stop triggers */
846  if (cmd->stop_src == TRIG_COUNT) {
847  outl(cmd->chanlist_len * cmd->stop_arg,
848  dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
849  tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
850  } else if (cmd->stop_src == TRIG_NONE &&
851  cmd->scan_end_src == TRIG_COUNT) {
852  outl(cmd->scan_end_arg,
853  dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
854  tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
855  } else {
856  tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
857  }
858 
859  /* Write the setup to the control register */
860  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
861 
862  /* Write the channel list */
863  ai_write_chanlist(dev, s, cmd);
864 
865  return 0;
866 }
867 
868 static int me4000_ai_do_cmd(struct comedi_device *dev,
869  struct comedi_subdevice *s)
870 {
871  int err;
872  unsigned int init_ticks = 0;
873  unsigned int scan_ticks = 0;
874  unsigned int chan_ticks = 0;
875  struct comedi_cmd *cmd = &s->async->cmd;
876 
877  /* Reset the analog input */
878  err = me4000_ai_cancel(dev, s);
879  if (err)
880  return err;
881 
882  /* Round the timer arguments */
883  err = ai_round_cmd_args(dev,
884  s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
885  if (err)
886  return err;
887 
888  /* Prepare the AI for acquisition */
889  err = ai_prepare(dev, s, cmd, init_ticks, scan_ticks, chan_ticks);
890  if (err)
891  return err;
892 
893  /* Start acquistion by dummy read */
894  inl(dev->iobase + ME4000_AI_START_REG);
895 
896  return 0;
897 }
898 
899 static int me4000_ai_do_cmd_test(struct comedi_device *dev,
900  struct comedi_subdevice *s,
901  struct comedi_cmd *cmd)
902 {
903 
904  unsigned int init_ticks;
905  unsigned int chan_ticks;
906  unsigned int scan_ticks;
907  int err = 0;
908 
909  /* Only rounding flags are implemented */
910  cmd->flags &= TRIG_ROUND_NEAREST | TRIG_ROUND_UP | TRIG_ROUND_DOWN;
911 
912  /* Round the timer arguments */
913  ai_round_cmd_args(dev, s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
914 
915  /* Step 1 : check if triggers are trivially valid */
916 
917  err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
918  err |= cfc_check_trigger_src(&cmd->scan_begin_src,
919  TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT);
920  err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
921  err |= cfc_check_trigger_src(&cmd->scan_end_src,
922  TRIG_NONE | TRIG_COUNT);
923  err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT);
924 
925  if (err)
926  return 1;
927 
928  /* Step 2a : make sure trigger sources are unique */
929 
930  err |= cfc_check_trigger_is_unique(cmd->start_src);
931  err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
932  err |= cfc_check_trigger_is_unique(cmd->convert_src);
933  err |= cfc_check_trigger_is_unique(cmd->scan_end_src);
934  err |= cfc_check_trigger_is_unique(cmd->stop_src);
935 
936  /* Step 2b : and mutually compatible */
937 
938  if (cmd->start_src == TRIG_NOW &&
939  cmd->scan_begin_src == TRIG_TIMER &&
940  cmd->convert_src == TRIG_TIMER) {
941  } else if (cmd->start_src == TRIG_NOW &&
942  cmd->scan_begin_src == TRIG_FOLLOW &&
943  cmd->convert_src == TRIG_TIMER) {
944  } else if (cmd->start_src == TRIG_EXT &&
945  cmd->scan_begin_src == TRIG_TIMER &&
946  cmd->convert_src == TRIG_TIMER) {
947  } else if (cmd->start_src == TRIG_EXT &&
948  cmd->scan_begin_src == TRIG_FOLLOW &&
949  cmd->convert_src == TRIG_TIMER) {
950  } else if (cmd->start_src == TRIG_EXT &&
951  cmd->scan_begin_src == TRIG_EXT &&
952  cmd->convert_src == TRIG_TIMER) {
953  } else if (cmd->start_src == TRIG_EXT &&
954  cmd->scan_begin_src == TRIG_EXT &&
955  cmd->convert_src == TRIG_EXT) {
956  } else {
957  err |= -EINVAL;
958  }
959 
960  if (cmd->stop_src == TRIG_NONE && cmd->scan_end_src == TRIG_NONE) {
961  } else if (cmd->stop_src == TRIG_COUNT &&
962  cmd->scan_end_src == TRIG_NONE) {
963  } else if (cmd->stop_src == TRIG_NONE &&
964  cmd->scan_end_src == TRIG_COUNT) {
965  } else if (cmd->stop_src == TRIG_COUNT &&
966  cmd->scan_end_src == TRIG_COUNT) {
967  } else {
968  err |= -EINVAL;
969  }
970 
971  if (err)
972  return 2;
973 
974  /*
975  * Stage 3. Check if arguments are generally valid.
976  */
977  if (cmd->chanlist_len < 1) {
978  dev_err(dev->class_dev, "No channel list\n");
979  cmd->chanlist_len = 1;
980  err++;
981  }
982  if (init_ticks < 66) {
983  dev_err(dev->class_dev, "Start arg to low\n");
984  cmd->start_arg = 2000;
985  err++;
986  }
987  if (scan_ticks && scan_ticks < 67) {
988  dev_err(dev->class_dev, "Scan begin arg to low\n");
989  cmd->scan_begin_arg = 2031;
990  err++;
991  }
992  if (chan_ticks < 66) {
993  dev_err(dev->class_dev, "Convert arg to low\n");
994  cmd->convert_arg = 2000;
995  err++;
996  }
997 
998  if (err)
999  return 3;
1000 
1001  /*
1002  * Stage 4. Check for argument conflicts.
1003  */
1004  if (cmd->start_src == TRIG_NOW &&
1005  cmd->scan_begin_src == TRIG_TIMER &&
1006  cmd->convert_src == TRIG_TIMER) {
1007 
1008  /* Check timer arguments */
1009  if (init_ticks < ME4000_AI_MIN_TICKS) {
1010  dev_err(dev->class_dev, "Invalid start arg\n");
1011  cmd->start_arg = 2000; /* 66 ticks at least */
1012  err++;
1013  }
1014  if (chan_ticks < ME4000_AI_MIN_TICKS) {
1015  dev_err(dev->class_dev, "Invalid convert arg\n");
1016  cmd->convert_arg = 2000; /* 66 ticks at least */
1017  err++;
1018  }
1019  if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1020  dev_err(dev->class_dev, "Invalid scan end arg\n");
1021 
1022  /* At least one tick more */
1023  cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1024  err++;
1025  }
1026  } else if (cmd->start_src == TRIG_NOW &&
1027  cmd->scan_begin_src == TRIG_FOLLOW &&
1028  cmd->convert_src == TRIG_TIMER) {
1029 
1030  /* Check timer arguments */
1031  if (init_ticks < ME4000_AI_MIN_TICKS) {
1032  dev_err(dev->class_dev, "Invalid start arg\n");
1033  cmd->start_arg = 2000; /* 66 ticks at least */
1034  err++;
1035  }
1036  if (chan_ticks < ME4000_AI_MIN_TICKS) {
1037  dev_err(dev->class_dev, "Invalid convert arg\n");
1038  cmd->convert_arg = 2000; /* 66 ticks at least */
1039  err++;
1040  }
1041  } else if (cmd->start_src == TRIG_EXT &&
1042  cmd->scan_begin_src == TRIG_TIMER &&
1043  cmd->convert_src == TRIG_TIMER) {
1044 
1045  /* Check timer arguments */
1046  if (init_ticks < ME4000_AI_MIN_TICKS) {
1047  dev_err(dev->class_dev, "Invalid start arg\n");
1048  cmd->start_arg = 2000; /* 66 ticks at least */
1049  err++;
1050  }
1051  if (chan_ticks < ME4000_AI_MIN_TICKS) {
1052  dev_err(dev->class_dev, "Invalid convert arg\n");
1053  cmd->convert_arg = 2000; /* 66 ticks at least */
1054  err++;
1055  }
1056  if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1057  dev_err(dev->class_dev, "Invalid scan end arg\n");
1058 
1059  /* At least one tick more */
1060  cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1061  err++;
1062  }
1063  } else if (cmd->start_src == TRIG_EXT &&
1064  cmd->scan_begin_src == TRIG_FOLLOW &&
1065  cmd->convert_src == TRIG_TIMER) {
1066 
1067  /* Check timer arguments */
1068  if (init_ticks < ME4000_AI_MIN_TICKS) {
1069  dev_err(dev->class_dev, "Invalid start arg\n");
1070  cmd->start_arg = 2000; /* 66 ticks at least */
1071  err++;
1072  }
1073  if (chan_ticks < ME4000_AI_MIN_TICKS) {
1074  dev_err(dev->class_dev, "Invalid convert arg\n");
1075  cmd->convert_arg = 2000; /* 66 ticks at least */
1076  err++;
1077  }
1078  } else if (cmd->start_src == TRIG_EXT &&
1079  cmd->scan_begin_src == TRIG_EXT &&
1080  cmd->convert_src == TRIG_TIMER) {
1081 
1082  /* Check timer arguments */
1083  if (init_ticks < ME4000_AI_MIN_TICKS) {
1084  dev_err(dev->class_dev, "Invalid start arg\n");
1085  cmd->start_arg = 2000; /* 66 ticks at least */
1086  err++;
1087  }
1088  if (chan_ticks < ME4000_AI_MIN_TICKS) {
1089  dev_err(dev->class_dev, "Invalid convert arg\n");
1090  cmd->convert_arg = 2000; /* 66 ticks at least */
1091  err++;
1092  }
1093  } else if (cmd->start_src == TRIG_EXT &&
1094  cmd->scan_begin_src == TRIG_EXT &&
1095  cmd->convert_src == TRIG_EXT) {
1096 
1097  /* Check timer arguments */
1098  if (init_ticks < ME4000_AI_MIN_TICKS) {
1099  dev_err(dev->class_dev, "Invalid start arg\n");
1100  cmd->start_arg = 2000; /* 66 ticks at least */
1101  err++;
1102  }
1103  }
1104  if (cmd->stop_src == TRIG_COUNT) {
1105  if (cmd->stop_arg == 0) {
1106  dev_err(dev->class_dev, "Invalid stop arg\n");
1107  cmd->stop_arg = 1;
1108  err++;
1109  }
1110  }
1111  if (cmd->scan_end_src == TRIG_COUNT) {
1112  if (cmd->scan_end_arg == 0) {
1113  dev_err(dev->class_dev, "Invalid scan end arg\n");
1114  cmd->scan_end_arg = 1;
1115  err++;
1116  }
1117  }
1118 
1119  if (err)
1120  return 4;
1121 
1122  /*
1123  * Stage 5. Check the channel list.
1124  */
1125  if (ai_check_chanlist(dev, s, cmd))
1126  return 5;
1127 
1128  return 0;
1129 }
1130 
1131 static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
1132 {
1133  unsigned int tmp;
1134  struct comedi_device *dev = dev_id;
1135  struct comedi_subdevice *s = &dev->subdevices[0];
1136  int i;
1137  int c = 0;
1138  long lval;
1139 
1140  if (!dev->attached)
1141  return IRQ_NONE;
1142 
1143  /* Reset all events */
1144  s->async->events = 0;
1145 
1146  /* Check if irq number is right */
1147  if (irq != dev->irq) {
1148  dev_err(dev->class_dev, "Incorrect interrupt num: %d\n", irq);
1149  return IRQ_HANDLED;
1150  }
1151 
1152  if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1153  ME4000_IRQ_STATUS_BIT_AI_HF) {
1154  /* Read status register to find out what happened */
1155  tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1156 
1157  if (!(tmp & ME4000_AI_STATUS_BIT_FF_DATA) &&
1158  !(tmp & ME4000_AI_STATUS_BIT_HF_DATA) &&
1159  (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1160  c = ME4000_AI_FIFO_COUNT;
1161 
1162  /*
1163  * FIFO overflow, so stop conversion
1164  * and disable all interrupts
1165  */
1166  tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1167  tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1168  ME4000_AI_CTRL_BIT_SC_IRQ);
1169  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1170 
1171  s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1172 
1173  dev_err(dev->class_dev, "FIFO overflow\n");
1174  } else if ((tmp & ME4000_AI_STATUS_BIT_FF_DATA)
1175  && !(tmp & ME4000_AI_STATUS_BIT_HF_DATA)
1176  && (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1177  s->async->events |= COMEDI_CB_BLOCK;
1178 
1179  c = ME4000_AI_FIFO_COUNT / 2;
1180  } else {
1181  dev_err(dev->class_dev,
1182  "Can't determine state of fifo\n");
1183  c = 0;
1184 
1185  /*
1186  * Undefined state, so stop conversion
1187  * and disable all interrupts
1188  */
1189  tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1190  tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1191  ME4000_AI_CTRL_BIT_SC_IRQ);
1192  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1193 
1194  s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1195 
1196  dev_err(dev->class_dev, "Undefined FIFO state\n");
1197  }
1198 
1199  for (i = 0; i < c; i++) {
1200  /* Read value from data fifo */
1201  lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1202  lval ^= 0x8000;
1203 
1204  if (!comedi_buf_put(s->async, lval)) {
1205  /*
1206  * Buffer overflow, so stop conversion
1207  * and disable all interrupts
1208  */
1209  tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1210  tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1211  ME4000_AI_CTRL_BIT_SC_IRQ);
1212  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1213 
1214  s->async->events |= COMEDI_CB_OVERFLOW;
1215 
1216  dev_err(dev->class_dev, "Buffer overflow\n");
1217 
1218  break;
1219  }
1220  }
1221 
1222  /* Work is done, so reset the interrupt */
1223  tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1224  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1225  tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1226  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1227  }
1228 
1229  if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1230  ME4000_IRQ_STATUS_BIT_SC) {
1231  s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOA;
1232 
1233  /*
1234  * Acquisition is complete, so stop
1235  * conversion and disable all interrupts
1236  */
1237  tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1238  tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1239  tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
1240  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1241 
1242  /* Poll data until fifo empty */
1243  while (inl(dev->iobase + ME4000_AI_CTRL_REG) &
1244  ME4000_AI_STATUS_BIT_EF_DATA) {
1245  /* Read value from data fifo */
1246  lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1247  lval ^= 0x8000;
1248 
1249  if (!comedi_buf_put(s->async, lval)) {
1250  dev_err(dev->class_dev, "Buffer overflow\n");
1251  s->async->events |= COMEDI_CB_OVERFLOW;
1252  break;
1253  }
1254  }
1255 
1256  /* Work is done, so reset the interrupt */
1257  tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1258  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1259  tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1260  outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1261  }
1262 
1263  if (s->async->events)
1264  comedi_event(dev, s);
1265 
1266  return IRQ_HANDLED;
1267 }
1268 
1269 /*=============================================================================
1270  Analog output section
1271  ===========================================================================*/
1272 
1273 static int me4000_ao_insn_write(struct comedi_device *dev,
1274  struct comedi_subdevice *s,
1275  struct comedi_insn *insn, unsigned int *data)
1276 {
1277  const struct me4000_board *thisboard = comedi_board(dev);
1278  struct me4000_info *info = dev->private;
1279  int chan = CR_CHAN(insn->chanspec);
1280  int rang = CR_RANGE(insn->chanspec);
1281  int aref = CR_AREF(insn->chanspec);
1282  unsigned long tmp;
1283 
1284  if (insn->n == 0) {
1285  return 0;
1286  } else if (insn->n > 1) {
1287  dev_err(dev->class_dev, "Invalid instruction length %d\n",
1288  insn->n);
1289  return -EINVAL;
1290  }
1291 
1292  if (chan >= thisboard->ao_nchan) {
1293  dev_err(dev->class_dev, "Invalid channel %d\n", insn->n);
1294  return -EINVAL;
1295  }
1296 
1297  if (rang != 0) {
1298  dev_err(dev->class_dev, "Invalid range %d\n", insn->n);
1299  return -EINVAL;
1300  }
1301 
1302  if (aref != AREF_GROUND && aref != AREF_COMMON) {
1303  dev_err(dev->class_dev, "Invalid aref %d\n", insn->n);
1304  return -EINVAL;
1305  }
1306 
1307  /* Stop any running conversion */
1308  tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan));
1309  tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
1310  outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan));
1311 
1312  /* Clear control register and set to single mode */
1313  outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));
1314 
1315  /* Write data value */
1316  outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));
1317 
1318  /* Store in the mirror */
1319  info->ao_readback[chan] = data[0];
1320 
1321  return 1;
1322 }
1323 
1324 static int me4000_ao_insn_read(struct comedi_device *dev,
1325  struct comedi_subdevice *s,
1326  struct comedi_insn *insn, unsigned int *data)
1327 {
1328  struct me4000_info *info = dev->private;
1329  int chan = CR_CHAN(insn->chanspec);
1330 
1331  if (insn->n == 0) {
1332  return 0;
1333  } else if (insn->n > 1) {
1334  dev_err(dev->class_dev, "Invalid instruction length\n");
1335  return -EINVAL;
1336  }
1337 
1338  data[0] = info->ao_readback[chan];
1339 
1340  return 1;
1341 }
1342 
1343 /*=============================================================================
1344  Digital I/O section
1345  ===========================================================================*/
1346 
1347 static int me4000_dio_insn_bits(struct comedi_device *dev,
1348  struct comedi_subdevice *s,
1349  struct comedi_insn *insn, unsigned int *data)
1350 {
1351  /*
1352  * The insn data consists of a mask in data[0] and the new data
1353  * in data[1]. The mask defines which bits we are concerning about.
1354  * The new data must be anded with the mask.
1355  * Each channel corresponds to a bit.
1356  */
1357  if (data[0]) {
1358  /* Check if requested ports are configured for output */
1359  if ((s->io_bits & data[0]) != data[0])
1360  return -EIO;
1361 
1362  s->state &= ~data[0];
1363  s->state |= data[0] & data[1];
1364 
1365  /* Write out the new digital output lines */
1366  outl((s->state >> 0) & 0xFF,
1367  dev->iobase + ME4000_DIO_PORT_0_REG);
1368  outl((s->state >> 8) & 0xFF,
1369  dev->iobase + ME4000_DIO_PORT_1_REG);
1370  outl((s->state >> 16) & 0xFF,
1371  dev->iobase + ME4000_DIO_PORT_2_REG);
1372  outl((s->state >> 24) & 0xFF,
1373  dev->iobase + ME4000_DIO_PORT_3_REG);
1374  }
1375 
1376  /* On return, data[1] contains the value of
1377  the digital input and output lines. */
1378  data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |
1379  ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |
1380  ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |
1381  ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);
1382 
1383  return insn->n;
1384 }
1385 
1386 static int me4000_dio_insn_config(struct comedi_device *dev,
1387  struct comedi_subdevice *s,
1388  struct comedi_insn *insn, unsigned int *data)
1389 {
1390  unsigned long tmp;
1391  int chan = CR_CHAN(insn->chanspec);
1392 
1393  switch (data[0]) {
1394  default:
1395  return -EINVAL;
1396  case INSN_CONFIG_DIO_QUERY:
1397  data[1] =
1398  (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1399  return insn->n;
1400  case INSN_CONFIG_DIO_INPUT:
1401  case INSN_CONFIG_DIO_OUTPUT:
1402  break;
1403  }
1404 
1405  /*
1406  * The input or output configuration of each digital line is
1407  * configured by a special insn_config instruction. chanspec
1408  * contains the channel to be changed, and data[0] contains the
1409  * value INSN_CONFIG_DIO_INPUT or INSN_CONFIG_DIO_OUTPUT.
1410  * On the ME-4000 it is only possible to switch port wise (8 bit)
1411  */
1412 
1413  tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG);
1414 
1415  if (data[0] == INSN_CONFIG_DIO_OUTPUT) {
1416  if (chan < 8) {
1417  s->io_bits |= 0xFF;
1418  tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 |
1419  ME4000_DIO_CTRL_BIT_MODE_1);
1420  tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1421  } else if (chan < 16) {
1422  /*
1423  * Chech for optoisolated ME-4000 version.
1424  * If one the first port is a fixed output
1425  * port and the second is a fixed input port.
1426  */
1427  if (!inl(dev->iobase + ME4000_DIO_DIR_REG))
1428  return -ENODEV;
1429 
1430  s->io_bits |= 0xFF00;
1431  tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1432  ME4000_DIO_CTRL_BIT_MODE_3);
1433  tmp |= ME4000_DIO_CTRL_BIT_MODE_2;
1434  } else if (chan < 24) {
1435  s->io_bits |= 0xFF0000;
1436  tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_4 |
1437  ME4000_DIO_CTRL_BIT_MODE_5);
1438  tmp |= ME4000_DIO_CTRL_BIT_MODE_4;
1439  } else if (chan < 32) {
1440  s->io_bits |= 0xFF000000;
1441  tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_6 |
1442  ME4000_DIO_CTRL_BIT_MODE_7);
1443  tmp |= ME4000_DIO_CTRL_BIT_MODE_6;
1444  } else {
1445  return -EINVAL;
1446  }
1447  } else {
1448  if (chan < 8) {
1449  /*
1450  * Chech for optoisolated ME-4000 version.
1451  * If one the first port is a fixed output
1452  * port and the second is a fixed input port.
1453  */
1454  if (!inl(dev->iobase + ME4000_DIO_DIR_REG))
1455  return -ENODEV;
1456 
1457  s->io_bits &= ~0xFF;
1458  tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 |
1459  ME4000_DIO_CTRL_BIT_MODE_1);
1460  } else if (chan < 16) {
1461  s->io_bits &= ~0xFF00;
1462  tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1463  ME4000_DIO_CTRL_BIT_MODE_3);
1464  } else if (chan < 24) {
1465  s->io_bits &= ~0xFF0000;
1466  tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_4 |
1467  ME4000_DIO_CTRL_BIT_MODE_5);
1468  } else if (chan < 32) {
1469  s->io_bits &= ~0xFF000000;
1470  tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_6 |
1471  ME4000_DIO_CTRL_BIT_MODE_7);
1472  } else {
1473  return -EINVAL;
1474  }
1475  }
1476 
1477  outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG);
1478 
1479  return 1;
1480 }
1481 
1482 /*=============================================================================
1483  Counter section
1484  ===========================================================================*/
1485 
1486 static int me4000_cnt_insn_config(struct comedi_device *dev,
1487  struct comedi_subdevice *s,
1488  struct comedi_insn *insn,
1489  unsigned int *data)
1490 {
1491  struct me4000_info *info = dev->private;
1492  int err;
1493 
1494  switch (data[0]) {
1495  case GPCT_RESET:
1496  if (insn->n != 1)
1497  return -EINVAL;
1498 
1499  err = i8254_load(info->timer_regbase, 0, insn->chanspec, 0,
1500  I8254_MODE0 | I8254_BINARY);
1501  if (err)
1502  return err;
1503  break;
1504  case GPCT_SET_OPERATION:
1505  if (insn->n != 2)
1506  return -EINVAL;
1507 
1508  err = i8254_set_mode(info->timer_regbase, 0, insn->chanspec,
1509  (data[1] << 1) | I8254_BINARY);
1510  if (err)
1511  return err;
1512  break;
1513  default:
1514  return -EINVAL;
1515  }
1516 
1517  return insn->n;
1518 }
1519 
1520 static int me4000_cnt_insn_read(struct comedi_device *dev,
1521  struct comedi_subdevice *s,
1522  struct comedi_insn *insn, unsigned int *data)
1523 {
1524  struct me4000_info *info = dev->private;
1525 
1526  if (insn->n == 0)
1527  return 0;
1528 
1529  if (insn->n > 1) {
1530  dev_err(dev->class_dev, "Invalid instruction length %d\n",
1531  insn->n);
1532  return -EINVAL;
1533  }
1534 
1535  data[0] = i8254_read(info->timer_regbase, 0, insn->chanspec);
1536 
1537  return 1;
1538 }
1539 
1540 static int me4000_cnt_insn_write(struct comedi_device *dev,
1541  struct comedi_subdevice *s,
1542  struct comedi_insn *insn, unsigned int *data)
1543 {
1544  struct me4000_info *info = dev->private;
1545 
1546  if (insn->n == 0) {
1547  return 0;
1548  } else if (insn->n > 1) {
1549  dev_err(dev->class_dev, "Invalid instruction length %d\n",
1550  insn->n);
1551  return -EINVAL;
1552  }
1553 
1554  i8254_write(info->timer_regbase, 0, insn->chanspec, data[0]);
1555 
1556  return 1;
1557 }
1558 
1559 static const void *me4000_find_boardinfo(struct comedi_device *dev,
1560  struct pci_dev *pcidev)
1561 {
1562  const struct me4000_board *thisboard;
1563  int i;
1564 
1565  for (i = 0; i < ARRAY_SIZE(me4000_boards); i++) {
1566  thisboard = &me4000_boards[i];
1567  if (thisboard->device_id == pcidev->device)
1568  return thisboard;
1569  }
1570  return NULL;
1571 }
1572 
1573 static int me4000_attach_pci(struct comedi_device *dev,
1574  struct pci_dev *pcidev)
1575 {
1576  const struct me4000_board *thisboard;
1577  struct me4000_info *info;
1578  struct comedi_subdevice *s;
1579  int result;
1580 
1581  comedi_set_hw_dev(dev, &pcidev->dev);
1582 
1583  thisboard = me4000_find_boardinfo(dev, pcidev);
1584  if (!thisboard)
1585  return -ENODEV;
1586  dev->board_ptr = thisboard;
1587  dev->board_name = thisboard->name;
1588 
1589  result = alloc_private(dev, sizeof(*info));
1590  if (result)
1591  return result;
1592  info = dev->private;
1593 
1594  result = comedi_pci_enable(pcidev, dev->board_name);
1595  if (result)
1596  return result;
1597 
1598  info->plx_regbase = pci_resource_start(pcidev, 1);
1599  dev->iobase = pci_resource_start(pcidev, 2);
1600  info->timer_regbase = pci_resource_start(pcidev, 3);
1601  if (!info->plx_regbase || !dev->iobase || !info->timer_regbase)
1602  return -ENODEV;
1603 
1604  result = xilinx_download(dev);
1605  if (result)
1606  return result;
1607 
1608  me4000_reset(dev);
1609 
1610  result = comedi_alloc_subdevices(dev, 4);
1611  if (result)
1612  return result;
1613 
1614  /*=========================================================================
1615  Analog input subdevice
1616  ========================================================================*/
1617 
1618  s = &dev->subdevices[0];
1619 
1620  if (thisboard->ai_nchan) {
1621  s->type = COMEDI_SUBD_AI;
1622  s->subdev_flags =
1623  SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF;
1624  s->n_chan = thisboard->ai_nchan;
1625  s->maxdata = 0xFFFF; /* 16 bit ADC */
1626  s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT;
1627  s->range_table = &me4000_ai_range;
1628  s->insn_read = me4000_ai_insn_read;
1629 
1630  if (pcidev->irq > 0) {
1631  if (request_irq(pcidev->irq, me4000_ai_isr,
1632  IRQF_SHARED, dev->board_name, dev)) {
1633  dev_warn(dev->class_dev,
1634  "request_irq failed\n");
1635  } else {
1636  dev->read_subdev = s;
1637  s->subdev_flags |= SDF_CMD_READ;
1638  s->cancel = me4000_ai_cancel;
1639  s->do_cmdtest = me4000_ai_do_cmd_test;
1640  s->do_cmd = me4000_ai_do_cmd;
1641 
1642  dev->irq = pcidev->irq;
1643  }
1644  } else {
1645  dev_warn(dev->class_dev, "No interrupt available\n");
1646  }
1647  } else {
1648  s->type = COMEDI_SUBD_UNUSED;
1649  }
1650 
1651  /*=========================================================================
1652  Analog output subdevice
1653  ========================================================================*/
1654 
1655  s = &dev->subdevices[1];
1656 
1657  if (thisboard->ao_nchan) {
1658  s->type = COMEDI_SUBD_AO;
1659  s->subdev_flags = SDF_WRITEABLE | SDF_COMMON | SDF_GROUND;
1660  s->n_chan = thisboard->ao_nchan;
1661  s->maxdata = 0xFFFF; /* 16 bit DAC */
1662  s->range_table = &range_bipolar10;
1663  s->insn_write = me4000_ao_insn_write;
1664  s->insn_read = me4000_ao_insn_read;
1665  } else {
1666  s->type = COMEDI_SUBD_UNUSED;
1667  }
1668 
1669  /*=========================================================================
1670  Digital I/O subdevice
1671  ========================================================================*/
1672 
1673  s = &dev->subdevices[2];
1674 
1675  if (thisboard->dio_nchan) {
1676  s->type = COMEDI_SUBD_DIO;
1677  s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1678  s->n_chan = thisboard->dio_nchan;
1679  s->maxdata = 1;
1680  s->range_table = &range_digital;
1681  s->insn_bits = me4000_dio_insn_bits;
1682  s->insn_config = me4000_dio_insn_config;
1683  } else {
1684  s->type = COMEDI_SUBD_UNUSED;
1685  }
1686 
1687  /*
1688  * Check for optoisolated ME-4000 version. If one the first
1689  * port is a fixed output port and the second is a fixed input port.
1690  */
1691  if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1692  s->io_bits |= 0xFF;
1693  outl(ME4000_DIO_CTRL_BIT_MODE_0,
1694  dev->iobase + ME4000_DIO_DIR_REG);
1695  }
1696 
1697  /*=========================================================================
1698  Counter subdevice
1699  ========================================================================*/
1700 
1701  s = &dev->subdevices[3];
1702 
1703  if (thisboard->has_counter) {
1704  s->type = COMEDI_SUBD_COUNTER;
1705  s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1706  s->n_chan = 3;
1707  s->maxdata = 0xFFFF; /* 16 bit counters */
1708  s->insn_read = me4000_cnt_insn_read;
1709  s->insn_write = me4000_cnt_insn_write;
1710  s->insn_config = me4000_cnt_insn_config;
1711  } else {
1712  s->type = COMEDI_SUBD_UNUSED;
1713  }
1714 
1715  return 0;
1716 }
1717 
1718 static void me4000_detach(struct comedi_device *dev)
1719 {
1720  struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1721 
1722  if (dev->irq)
1723  free_irq(dev->irq, dev);
1724  if (pcidev) {
1725  if (dev->iobase) {
1726  me4000_reset(dev);
1727  comedi_pci_disable(pcidev);
1728  }
1729  }
1730 }
1731 
1732 static struct comedi_driver me4000_driver = {
1733  .driver_name = "me4000",
1734  .module = THIS_MODULE,
1735  .attach_pci = me4000_attach_pci,
1736  .detach = me4000_detach,
1737 };
1738 
1739 static int __devinit me4000_pci_probe(struct pci_dev *dev,
1740  const struct pci_device_id *ent)
1741 {
1742  return comedi_pci_auto_config(dev, &me4000_driver);
1743 }
1744 
1745 static void __devexit me4000_pci_remove(struct pci_dev *dev)
1746 {
1747  comedi_pci_auto_unconfig(dev);
1748 }
1749 
1750 static DEFINE_PCI_DEVICE_TABLE(me4000_pci_table) = {
1751  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4650)},
1752  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660)},
1753  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660I)},
1754  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660S)},
1755  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660IS)},
1756  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670)},
1757  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670I)},
1758  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670S)},
1759  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670IS)},
1760  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680)},
1761  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680I)},
1762  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680S)},
1763  {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680IS)},
1764  {0}
1765 };
1766 MODULE_DEVICE_TABLE(pci, me4000_pci_table);
1767 
1768 static struct pci_driver me4000_pci_driver = {
1769  .name = "me4000",
1770  .id_table = me4000_pci_table,
1771  .probe = me4000_pci_probe,
1772  .remove = __devexit_p(me4000_pci_remove),
1773 };
1774 module_comedi_pci_driver(me4000_driver, me4000_pci_driver);
1775 
1776 MODULE_AUTHOR("Comedi http://www.comedi.org");
1777 MODULE_DESCRIPTION("Comedi low-level driver");
1778 MODULE_LICENSE("GPL");
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