|
| #define | TX_RING_ENTRIES 64 /* 64-512?*/ |
| |
| #define | RX_RING_ENTRIES 16 /* Do not change */ |
| |
| #define | TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet)) |
| |
| #define | RX_BUFFER_SIZE 1546 /* ethenet packet size */ |
| |
| #define | METH_RX_BUFF_SIZE 4096 |
| |
| #define | METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */ |
| |
| #define | RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */ |
| |
| #define | RX_BUCKET_SIZE 256 |
| |
| #define | TX_INFO_RPTR 0x00FF0000 |
| |
| #define | TX_INFO_WPTR 0x000000FF |
| |
| #define | SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */ |
| |
| #define | METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */ |
| |
| #define | METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */ |
| |
| #define | METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */ |
| |
| #define | METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */ |
| |
| #define | METH_ACCEPT_MY 0 /* 00: Accept PHY address only */ |
| |
| #define | METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only */ |
| |
| #define | METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */ |
| |
| #define | METH_PROMISC 0x60 /* 11: Promiscious mode */ |
| |
| #define | METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */ |
| |
| #define | METH_MAC_IPG 0x1ffff00 |
| |
| #define | METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8)) |
| |
| #define | METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */ |
| |
| #define | METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */ |
| |
| #define | METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */ |
| |
| #define | METH_DMA_TX_EN BIT(1) /* enable TX DMA */ |
| |
| #define | METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */ |
| |
| #define | METH_DMA_RX_EN BIT(15) /* Enable RX */ |
| |
| #define | METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */ |
| |
| #define | METH_RX_FIFO_WPTR(x) (((x)>>16)&0xf) |
| |
| #define | METH_RX_FIFO_RPTR(x) (((x)>>8)&0xf) |
| |
| #define | METH_RX_FIFO_DEPTH(x) ((x)&0x1f) |
| |
| #define | METH_RX_ST_VALID BIT(63) |
| |
| #define | METH_RX_ST_RCV_CODE_VIOLATION BIT(16) |
| |
| #define | METH_RX_ST_DRBL_NBL BIT(17) |
| |
| #define | METH_RX_ST_CRC_ERR BIT(18) |
| |
| #define | METH_RX_ST_MCAST_PKT BIT(19) |
| |
| #define | METH_RX_ST_BCAST_PKT BIT(20) |
| |
| #define | METH_RX_ST_INV_PREAMBLE_CTX BIT(21) |
| |
| #define | METH_RX_ST_LONG_EVT_SEEN BIT(22) |
| |
| #define | METH_RX_ST_BAD_PACKET BIT(23) |
| |
| #define | METH_RX_ST_CARRIER_EVT_SEEN BIT(24) |
| |
| #define | METH_RX_ST_MCAST_FILTER_MATCH BIT(25) |
| |
| #define | METH_RX_ST_PHYS_ADDR_MATCH BIT(26) |
| |
| #define | METH_RX_STATUS_ERRORS |
| |
| #define | METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */ |
| |
| #define | METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */ |
| |
| #define | METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */ |
| |
| #define | METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */ |
| |
| #define | METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */ |
| |
| #define | METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */ |
| |
| #define | METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */ |
| |
| #define | METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */ |
| |
| #define | METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/ |
| |
| #define | METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */ |
| |
| #define | METH_INT_RX_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */ |
| |
| #define | METH_INT_ERROR |
| |
| #define | METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */ |
| |
| #define | METH_TX_ST_DONE BIT(63) /* TX complete */ |
| |
| #define | METH_TX_ST_SUCCESS BIT(23) /* Packet was transmitted successfully */ |
| |
| #define | METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */ |
| |
| #define | METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */ |
| |
| #define | METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */ |
| |
| #define | METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */ |
| |
| #define | METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */ |
| |
| #define | METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */ |
| |
| #define | MDIO_BUSY BIT(16) |
| |
| #define | MDIO_DATA_MASK 0xFFFF |
| |
| #define | PHY_QS6612X 0x0181441 /* Quality TX */ |
| |
| #define | PHY_ICS1889 0x0015F41 /* ICS FX */ |
| |
| #define | PHY_ICS1890 0x0015F42 /* ICS TX */ |
| |
| #define | PHY_DP83840 0x20005C0 /* National TX */ |
| |
| #define | ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1) |
| |
1.8.2