35 #include <linux/types.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
56 static void *pci_config_base;
58 #define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
67 cfgaddr = (
u32 *)(pci_config_base +
73 static inline void pci_cfg_write_32bit(
struct pci_bus *
bus,
unsigned int devfn,
78 cfgaddr = (
u32 *)(pci_config_base +
83 static int nlm_pcibios_read(
struct pci_bus *bus,
unsigned int devfn,
88 if ((size == 2) && (where & 1))
90 else if ((size == 4) && (where & 3))
93 data = pci_cfg_read_32bit(bus, devfn, where);
96 *val = (data >> ((where & 3) << 3)) & 0xff;
98 *val = (data >> ((where & 3) << 3)) & 0xffff;
106 static int nlm_pcibios_write(
struct pci_bus *bus,
unsigned int devfn,
107 int where,
int size,
u32 val)
111 if ((size == 2) && (where & 1))
113 else if ((size == 4) && (where & 3))
116 data = pci_cfg_read_32bit(bus, devfn, where);
119 data = (data & ~(0xff << ((where & 3) << 3))) |
120 (val << ((where & 3) << 3));
122 data = (data & ~(0xffff << ((where & 3) << 3))) |
123 (val << ((where & 3) << 3));
127 pci_cfg_write_32bit(bus, devfn, where, data);
133 .read = nlm_pcibios_read,
134 .write = nlm_pcibios_write
137 static struct resource nlm_pci_mem_resource = {
138 .name =
"XLP PCI MEM",
139 .start = 0xd0000000
UL,
144 static struct resource nlm_pci_io_resource = {
145 .name =
"XLP IO MEM",
146 .start = 0x14000000
UL,
154 .mem_resource = &nlm_pci_mem_resource,
155 .mem_offset = 0x00000000
UL,
156 .io_resource = &nlm_pci_io_resource,
157 .io_offset = 0x00000000
UL,
160 static int get_irq_vector(
const struct pci_dev *
dev)
169 switch (dev->
bus->self->devfn) {
179 WARN(1,
"Unexpected devfn %d\n", dev->
bus->self->devfn);
185 return get_irq_vector(dev);
194 static int xlp_enable_pci_bswap(
void)
207 for (i = 0; i < 4; i++) {
231 pci_set_flags(PCI_PROBE_ONLY);
238 xlp_enable_pci_bswap();
240 nlm_pci_controller.io_map_base =
CKSEG1;
243 pr_info(
"XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
244 &nlm_pci_mem_resource);