pxa2xx_ssp.h File Reference

#include <linux/list.h>
#include <linux/io.h>

Go to the source code of this file.

Data Structures
struct	ssp_device

Macros
#define	SSCR0   (0x00) /* SSP Control Register 0 */
#define	SSCR1   (0x04) /* SSP Control Register 1 */
#define	SSSR   (0x08) /* SSP Status Register */
#define	SSITR   (0x0C) /* SSP Interrupt Test Register */
#define	SSDR   (0x10) /* SSP Data Write/Data Read Register */
#define	SSTO   (0x28) /* SSP Time Out Register */
#define	SSPSP   (0x2C) /* SSP Programmable Serial Protocol */
#define	SSTSA   (0x30) /* SSP Tx Timeslot Active */
#define	SSRSA   (0x34) /* SSP Rx Timeslot Active */
#define	SSTSS   (0x38) /* SSP Timeslot Status */
#define	SSACD   (0x3C) /* SSP Audio Clock Divider */
#define	SSACDD   (0x40) /* SSP Audio Clock Dither Divider */
#define	SSCR0_DSS   (0x0000000f) /* Data Size Select (mask) */
#define	SSCR0_DataSize(x)   ((x) - 1) /* Data Size Select [4..16] */
#define	SSCR0_FRF   (0x00000030) /* FRame Format (mask) */
#define	SSCR0_Motorola   (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
#define	SSCR0_TI   (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
#define	SSCR0_National   (0x2 << 4) /* National Microwire */
#define	SSCR0_ECS   (1 << 6) /* External clock select */
#define	SSCR0_SSE   (1 << 7) /* Synchronous Serial Port Enable */
#define	SSCR0_SCR(x)   ((x) << 8) /* Serial Clock Rate (mask) */
#define	SSCR0_EDSS   (1 << 20) /* Extended data size select */
#define	SSCR0_NCS   (1 << 21) /* Network clock select */
#define	SSCR0_RIM   (1 << 22) /* Receive FIFO overrrun interrupt mask */
#define	SSCR0_TUM   (1 << 23) /* Transmit FIFO underrun interrupt mask */
#define	SSCR0_FRDC   (0x07000000) /* Frame rate divider control (mask) */
#define	SSCR0_SlotsPerFrm(x)   (((x) - 1) << 24) /* Time slots per frame [1..8] */
#define	SSCR0_FPCKE   (1 << 29) /* FIFO packing enable */
#define	SSCR0_ACS   (1 << 30) /* Audio clock select */
#define	SSCR0_MOD   (1 << 31) /* Mode (normal or network) */
#define	SSCR1_RIE   (1 << 0) /* Receive FIFO Interrupt Enable */
#define	SSCR1_TIE   (1 << 1) /* Transmit FIFO Interrupt Enable */
#define	SSCR1_LBM   (1 << 2) /* Loop-Back Mode */
#define	SSCR1_SPO   (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
#define	SSCR1_SPH   (1 << 4) /* Motorola SPI SSPSCLK phase setting */
#define	SSCR1_MWDS   (1 << 5) /* Microwire Transmit Data Size */
#define	SSSR_ALT_FRM_MASK   3 /* Masks the SFRM signal number */
#define	SSSR_TNF   (1 << 2) /* Transmit FIFO Not Full */
#define	SSSR_RNE   (1 << 3) /* Receive FIFO Not Empty */
#define	SSSR_BSY   (1 << 4) /* SSP Busy */
#define	SSSR_TFS   (1 << 5) /* Transmit FIFO Service Request */
#define	SSSR_RFS   (1 << 6) /* Receive FIFO Service Request */
#define	SSSR_ROR   (1 << 7) /* Receive FIFO Overrun */
#define	RX_THRESH_DFLT   2
#define	TX_THRESH_DFLT   2
#define	SSSR_TFL_MASK   (0x3 << 8) /* Transmit FIFO Level mask */
#define	SSSR_RFL_MASK   (0x3 << 12) /* Receive FIFO Level mask */
#define	SSCR1_TFT   (0x000000c0) /* Transmit FIFO Threshold (mask) */
#define	SSCR1_TxTresh(x)   (((x) - 1) << 6) /* level [1..4] */
#define	SSCR1_RFT   (0x00000c00) /* Receive FIFO Threshold (mask) */
#define	SSCR1_RxTresh(x)   (((x) - 1) << 10) /* level [1..4] */
#define	SSCR0_TISSP   (1 << 4) /* TI Sync Serial Protocol */
#define	SSCR0_PSP   (3 << 4) /* PSP - Programmable Serial Protocol */
#define	SSCR1_TTELP   (1 << 31) /* TXD Tristate Enable Last Phase */
#define	SSCR1_TTE   (1 << 30) /* TXD Tristate Enable */
#define	SSCR1_EBCEI   (1 << 29) /* Enable Bit Count Error interrupt */
#define	SSCR1_SCFR   (1 << 28) /* Slave Clock free Running */
#define	SSCR1_ECRA   (1 << 27) /* Enable Clock Request A */
#define	SSCR1_ECRB   (1 << 26) /* Enable Clock request B */
#define	SSCR1_SCLKDIR   (1 << 25) /* Serial Bit Rate Clock Direction */
#define	SSCR1_SFRMDIR   (1 << 24) /* Frame Direction */
#define	SSCR1_RWOT   (1 << 23) /* Receive Without Transmit */
#define	SSCR1_TRAIL   (1 << 22) /* Trailing Byte */
#define	SSCR1_TSRE   (1 << 21) /* Transmit Service Request Enable */
#define	SSCR1_RSRE   (1 << 20) /* Receive Service Request Enable */
#define	SSCR1_TINTE   (1 << 19) /* Receiver Time-out Interrupt enable */
#define	SSCR1_PINTE   (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */
#define	SSCR1_IFS   (1 << 16) /* Invert Frame Signal */
#define	SSCR1_STRF   (1 << 15) /* Select FIFO or EFWR */
#define	SSCR1_EFWR   (1 << 14) /* Enable FIFO Write/Read */
#define	SSSR_BCE   (1 << 23) /* Bit Count Error */
#define	SSSR_CSS   (1 << 22) /* Clock Synchronisation Status */
#define	SSSR_TUR   (1 << 21) /* Transmit FIFO Under Run */
#define	SSSR_EOC   (1 << 20) /* End Of Chain */
#define	SSSR_TINT   (1 << 19) /* Receiver Time-out Interrupt */
#define	SSSR_PINT   (1 << 18) /* Peripheral Trailing Byte Interrupt */
#define	SSPSP_SCMODE(x)   ((x) << 0) /* Serial Bit Rate Clock Mode */
#define	SSPSP_SFRMP   (1 << 2) /* Serial Frame Polarity */
#define	SSPSP_ETDS   (1 << 3) /* End of Transfer data State */
#define	SSPSP_STRTDLY(x)   ((x) << 4) /* Start Delay */
#define	SSPSP_DMYSTRT(x)   ((x) << 7) /* Dummy Start */
#define	SSPSP_SFRMDLY(x)   ((x) << 9) /* Serial Frame Delay */
#define	SSPSP_SFRMWDTH(x)   ((x) << 16) /* Serial Frame Width */
#define	SSPSP_DMYSTOP(x)   ((x) << 23) /* Dummy Stop */
#define	SSPSP_FSRT   (1 << 25) /* Frame Sync Relative Timing */
#define	SSPSP_EDMYSTRT(x)   ((x) << 26) /* Extended Dummy Start */
#define	SSPSP_EDMYSTOP(x)   ((x) << 28) /* Extended Dummy Stop */
#define	SSPSP_TIMING_MASK   (0x7f8001f0)
#define	SSACD_SCDB   (1 << 3) /* SSPSYSCLK Divider Bypass */
#define	SSACD_ACPS(x)   ((x) << 4) /* Audio clock PLL select */
#define	SSACD_ACDS(x)   ((x) << 0) /* Audio clock divider select */
#define	SSACD_SCDX8   (1 << 7) /* SYSCLK division ratio select */

Enumerations
enum	pxa_ssp_type {   SSP_UNDEFINED = 0, PXA25x_SSP, PXA25x_NSSP, PXA27x_SSP,   PXA3xx_SSP, PXA168_SSP, PXA910_SSP, CE4100_SSP }

Functions
struct ssp_device *	pxa_ssp_request (int port, const char *label)
void	pxa_ssp_free (struct ssp_device *)

Macro Definition Documentation

#define RX_THRESH_DFLT   2

Definition at line 97 of file pxa2xx_ssp.h.

#define SSACD   (0x3C) /* SSP Audio Clock Divider */

Definition at line 42 of file pxa2xx_ssp.h.

#define SSACD_ACDS

(

x

)

((x) << 0) /* Audio clock divider select */

Definition at line 155 of file pxa2xx_ssp.h.

#define SSACD_ACPS

(

x

)

((x) << 4) /* Audio clock PLL select */

Definition at line 154 of file pxa2xx_ssp.h.

#define SSACD_SCDB   (1 << 3) /* SSPSYSCLK Divider Bypass */

Definition at line 153 of file pxa2xx_ssp.h.

#define SSACD_SCDX8   (1 << 7) /* SYSCLK division ratio select */

Definition at line 156 of file pxa2xx_ssp.h.

#define SSACDD   (0x40) /* SSP Audio Clock Dither Divider */

Definition at line 43 of file pxa2xx_ssp.h.

#define SSCR0   (0x00) /* SSP Control Register 0 */

Definition at line 31 of file pxa2xx_ssp.h.

#define SSCR0_ACS   (1 << 30) /* Audio clock select */

Definition at line 64 of file pxa2xx_ssp.h.

#define SSCR0_DataSize

(

x

)

((x) - 1) /* Data Size Select [4..16] */

Definition at line 47 of file pxa2xx_ssp.h.

#define SSCR0_DSS   (0x0000000f) /* Data Size Select (mask) */

Definition at line 46 of file pxa2xx_ssp.h.

#define SSCR0_ECS   (1 << 6) /* External clock select */

Definition at line 52 of file pxa2xx_ssp.h.

#define SSCR0_EDSS   (1 << 20) /* Extended data size select */

Definition at line 57 of file pxa2xx_ssp.h.

#define SSCR0_FPCKE   (1 << 29) /* FIFO packing enable */

Definition at line 63 of file pxa2xx_ssp.h.

#define SSCR0_FRDC   (0x07000000) /* Frame rate divider control (mask) */

Definition at line 61 of file pxa2xx_ssp.h.

#define SSCR0_FRF   (0x00000030) /* FRame Format (mask) */

Definition at line 48 of file pxa2xx_ssp.h.

#define SSCR0_MOD   (1 << 31) /* Mode (normal or network) */

Definition at line 65 of file pxa2xx_ssp.h.

#define SSCR0_Motorola   (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */

Definition at line 49 of file pxa2xx_ssp.h.

#define SSCR0_National   (0x2 << 4) /* National Microwire */

Definition at line 51 of file pxa2xx_ssp.h.

#define SSCR0_NCS   (1 << 21) /* Network clock select */

Definition at line 58 of file pxa2xx_ssp.h.

#define SSCR0_PSP   (3 << 4) /* PSP - Programmable Serial Protocol */

Definition at line 111 of file pxa2xx_ssp.h.

#define SSCR0_RIM   (1 << 22) /* Receive FIFO overrrun interrupt mask */

Definition at line 59 of file pxa2xx_ssp.h.

#define SSCR0_SCR

(

x

)

((x) << 8) /* Serial Clock Rate (mask) */

Definition at line 54 of file pxa2xx_ssp.h.

#define SSCR0_SlotsPerFrm

(

x

)

(((x) - 1) << 24) /* Time slots per frame [1..8] */

Definition at line 62 of file pxa2xx_ssp.h.

#define SSCR0_SSE   (1 << 7) /* Synchronous Serial Port Enable */

Definition at line 53 of file pxa2xx_ssp.h.

#define SSCR0_TI   (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */

Definition at line 50 of file pxa2xx_ssp.h.

#define SSCR0_TISSP   (1 << 4) /* TI Sync Serial Protocol */

Definition at line 110 of file pxa2xx_ssp.h.

#define SSCR0_TUM   (1 << 23) /* Transmit FIFO underrun interrupt mask */

Definition at line 60 of file pxa2xx_ssp.h.

#define SSCR1   (0x04) /* SSP Control Register 1 */

Definition at line 32 of file pxa2xx_ssp.h.

#define SSCR1_EBCEI   (1 << 29) /* Enable Bit Count Error interrupt */

Definition at line 114 of file pxa2xx_ssp.h.

#define SSCR1_ECRA   (1 << 27) /* Enable Clock Request A */

Definition at line 116 of file pxa2xx_ssp.h.

#define SSCR1_ECRB   (1 << 26) /* Enable Clock request B */

Definition at line 117 of file pxa2xx_ssp.h.

#define SSCR1_EFWR   (1 << 14) /* Enable FIFO Write/Read */

Definition at line 128 of file pxa2xx_ssp.h.

#define SSCR1_IFS   (1 << 16) /* Invert Frame Signal */

Definition at line 126 of file pxa2xx_ssp.h.

#define SSCR1_LBM   (1 << 2) /* Loop-Back Mode */

Definition at line 70 of file pxa2xx_ssp.h.

#define SSCR1_MWDS   (1 << 5) /* Microwire Transmit Data Size */

Definition at line 73 of file pxa2xx_ssp.h.

#define SSCR1_PINTE   (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */

Definition at line 125 of file pxa2xx_ssp.h.

#define SSCR1_RFT   (0x00000c00) /* Receive FIFO Threshold (mask) */

Definition at line 105 of file pxa2xx_ssp.h.

#define SSCR1_RIE   (1 << 0) /* Receive FIFO Interrupt Enable */

Definition at line 68 of file pxa2xx_ssp.h.

#define SSCR1_RSRE   (1 << 20) /* Receive Service Request Enable */

Definition at line 123 of file pxa2xx_ssp.h.

#define SSCR1_RWOT   (1 << 23) /* Receive Without Transmit */

Definition at line 120 of file pxa2xx_ssp.h.

#define SSCR1_RxTresh

(

x

)

(((x) - 1) << 10) /* level [1..4] */

Definition at line 106 of file pxa2xx_ssp.h.

#define SSCR1_SCFR   (1 << 28) /* Slave Clock free Running */

Definition at line 115 of file pxa2xx_ssp.h.

#define SSCR1_SCLKDIR   (1 << 25) /* Serial Bit Rate Clock Direction */

Definition at line 118 of file pxa2xx_ssp.h.

#define SSCR1_SFRMDIR   (1 << 24) /* Frame Direction */

Definition at line 119 of file pxa2xx_ssp.h.

#define SSCR1_SPH   (1 << 4) /* Motorola SPI SSPSCLK phase setting */

Definition at line 72 of file pxa2xx_ssp.h.

#define SSCR1_SPO   (1 << 3) /* Motorola SPI SSPSCLK polarity setting */

Definition at line 71 of file pxa2xx_ssp.h.

#define SSCR1_STRF   (1 << 15) /* Select FIFO or EFWR */

Definition at line 127 of file pxa2xx_ssp.h.

#define SSCR1_TFT   (0x000000c0) /* Transmit FIFO Threshold (mask) */

Definition at line 103 of file pxa2xx_ssp.h.

#define SSCR1_TIE   (1 << 1) /* Transmit FIFO Interrupt Enable */

Definition at line 69 of file pxa2xx_ssp.h.

#define SSCR1_TINTE   (1 << 19) /* Receiver Time-out Interrupt enable */

Definition at line 124 of file pxa2xx_ssp.h.

#define SSCR1_TRAIL   (1 << 22) /* Trailing Byte */

Definition at line 121 of file pxa2xx_ssp.h.

#define SSCR1_TSRE   (1 << 21) /* Transmit Service Request Enable */

Definition at line 122 of file pxa2xx_ssp.h.

#define SSCR1_TTE   (1 << 30) /* TXD Tristate Enable */

Definition at line 113 of file pxa2xx_ssp.h.

#define SSCR1_TTELP   (1 << 31) /* TXD Tristate Enable Last Phase */

Definition at line 112 of file pxa2xx_ssp.h.

#define SSCR1_TxTresh

(

x

)

(((x) - 1) << 6) /* level [1..4] */

Definition at line 104 of file pxa2xx_ssp.h.

#define SSDR   (0x10) /* SSP Data Write/Data Read Register */

Definition at line 35 of file pxa2xx_ssp.h.

#define SSITR   (0x0C) /* SSP Interrupt Test Register */

Definition at line 34 of file pxa2xx_ssp.h.

#define SSPSP   (0x2C) /* SSP Programmable Serial Protocol */

Definition at line 38 of file pxa2xx_ssp.h.

#define SSPSP_DMYSTOP

(

x

)

((x) << 23) /* Dummy Stop */

Definition at line 145 of file pxa2xx_ssp.h.

#define SSPSP_DMYSTRT

(

x

)

((x) << 7) /* Dummy Start */

Definition at line 142 of file pxa2xx_ssp.h.

#define SSPSP_EDMYSTOP

(

x

)

((x) << 28) /* Extended Dummy Stop */

Definition at line 150 of file pxa2xx_ssp.h.

#define SSPSP_EDMYSTRT

(

x

)

((x) << 26) /* Extended Dummy Start */

Definition at line 149 of file pxa2xx_ssp.h.

#define SSPSP_ETDS   (1 << 3) /* End of Transfer data State */

Definition at line 140 of file pxa2xx_ssp.h.

#define SSPSP_FSRT   (1 << 25) /* Frame Sync Relative Timing */

Definition at line 146 of file pxa2xx_ssp.h.

#define SSPSP_SCMODE

(

x

)

((x) << 0) /* Serial Bit Rate Clock Mode */

Definition at line 138 of file pxa2xx_ssp.h.

#define SSPSP_SFRMDLY

(

x

)

((x) << 9) /* Serial Frame Delay */

Definition at line 143 of file pxa2xx_ssp.h.

#define SSPSP_SFRMP   (1 << 2) /* Serial Frame Polarity */

Definition at line 139 of file pxa2xx_ssp.h.

#define SSPSP_SFRMWDTH

(

x

)

((x) << 16) /* Serial Frame Width */

Definition at line 144 of file pxa2xx_ssp.h.

#define SSPSP_STRTDLY

(

x

)

((x) << 4) /* Start Delay */

Definition at line 141 of file pxa2xx_ssp.h.

#define SSPSP_TIMING_MASK   (0x7f8001f0)

Definition at line 151 of file pxa2xx_ssp.h.

#define SSRSA   (0x34) /* SSP Rx Timeslot Active */

Definition at line 40 of file pxa2xx_ssp.h.

#define SSSR   (0x08) /* SSP Status Register */

Definition at line 33 of file pxa2xx_ssp.h.

#define SSSR_ALT_FRM_MASK   3 /* Masks the SFRM signal number */

Definition at line 75 of file pxa2xx_ssp.h.

#define SSSR_BCE   (1 << 23) /* Bit Count Error */

Definition at line 130 of file pxa2xx_ssp.h.

#define SSSR_BSY   (1 << 4) /* SSP Busy */

Definition at line 78 of file pxa2xx_ssp.h.

#define SSSR_CSS   (1 << 22) /* Clock Synchronisation Status */

Definition at line 131 of file pxa2xx_ssp.h.

#define SSSR_EOC   (1 << 20) /* End Of Chain */

Definition at line 133 of file pxa2xx_ssp.h.

#define SSSR_PINT   (1 << 18) /* Peripheral Trailing Byte Interrupt */

Definition at line 135 of file pxa2xx_ssp.h.

#define SSSR_RFL_MASK   (0x3 << 12) /* Receive FIFO Level mask */

Definition at line 101 of file pxa2xx_ssp.h.

#define SSSR_RFS   (1 << 6) /* Receive FIFO Service Request */

Definition at line 80 of file pxa2xx_ssp.h.

#define SSSR_RNE   (1 << 3) /* Receive FIFO Not Empty */

Definition at line 77 of file pxa2xx_ssp.h.

#define SSSR_ROR   (1 << 7) /* Receive FIFO Overrun */

Definition at line 81 of file pxa2xx_ssp.h.

#define SSSR_TFL_MASK   (0x3 << 8) /* Transmit FIFO Level mask */

Definition at line 100 of file pxa2xx_ssp.h.

#define SSSR_TFS   (1 << 5) /* Transmit FIFO Service Request */

Definition at line 79 of file pxa2xx_ssp.h.

#define SSSR_TINT   (1 << 19) /* Receiver Time-out Interrupt */

Definition at line 134 of file pxa2xx_ssp.h.

#define SSSR_TNF   (1 << 2) /* Transmit FIFO Not Full */

Definition at line 76 of file pxa2xx_ssp.h.

#define SSSR_TUR   (1 << 21) /* Transmit FIFO Under Run */

Definition at line 132 of file pxa2xx_ssp.h.

#define SSTO   (0x28) /* SSP Time Out Register */

Definition at line 37 of file pxa2xx_ssp.h.

#define SSTSA   (0x30) /* SSP Tx Timeslot Active */

Definition at line 39 of file pxa2xx_ssp.h.

#define SSTSS   (0x38) /* SSP Timeslot Status */

Definition at line 41 of file pxa2xx_ssp.h.

#define TX_THRESH_DFLT   2

Definition at line 98 of file pxa2xx_ssp.h.

Enumeration Type Documentation

enum pxa_ssp_type

Enumerator:

SSP_UNDEFINED
PXA25x_SSP
PXA25x_NSSP
PXA27x_SSP
PXA3xx_SSP
PXA168_SSP
PXA910_SSP
CE4100_SSP

Definition at line 158 of file pxa2xx_ssp.h.

Function Documentation

void pxa_ssp_free

(

struct ssp_device *

)

Definition at line 63 of file ssp.c.

struct ssp_device* pxa_ssp_request ( int  port, const char *  label  )

read

Definition at line 40 of file ssp.c.