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r600_cp.c
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1 /*
2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  * Dave Airlie <[email protected]>
26  * Alex Deucher <[email protected]>
27  */
28 
29 #include <linux/module.h>
30 
31 #include <drm/drmP.h>
32 #include <drm/radeon_drm.h>
33 #include "radeon_drv.h"
34 
35 #define PFP_UCODE_SIZE 576
36 #define PM4_UCODE_SIZE 1792
37 #define R700_PFP_UCODE_SIZE 848
38 #define R700_PM4_UCODE_SIZE 1360
39 
40 /* Firmware Names */
41 MODULE_FIRMWARE("radeon/R600_pfp.bin");
42 MODULE_FIRMWARE("radeon/R600_me.bin");
43 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
44 MODULE_FIRMWARE("radeon/RV610_me.bin");
45 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
46 MODULE_FIRMWARE("radeon/RV630_me.bin");
47 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
48 MODULE_FIRMWARE("radeon/RV620_me.bin");
49 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV635_me.bin");
51 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV670_me.bin");
53 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
54 MODULE_FIRMWARE("radeon/RS780_me.bin");
55 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV770_me.bin");
57 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV730_me.bin");
59 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV710_me.bin");
61 
62 
63 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
64  unsigned family, u32 *ib, int *l);
65 void r600_cs_legacy_init(void);
66 
67 
68 # define ATI_PCIGART_PAGE_SIZE 4096
69 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
70 
71 #define R600_PTE_VALID (1 << 0)
72 #define R600_PTE_SYSTEM (1 << 1)
73 #define R600_PTE_SNOOPED (1 << 2)
74 #define R600_PTE_READABLE (1 << 5)
75 #define R600_PTE_WRITEABLE (1 << 6)
76 
77 /* MAX values used for gfx init */
78 #define R6XX_MAX_SH_GPRS 256
79 #define R6XX_MAX_TEMP_GPRS 16
80 #define R6XX_MAX_SH_THREADS 256
81 #define R6XX_MAX_SH_STACK_ENTRIES 4096
82 #define R6XX_MAX_BACKENDS 8
83 #define R6XX_MAX_BACKENDS_MASK 0xff
84 #define R6XX_MAX_SIMDS 8
85 #define R6XX_MAX_SIMDS_MASK 0xff
86 #define R6XX_MAX_PIPES 8
87 #define R6XX_MAX_PIPES_MASK 0xff
88 
89 #define R7XX_MAX_SH_GPRS 256
90 #define R7XX_MAX_TEMP_GPRS 16
91 #define R7XX_MAX_SH_THREADS 256
92 #define R7XX_MAX_SH_STACK_ENTRIES 4096
93 #define R7XX_MAX_BACKENDS 8
94 #define R7XX_MAX_BACKENDS_MASK 0xff
95 #define R7XX_MAX_SIMDS 16
96 #define R7XX_MAX_SIMDS_MASK 0xffff
97 #define R7XX_MAX_PIPES 8
98 #define R7XX_MAX_PIPES_MASK 0xff
99 
100 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
101 {
102  int i;
103 
104  dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
105 
106  for (i = 0; i < dev_priv->usec_timeout; i++) {
107  int slots;
108  if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
109  slots = (RADEON_READ(R600_GRBM_STATUS)
110  & R700_CMDFIFO_AVAIL_MASK);
111  else
112  slots = (RADEON_READ(R600_GRBM_STATUS)
113  & R600_CMDFIFO_AVAIL_MASK);
114  if (slots >= entries)
115  return 0;
116  DRM_UDELAY(1);
117  }
118  DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
119  RADEON_READ(R600_GRBM_STATUS),
120  RADEON_READ(R600_GRBM_STATUS2));
121 
122  return -EBUSY;
123 }
124 
125 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
126 {
127  int i, ret;
128 
129  dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
130 
131  if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
132  ret = r600_do_wait_for_fifo(dev_priv, 8);
133  else
134  ret = r600_do_wait_for_fifo(dev_priv, 16);
135  if (ret)
136  return ret;
137  for (i = 0; i < dev_priv->usec_timeout; i++) {
138  if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
139  return 0;
140  DRM_UDELAY(1);
141  }
142  DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
143  RADEON_READ(R600_GRBM_STATUS),
144  RADEON_READ(R600_GRBM_STATUS2));
145 
146  return -EBUSY;
147 }
148 
149 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
150 {
151  struct drm_sg_mem *entry = dev->sg;
152  int max_pages;
153  int pages;
154  int i;
155 
156  if (!entry)
157  return;
158 
159  if (gart_info->bus_addr) {
160  max_pages = (gart_info->table_size / sizeof(u64));
161  pages = (entry->pages <= max_pages)
162  ? entry->pages : max_pages;
163 
164  for (i = 0; i < pages; i++) {
165  if (!entry->busaddr[i])
166  break;
167  pci_unmap_page(dev->pdev, entry->busaddr[i],
168  PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
169  }
170  if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
171  gart_info->bus_addr = 0;
172  }
173 }
174 
175 /* R600 has page table setup */
176 int r600_page_table_init(struct drm_device *dev)
177 {
178  drm_radeon_private_t *dev_priv = dev->dev_private;
179  struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
180  struct drm_local_map *map = &gart_info->mapping;
181  struct drm_sg_mem *entry = dev->sg;
182  int ret = 0;
183  int i, j;
184  int pages;
185  u64 page_base;
186  dma_addr_t entry_addr;
187  int max_ati_pages, max_real_pages, gart_idx;
188 
189  /* okay page table is available - lets rock */
190  max_ati_pages = (gart_info->table_size / sizeof(u64));
191  max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
192 
193  pages = (entry->pages <= max_real_pages) ?
194  entry->pages : max_real_pages;
195 
196  memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
197 
198  gart_idx = 0;
199  for (i = 0; i < pages; i++) {
200  entry->busaddr[i] = pci_map_page(dev->pdev,
201  entry->pagelist[i], 0,
202  PAGE_SIZE,
203  PCI_DMA_BIDIRECTIONAL);
204  if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
205  DRM_ERROR("unable to map PCIGART pages!\n");
206  r600_page_table_cleanup(dev, gart_info);
207  goto done;
208  }
209  entry_addr = entry->busaddr[i];
210  for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
211  page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
212  page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
213  page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
214 
215  DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
216 
217  gart_idx++;
218 
219  if ((i % 128) == 0)
220  DRM_DEBUG("page entry %d: 0x%016llx\n",
221  i, (unsigned long long)page_base);
222  entry_addr += ATI_PCIGART_PAGE_SIZE;
223  }
224  }
225  ret = 1;
226 done:
227  return ret;
228 }
229 
230 static void r600_vm_flush_gart_range(struct drm_device *dev)
231 {
232  drm_radeon_private_t *dev_priv = dev->dev_private;
233  u32 resp, countdown = 1000;
234  RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
235  RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
236  RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
237 
238  do {
239  resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
240  countdown--;
241  DRM_UDELAY(1);
242  } while (((resp & 0xf0) == 0) && countdown);
243 }
244 
245 static void r600_vm_init(struct drm_device *dev)
246 {
247  drm_radeon_private_t *dev_priv = dev->dev_private;
248  /* initialise the VM to use the page table we constructed up there */
249  u32 vm_c0, i;
250  u32 mc_rd_a;
251  u32 vm_l2_cntl, vm_l2_cntl3;
252  /* okay set up the PCIE aperture type thingo */
253  RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
254  RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
255  RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
256 
257  /* setup MC RD a */
258  mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
259  R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
260  R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
261 
262  RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
263  RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
264 
265  RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
266  RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
267 
268  RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
269  RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
270 
271  RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
272  RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
273 
274  RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
275  RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
276 
277  RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
278  RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
279 
280  RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
281  RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
282 
283  vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
284  vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
285  RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
286 
287  RADEON_WRITE(R600_VM_L2_CNTL2, 0);
288  vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
289  R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
290  R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
291  RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
292 
293  vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
294 
295  RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
296 
297  vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
298 
299  /* disable all other contexts */
300  for (i = 1; i < 8; i++)
301  RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
302 
303  RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
304  RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
305  RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
306 
307  r600_vm_flush_gart_range(dev);
308 }
309 
310 static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
311 {
312  struct platform_device *pdev;
313  const char *chip_name;
314  size_t pfp_req_size, me_req_size;
315  char fw_name[30];
316  int err;
317 
318  pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
319  err = IS_ERR(pdev);
320  if (err) {
321  printk(KERN_ERR "r600_cp: Failed to register firmware\n");
322  return -EINVAL;
323  }
324 
325  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
326  case CHIP_R600: chip_name = "R600"; break;
327  case CHIP_RV610: chip_name = "RV610"; break;
328  case CHIP_RV630: chip_name = "RV630"; break;
329  case CHIP_RV620: chip_name = "RV620"; break;
330  case CHIP_RV635: chip_name = "RV635"; break;
331  case CHIP_RV670: chip_name = "RV670"; break;
332  case CHIP_RS780:
333  case CHIP_RS880: chip_name = "RS780"; break;
334  case CHIP_RV770: chip_name = "RV770"; break;
335  case CHIP_RV730:
336  case CHIP_RV740: chip_name = "RV730"; break;
337  case CHIP_RV710: chip_name = "RV710"; break;
338  default: BUG();
339  }
340 
341  if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
342  pfp_req_size = R700_PFP_UCODE_SIZE * 4;
343  me_req_size = R700_PM4_UCODE_SIZE * 4;
344  } else {
345  pfp_req_size = PFP_UCODE_SIZE * 4;
346  me_req_size = PM4_UCODE_SIZE * 12;
347  }
348 
349  DRM_INFO("Loading %s CP Microcode\n", chip_name);
350 
351  snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
352  err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
353  if (err)
354  goto out;
355  if (dev_priv->pfp_fw->size != pfp_req_size) {
356  printk(KERN_ERR
357  "r600_cp: Bogus length %zu in firmware \"%s\"\n",
358  dev_priv->pfp_fw->size, fw_name);
359  err = -EINVAL;
360  goto out;
361  }
362 
363  snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
364  err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
365  if (err)
366  goto out;
367  if (dev_priv->me_fw->size != me_req_size) {
368  printk(KERN_ERR
369  "r600_cp: Bogus length %zu in firmware \"%s\"\n",
370  dev_priv->me_fw->size, fw_name);
371  err = -EINVAL;
372  }
373 out:
374  platform_device_unregister(pdev);
375 
376  if (err) {
377  if (err != -EINVAL)
378  printk(KERN_ERR
379  "r600_cp: Failed to load firmware \"%s\"\n",
380  fw_name);
381  release_firmware(dev_priv->pfp_fw);
382  dev_priv->pfp_fw = NULL;
383  release_firmware(dev_priv->me_fw);
384  dev_priv->me_fw = NULL;
385  }
386  return err;
387 }
388 
389 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
390 {
391  const __be32 *fw_data;
392  int i;
393 
394  if (!dev_priv->me_fw || !dev_priv->pfp_fw)
395  return;
396 
397  r600_do_cp_stop(dev_priv);
398 
399  RADEON_WRITE(R600_CP_RB_CNTL,
400 #ifdef __BIG_ENDIAN
401  R600_BUF_SWAP_32BIT |
402 #endif
403  R600_RB_NO_UPDATE |
404  R600_RB_BLKSZ(15) |
405  R600_RB_BUFSZ(3));
406 
407  RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
408  RADEON_READ(R600_GRBM_SOFT_RESET);
409  mdelay(15);
410  RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
411 
412  fw_data = (const __be32 *)dev_priv->me_fw->data;
413  RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
414  for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
415  RADEON_WRITE(R600_CP_ME_RAM_DATA,
416  be32_to_cpup(fw_data++));
417 
418  fw_data = (const __be32 *)dev_priv->pfp_fw->data;
419  RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
420  for (i = 0; i < PFP_UCODE_SIZE; i++)
421  RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
422  be32_to_cpup(fw_data++));
423 
424  RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
425  RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
426  RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
427 
428 }
429 
430 static void r700_vm_init(struct drm_device *dev)
431 {
432  drm_radeon_private_t *dev_priv = dev->dev_private;
433  /* initialise the VM to use the page table we constructed up there */
434  u32 vm_c0, i;
435  u32 mc_vm_md_l1;
436  u32 vm_l2_cntl, vm_l2_cntl3;
437  /* okay set up the PCIE aperture type thingo */
438  RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
439  RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
440  RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
441 
442  mc_vm_md_l1 = R700_ENABLE_L1_TLB |
443  R700_ENABLE_L1_FRAGMENT_PROCESSING |
444  R700_SYSTEM_ACCESS_MODE_IN_SYS |
445  R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
446  R700_EFFECTIVE_L1_TLB_SIZE(5) |
447  R700_EFFECTIVE_L1_QUEUE_SIZE(5);
448 
449  RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
450  RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
451  RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
452  RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
453  RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
454  RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
455  RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
456 
457  vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
458  vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
459  RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
460 
461  RADEON_WRITE(R600_VM_L2_CNTL2, 0);
462  vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
463  RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
464 
465  vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
466 
467  RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
468 
469  vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
470 
471  /* disable all other contexts */
472  for (i = 1; i < 8; i++)
473  RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
474 
475  RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
476  RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
477  RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
478 
479  r600_vm_flush_gart_range(dev);
480 }
481 
482 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
483 {
484  const __be32 *fw_data;
485  int i;
486 
487  if (!dev_priv->me_fw || !dev_priv->pfp_fw)
488  return;
489 
490  r600_do_cp_stop(dev_priv);
491 
492  RADEON_WRITE(R600_CP_RB_CNTL,
493 #ifdef __BIG_ENDIAN
494  R600_BUF_SWAP_32BIT |
495 #endif
496  R600_RB_NO_UPDATE |
497  R600_RB_BLKSZ(15) |
498  R600_RB_BUFSZ(3));
499 
500  RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
501  RADEON_READ(R600_GRBM_SOFT_RESET);
502  mdelay(15);
503  RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
504 
505  fw_data = (const __be32 *)dev_priv->pfp_fw->data;
506  RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
507  for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
508  RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
509  RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
510 
511  fw_data = (const __be32 *)dev_priv->me_fw->data;
512  RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
513  for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
514  RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
515  RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
516 
517  RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
518  RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
519  RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
520 
521 }
522 
523 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
524 {
525  u32 tmp;
526 
527  /* Start with assuming that writeback doesn't work */
528  dev_priv->writeback_works = 0;
529 
530  /* Writeback doesn't seem to work everywhere, test it here and possibly
531  * enable it if it appears to work
532  */
533  radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
534 
535  RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
536 
537  for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
538  u32 val;
539 
540  val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
541  if (val == 0xdeadbeef)
542  break;
543  DRM_UDELAY(1);
544  }
545 
546  if (tmp < dev_priv->usec_timeout) {
547  dev_priv->writeback_works = 1;
548  DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
549  } else {
550  dev_priv->writeback_works = 0;
551  DRM_INFO("writeback test failed\n");
552  }
553  if (radeon_no_wb == 1) {
554  dev_priv->writeback_works = 0;
555  DRM_INFO("writeback forced off\n");
556  }
557 
558  if (!dev_priv->writeback_works) {
559  /* Disable writeback to avoid unnecessary bus master transfer */
560  RADEON_WRITE(R600_CP_RB_CNTL,
561 #ifdef __BIG_ENDIAN
562  R600_BUF_SWAP_32BIT |
563 #endif
564  RADEON_READ(R600_CP_RB_CNTL) |
565  R600_RB_NO_UPDATE);
566  RADEON_WRITE(R600_SCRATCH_UMSK, 0);
567  }
568 }
569 
570 int r600_do_engine_reset(struct drm_device *dev)
571 {
572  drm_radeon_private_t *dev_priv = dev->dev_private;
573  u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
574 
575  DRM_INFO("Resetting GPU\n");
576 
577  cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
578  cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
579  RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
580 
581  RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
582  RADEON_READ(R600_GRBM_SOFT_RESET);
583  DRM_UDELAY(50);
584  RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
585  RADEON_READ(R600_GRBM_SOFT_RESET);
586 
587  RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
588  cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
589  RADEON_WRITE(R600_CP_RB_CNTL,
590 #ifdef __BIG_ENDIAN
591  R600_BUF_SWAP_32BIT |
592 #endif
593  R600_RB_RPTR_WR_ENA);
594 
595  RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
596  RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
597  RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
598  RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
599 
600  /* Reset the CP ring */
601  r600_do_cp_reset(dev_priv);
602 
603  /* The CP is no longer running after an engine reset */
604  dev_priv->cp_running = 0;
605 
606  /* Reset any pending vertex, indirect buffers */
607  radeon_freelist_reset(dev);
608 
609  return 0;
610 
611 }
612 
613 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
614  u32 num_backends,
615  u32 backend_disable_mask)
616 {
617  u32 backend_map = 0;
618  u32 enabled_backends_mask;
619  u32 enabled_backends_count;
620  u32 cur_pipe;
621  u32 swizzle_pipe[R6XX_MAX_PIPES];
622  u32 cur_backend;
623  u32 i;
624 
625  if (num_tile_pipes > R6XX_MAX_PIPES)
626  num_tile_pipes = R6XX_MAX_PIPES;
627  if (num_tile_pipes < 1)
628  num_tile_pipes = 1;
629  if (num_backends > R6XX_MAX_BACKENDS)
630  num_backends = R6XX_MAX_BACKENDS;
631  if (num_backends < 1)
632  num_backends = 1;
633 
634  enabled_backends_mask = 0;
635  enabled_backends_count = 0;
636  for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
637  if (((backend_disable_mask >> i) & 1) == 0) {
638  enabled_backends_mask |= (1 << i);
639  ++enabled_backends_count;
640  }
641  if (enabled_backends_count == num_backends)
642  break;
643  }
644 
645  if (enabled_backends_count == 0) {
646  enabled_backends_mask = 1;
647  enabled_backends_count = 1;
648  }
649 
650  if (enabled_backends_count != num_backends)
651  num_backends = enabled_backends_count;
652 
653  memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
654  switch (num_tile_pipes) {
655  case 1:
656  swizzle_pipe[0] = 0;
657  break;
658  case 2:
659  swizzle_pipe[0] = 0;
660  swizzle_pipe[1] = 1;
661  break;
662  case 3:
663  swizzle_pipe[0] = 0;
664  swizzle_pipe[1] = 1;
665  swizzle_pipe[2] = 2;
666  break;
667  case 4:
668  swizzle_pipe[0] = 0;
669  swizzle_pipe[1] = 1;
670  swizzle_pipe[2] = 2;
671  swizzle_pipe[3] = 3;
672  break;
673  case 5:
674  swizzle_pipe[0] = 0;
675  swizzle_pipe[1] = 1;
676  swizzle_pipe[2] = 2;
677  swizzle_pipe[3] = 3;
678  swizzle_pipe[4] = 4;
679  break;
680  case 6:
681  swizzle_pipe[0] = 0;
682  swizzle_pipe[1] = 2;
683  swizzle_pipe[2] = 4;
684  swizzle_pipe[3] = 5;
685  swizzle_pipe[4] = 1;
686  swizzle_pipe[5] = 3;
687  break;
688  case 7:
689  swizzle_pipe[0] = 0;
690  swizzle_pipe[1] = 2;
691  swizzle_pipe[2] = 4;
692  swizzle_pipe[3] = 6;
693  swizzle_pipe[4] = 1;
694  swizzle_pipe[5] = 3;
695  swizzle_pipe[6] = 5;
696  break;
697  case 8:
698  swizzle_pipe[0] = 0;
699  swizzle_pipe[1] = 2;
700  swizzle_pipe[2] = 4;
701  swizzle_pipe[3] = 6;
702  swizzle_pipe[4] = 1;
703  swizzle_pipe[5] = 3;
704  swizzle_pipe[6] = 5;
705  swizzle_pipe[7] = 7;
706  break;
707  }
708 
709  cur_backend = 0;
710  for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
711  while (((1 << cur_backend) & enabled_backends_mask) == 0)
712  cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
713 
714  backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
715 
716  cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
717  }
718 
719  return backend_map;
720 }
721 
722 static int r600_count_pipe_bits(uint32_t val)
723 {
724  int i, ret = 0;
725  for (i = 0; i < 32; i++) {
726  ret += val & 1;
727  val >>= 1;
728  }
729  return ret;
730 }
731 
732 static void r600_gfx_init(struct drm_device *dev,
733  drm_radeon_private_t *dev_priv)
734 {
735  int i, j, num_qd_pipes;
736  u32 sx_debug_1;
737  u32 tc_cntl;
738  u32 arb_pop;
739  u32 num_gs_verts_per_thread;
740  u32 vgt_gs_per_es;
741  u32 gs_prim_buffer_depth = 0;
742  u32 sq_ms_fifo_sizes;
743  u32 sq_config;
744  u32 sq_gpr_resource_mgmt_1 = 0;
745  u32 sq_gpr_resource_mgmt_2 = 0;
746  u32 sq_thread_resource_mgmt = 0;
747  u32 sq_stack_resource_mgmt_1 = 0;
748  u32 sq_stack_resource_mgmt_2 = 0;
749  u32 hdp_host_path_cntl;
750  u32 backend_map;
751  u32 gb_tiling_config = 0;
752  u32 cc_rb_backend_disable;
753  u32 cc_gc_shader_pipe_config;
754  u32 ramcfg;
755 
756  /* setup chip specs */
757  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
758  case CHIP_R600:
759  dev_priv->r600_max_pipes = 4;
760  dev_priv->r600_max_tile_pipes = 8;
761  dev_priv->r600_max_simds = 4;
762  dev_priv->r600_max_backends = 4;
763  dev_priv->r600_max_gprs = 256;
764  dev_priv->r600_max_threads = 192;
765  dev_priv->r600_max_stack_entries = 256;
766  dev_priv->r600_max_hw_contexts = 8;
767  dev_priv->r600_max_gs_threads = 16;
768  dev_priv->r600_sx_max_export_size = 128;
769  dev_priv->r600_sx_max_export_pos_size = 16;
770  dev_priv->r600_sx_max_export_smx_size = 128;
771  dev_priv->r600_sq_num_cf_insts = 2;
772  break;
773  case CHIP_RV630:
774  case CHIP_RV635:
775  dev_priv->r600_max_pipes = 2;
776  dev_priv->r600_max_tile_pipes = 2;
777  dev_priv->r600_max_simds = 3;
778  dev_priv->r600_max_backends = 1;
779  dev_priv->r600_max_gprs = 128;
780  dev_priv->r600_max_threads = 192;
781  dev_priv->r600_max_stack_entries = 128;
782  dev_priv->r600_max_hw_contexts = 8;
783  dev_priv->r600_max_gs_threads = 4;
784  dev_priv->r600_sx_max_export_size = 128;
785  dev_priv->r600_sx_max_export_pos_size = 16;
786  dev_priv->r600_sx_max_export_smx_size = 128;
787  dev_priv->r600_sq_num_cf_insts = 2;
788  break;
789  case CHIP_RV610:
790  case CHIP_RS780:
791  case CHIP_RS880:
792  case CHIP_RV620:
793  dev_priv->r600_max_pipes = 1;
794  dev_priv->r600_max_tile_pipes = 1;
795  dev_priv->r600_max_simds = 2;
796  dev_priv->r600_max_backends = 1;
797  dev_priv->r600_max_gprs = 128;
798  dev_priv->r600_max_threads = 192;
799  dev_priv->r600_max_stack_entries = 128;
800  dev_priv->r600_max_hw_contexts = 4;
801  dev_priv->r600_max_gs_threads = 4;
802  dev_priv->r600_sx_max_export_size = 128;
803  dev_priv->r600_sx_max_export_pos_size = 16;
804  dev_priv->r600_sx_max_export_smx_size = 128;
805  dev_priv->r600_sq_num_cf_insts = 1;
806  break;
807  case CHIP_RV670:
808  dev_priv->r600_max_pipes = 4;
809  dev_priv->r600_max_tile_pipes = 4;
810  dev_priv->r600_max_simds = 4;
811  dev_priv->r600_max_backends = 4;
812  dev_priv->r600_max_gprs = 192;
813  dev_priv->r600_max_threads = 192;
814  dev_priv->r600_max_stack_entries = 256;
815  dev_priv->r600_max_hw_contexts = 8;
816  dev_priv->r600_max_gs_threads = 16;
817  dev_priv->r600_sx_max_export_size = 128;
818  dev_priv->r600_sx_max_export_pos_size = 16;
819  dev_priv->r600_sx_max_export_smx_size = 128;
820  dev_priv->r600_sq_num_cf_insts = 2;
821  break;
822  default:
823  break;
824  }
825 
826  /* Initialize HDP */
827  j = 0;
828  for (i = 0; i < 32; i++) {
829  RADEON_WRITE((0x2c14 + j), 0x00000000);
830  RADEON_WRITE((0x2c18 + j), 0x00000000);
831  RADEON_WRITE((0x2c1c + j), 0x00000000);
832  RADEON_WRITE((0x2c20 + j), 0x00000000);
833  RADEON_WRITE((0x2c24 + j), 0x00000000);
834  j += 0x18;
835  }
836 
837  RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
838 
839  /* setup tiling, simd, pipe config */
840  ramcfg = RADEON_READ(R600_RAMCFG);
841 
842  switch (dev_priv->r600_max_tile_pipes) {
843  case 1:
844  gb_tiling_config |= R600_PIPE_TILING(0);
845  break;
846  case 2:
847  gb_tiling_config |= R600_PIPE_TILING(1);
848  break;
849  case 4:
850  gb_tiling_config |= R600_PIPE_TILING(2);
851  break;
852  case 8:
853  gb_tiling_config |= R600_PIPE_TILING(3);
854  break;
855  default:
856  break;
857  }
858 
859  gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
860 
861  gb_tiling_config |= R600_GROUP_SIZE(0);
862 
863  if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
864  gb_tiling_config |= R600_ROW_TILING(3);
865  gb_tiling_config |= R600_SAMPLE_SPLIT(3);
866  } else {
867  gb_tiling_config |=
868  R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
869  gb_tiling_config |=
870  R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
871  }
872 
873  gb_tiling_config |= R600_BANK_SWAPS(1);
874 
875  cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
876  cc_rb_backend_disable |=
877  R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
878 
879  cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
880  cc_gc_shader_pipe_config |=
881  R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
882  cc_gc_shader_pipe_config |=
883  R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
884 
885  backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
886  (R6XX_MAX_BACKENDS -
887  r600_count_pipe_bits((cc_rb_backend_disable &
888  R6XX_MAX_BACKENDS_MASK) >> 16)),
889  (cc_rb_backend_disable >> 16));
890  gb_tiling_config |= R600_BACKEND_MAP(backend_map);
891 
892  RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
893  RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
894  RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
895  if (gb_tiling_config & 0xc0) {
896  dev_priv->r600_group_size = 512;
897  } else {
898  dev_priv->r600_group_size = 256;
899  }
900  dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
901  if (gb_tiling_config & 0x30) {
902  dev_priv->r600_nbanks = 8;
903  } else {
904  dev_priv->r600_nbanks = 4;
905  }
906 
907  RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
908  RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
909  RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
910 
911  num_qd_pipes =
912  R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
913  RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
914  RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
915 
916  /* set HW defaults for 3D engine */
917  RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
918  R600_ROQ_IB2_START(0x2b)));
919 
920  RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
921  R600_ROQ_END(0x40)));
922 
923  RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
924  R600_SYNC_GRADIENT |
925  R600_SYNC_WALKER |
926  R600_SYNC_ALIGNER));
927 
928  if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
929  RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
930 
931  sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
932  sx_debug_1 |= R600_SMX_EVENT_RELEASE;
933  if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
934  sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
935  RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
936 
937  if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
938  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
939  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
940  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
941  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
942  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
943  RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
944  else
945  RADEON_WRITE(R600_DB_DEBUG, 0);
946 
947  RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
948  R600_DEPTH_FLUSH(16) |
949  R600_DEPTH_PENDING_FREE(4) |
950  R600_DEPTH_CACHELINE_FREE(16)));
951  RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
952  RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
953 
954  RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
955  RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
956 
957  sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
958  if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
959  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
960  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
961  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
962  sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
963  R600_FETCH_FIFO_HIWATER(0xa) |
964  R600_DONE_FIFO_HIWATER(0xe0) |
965  R600_ALU_UPDATE_FIFO_HIWATER(0x8));
966  } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
967  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
968  sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
969  sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
970  }
971  RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
972 
973  /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
974  * should be adjusted as needed by the 2D/3D drivers. This just sets default values
975  */
976  sq_config = RADEON_READ(R600_SQ_CONFIG);
977  sq_config &= ~(R600_PS_PRIO(3) |
978  R600_VS_PRIO(3) |
979  R600_GS_PRIO(3) |
980  R600_ES_PRIO(3));
981  sq_config |= (R600_DX9_CONSTS |
982  R600_VC_ENABLE |
983  R600_PS_PRIO(0) |
984  R600_VS_PRIO(1) |
985  R600_GS_PRIO(2) |
986  R600_ES_PRIO(3));
987 
988  if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
989  sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
990  R600_NUM_VS_GPRS(124) |
991  R600_NUM_CLAUSE_TEMP_GPRS(4));
992  sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
993  R600_NUM_ES_GPRS(0));
994  sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
995  R600_NUM_VS_THREADS(48) |
996  R600_NUM_GS_THREADS(4) |
997  R600_NUM_ES_THREADS(4));
998  sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
999  R600_NUM_VS_STACK_ENTRIES(128));
1000  sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
1001  R600_NUM_ES_STACK_ENTRIES(0));
1002  } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1003  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1004  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1005  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
1006  /* no vertex cache */
1007  sq_config &= ~R600_VC_ENABLE;
1008 
1009  sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1010  R600_NUM_VS_GPRS(44) |
1011  R600_NUM_CLAUSE_TEMP_GPRS(2));
1012  sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1013  R600_NUM_ES_GPRS(17));
1014  sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1015  R600_NUM_VS_THREADS(78) |
1016  R600_NUM_GS_THREADS(4) |
1017  R600_NUM_ES_THREADS(31));
1018  sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1019  R600_NUM_VS_STACK_ENTRIES(40));
1020  sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1021  R600_NUM_ES_STACK_ENTRIES(16));
1022  } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1023  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1024  sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1025  R600_NUM_VS_GPRS(44) |
1026  R600_NUM_CLAUSE_TEMP_GPRS(2));
1027  sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1028  R600_NUM_ES_GPRS(18));
1029  sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1030  R600_NUM_VS_THREADS(78) |
1031  R600_NUM_GS_THREADS(4) |
1032  R600_NUM_ES_THREADS(31));
1033  sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1034  R600_NUM_VS_STACK_ENTRIES(40));
1035  sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1036  R600_NUM_ES_STACK_ENTRIES(16));
1037  } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1038  sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1039  R600_NUM_VS_GPRS(44) |
1040  R600_NUM_CLAUSE_TEMP_GPRS(2));
1041  sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1042  R600_NUM_ES_GPRS(17));
1043  sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1044  R600_NUM_VS_THREADS(78) |
1045  R600_NUM_GS_THREADS(4) |
1046  R600_NUM_ES_THREADS(31));
1047  sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1048  R600_NUM_VS_STACK_ENTRIES(64));
1049  sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1050  R600_NUM_ES_STACK_ENTRIES(64));
1051  }
1052 
1053  RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1054  RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1055  RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1056  RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1057  RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1058  RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1059 
1060  if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1061  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1062  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1063  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1064  RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1065  else
1066  RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1067 
1068  RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1069  R600_S0_Y(0x4) |
1070  R600_S1_X(0x4) |
1071  R600_S1_Y(0xc)));
1072  RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1073  R600_S0_Y(0xe) |
1074  R600_S1_X(0x2) |
1075  R600_S1_Y(0x2) |
1076  R600_S2_X(0xa) |
1077  R600_S2_Y(0x6) |
1078  R600_S3_X(0x6) |
1079  R600_S3_Y(0xa)));
1080  RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1081  R600_S0_Y(0xb) |
1082  R600_S1_X(0x4) |
1083  R600_S1_Y(0xc) |
1084  R600_S2_X(0x1) |
1085  R600_S2_Y(0x6) |
1086  R600_S3_X(0xa) |
1087  R600_S3_Y(0xe)));
1088  RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1089  R600_S4_Y(0x1) |
1090  R600_S5_X(0x0) |
1091  R600_S5_Y(0x0) |
1092  R600_S6_X(0xb) |
1093  R600_S6_Y(0x4) |
1094  R600_S7_X(0x7) |
1095  R600_S7_Y(0x8)));
1096 
1097 
1098  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1099  case CHIP_R600:
1100  case CHIP_RV630:
1101  case CHIP_RV635:
1102  gs_prim_buffer_depth = 0;
1103  break;
1104  case CHIP_RV610:
1105  case CHIP_RS780:
1106  case CHIP_RS880:
1107  case CHIP_RV620:
1108  gs_prim_buffer_depth = 32;
1109  break;
1110  case CHIP_RV670:
1111  gs_prim_buffer_depth = 128;
1112  break;
1113  default:
1114  break;
1115  }
1116 
1117  num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1118  vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1119  /* Max value for this is 256 */
1120  if (vgt_gs_per_es > 256)
1121  vgt_gs_per_es = 256;
1122 
1123  RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1124  RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1125  RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1126  RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1127 
1128  /* more default values. 2D/3D driver should adjust as needed */
1129  RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1130  RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1131  RADEON_WRITE(R600_SX_MISC, 0);
1132  RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1133  RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1134  RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1135  RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1136  RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1137  RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1138 
1139  /* clear render buffer base addresses */
1140  RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1141  RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1142  RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1143  RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1144  RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1145  RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1146  RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1147  RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1148 
1149  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1150  case CHIP_RV610:
1151  case CHIP_RS780:
1152  case CHIP_RS880:
1153  case CHIP_RV620:
1154  tc_cntl = R600_TC_L2_SIZE(8);
1155  break;
1156  case CHIP_RV630:
1157  case CHIP_RV635:
1158  tc_cntl = R600_TC_L2_SIZE(4);
1159  break;
1160  case CHIP_R600:
1161  tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1162  break;
1163  default:
1164  tc_cntl = R600_TC_L2_SIZE(0);
1165  break;
1166  }
1167 
1168  RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1169 
1170  hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1171  RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1172 
1173  arb_pop = RADEON_READ(R600_ARB_POP);
1174  arb_pop |= R600_ENABLE_TC128;
1175  RADEON_WRITE(R600_ARB_POP, arb_pop);
1176 
1177  RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1178  RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1179  R600_NUM_CLIP_SEQ(3)));
1180  RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1181 
1182 }
1183 
1184 static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv,
1185  u32 num_tile_pipes,
1186  u32 num_backends,
1187  u32 backend_disable_mask)
1188 {
1189  u32 backend_map = 0;
1190  u32 enabled_backends_mask;
1191  u32 enabled_backends_count;
1192  u32 cur_pipe;
1193  u32 swizzle_pipe[R7XX_MAX_PIPES];
1194  u32 cur_backend;
1195  u32 i;
1196  bool force_no_swizzle;
1197 
1198  if (num_tile_pipes > R7XX_MAX_PIPES)
1199  num_tile_pipes = R7XX_MAX_PIPES;
1200  if (num_tile_pipes < 1)
1201  num_tile_pipes = 1;
1202  if (num_backends > R7XX_MAX_BACKENDS)
1203  num_backends = R7XX_MAX_BACKENDS;
1204  if (num_backends < 1)
1205  num_backends = 1;
1206 
1207  enabled_backends_mask = 0;
1208  enabled_backends_count = 0;
1209  for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1210  if (((backend_disable_mask >> i) & 1) == 0) {
1211  enabled_backends_mask |= (1 << i);
1212  ++enabled_backends_count;
1213  }
1214  if (enabled_backends_count == num_backends)
1215  break;
1216  }
1217 
1218  if (enabled_backends_count == 0) {
1219  enabled_backends_mask = 1;
1220  enabled_backends_count = 1;
1221  }
1222 
1223  if (enabled_backends_count != num_backends)
1224  num_backends = enabled_backends_count;
1225 
1226  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1227  case CHIP_RV770:
1228  case CHIP_RV730:
1229  force_no_swizzle = false;
1230  break;
1231  case CHIP_RV710:
1232  case CHIP_RV740:
1233  default:
1234  force_no_swizzle = true;
1235  break;
1236  }
1237 
1238  memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1239  switch (num_tile_pipes) {
1240  case 1:
1241  swizzle_pipe[0] = 0;
1242  break;
1243  case 2:
1244  swizzle_pipe[0] = 0;
1245  swizzle_pipe[1] = 1;
1246  break;
1247  case 3:
1248  if (force_no_swizzle) {
1249  swizzle_pipe[0] = 0;
1250  swizzle_pipe[1] = 1;
1251  swizzle_pipe[2] = 2;
1252  } else {
1253  swizzle_pipe[0] = 0;
1254  swizzle_pipe[1] = 2;
1255  swizzle_pipe[2] = 1;
1256  }
1257  break;
1258  case 4:
1259  if (force_no_swizzle) {
1260  swizzle_pipe[0] = 0;
1261  swizzle_pipe[1] = 1;
1262  swizzle_pipe[2] = 2;
1263  swizzle_pipe[3] = 3;
1264  } else {
1265  swizzle_pipe[0] = 0;
1266  swizzle_pipe[1] = 2;
1267  swizzle_pipe[2] = 3;
1268  swizzle_pipe[3] = 1;
1269  }
1270  break;
1271  case 5:
1272  if (force_no_swizzle) {
1273  swizzle_pipe[0] = 0;
1274  swizzle_pipe[1] = 1;
1275  swizzle_pipe[2] = 2;
1276  swizzle_pipe[3] = 3;
1277  swizzle_pipe[4] = 4;
1278  } else {
1279  swizzle_pipe[0] = 0;
1280  swizzle_pipe[1] = 2;
1281  swizzle_pipe[2] = 4;
1282  swizzle_pipe[3] = 1;
1283  swizzle_pipe[4] = 3;
1284  }
1285  break;
1286  case 6:
1287  if (force_no_swizzle) {
1288  swizzle_pipe[0] = 0;
1289  swizzle_pipe[1] = 1;
1290  swizzle_pipe[2] = 2;
1291  swizzle_pipe[3] = 3;
1292  swizzle_pipe[4] = 4;
1293  swizzle_pipe[5] = 5;
1294  } else {
1295  swizzle_pipe[0] = 0;
1296  swizzle_pipe[1] = 2;
1297  swizzle_pipe[2] = 4;
1298  swizzle_pipe[3] = 5;
1299  swizzle_pipe[4] = 3;
1300  swizzle_pipe[5] = 1;
1301  }
1302  break;
1303  case 7:
1304  if (force_no_swizzle) {
1305  swizzle_pipe[0] = 0;
1306  swizzle_pipe[1] = 1;
1307  swizzle_pipe[2] = 2;
1308  swizzle_pipe[3] = 3;
1309  swizzle_pipe[4] = 4;
1310  swizzle_pipe[5] = 5;
1311  swizzle_pipe[6] = 6;
1312  } else {
1313  swizzle_pipe[0] = 0;
1314  swizzle_pipe[1] = 2;
1315  swizzle_pipe[2] = 4;
1316  swizzle_pipe[3] = 6;
1317  swizzle_pipe[4] = 3;
1318  swizzle_pipe[5] = 1;
1319  swizzle_pipe[6] = 5;
1320  }
1321  break;
1322  case 8:
1323  if (force_no_swizzle) {
1324  swizzle_pipe[0] = 0;
1325  swizzle_pipe[1] = 1;
1326  swizzle_pipe[2] = 2;
1327  swizzle_pipe[3] = 3;
1328  swizzle_pipe[4] = 4;
1329  swizzle_pipe[5] = 5;
1330  swizzle_pipe[6] = 6;
1331  swizzle_pipe[7] = 7;
1332  } else {
1333  swizzle_pipe[0] = 0;
1334  swizzle_pipe[1] = 2;
1335  swizzle_pipe[2] = 4;
1336  swizzle_pipe[3] = 6;
1337  swizzle_pipe[4] = 3;
1338  swizzle_pipe[5] = 1;
1339  swizzle_pipe[6] = 7;
1340  swizzle_pipe[7] = 5;
1341  }
1342  break;
1343  }
1344 
1345  cur_backend = 0;
1346  for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1347  while (((1 << cur_backend) & enabled_backends_mask) == 0)
1348  cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1349 
1350  backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1351 
1352  cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1353  }
1354 
1355  return backend_map;
1356 }
1357 
1358 static void r700_gfx_init(struct drm_device *dev,
1359  drm_radeon_private_t *dev_priv)
1360 {
1361  int i, j, num_qd_pipes;
1362  u32 ta_aux_cntl;
1363  u32 sx_debug_1;
1364  u32 smx_dc_ctl0;
1365  u32 db_debug3;
1366  u32 num_gs_verts_per_thread;
1367  u32 vgt_gs_per_es;
1368  u32 gs_prim_buffer_depth = 0;
1369  u32 sq_ms_fifo_sizes;
1370  u32 sq_config;
1371  u32 sq_thread_resource_mgmt;
1372  u32 hdp_host_path_cntl;
1373  u32 sq_dyn_gpr_size_simd_ab_0;
1374  u32 backend_map;
1375  u32 gb_tiling_config = 0;
1376  u32 cc_rb_backend_disable;
1377  u32 cc_gc_shader_pipe_config;
1378  u32 mc_arb_ramcfg;
1379  u32 db_debug4;
1380 
1381  /* setup chip specs */
1382  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1383  case CHIP_RV770:
1384  dev_priv->r600_max_pipes = 4;
1385  dev_priv->r600_max_tile_pipes = 8;
1386  dev_priv->r600_max_simds = 10;
1387  dev_priv->r600_max_backends = 4;
1388  dev_priv->r600_max_gprs = 256;
1389  dev_priv->r600_max_threads = 248;
1390  dev_priv->r600_max_stack_entries = 512;
1391  dev_priv->r600_max_hw_contexts = 8;
1392  dev_priv->r600_max_gs_threads = 16 * 2;
1393  dev_priv->r600_sx_max_export_size = 128;
1394  dev_priv->r600_sx_max_export_pos_size = 16;
1395  dev_priv->r600_sx_max_export_smx_size = 112;
1396  dev_priv->r600_sq_num_cf_insts = 2;
1397 
1398  dev_priv->r700_sx_num_of_sets = 7;
1399  dev_priv->r700_sc_prim_fifo_size = 0xF9;
1400  dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1401  dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1402  break;
1403  case CHIP_RV730:
1404  dev_priv->r600_max_pipes = 2;
1405  dev_priv->r600_max_tile_pipes = 4;
1406  dev_priv->r600_max_simds = 8;
1407  dev_priv->r600_max_backends = 2;
1408  dev_priv->r600_max_gprs = 128;
1409  dev_priv->r600_max_threads = 248;
1410  dev_priv->r600_max_stack_entries = 256;
1411  dev_priv->r600_max_hw_contexts = 8;
1412  dev_priv->r600_max_gs_threads = 16 * 2;
1413  dev_priv->r600_sx_max_export_size = 256;
1414  dev_priv->r600_sx_max_export_pos_size = 32;
1415  dev_priv->r600_sx_max_export_smx_size = 224;
1416  dev_priv->r600_sq_num_cf_insts = 2;
1417 
1418  dev_priv->r700_sx_num_of_sets = 7;
1419  dev_priv->r700_sc_prim_fifo_size = 0xf9;
1420  dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1421  dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1422  if (dev_priv->r600_sx_max_export_pos_size > 16) {
1423  dev_priv->r600_sx_max_export_pos_size -= 16;
1424  dev_priv->r600_sx_max_export_smx_size += 16;
1425  }
1426  break;
1427  case CHIP_RV710:
1428  dev_priv->r600_max_pipes = 2;
1429  dev_priv->r600_max_tile_pipes = 2;
1430  dev_priv->r600_max_simds = 2;
1431  dev_priv->r600_max_backends = 1;
1432  dev_priv->r600_max_gprs = 256;
1433  dev_priv->r600_max_threads = 192;
1434  dev_priv->r600_max_stack_entries = 256;
1435  dev_priv->r600_max_hw_contexts = 4;
1436  dev_priv->r600_max_gs_threads = 8 * 2;
1437  dev_priv->r600_sx_max_export_size = 128;
1438  dev_priv->r600_sx_max_export_pos_size = 16;
1439  dev_priv->r600_sx_max_export_smx_size = 112;
1440  dev_priv->r600_sq_num_cf_insts = 1;
1441 
1442  dev_priv->r700_sx_num_of_sets = 7;
1443  dev_priv->r700_sc_prim_fifo_size = 0x40;
1444  dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1445  dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1446  break;
1447  case CHIP_RV740:
1448  dev_priv->r600_max_pipes = 4;
1449  dev_priv->r600_max_tile_pipes = 4;
1450  dev_priv->r600_max_simds = 8;
1451  dev_priv->r600_max_backends = 4;
1452  dev_priv->r600_max_gprs = 256;
1453  dev_priv->r600_max_threads = 248;
1454  dev_priv->r600_max_stack_entries = 512;
1455  dev_priv->r600_max_hw_contexts = 8;
1456  dev_priv->r600_max_gs_threads = 16 * 2;
1457  dev_priv->r600_sx_max_export_size = 256;
1458  dev_priv->r600_sx_max_export_pos_size = 32;
1459  dev_priv->r600_sx_max_export_smx_size = 224;
1460  dev_priv->r600_sq_num_cf_insts = 2;
1461 
1462  dev_priv->r700_sx_num_of_sets = 7;
1463  dev_priv->r700_sc_prim_fifo_size = 0x100;
1464  dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1465  dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1466 
1467  if (dev_priv->r600_sx_max_export_pos_size > 16) {
1468  dev_priv->r600_sx_max_export_pos_size -= 16;
1469  dev_priv->r600_sx_max_export_smx_size += 16;
1470  }
1471  break;
1472  default:
1473  break;
1474  }
1475 
1476  /* Initialize HDP */
1477  j = 0;
1478  for (i = 0; i < 32; i++) {
1479  RADEON_WRITE((0x2c14 + j), 0x00000000);
1480  RADEON_WRITE((0x2c18 + j), 0x00000000);
1481  RADEON_WRITE((0x2c1c + j), 0x00000000);
1482  RADEON_WRITE((0x2c20 + j), 0x00000000);
1483  RADEON_WRITE((0x2c24 + j), 0x00000000);
1484  j += 0x18;
1485  }
1486 
1487  RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1488 
1489  /* setup tiling, simd, pipe config */
1490  mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1491 
1492  switch (dev_priv->r600_max_tile_pipes) {
1493  case 1:
1494  gb_tiling_config |= R600_PIPE_TILING(0);
1495  break;
1496  case 2:
1497  gb_tiling_config |= R600_PIPE_TILING(1);
1498  break;
1499  case 4:
1500  gb_tiling_config |= R600_PIPE_TILING(2);
1501  break;
1502  case 8:
1503  gb_tiling_config |= R600_PIPE_TILING(3);
1504  break;
1505  default:
1506  break;
1507  }
1508 
1509  if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1510  gb_tiling_config |= R600_BANK_TILING(1);
1511  else
1512  gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1513 
1514  gb_tiling_config |= R600_GROUP_SIZE(0);
1515 
1516  if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1517  gb_tiling_config |= R600_ROW_TILING(3);
1518  gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1519  } else {
1520  gb_tiling_config |=
1521  R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1522  gb_tiling_config |=
1523  R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1524  }
1525 
1526  gb_tiling_config |= R600_BANK_SWAPS(1);
1527 
1528  cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1529  cc_rb_backend_disable |=
1530  R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1531 
1532  cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1533  cc_gc_shader_pipe_config |=
1534  R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1535  cc_gc_shader_pipe_config |=
1536  R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1537 
1538  if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)
1539  backend_map = 0x28;
1540  else
1541  backend_map = r700_get_tile_pipe_to_backend_map(dev_priv,
1542  dev_priv->r600_max_tile_pipes,
1543  (R7XX_MAX_BACKENDS -
1544  r600_count_pipe_bits((cc_rb_backend_disable &
1545  R7XX_MAX_BACKENDS_MASK) >> 16)),
1546  (cc_rb_backend_disable >> 16));
1547  gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1548 
1549  RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1550  RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1551  RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1552  if (gb_tiling_config & 0xc0) {
1553  dev_priv->r600_group_size = 512;
1554  } else {
1555  dev_priv->r600_group_size = 256;
1556  }
1557  dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1558  if (gb_tiling_config & 0x30) {
1559  dev_priv->r600_nbanks = 8;
1560  } else {
1561  dev_priv->r600_nbanks = 4;
1562  }
1563 
1564  RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1565  RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1566  RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1567 
1568  RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1569  RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1570  RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1571  RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1572  RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1573 
1574  num_qd_pipes =
1575  R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
1576  RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1577  RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1578 
1579  /* set HW defaults for 3D engine */
1580  RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1581  R600_ROQ_IB2_START(0x2b)));
1582 
1583  RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1584 
1585  ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX);
1586  RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO);
1587 
1588  sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1589  sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1590  RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1591 
1592  smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1593  smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1594  smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1595  RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1596 
1597  if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740)
1598  RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1599  R700_GS_FLUSH_CTL(4) |
1600  R700_ACK_FLUSH_CTL(3) |
1601  R700_SYNC_FLUSH_CTL));
1602 
1603  db_debug3 = RADEON_READ(R700_DB_DEBUG3);
1604  db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f);
1605  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1606  case CHIP_RV770:
1607  case CHIP_RV740:
1608  db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f);
1609  break;
1610  case CHIP_RV710:
1611  case CHIP_RV730:
1612  default:
1613  db_debug3 |= R700_DB_CLK_OFF_DELAY(2);
1614  break;
1615  }
1616  RADEON_WRITE(R700_DB_DEBUG3, db_debug3);
1617 
1618  if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) {
1619  db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1620  db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1621  RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1622  }
1623 
1624  RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1625  R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1626  R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1627 
1628  RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1629  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1630  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1631 
1632  RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1633 
1634  RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1635 
1636  RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1637 
1638  RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1639 
1640  RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1641 
1642  sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1643  R600_DONE_FIFO_HIWATER(0xe0) |
1644  R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1645  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1646  case CHIP_RV770:
1647  case CHIP_RV730:
1648  case CHIP_RV710:
1649  sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1650  break;
1651  case CHIP_RV740:
1652  default:
1653  sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1654  break;
1655  }
1656  RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1657 
1658  /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1659  * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1660  */
1661  sq_config = RADEON_READ(R600_SQ_CONFIG);
1662  sq_config &= ~(R600_PS_PRIO(3) |
1663  R600_VS_PRIO(3) |
1664  R600_GS_PRIO(3) |
1665  R600_ES_PRIO(3));
1666  sq_config |= (R600_DX9_CONSTS |
1667  R600_VC_ENABLE |
1668  R600_EXPORT_SRC_C |
1669  R600_PS_PRIO(0) |
1670  R600_VS_PRIO(1) |
1671  R600_GS_PRIO(2) |
1672  R600_ES_PRIO(3));
1673  if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1674  /* no vertex cache */
1675  sq_config &= ~R600_VC_ENABLE;
1676 
1677  RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1678 
1679  RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1680  R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1681  R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1682 
1683  RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1684  R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1685 
1686  sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1687  R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1688  R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1689  if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1690  sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1691  else
1692  sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1693  RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1694 
1695  RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1696  R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1697 
1698  RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1699  R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1700 
1701  sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1702  R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1703  R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1704  R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1705 
1706  RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1707  RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1708  RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1709  RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1710  RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1711  RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1712  RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1713  RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1714 
1715  RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1716  R700_FORCE_EOV_MAX_REZ_CNT(255)));
1717 
1718  if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1719  RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1720  R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1721  else
1722  RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1723  R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1724 
1725  switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1726  case CHIP_RV770:
1727  case CHIP_RV730:
1728  case CHIP_RV740:
1729  gs_prim_buffer_depth = 384;
1730  break;
1731  case CHIP_RV710:
1732  gs_prim_buffer_depth = 128;
1733  break;
1734  default:
1735  break;
1736  }
1737 
1738  num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1739  vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1740  /* Max value for this is 256 */
1741  if (vgt_gs_per_es > 256)
1742  vgt_gs_per_es = 256;
1743 
1744  RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1745  RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1746  RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1747 
1748  /* more default values. 2D/3D driver should adjust as needed */
1749  RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1750  RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1751  RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1752  RADEON_WRITE(R600_SX_MISC, 0);
1753  RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1754  RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1755  RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1756  RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1757  RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1758  RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1759  RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1760  RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1761 
1762  /* clear render buffer base addresses */
1763  RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1764  RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1765  RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1766  RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1767  RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1768  RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1769  RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1770  RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1771 
1772  RADEON_WRITE(R700_TCP_CNTL, 0);
1773 
1774  hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1775  RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1776 
1777  RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1778 
1779  RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1780  R600_NUM_CLIP_SEQ(3)));
1781 
1782 }
1783 
1784 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1785  drm_radeon_private_t *dev_priv,
1786  struct drm_file *file_priv)
1787 {
1788  struct drm_radeon_master_private *master_priv;
1789  u32 ring_start;
1790  u64 rptr_addr;
1791 
1792  if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1793  r700_gfx_init(dev, dev_priv);
1794  else
1795  r600_gfx_init(dev, dev_priv);
1796 
1797  RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1798  RADEON_READ(R600_GRBM_SOFT_RESET);
1799  mdelay(15);
1800  RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1801 
1802 
1803  /* Set ring buffer size */
1804 #ifdef __BIG_ENDIAN
1805  RADEON_WRITE(R600_CP_RB_CNTL,
1806  R600_BUF_SWAP_32BIT |
1807  R600_RB_NO_UPDATE |
1808  (dev_priv->ring.rptr_update_l2qw << 8) |
1809  dev_priv->ring.size_l2qw);
1810 #else
1811  RADEON_WRITE(R600_CP_RB_CNTL,
1812  RADEON_RB_NO_UPDATE |
1813  (dev_priv->ring.rptr_update_l2qw << 8) |
1814  dev_priv->ring.size_l2qw);
1815 #endif
1816 
1817  RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0);
1818 
1819  /* Set the write pointer delay */
1820  RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1821 
1822 #ifdef __BIG_ENDIAN
1823  RADEON_WRITE(R600_CP_RB_CNTL,
1824  R600_BUF_SWAP_32BIT |
1825  R600_RB_NO_UPDATE |
1826  R600_RB_RPTR_WR_ENA |
1827  (dev_priv->ring.rptr_update_l2qw << 8) |
1828  dev_priv->ring.size_l2qw);
1829 #else
1830  RADEON_WRITE(R600_CP_RB_CNTL,
1831  R600_RB_NO_UPDATE |
1832  R600_RB_RPTR_WR_ENA |
1833  (dev_priv->ring.rptr_update_l2qw << 8) |
1834  dev_priv->ring.size_l2qw);
1835 #endif
1836 
1837  /* Initialize the ring buffer's read and write pointers */
1838  RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1839  RADEON_WRITE(R600_CP_RB_WPTR, 0);
1840  SET_RING_HEAD(dev_priv, 0);
1841  dev_priv->ring.tail = 0;
1842 
1843 #if __OS_HAS_AGP
1844  if (dev_priv->flags & RADEON_IS_AGP) {
1845  rptr_addr = dev_priv->ring_rptr->offset
1846  - dev->agp->base +
1847  dev_priv->gart_vm_start;
1848  } else
1849 #endif
1850  {
1851  rptr_addr = dev_priv->ring_rptr->offset
1852  - ((unsigned long) dev->sg->virtual)
1853  + dev_priv->gart_vm_start;
1854  }
1855  RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc));
1856  RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr));
1857 
1858 #ifdef __BIG_ENDIAN
1859  RADEON_WRITE(R600_CP_RB_CNTL,
1860  RADEON_BUF_SWAP_32BIT |
1861  (dev_priv->ring.rptr_update_l2qw << 8) |
1862  dev_priv->ring.size_l2qw);
1863 #else
1864  RADEON_WRITE(R600_CP_RB_CNTL,
1865  (dev_priv->ring.rptr_update_l2qw << 8) |
1866  dev_priv->ring.size_l2qw);
1867 #endif
1868 
1869 #if __OS_HAS_AGP
1870  if (dev_priv->flags & RADEON_IS_AGP) {
1871  /* XXX */
1872  radeon_write_agp_base(dev_priv, dev->agp->base);
1873 
1874  /* XXX */
1875  radeon_write_agp_location(dev_priv,
1876  (((dev_priv->gart_vm_start - 1 +
1877  dev_priv->gart_size) & 0xffff0000) |
1878  (dev_priv->gart_vm_start >> 16)));
1879 
1880  ring_start = (dev_priv->cp_ring->offset
1881  - dev->agp->base
1882  + dev_priv->gart_vm_start);
1883  } else
1884 #endif
1885  ring_start = (dev_priv->cp_ring->offset
1886  - (unsigned long)dev->sg->virtual
1887  + dev_priv->gart_vm_start);
1888 
1889  RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1890 
1891  RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1892 
1893  RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1894 
1895  /* Initialize the scratch register pointer. This will cause
1896  * the scratch register values to be written out to memory
1897  * whenever they are updated.
1898  *
1899  * We simply put this behind the ring read pointer, this works
1900  * with PCI GART as well as (whatever kind of) AGP GART
1901  */
1902  {
1903  u64 scratch_addr;
1904 
1905  scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC;
1906  scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1907  scratch_addr += R600_SCRATCH_REG_OFFSET;
1908  scratch_addr >>= 8;
1909  scratch_addr &= 0xffffffff;
1910 
1911  RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1912  }
1913 
1914  RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1915 
1916  /* Turn on bus mastering */
1917  radeon_enable_bm(dev_priv);
1918 
1919  radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1920  RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1921 
1922  radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1923  RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1924 
1925  radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1926  RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1927 
1928  /* reset sarea copies of these */
1929  master_priv = file_priv->master->driver_priv;
1930  if (master_priv->sarea_priv) {
1931  master_priv->sarea_priv->last_frame = 0;
1932  master_priv->sarea_priv->last_dispatch = 0;
1933  master_priv->sarea_priv->last_clear = 0;
1934  }
1935 
1936  r600_do_wait_for_idle(dev_priv);
1937 
1938 }
1939 
1940 int r600_do_cleanup_cp(struct drm_device *dev)
1941 {
1942  drm_radeon_private_t *dev_priv = dev->dev_private;
1943  DRM_DEBUG("\n");
1944 
1945  /* Make sure interrupts are disabled here because the uninstall ioctl
1946  * may not have been called from userspace and after dev_private
1947  * is freed, it's too late.
1948  */
1949  if (dev->irq_enabled)
1950  drm_irq_uninstall(dev);
1951 
1952 #if __OS_HAS_AGP
1953  if (dev_priv->flags & RADEON_IS_AGP) {
1954  if (dev_priv->cp_ring != NULL) {
1955  drm_core_ioremapfree(dev_priv->cp_ring, dev);
1956  dev_priv->cp_ring = NULL;
1957  }
1958  if (dev_priv->ring_rptr != NULL) {
1959  drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1960  dev_priv->ring_rptr = NULL;
1961  }
1962  if (dev->agp_buffer_map != NULL) {
1963  drm_core_ioremapfree(dev->agp_buffer_map, dev);
1964  dev->agp_buffer_map = NULL;
1965  }
1966  } else
1967 #endif
1968  {
1969 
1970  if (dev_priv->gart_info.bus_addr)
1971  r600_page_table_cleanup(dev, &dev_priv->gart_info);
1972 
1973  if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1974  drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1975  dev_priv->gart_info.addr = NULL;
1976  }
1977  }
1978  /* only clear to the start of flags */
1979  memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1980 
1981  return 0;
1982 }
1983 
1984 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1985  struct drm_file *file_priv)
1986 {
1987  drm_radeon_private_t *dev_priv = dev->dev_private;
1988  struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1989 
1990  DRM_DEBUG("\n");
1991 
1992  mutex_init(&dev_priv->cs_mutex);
1993  r600_cs_legacy_init();
1994  /* if we require new memory map but we don't have it fail */
1995  if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1996  DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1997  r600_do_cleanup_cp(dev);
1998  return -EINVAL;
1999  }
2000 
2001  if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
2002  DRM_DEBUG("Forcing AGP card to PCI mode\n");
2003  dev_priv->flags &= ~RADEON_IS_AGP;
2004  /* The writeback test succeeds, but when writeback is enabled,
2005  * the ring buffer read ptr update fails after first 128 bytes.
2006  */
2007  radeon_no_wb = 1;
2008  } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
2009  && !init->is_pci) {
2010  DRM_DEBUG("Restoring AGP flag\n");
2011  dev_priv->flags |= RADEON_IS_AGP;
2012  }
2013 
2014  dev_priv->usec_timeout = init->usec_timeout;
2015  if (dev_priv->usec_timeout < 1 ||
2016  dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
2017  DRM_DEBUG("TIMEOUT problem!\n");
2018  r600_do_cleanup_cp(dev);
2019  return -EINVAL;
2020  }
2021 
2022  /* Enable vblank on CRTC1 for older X servers
2023  */
2024  dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
2025  dev_priv->do_boxes = 0;
2026  dev_priv->cp_mode = init->cp_mode;
2027 
2028  /* We don't support anything other than bus-mastering ring mode,
2029  * but the ring can be in either AGP or PCI space for the ring
2030  * read pointer.
2031  */
2032  if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
2033  (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
2034  DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
2035  r600_do_cleanup_cp(dev);
2036  return -EINVAL;
2037  }
2038 
2039  switch (init->fb_bpp) {
2040  case 16:
2041  dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
2042  break;
2043  case 32:
2044  default:
2045  dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
2046  break;
2047  }
2048  dev_priv->front_offset = init->front_offset;
2049  dev_priv->front_pitch = init->front_pitch;
2050  dev_priv->back_offset = init->back_offset;
2051  dev_priv->back_pitch = init->back_pitch;
2052 
2053  dev_priv->ring_offset = init->ring_offset;
2054  dev_priv->ring_rptr_offset = init->ring_rptr_offset;
2055  dev_priv->buffers_offset = init->buffers_offset;
2056  dev_priv->gart_textures_offset = init->gart_textures_offset;
2057 
2058  master_priv->sarea = drm_getsarea(dev);
2059  if (!master_priv->sarea) {
2060  DRM_ERROR("could not find sarea!\n");
2061  r600_do_cleanup_cp(dev);
2062  return -EINVAL;
2063  }
2064 
2065  dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
2066  if (!dev_priv->cp_ring) {
2067  DRM_ERROR("could not find cp ring region!\n");
2068  r600_do_cleanup_cp(dev);
2069  return -EINVAL;
2070  }
2071  dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
2072  if (!dev_priv->ring_rptr) {
2073  DRM_ERROR("could not find ring read pointer!\n");
2074  r600_do_cleanup_cp(dev);
2075  return -EINVAL;
2076  }
2077  dev->agp_buffer_token = init->buffers_offset;
2078  dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
2079  if (!dev->agp_buffer_map) {
2080  DRM_ERROR("could not find dma buffer region!\n");
2081  r600_do_cleanup_cp(dev);
2082  return -EINVAL;
2083  }
2084 
2085  if (init->gart_textures_offset) {
2086  dev_priv->gart_textures =
2087  drm_core_findmap(dev, init->gart_textures_offset);
2088  if (!dev_priv->gart_textures) {
2089  DRM_ERROR("could not find GART texture region!\n");
2090  r600_do_cleanup_cp(dev);
2091  return -EINVAL;
2092  }
2093  }
2094 
2095 #if __OS_HAS_AGP
2096  /* XXX */
2097  if (dev_priv->flags & RADEON_IS_AGP) {
2098  drm_core_ioremap_wc(dev_priv->cp_ring, dev);
2099  drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
2100  drm_core_ioremap_wc(dev->agp_buffer_map, dev);
2101  if (!dev_priv->cp_ring->handle ||
2102  !dev_priv->ring_rptr->handle ||
2103  !dev->agp_buffer_map->handle) {
2104  DRM_ERROR("could not find ioremap agp regions!\n");
2105  r600_do_cleanup_cp(dev);
2106  return -EINVAL;
2107  }
2108  } else
2109 #endif
2110  {
2111  dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
2112  dev_priv->ring_rptr->handle =
2113  (void *)(unsigned long)dev_priv->ring_rptr->offset;
2114  dev->agp_buffer_map->handle =
2115  (void *)(unsigned long)dev->agp_buffer_map->offset;
2116 
2117  DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2118  dev_priv->cp_ring->handle);
2119  DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2120  dev_priv->ring_rptr->handle);
2121  DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2122  dev->agp_buffer_map->handle);
2123  }
2124 
2125  dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2126  dev_priv->fb_size =
2127  (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2128  - dev_priv->fb_location;
2129 
2130  dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2131  ((dev_priv->front_offset
2132  + dev_priv->fb_location) >> 10));
2133 
2134  dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2135  ((dev_priv->back_offset
2136  + dev_priv->fb_location) >> 10));
2137 
2138  dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2139  ((dev_priv->depth_offset
2140  + dev_priv->fb_location) >> 10));
2141 
2142  dev_priv->gart_size = init->gart_size;
2143 
2144  /* New let's set the memory map ... */
2145  if (dev_priv->new_memmap) {
2146  u32 base = 0;
2147 
2148  DRM_INFO("Setting GART location based on new memory map\n");
2149 
2150  /* If using AGP, try to locate the AGP aperture at the same
2151  * location in the card and on the bus, though we have to
2152  * align it down.
2153  */
2154 #if __OS_HAS_AGP
2155  /* XXX */
2156  if (dev_priv->flags & RADEON_IS_AGP) {
2157  base = dev->agp->base;
2158  /* Check if valid */
2159  if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2160  base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2161  DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2162  dev->agp->base);
2163  base = 0;
2164  }
2165  }
2166 #endif
2167  /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2168  if (base == 0) {
2169  base = dev_priv->fb_location + dev_priv->fb_size;
2170  if (base < dev_priv->fb_location ||
2171  ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2172  base = dev_priv->fb_location
2173  - dev_priv->gart_size;
2174  }
2175  dev_priv->gart_vm_start = base & 0xffc00000u;
2176  if (dev_priv->gart_vm_start != base)
2177  DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2178  base, dev_priv->gart_vm_start);
2179  }
2180 
2181 #if __OS_HAS_AGP
2182  /* XXX */
2183  if (dev_priv->flags & RADEON_IS_AGP)
2184  dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2185  - dev->agp->base
2186  + dev_priv->gart_vm_start);
2187  else
2188 #endif
2189  dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2190  - (unsigned long)dev->sg->virtual
2191  + dev_priv->gart_vm_start);
2192 
2193  DRM_DEBUG("fb 0x%08x size %d\n",
2194  (unsigned int) dev_priv->fb_location,
2195  (unsigned int) dev_priv->fb_size);
2196  DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2197  DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2198  (unsigned int) dev_priv->gart_vm_start);
2199  DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2200  dev_priv->gart_buffers_offset);
2201 
2202  dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2203  dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2204  + init->ring_size / sizeof(u32));
2205  dev_priv->ring.size = init->ring_size;
2206  dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2207 
2208  dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2209  dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2210 
2211  dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2212  dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2213 
2214  dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2215 
2216  dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2217 
2218 #if __OS_HAS_AGP
2219  if (dev_priv->flags & RADEON_IS_AGP) {
2220  /* XXX turn off pcie gart */
2221  } else
2222 #endif
2223  {
2224  dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2225  /* if we have an offset set from userspace */
2226  if (!dev_priv->pcigart_offset_set) {
2227  DRM_ERROR("Need gart offset from userspace\n");
2228  r600_do_cleanup_cp(dev);
2229  return -EINVAL;
2230  }
2231 
2232  DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2233 
2234  dev_priv->gart_info.bus_addr =
2235  dev_priv->pcigart_offset + dev_priv->fb_location;
2236  dev_priv->gart_info.mapping.offset =
2237  dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2238  dev_priv->gart_info.mapping.size =
2239  dev_priv->gart_info.table_size;
2240 
2241  drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2242  if (!dev_priv->gart_info.mapping.handle) {
2243  DRM_ERROR("ioremap failed.\n");
2244  r600_do_cleanup_cp(dev);
2245  return -EINVAL;
2246  }
2247 
2248  dev_priv->gart_info.addr =
2249  dev_priv->gart_info.mapping.handle;
2250 
2251  DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2252  dev_priv->gart_info.addr,
2253  dev_priv->pcigart_offset);
2254 
2255  if (!r600_page_table_init(dev)) {
2256  DRM_ERROR("Failed to init GART table\n");
2257  r600_do_cleanup_cp(dev);
2258  return -EINVAL;
2259  }
2260 
2261  if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2262  r700_vm_init(dev);
2263  else
2264  r600_vm_init(dev);
2265  }
2266 
2267  if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2268  int err = r600_cp_init_microcode(dev_priv);
2269  if (err) {
2270  DRM_ERROR("Failed to load firmware!\n");
2271  r600_do_cleanup_cp(dev);
2272  return err;
2273  }
2274  }
2275  if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2276  r700_cp_load_microcode(dev_priv);
2277  else
2278  r600_cp_load_microcode(dev_priv);
2279 
2280  r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2281 
2282  dev_priv->last_buf = 0;
2283 
2284  r600_do_engine_reset(dev);
2285  r600_test_writeback(dev_priv);
2286 
2287  return 0;
2288 }
2289 
2290 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2291 {
2292  drm_radeon_private_t *dev_priv = dev->dev_private;
2293 
2294  DRM_DEBUG("\n");
2295  if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2296  r700_vm_init(dev);
2297  r700_cp_load_microcode(dev_priv);
2298  } else {
2299  r600_vm_init(dev);
2300  r600_cp_load_microcode(dev_priv);
2301  }
2302  r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2303  r600_do_engine_reset(dev);
2304 
2305  return 0;
2306 }
2307 
2308 /* Wait for the CP to go idle.
2309  */
2310 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2311 {
2312  RING_LOCALS;
2313  DRM_DEBUG("\n");
2314 
2315  BEGIN_RING(5);
2316  OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2317  OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2318  /* wait for 3D idle clean */
2319  OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2320  OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2321  OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2322 
2323  ADVANCE_RING();
2324  COMMIT_RING();
2325 
2326  return r600_do_wait_for_idle(dev_priv);
2327 }
2328 
2329 /* Start the Command Processor.
2330  */
2331 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2332 {
2333  u32 cp_me;
2334  RING_LOCALS;
2335  DRM_DEBUG("\n");
2336 
2337  BEGIN_RING(7);
2338  OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2339  OUT_RING(0x00000001);
2340  if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2341  OUT_RING(0x00000003);
2342  else
2343  OUT_RING(0x00000000);
2344  OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2345  OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2346  OUT_RING(0x00000000);
2347  OUT_RING(0x00000000);
2348  ADVANCE_RING();
2349  COMMIT_RING();
2350 
2351  /* set the mux and reset the halt bit */
2352  cp_me = 0xff;
2353  RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2354 
2355  dev_priv->cp_running = 1;
2356 
2357 }
2358 
2359 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2360 {
2361  u32 cur_read_ptr;
2362  DRM_DEBUG("\n");
2363 
2364  cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2365  RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2366  SET_RING_HEAD(dev_priv, cur_read_ptr);
2367  dev_priv->ring.tail = cur_read_ptr;
2368 }
2369 
2370 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2371 {
2372  uint32_t cp_me;
2373 
2374  DRM_DEBUG("\n");
2375 
2376  cp_me = 0xff | R600_CP_ME_HALT;
2377 
2378  RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2379 
2380  dev_priv->cp_running = 0;
2381 }
2382 
2383 int r600_cp_dispatch_indirect(struct drm_device *dev,
2384  struct drm_buf *buf, int start, int end)
2385 {
2386  drm_radeon_private_t *dev_priv = dev->dev_private;
2387  RING_LOCALS;
2388 
2389  if (start != end) {
2390  unsigned long offset = (dev_priv->gart_buffers_offset
2391  + buf->offset + start);
2392  int dwords = (end - start + 3) / sizeof(u32);
2393 
2394  DRM_DEBUG("dwords:%d\n", dwords);
2395  DRM_DEBUG("offset 0x%lx\n", offset);
2396 
2397 
2398  /* Indirect buffer data must be a multiple of 16 dwords.
2399  * pad the data with a Type-2 CP packet.
2400  */
2401  while (dwords & 0xf) {
2402  u32 *data = (u32 *)
2403  ((char *)dev->agp_buffer_map->handle
2404  + buf->offset + start);
2405  data[dwords++] = RADEON_CP_PACKET2;
2406  }
2407 
2408  /* Fire off the indirect buffer */
2409  BEGIN_RING(4);
2410  OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2411  OUT_RING((offset & 0xfffffffc));
2412  OUT_RING((upper_32_bits(offset) & 0xff));
2413  OUT_RING(dwords);
2414  ADVANCE_RING();
2415  }
2416 
2417  return 0;
2418 }
2419 
2420 void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
2421 {
2422  drm_radeon_private_t *dev_priv = dev->dev_private;
2423  struct drm_master *master = file_priv->master;
2424  struct drm_radeon_master_private *master_priv = master->driver_priv;
2425  drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2426  int nbox = sarea_priv->nbox;
2427  struct drm_clip_rect *pbox = sarea_priv->boxes;
2428  int i, cpp, src_pitch, dst_pitch;
2429  uint64_t src, dst;
2430  RING_LOCALS;
2431  DRM_DEBUG("\n");
2432 
2433  if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2434  cpp = 4;
2435  else
2436  cpp = 2;
2437 
2438  if (sarea_priv->pfCurrentPage == 0) {
2439  src_pitch = dev_priv->back_pitch;
2440  dst_pitch = dev_priv->front_pitch;
2441  src = dev_priv->back_offset + dev_priv->fb_location;
2442  dst = dev_priv->front_offset + dev_priv->fb_location;
2443  } else {
2444  src_pitch = dev_priv->front_pitch;
2445  dst_pitch = dev_priv->back_pitch;
2446  src = dev_priv->front_offset + dev_priv->fb_location;
2447  dst = dev_priv->back_offset + dev_priv->fb_location;
2448  }
2449 
2450  if (r600_prepare_blit_copy(dev, file_priv)) {
2451  DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2452  return;
2453  }
2454  for (i = 0; i < nbox; i++) {
2455  int x = pbox[i].x1;
2456  int y = pbox[i].y1;
2457  int w = pbox[i].x2 - x;
2458  int h = pbox[i].y2 - y;
2459 
2460  DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2461 
2462  r600_blit_swap(dev,
2463  src, dst,
2464  x, y, x, y, w, h,
2465  src_pitch, dst_pitch, cpp);
2466  }
2467  r600_done_blit_copy(dev);
2468 
2469  /* Increment the frame counter. The client-side 3D driver must
2470  * throttle the framerate by waiting for this value before
2471  * performing the swapbuffer ioctl.
2472  */
2473  sarea_priv->last_frame++;
2474 
2475  BEGIN_RING(3);
2476  R600_FRAME_AGE(sarea_priv->last_frame);
2477  ADVANCE_RING();
2478 }
2479 
2480 int r600_cp_dispatch_texture(struct drm_device *dev,
2481  struct drm_file *file_priv,
2482  drm_radeon_texture_t *tex,
2483  drm_radeon_tex_image_t *image)
2484 {
2485  drm_radeon_private_t *dev_priv = dev->dev_private;
2486  struct drm_buf *buf;
2487  u32 *buffer;
2488  const u8 __user *data;
2489  int size, pass_size;
2490  u64 src_offset, dst_offset;
2491 
2492  if (!radeon_check_offset(dev_priv, tex->offset)) {
2493  DRM_ERROR("Invalid destination offset\n");
2494  return -EINVAL;
2495  }
2496 
2497  /* this might fail for zero-sized uploads - are those illegal? */
2498  if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2499  DRM_ERROR("Invalid final destination offset\n");
2500  return -EINVAL;
2501  }
2502 
2503  size = tex->height * tex->pitch;
2504 
2505  if (size == 0)
2506  return 0;
2507 
2508  dst_offset = tex->offset;
2509 
2510  if (r600_prepare_blit_copy(dev, file_priv)) {
2511  DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2512  return -EAGAIN;
2513  }
2514  do {
2515  data = (const u8 __user *)image->data;
2516  pass_size = size;
2517 
2518  buf = radeon_freelist_get(dev);
2519  if (!buf) {
2520  DRM_DEBUG("EAGAIN\n");
2521  if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2522  return -EFAULT;
2523  return -EAGAIN;
2524  }
2525 
2526  if (pass_size > buf->total)
2527  pass_size = buf->total;
2528 
2529  /* Dispatch the indirect buffer.
2530  */
2531  buffer =
2532  (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2533 
2534  if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2535  DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2536  return -EFAULT;
2537  }
2538 
2539  buf->file_priv = file_priv;
2540  buf->used = pass_size;
2541  src_offset = dev_priv->gart_buffers_offset + buf->offset;
2542 
2543  r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2544 
2545  radeon_cp_discard_buffer(dev, file_priv->master, buf);
2546 
2547  /* Update the input parameters for next time */
2548  image->data = (const u8 __user *)image->data + pass_size;
2549  dst_offset += pass_size;
2550  size -= pass_size;
2551  } while (size > 0);
2552  r600_done_blit_copy(dev);
2553 
2554  return 0;
2555 }
2556 
2557 /*
2558  * Legacy cs ioctl
2559  */
2560 static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
2561 {
2562  /* FIXME: check if wrap affect last reported wrap & sequence */
2563  radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
2564  if (!radeon->cs_id_scnt) {
2565  /* increment wrap counter */
2566  radeon->cs_id_wcnt += 0x01000000;
2567  /* valid sequence counter start at 1 */
2568  radeon->cs_id_scnt = 1;
2569  }
2570  return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
2571 }
2572 
2573 static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2574 {
2575  RING_LOCALS;
2576 
2577  *id = radeon_cs_id_get(dev_priv);
2578 
2579  /* SCRATCH 2 */
2580  BEGIN_RING(3);
2581  R600_CLEAR_AGE(*id);
2582  ADVANCE_RING();
2583  COMMIT_RING();
2584 }
2585 
2586 static int r600_ib_get(struct drm_device *dev,
2587  struct drm_file *fpriv,
2588  struct drm_buf **buffer)
2589 {
2590  struct drm_buf *buf;
2591 
2592  *buffer = NULL;
2593  buf = radeon_freelist_get(dev);
2594  if (!buf) {
2595  return -EBUSY;
2596  }
2597  buf->file_priv = fpriv;
2598  *buffer = buf;
2599  return 0;
2600 }
2601 
2602 static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
2603  struct drm_file *fpriv, int l, int r)
2604 {
2605  drm_radeon_private_t *dev_priv = dev->dev_private;
2606 
2607  if (buf) {
2608  if (!r)
2609  r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
2610  radeon_cp_discard_buffer(dev, fpriv->master, buf);
2611  COMMIT_RING();
2612  }
2613 }
2614 
2615 int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
2616 {
2617  struct drm_radeon_private *dev_priv = dev->dev_private;
2618  struct drm_radeon_cs *cs = data;
2619  struct drm_buf *buf;
2620  unsigned family;
2621  int l, r = 0;
2622  u32 *ib, cs_id = 0;
2623 
2624  if (dev_priv == NULL) {
2625  DRM_ERROR("called with no initialization\n");
2626  return -EINVAL;
2627  }
2628  family = dev_priv->flags & RADEON_FAMILY_MASK;
2629  if (family < CHIP_R600) {
2630  DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2631  return -EINVAL;
2632  }
2633  mutex_lock(&dev_priv->cs_mutex);
2634  /* get ib */
2635  r = r600_ib_get(dev, fpriv, &buf);
2636  if (r) {
2637  DRM_ERROR("ib_get failed\n");
2638  goto out;
2639  }
2640  ib = dev->agp_buffer_map->handle + buf->offset;
2641  /* now parse command stream */
2642  r = r600_cs_legacy(dev, data, fpriv, family, ib, &l);
2643  if (r) {
2644  goto out;
2645  }
2646 
2647 out:
2648  r600_ib_free(dev, buf, fpriv, l, r);
2649  /* emit cs id sequence */
2650  r600_cs_id_emit(dev_priv, &cs_id);
2651  cs->cs_id = cs_id;
2652  mutex_unlock(&dev_priv->cs_mutex);
2653  return r;
2654 }
2655 
2656 void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)
2657 {
2658  struct drm_radeon_private *dev_priv = dev->dev_private;
2659 
2660  *npipes = dev_priv->r600_npipes;
2661  *nbanks = dev_priv->r600_nbanks;
2662  *group_size = dev_priv->r600_group_size;
2663 }
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