45 static void radeon_legacy_rmx_mode_set(
struct drm_crtc *
crtc,
53 bool hscale =
true, vscale =
true;
58 u32 scale,
inc, crtc_more_cntl;
59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
80 fp_crtc_h_total_disp = ((((mode->
crtc_htotal / 8) - 1) & 0x3ff)
88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
89 | ((hsync_wid & 0x3f) << 16)
94 fp_crtc_v_total_disp = (((mode->
crtc_vtotal - 1) & 0xffff)
102 | ((vsync_wid & 0x1f) << 16)
107 fp_horz_vert_active = 0;
129 fp_horz_stretch |= ((xres/8-1) << 16);
137 ((native_mode->
hdisplay/8-1) << 16));
141 fp_vert_stretch |= ((yres-1) << 12);
153 fp_horz_stretch |= ((xres/8-1) << 16);
154 fp_vert_stretch |= ((yres-1) << 12);
160 if (blank_width > 110)
163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
171 | ((hsync_wid & 0x3f) << 16)
184 | ((vsync_wid & 0x1f) << 16)
189 fp_horz_vert_active = (((native_mode->
vdisplay) & 0xfff) |
190 (((native_mode->
hdisplay / 8) & 0x1ff) << 16));
194 fp_horz_stretch |= ((xres/8-1) << 16);
195 fp_vert_stretch |= ((yres-1) << 12);
209 static void radeon_pll_wait_for_read_update_complete(
struct drm_device *dev)
224 static void radeon_pll_write_update(
struct drm_device *dev)
235 static void radeon_pll2_wait_for_read_update_complete(
struct drm_device *dev)
251 static void radeon_pll2_write_update(
struct drm_device *dev)
265 unsigned int vcoFreq;
270 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
276 if (vcoFreq >= 30000)
281 else if (vcoFreq >= 18000)
293 static void radeon_crtc_dpms(
struct drm_crtc *crtc,
int mode)
369 int x,
int y,
int atomic)
376 struct drm_gem_object *obj;
379 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
383 uint32_t gen_cntl_reg, gen_cntl_val;
388 if (!atomic && !crtc->
fb) {
389 DRM_DEBUG_KMS(
"No FB bound\n");
399 target_fb = crtc->
fb;
423 obj = radeon_fb->
obj;
432 radeon_bo_unreserve(rbo);
436 radeon_bo_unreserve(rbo);
438 DRM_ERROR(
"trying to scanout microtiled buffer\n");
446 crtc_offset_cntl = 0;
452 crtc_pitch |= crtc_pitch << 16;
471 if (tiling_flags & RADEON_TILING_MACRO) {
473 crtc_tile_x0_y0 = x | (y << 16);
477 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
478 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
479 crtc_offset_cntl |= (y % 16);
482 int offset = y * pitch_pixels +
x;
510 gen_cntl_val =
RREG32(gen_cntl_reg);
511 gen_cntl_val &= ~(0xf << 8);
512 gen_cntl_val |= (format << 8);
514 WREG32(gen_cntl_reg, gen_cntl_val);
516 crtc_offset = (
u32)base;
530 if (!atomic && fb && fb != crtc->
fb) {
537 radeon_bo_unreserve(rbo);
564 if (encoder->
crtc == crtc) {
568 DRM_INFO(
"crtc %d is connected to a TV\n", radeon_crtc->
crtc_id);
574 switch (crtc->
fb->bits_per_pixel) {
594 crtc_h_total_disp = ((((mode->
crtc_htotal / 8) - 1) & 0x3ff)
602 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
603 | ((hsync_wid & 0x3f) << 16)
609 crtc_v_total_disp = (((mode->
crtc_vtotal - 1) & 0xffff)
617 | ((vsync_wid & 0x1f) << 16)
628 crtc2_gen_cntl |= ((format << 8)
694 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
695 &crtc_v_sync_strt_wid);
717 bool use_bios_divs =
false;
728 } *post_div, post_divs[] = {
746 pll = &rdev->
clock.p2pll;
748 pll = &rdev->
clock.p1pll;
752 if (mode->
clock > 200000)
758 if (encoder->
crtc == crtc) {
778 use_bios_divs =
true;
789 if (!use_bios_divs) {
791 &freq, &feedback_div, &frac_fb_div,
792 &reference_div, &post_divider);
794 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
795 if (post_div->divider == post_divider)
799 if (!post_div->divider)
800 post_div = &post_divs[0];
802 DRM_DEBUG_KMS(
"dc=%u, fd=%d, rd=%d, pd=%d\n",
808 pll_ref_div = reference_div;
809 #if defined(__powerpc__) && (0)
811 if (
info->MacModel == RADEON_MAC_IBOOK)
812 pll_fb_post_div = 0x000600ad;
815 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
817 htotal_cntl = mode->
htotal & 0x7;
823 pll_fb_post_div & 0x7ff);
832 &pll_ref_div, &pll_fb_post_div,
860 radeon_pll2_write_update(dev);
861 radeon_pll2_wait_for_read_update_complete(dev);
871 DRM_DEBUG_KMS(
"Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
872 (
unsigned)pll_ref_div,
873 (
unsigned)pll_fb_post_div,
874 (
unsigned)htotal_cntl,
876 DRM_DEBUG_KMS(
"Wrote2: rd=%u, fd=%u, pd=%u\n",
879 (
unsigned)((pll_fb_post_div &
896 &pll_fb_post_div, &pixclks_cntl);
950 ~R300_PPLL_REF_DIV_ACC_MASK);
955 ~RADEON_PPLL_REF_DIV_MASK);
965 radeon_pll_write_update(dev);
966 radeon_pll_wait_for_read_update_complete(dev);
977 DRM_DEBUG_KMS(
"Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
980 (
unsigned)htotal_cntl,
982 DRM_DEBUG_KMS(
"Wrote: rd=%d, fd=%d, pd=%d\n",
983 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
998 static bool radeon_crtc_mode_fixup(
struct drm_crtc *crtc,
1007 static int radeon_crtc_mode_set(
struct drm_crtc *crtc,
1016 radeon_set_crtc_timing(crtc, adjusted_mode);
1017 radeon_set_pll(crtc, adjusted_mode);
1018 radeon_overscan_setup(crtc, adjusted_mode);
1019 if (radeon_crtc->
crtc_id == 0) {
1020 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1026 DRM_ERROR(
"Mode need scaling but only first crtc can do that.\n");
1032 static void radeon_crtc_prepare(
struct drm_crtc *crtc)
1064 .dpms = radeon_crtc_dpms,
1065 .mode_fixup = radeon_crtc_mode_fixup,
1066 .mode_set = radeon_crtc_mode_set,
1069 .prepare = radeon_crtc_prepare,
1070 .commit = radeon_crtc_commit,
1076 struct radeon_crtc *radeon_crtc)
1078 if (radeon_crtc->
crtc_id == 1)
1080 drm_crtc_helper_add(&radeon_crtc->
base, &legacy_helper_funcs);