Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
rme96.c
Go to the documentation of this file.
1 /*
2  * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3  * interfaces
4  *
5  * Copyright (c) 2000, 2001 Anders Torger <[email protected]>
6  *
7  * Thanks to Henk Hesselink <[email protected]> for the analog volume control
8  * code.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23  *
24  */
25 
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/module.h>
31 
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/asoundef.h>
38 #include <sound/initval.h>
39 
40 #include <asm/io.h>
41 
42 /* note, two last pcis should be equal, it is not a bug */
43 
44 MODULE_AUTHOR("Anders Torger <[email protected]>");
45 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
46  "Digi96/8 PAD");
47 MODULE_LICENSE("GPL");
48 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
49  "{RME,Digi96/8},"
50  "{RME,Digi96/8 PRO},"
51  "{RME,Digi96/8 PST},"
52  "{RME,Digi96/8 PAD}}");
53 
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
56 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
57 
58 module_param_array(index, int, NULL, 0444);
59 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
60 module_param_array(id, charp, NULL, 0444);
61 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
62 module_param_array(enable, bool, NULL, 0444);
63 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
64 
65 /*
66  * Defines for RME Digi96 series, from internal RME reference documents
67  * dated 12.01.00
68  */
69 
70 #define RME96_SPDIF_NCHANNELS 2
71 
72 /* Playback and capture buffer size */
73 #define RME96_BUFFER_SIZE 0x10000
74 
75 /* IO area size */
76 #define RME96_IO_SIZE 0x60000
77 
78 /* IO area offsets */
79 #define RME96_IO_PLAY_BUFFER 0x0
80 #define RME96_IO_REC_BUFFER 0x10000
81 #define RME96_IO_CONTROL_REGISTER 0x20000
82 #define RME96_IO_ADDITIONAL_REG 0x20004
83 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
84 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
85 #define RME96_IO_SET_PLAY_POS 0x40000
86 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
87 #define RME96_IO_SET_REC_POS 0x50000
88 #define RME96_IO_RESET_REC_POS 0x5FFFC
89 #define RME96_IO_GET_PLAY_POS 0x20000
90 #define RME96_IO_GET_REC_POS 0x30000
91 
92 /* Write control register bits */
93 #define RME96_WCR_START (1 << 0)
94 #define RME96_WCR_START_2 (1 << 1)
95 #define RME96_WCR_GAIN_0 (1 << 2)
96 #define RME96_WCR_GAIN_1 (1 << 3)
97 #define RME96_WCR_MODE24 (1 << 4)
98 #define RME96_WCR_MODE24_2 (1 << 5)
99 #define RME96_WCR_BM (1 << 6)
100 #define RME96_WCR_BM_2 (1 << 7)
101 #define RME96_WCR_ADAT (1 << 8)
102 #define RME96_WCR_FREQ_0 (1 << 9)
103 #define RME96_WCR_FREQ_1 (1 << 10)
104 #define RME96_WCR_DS (1 << 11)
105 #define RME96_WCR_PRO (1 << 12)
106 #define RME96_WCR_EMP (1 << 13)
107 #define RME96_WCR_SEL (1 << 14)
108 #define RME96_WCR_MASTER (1 << 15)
109 #define RME96_WCR_PD (1 << 16)
110 #define RME96_WCR_INP_0 (1 << 17)
111 #define RME96_WCR_INP_1 (1 << 18)
112 #define RME96_WCR_THRU_0 (1 << 19)
113 #define RME96_WCR_THRU_1 (1 << 20)
114 #define RME96_WCR_THRU_2 (1 << 21)
115 #define RME96_WCR_THRU_3 (1 << 22)
116 #define RME96_WCR_THRU_4 (1 << 23)
117 #define RME96_WCR_THRU_5 (1 << 24)
118 #define RME96_WCR_THRU_6 (1 << 25)
119 #define RME96_WCR_THRU_7 (1 << 26)
120 #define RME96_WCR_DOLBY (1 << 27)
121 #define RME96_WCR_MONITOR_0 (1 << 28)
122 #define RME96_WCR_MONITOR_1 (1 << 29)
123 #define RME96_WCR_ISEL (1 << 30)
124 #define RME96_WCR_IDIS (1 << 31)
125 
126 #define RME96_WCR_BITPOS_GAIN_0 2
127 #define RME96_WCR_BITPOS_GAIN_1 3
128 #define RME96_WCR_BITPOS_FREQ_0 9
129 #define RME96_WCR_BITPOS_FREQ_1 10
130 #define RME96_WCR_BITPOS_INP_0 17
131 #define RME96_WCR_BITPOS_INP_1 18
132 #define RME96_WCR_BITPOS_MONITOR_0 28
133 #define RME96_WCR_BITPOS_MONITOR_1 29
134 
135 /* Read control register bits */
136 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
137 #define RME96_RCR_IRQ_2 (1 << 16)
138 #define RME96_RCR_T_OUT (1 << 17)
139 #define RME96_RCR_DEV_ID_0 (1 << 21)
140 #define RME96_RCR_DEV_ID_1 (1 << 22)
141 #define RME96_RCR_LOCK (1 << 23)
142 #define RME96_RCR_VERF (1 << 26)
143 #define RME96_RCR_F0 (1 << 27)
144 #define RME96_RCR_F1 (1 << 28)
145 #define RME96_RCR_F2 (1 << 29)
146 #define RME96_RCR_AUTOSYNC (1 << 30)
147 #define RME96_RCR_IRQ (1 << 31)
148 
149 #define RME96_RCR_BITPOS_F0 27
150 #define RME96_RCR_BITPOS_F1 28
151 #define RME96_RCR_BITPOS_F2 29
152 
153 /* Additional register bits */
154 #define RME96_AR_WSEL (1 << 0)
155 #define RME96_AR_ANALOG (1 << 1)
156 #define RME96_AR_FREQPAD_0 (1 << 2)
157 #define RME96_AR_FREQPAD_1 (1 << 3)
158 #define RME96_AR_FREQPAD_2 (1 << 4)
159 #define RME96_AR_PD2 (1 << 5)
160 #define RME96_AR_DAC_EN (1 << 6)
161 #define RME96_AR_CLATCH (1 << 7)
162 #define RME96_AR_CCLK (1 << 8)
163 #define RME96_AR_CDATA (1 << 9)
164 
165 #define RME96_AR_BITPOS_F0 2
166 #define RME96_AR_BITPOS_F1 3
167 #define RME96_AR_BITPOS_F2 4
168 
169 /* Monitor tracks */
170 #define RME96_MONITOR_TRACKS_1_2 0
171 #define RME96_MONITOR_TRACKS_3_4 1
172 #define RME96_MONITOR_TRACKS_5_6 2
173 #define RME96_MONITOR_TRACKS_7_8 3
174 
175 /* Attenuation */
176 #define RME96_ATTENUATION_0 0
177 #define RME96_ATTENUATION_6 1
178 #define RME96_ATTENUATION_12 2
179 #define RME96_ATTENUATION_18 3
180 
181 /* Input types */
182 #define RME96_INPUT_OPTICAL 0
183 #define RME96_INPUT_COAXIAL 1
184 #define RME96_INPUT_INTERNAL 2
185 #define RME96_INPUT_XLR 3
186 #define RME96_INPUT_ANALOG 4
187 
188 /* Clock modes */
189 #define RME96_CLOCKMODE_SLAVE 0
190 #define RME96_CLOCKMODE_MASTER 1
191 #define RME96_CLOCKMODE_WORDCLOCK 2
192 
193 /* Block sizes in bytes */
194 #define RME96_SMALL_BLOCK_SIZE 2048
195 #define RME96_LARGE_BLOCK_SIZE 8192
196 
197 /* Volume control */
198 #define RME96_AD1852_VOL_BITS 14
199 #define RME96_AD1855_VOL_BITS 10
200 
201 
202 struct rme96 {
203  spinlock_t lock;
204  int irq;
205  unsigned long port;
206  void __iomem *iobase;
207 
208  u32 wcreg; /* cached write control register value */
209  u32 wcreg_spdif; /* S/PDIF setup */
210  u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
211  u32 rcreg; /* cached read control register value */
212  u32 areg; /* cached additional register value */
213  u16 vol[2]; /* cached volume of analog output */
214 
215  u8 rev; /* card revision number */
216 
217  struct snd_pcm_substream *playback_substream;
218  struct snd_pcm_substream *capture_substream;
219 
220  int playback_frlog; /* log2 of framesize */
221  int capture_frlog;
222 
223  size_t playback_periodsize; /* in bytes, zero if not used */
224  size_t capture_periodsize; /* in bytes, zero if not used */
225 
226  struct snd_card *card;
227  struct snd_pcm *spdif_pcm;
228  struct snd_pcm *adat_pcm;
229  struct pci_dev *pci;
230  struct snd_kcontrol *spdif_ctl;
231 };
232 
233 static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = {
234  { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
235  { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
236  { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
237  { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
238  { 0, }
239 };
240 
241 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
242 
243 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
244 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
245 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
246 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
247  (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
248 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
249 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
250  ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
251 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
252 
253 static int
254 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
255 
256 static int
257 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
258 
259 static int
260 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
261  int cmd);
262 
263 static int
264 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
265  int cmd);
266 
267 static snd_pcm_uframes_t
268 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
269 
270 static snd_pcm_uframes_t
271 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
272 
273 static void __devinit
274 snd_rme96_proc_init(struct rme96 *rme96);
275 
276 static int
277 snd_rme96_create_switches(struct snd_card *card,
278  struct rme96 *rme96);
279 
280 static int
281 snd_rme96_getinputtype(struct rme96 *rme96);
282 
283 static inline unsigned int
284 snd_rme96_playback_ptr(struct rme96 *rme96)
285 {
286  return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
287  & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
288 }
289 
290 static inline unsigned int
291 snd_rme96_capture_ptr(struct rme96 *rme96)
292 {
293  return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
294  & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
295 }
296 
297 static int
298 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
299  int channel, /* not used (interleaved data) */
300  snd_pcm_uframes_t pos,
301  snd_pcm_uframes_t count)
302 {
303  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
304  count <<= rme96->playback_frlog;
305  pos <<= rme96->playback_frlog;
306  memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
307  0, count);
308  return 0;
309 }
310 
311 static int
312 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
313  int channel, /* not used (interleaved data) */
314  snd_pcm_uframes_t pos,
315  void __user *src,
316  snd_pcm_uframes_t count)
317 {
318  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
319  count <<= rme96->playback_frlog;
320  pos <<= rme96->playback_frlog;
321  copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
322  count);
323  return 0;
324 }
325 
326 static int
327 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
328  int channel, /* not used (interleaved data) */
329  snd_pcm_uframes_t pos,
330  void __user *dst,
331  snd_pcm_uframes_t count)
332 {
333  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
334  count <<= rme96->capture_frlog;
335  pos <<= rme96->capture_frlog;
336  copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
337  count);
338  return 0;
339 }
340 
341 /*
342  * Digital output capabilities (S/PDIF)
343  */
344 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
345 {
346  .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
347  SNDRV_PCM_INFO_MMAP_VALID |
348  SNDRV_PCM_INFO_INTERLEAVED |
349  SNDRV_PCM_INFO_PAUSE),
350  .formats = (SNDRV_PCM_FMTBIT_S16_LE |
351  SNDRV_PCM_FMTBIT_S32_LE),
352  .rates = (SNDRV_PCM_RATE_32000 |
353  SNDRV_PCM_RATE_44100 |
354  SNDRV_PCM_RATE_48000 |
355  SNDRV_PCM_RATE_64000 |
356  SNDRV_PCM_RATE_88200 |
357  SNDRV_PCM_RATE_96000),
358  .rate_min = 32000,
359  .rate_max = 96000,
360  .channels_min = 2,
361  .channels_max = 2,
362  .buffer_bytes_max = RME96_BUFFER_SIZE,
363  .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
364  .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
365  .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
366  .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
367  .fifo_size = 0,
368 };
369 
370 /*
371  * Digital input capabilities (S/PDIF)
372  */
373 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
374 {
375  .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
376  SNDRV_PCM_INFO_MMAP_VALID |
377  SNDRV_PCM_INFO_INTERLEAVED |
378  SNDRV_PCM_INFO_PAUSE),
379  .formats = (SNDRV_PCM_FMTBIT_S16_LE |
380  SNDRV_PCM_FMTBIT_S32_LE),
381  .rates = (SNDRV_PCM_RATE_32000 |
382  SNDRV_PCM_RATE_44100 |
383  SNDRV_PCM_RATE_48000 |
384  SNDRV_PCM_RATE_64000 |
385  SNDRV_PCM_RATE_88200 |
386  SNDRV_PCM_RATE_96000),
387  .rate_min = 32000,
388  .rate_max = 96000,
389  .channels_min = 2,
390  .channels_max = 2,
391  .buffer_bytes_max = RME96_BUFFER_SIZE,
392  .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
393  .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
394  .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
395  .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
396  .fifo_size = 0,
397 };
398 
399 /*
400  * Digital output capabilities (ADAT)
401  */
402 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
403 {
404  .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
405  SNDRV_PCM_INFO_MMAP_VALID |
406  SNDRV_PCM_INFO_INTERLEAVED |
407  SNDRV_PCM_INFO_PAUSE),
408  .formats = (SNDRV_PCM_FMTBIT_S16_LE |
409  SNDRV_PCM_FMTBIT_S32_LE),
410  .rates = (SNDRV_PCM_RATE_44100 |
411  SNDRV_PCM_RATE_48000),
412  .rate_min = 44100,
413  .rate_max = 48000,
414  .channels_min = 8,
415  .channels_max = 8,
416  .buffer_bytes_max = RME96_BUFFER_SIZE,
417  .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
418  .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
419  .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
420  .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
421  .fifo_size = 0,
422 };
423 
424 /*
425  * Digital input capabilities (ADAT)
426  */
427 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
428 {
429  .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
430  SNDRV_PCM_INFO_MMAP_VALID |
431  SNDRV_PCM_INFO_INTERLEAVED |
432  SNDRV_PCM_INFO_PAUSE),
433  .formats = (SNDRV_PCM_FMTBIT_S16_LE |
434  SNDRV_PCM_FMTBIT_S32_LE),
435  .rates = (SNDRV_PCM_RATE_44100 |
436  SNDRV_PCM_RATE_48000),
437  .rate_min = 44100,
438  .rate_max = 48000,
439  .channels_min = 8,
440  .channels_max = 8,
441  .buffer_bytes_max = RME96_BUFFER_SIZE,
442  .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
443  .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
444  .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
445  .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
446  .fifo_size = 0,
447 };
448 
449 /*
450  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
451  * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
452  * on the falling edge of CCLK and be stable on the rising edge. The rising
453  * edge of CLATCH after the last data bit clocks in the whole data word.
454  * A fast processor could probably drive the SPI interface faster than the
455  * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
456  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
457  *
458  * NOTE: increased delay from 1 to 10, since there where problems setting
459  * the volume.
460  */
461 static void
462 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
463 {
464  int i;
465 
466  for (i = 0; i < 16; i++) {
467  if (val & 0x8000) {
468  rme96->areg |= RME96_AR_CDATA;
469  } else {
470  rme96->areg &= ~RME96_AR_CDATA;
471  }
472  rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
473  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
474  udelay(10);
475  rme96->areg |= RME96_AR_CCLK;
476  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
477  udelay(10);
478  val <<= 1;
479  }
480  rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
481  rme96->areg |= RME96_AR_CLATCH;
482  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
483  udelay(10);
484  rme96->areg &= ~RME96_AR_CLATCH;
485  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
486 }
487 
488 static void
489 snd_rme96_apply_dac_volume(struct rme96 *rme96)
490 {
491  if (RME96_DAC_IS_1852(rme96)) {
492  snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
493  snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
494  } else if (RME96_DAC_IS_1855(rme96)) {
495  snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
496  snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
497  }
498 }
499 
500 static void
501 snd_rme96_reset_dac(struct rme96 *rme96)
502 {
503  writel(rme96->wcreg | RME96_WCR_PD,
504  rme96->iobase + RME96_IO_CONTROL_REGISTER);
505  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
506 }
507 
508 static int
509 snd_rme96_getmontracks(struct rme96 *rme96)
510 {
511  return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
512  (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
513 }
514 
515 static int
516 snd_rme96_setmontracks(struct rme96 *rme96,
517  int montracks)
518 {
519  if (montracks & 1) {
520  rme96->wcreg |= RME96_WCR_MONITOR_0;
521  } else {
522  rme96->wcreg &= ~RME96_WCR_MONITOR_0;
523  }
524  if (montracks & 2) {
525  rme96->wcreg |= RME96_WCR_MONITOR_1;
526  } else {
527  rme96->wcreg &= ~RME96_WCR_MONITOR_1;
528  }
529  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
530  return 0;
531 }
532 
533 static int
534 snd_rme96_getattenuation(struct rme96 *rme96)
535 {
536  return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
537  (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
538 }
539 
540 static int
541 snd_rme96_setattenuation(struct rme96 *rme96,
542  int attenuation)
543 {
544  switch (attenuation) {
545  case 0:
546  rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
547  ~RME96_WCR_GAIN_1;
548  break;
549  case 1:
550  rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
551  ~RME96_WCR_GAIN_1;
552  break;
553  case 2:
554  rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
555  RME96_WCR_GAIN_1;
556  break;
557  case 3:
558  rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
559  RME96_WCR_GAIN_1;
560  break;
561  default:
562  return -EINVAL;
563  }
564  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
565  return 0;
566 }
567 
568 static int
569 snd_rme96_capture_getrate(struct rme96 *rme96,
570  int *is_adat)
571 {
572  int n, rate;
573 
574  *is_adat = 0;
575  if (rme96->areg & RME96_AR_ANALOG) {
576  /* Analog input, overrides S/PDIF setting */
577  n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
578  (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
579  switch (n) {
580  case 1:
581  rate = 32000;
582  break;
583  case 2:
584  rate = 44100;
585  break;
586  case 3:
587  rate = 48000;
588  break;
589  default:
590  return -1;
591  }
592  return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
593  }
594 
595  rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
596  if (rme96->rcreg & RME96_RCR_LOCK) {
597  /* ADAT rate */
598  *is_adat = 1;
599  if (rme96->rcreg & RME96_RCR_T_OUT) {
600  return 48000;
601  }
602  return 44100;
603  }
604 
605  if (rme96->rcreg & RME96_RCR_VERF) {
606  return -1;
607  }
608 
609  /* S/PDIF rate */
610  n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
611  (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
612  (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
613 
614  switch (n) {
615  case 0:
616  if (rme96->rcreg & RME96_RCR_T_OUT) {
617  return 64000;
618  }
619  return -1;
620  case 3: return 96000;
621  case 4: return 88200;
622  case 5: return 48000;
623  case 6: return 44100;
624  case 7: return 32000;
625  default:
626  break;
627  }
628  return -1;
629 }
630 
631 static int
632 snd_rme96_playback_getrate(struct rme96 *rme96)
633 {
634  int rate, dummy;
635 
636  if (!(rme96->wcreg & RME96_WCR_MASTER) &&
637  snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
638  (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
639  {
640  /* slave clock */
641  return rate;
642  }
643  rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
644  (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
645  switch (rate) {
646  case 1:
647  rate = 32000;
648  break;
649  case 2:
650  rate = 44100;
651  break;
652  case 3:
653  rate = 48000;
654  break;
655  default:
656  return -1;
657  }
658  return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
659 }
660 
661 static int
662 snd_rme96_playback_setrate(struct rme96 *rme96,
663  int rate)
664 {
665  int ds;
666 
667  ds = rme96->wcreg & RME96_WCR_DS;
668  switch (rate) {
669  case 32000:
670  rme96->wcreg &= ~RME96_WCR_DS;
671  rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
672  ~RME96_WCR_FREQ_1;
673  break;
674  case 44100:
675  rme96->wcreg &= ~RME96_WCR_DS;
676  rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
677  ~RME96_WCR_FREQ_0;
678  break;
679  case 48000:
680  rme96->wcreg &= ~RME96_WCR_DS;
681  rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
682  RME96_WCR_FREQ_1;
683  break;
684  case 64000:
685  rme96->wcreg |= RME96_WCR_DS;
686  rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
687  ~RME96_WCR_FREQ_1;
688  break;
689  case 88200:
690  rme96->wcreg |= RME96_WCR_DS;
691  rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
692  ~RME96_WCR_FREQ_0;
693  break;
694  case 96000:
695  rme96->wcreg |= RME96_WCR_DS;
696  rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
697  RME96_WCR_FREQ_1;
698  break;
699  default:
700  return -EINVAL;
701  }
702  if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
703  (ds && !(rme96->wcreg & RME96_WCR_DS)))
704  {
705  /* change to/from double-speed: reset the DAC (if available) */
706  snd_rme96_reset_dac(rme96);
707  } else {
708  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
709  }
710  return 0;
711 }
712 
713 static int
714 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
715  int rate)
716 {
717  switch (rate) {
718  case 32000:
719  rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
720  ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
721  break;
722  case 44100:
723  rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
724  RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
725  break;
726  case 48000:
727  rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
728  RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
729  break;
730  case 64000:
731  if (rme96->rev < 4) {
732  return -EINVAL;
733  }
734  rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
735  ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
736  break;
737  case 88200:
738  if (rme96->rev < 4) {
739  return -EINVAL;
740  }
741  rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
742  RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
743  break;
744  case 96000:
745  rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
746  RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
747  break;
748  default:
749  return -EINVAL;
750  }
751  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
752  return 0;
753 }
754 
755 static int
756 snd_rme96_setclockmode(struct rme96 *rme96,
757  int mode)
758 {
759  switch (mode) {
760  case RME96_CLOCKMODE_SLAVE:
761  /* AutoSync */
762  rme96->wcreg &= ~RME96_WCR_MASTER;
763  rme96->areg &= ~RME96_AR_WSEL;
764  break;
765  case RME96_CLOCKMODE_MASTER:
766  /* Internal */
767  rme96->wcreg |= RME96_WCR_MASTER;
768  rme96->areg &= ~RME96_AR_WSEL;
769  break;
770  case RME96_CLOCKMODE_WORDCLOCK:
771  /* Word clock is a master mode */
772  rme96->wcreg |= RME96_WCR_MASTER;
773  rme96->areg |= RME96_AR_WSEL;
774  break;
775  default:
776  return -EINVAL;
777  }
778  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
779  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
780  return 0;
781 }
782 
783 static int
784 snd_rme96_getclockmode(struct rme96 *rme96)
785 {
786  if (rme96->areg & RME96_AR_WSEL) {
787  return RME96_CLOCKMODE_WORDCLOCK;
788  }
789  return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
790  RME96_CLOCKMODE_SLAVE;
791 }
792 
793 static int
794 snd_rme96_setinputtype(struct rme96 *rme96,
795  int type)
796 {
797  int n;
798 
799  switch (type) {
800  case RME96_INPUT_OPTICAL:
801  rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
802  ~RME96_WCR_INP_1;
803  break;
804  case RME96_INPUT_COAXIAL:
805  rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
806  ~RME96_WCR_INP_1;
807  break;
808  case RME96_INPUT_INTERNAL:
809  rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
810  RME96_WCR_INP_1;
811  break;
812  case RME96_INPUT_XLR:
813  if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
814  rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
815  (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
816  rme96->rev > 4))
817  {
818  /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
819  return -EINVAL;
820  }
821  rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
822  RME96_WCR_INP_1;
823  break;
824  case RME96_INPUT_ANALOG:
825  if (!RME96_HAS_ANALOG_IN(rme96)) {
826  return -EINVAL;
827  }
828  rme96->areg |= RME96_AR_ANALOG;
829  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
830  if (rme96->rev < 4) {
831  /*
832  * Revision less than 004 does not support 64 and
833  * 88.2 kHz
834  */
835  if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
836  snd_rme96_capture_analog_setrate(rme96, 44100);
837  }
838  if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
839  snd_rme96_capture_analog_setrate(rme96, 32000);
840  }
841  }
842  return 0;
843  default:
844  return -EINVAL;
845  }
846  if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
847  rme96->areg &= ~RME96_AR_ANALOG;
848  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
849  }
850  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
851  return 0;
852 }
853 
854 static int
855 snd_rme96_getinputtype(struct rme96 *rme96)
856 {
857  if (rme96->areg & RME96_AR_ANALOG) {
858  return RME96_INPUT_ANALOG;
859  }
860  return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
861  (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
862 }
863 
864 static void
865 snd_rme96_setframelog(struct rme96 *rme96,
866  int n_channels,
867  int is_playback)
868 {
869  int frlog;
870 
871  if (n_channels == 2) {
872  frlog = 1;
873  } else {
874  /* assume 8 channels */
875  frlog = 3;
876  }
877  if (is_playback) {
878  frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
879  rme96->playback_frlog = frlog;
880  } else {
881  frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
882  rme96->capture_frlog = frlog;
883  }
884 }
885 
886 static int
887 snd_rme96_playback_setformat(struct rme96 *rme96,
888  int format)
889 {
890  switch (format) {
891  case SNDRV_PCM_FORMAT_S16_LE:
892  rme96->wcreg &= ~RME96_WCR_MODE24;
893  break;
894  case SNDRV_PCM_FORMAT_S32_LE:
895  rme96->wcreg |= RME96_WCR_MODE24;
896  break;
897  default:
898  return -EINVAL;
899  }
900  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
901  return 0;
902 }
903 
904 static int
905 snd_rme96_capture_setformat(struct rme96 *rme96,
906  int format)
907 {
908  switch (format) {
909  case SNDRV_PCM_FORMAT_S16_LE:
910  rme96->wcreg &= ~RME96_WCR_MODE24_2;
911  break;
912  case SNDRV_PCM_FORMAT_S32_LE:
913  rme96->wcreg |= RME96_WCR_MODE24_2;
914  break;
915  default:
916  return -EINVAL;
917  }
918  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
919  return 0;
920 }
921 
922 static void
923 snd_rme96_set_period_properties(struct rme96 *rme96,
924  size_t period_bytes)
925 {
926  switch (period_bytes) {
927  case RME96_LARGE_BLOCK_SIZE:
928  rme96->wcreg &= ~RME96_WCR_ISEL;
929  break;
930  case RME96_SMALL_BLOCK_SIZE:
931  rme96->wcreg |= RME96_WCR_ISEL;
932  break;
933  default:
934  snd_BUG();
935  break;
936  }
937  rme96->wcreg &= ~RME96_WCR_IDIS;
938  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
939 }
940 
941 static int
942 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
943  struct snd_pcm_hw_params *params)
944 {
945  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
946  struct snd_pcm_runtime *runtime = substream->runtime;
947  int err, rate, dummy;
948 
949  runtime->dma_area = (void __force *)(rme96->iobase +
950  RME96_IO_PLAY_BUFFER);
951  runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
952  runtime->dma_bytes = RME96_BUFFER_SIZE;
953 
954  spin_lock_irq(&rme96->lock);
955  if (!(rme96->wcreg & RME96_WCR_MASTER) &&
956  snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
957  (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
958  {
959  /* slave clock */
960  if ((int)params_rate(params) != rate) {
961  spin_unlock_irq(&rme96->lock);
962  return -EIO;
963  }
964  } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
965  spin_unlock_irq(&rme96->lock);
966  return err;
967  }
968  if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
969  spin_unlock_irq(&rme96->lock);
970  return err;
971  }
972  snd_rme96_setframelog(rme96, params_channels(params), 1);
973  if (rme96->capture_periodsize != 0) {
974  if (params_period_size(params) << rme96->playback_frlog !=
975  rme96->capture_periodsize)
976  {
977  spin_unlock_irq(&rme96->lock);
978  return -EBUSY;
979  }
980  }
981  rme96->playback_periodsize =
982  params_period_size(params) << rme96->playback_frlog;
983  snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
984  /* S/PDIF setup */
985  if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
986  rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
987  writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
988  }
989  spin_unlock_irq(&rme96->lock);
990 
991  return 0;
992 }
993 
994 static int
995 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
996  struct snd_pcm_hw_params *params)
997 {
998  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
999  struct snd_pcm_runtime *runtime = substream->runtime;
1000  int err, isadat, rate;
1001 
1002  runtime->dma_area = (void __force *)(rme96->iobase +
1003  RME96_IO_REC_BUFFER);
1004  runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1005  runtime->dma_bytes = RME96_BUFFER_SIZE;
1006 
1007  spin_lock_irq(&rme96->lock);
1008  if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1009  spin_unlock_irq(&rme96->lock);
1010  return err;
1011  }
1012  if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1013  if ((err = snd_rme96_capture_analog_setrate(rme96,
1014  params_rate(params))) < 0)
1015  {
1016  spin_unlock_irq(&rme96->lock);
1017  return err;
1018  }
1019  } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1020  if ((int)params_rate(params) != rate) {
1021  spin_unlock_irq(&rme96->lock);
1022  return -EIO;
1023  }
1024  if ((isadat && runtime->hw.channels_min == 2) ||
1025  (!isadat && runtime->hw.channels_min == 8))
1026  {
1027  spin_unlock_irq(&rme96->lock);
1028  return -EIO;
1029  }
1030  }
1031  snd_rme96_setframelog(rme96, params_channels(params), 0);
1032  if (rme96->playback_periodsize != 0) {
1033  if (params_period_size(params) << rme96->capture_frlog !=
1034  rme96->playback_periodsize)
1035  {
1036  spin_unlock_irq(&rme96->lock);
1037  return -EBUSY;
1038  }
1039  }
1040  rme96->capture_periodsize =
1041  params_period_size(params) << rme96->capture_frlog;
1042  snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1043  spin_unlock_irq(&rme96->lock);
1044 
1045  return 0;
1046 }
1047 
1048 static void
1049 snd_rme96_playback_start(struct rme96 *rme96,
1050  int from_pause)
1051 {
1052  if (!from_pause) {
1053  writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1054  }
1055 
1056  rme96->wcreg |= RME96_WCR_START;
1057  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1058 }
1059 
1060 static void
1061 snd_rme96_capture_start(struct rme96 *rme96,
1062  int from_pause)
1063 {
1064  if (!from_pause) {
1065  writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1066  }
1067 
1068  rme96->wcreg |= RME96_WCR_START_2;
1069  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1070 }
1071 
1072 static void
1073 snd_rme96_playback_stop(struct rme96 *rme96)
1074 {
1075  /*
1076  * Check if there is an unconfirmed IRQ, if so confirm it, or else
1077  * the hardware will not stop generating interrupts
1078  */
1079  rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1080  if (rme96->rcreg & RME96_RCR_IRQ) {
1081  writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1082  }
1083  rme96->wcreg &= ~RME96_WCR_START;
1084  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1085 }
1086 
1087 static void
1088 snd_rme96_capture_stop(struct rme96 *rme96)
1089 {
1090  rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1091  if (rme96->rcreg & RME96_RCR_IRQ_2) {
1092  writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1093  }
1094  rme96->wcreg &= ~RME96_WCR_START_2;
1095  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1096 }
1097 
1098 static irqreturn_t
1099 snd_rme96_interrupt(int irq,
1100  void *dev_id)
1101 {
1102  struct rme96 *rme96 = (struct rme96 *)dev_id;
1103 
1104  rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1105  /* fastpath out, to ease interrupt sharing */
1106  if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1107  (rme96->rcreg & RME96_RCR_IRQ_2)))
1108  {
1109  return IRQ_NONE;
1110  }
1111 
1112  if (rme96->rcreg & RME96_RCR_IRQ) {
1113  /* playback */
1114  snd_pcm_period_elapsed(rme96->playback_substream);
1115  writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1116  }
1117  if (rme96->rcreg & RME96_RCR_IRQ_2) {
1118  /* capture */
1119  snd_pcm_period_elapsed(rme96->capture_substream);
1120  writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1121  }
1122  return IRQ_HANDLED;
1123 }
1124 
1125 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1126 
1127 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1128  .count = ARRAY_SIZE(period_bytes),
1129  .list = period_bytes,
1130  .mask = 0
1131 };
1132 
1133 static void
1134 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1135  struct snd_pcm_runtime *runtime)
1136 {
1137  unsigned int size;
1138 
1139  snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1140  RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1141  if ((size = rme96->playback_periodsize) != 0 ||
1142  (size = rme96->capture_periodsize) != 0)
1143  snd_pcm_hw_constraint_minmax(runtime,
1144  SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1145  size, size);
1146  else
1147  snd_pcm_hw_constraint_list(runtime, 0,
1148  SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1149  &hw_constraints_period_bytes);
1150 }
1151 
1152 static int
1153 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1154 {
1155  int rate, dummy;
1156  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1157  struct snd_pcm_runtime *runtime = substream->runtime;
1158 
1159  spin_lock_irq(&rme96->lock);
1160  if (rme96->playback_substream != NULL) {
1161  spin_unlock_irq(&rme96->lock);
1162  return -EBUSY;
1163  }
1164  rme96->wcreg &= ~RME96_WCR_ADAT;
1165  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1166  rme96->playback_substream = substream;
1167  spin_unlock_irq(&rme96->lock);
1168 
1169  runtime->hw = snd_rme96_playback_spdif_info;
1170  if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1171  snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1172  (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1173  {
1174  /* slave clock */
1175  runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1176  runtime->hw.rate_min = rate;
1177  runtime->hw.rate_max = rate;
1178  }
1179  rme96_set_buffer_size_constraint(rme96, runtime);
1180 
1181  rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1182  rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1183  snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1184  SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1185  return 0;
1186 }
1187 
1188 static int
1189 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1190 {
1191  int isadat, rate;
1192  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1193  struct snd_pcm_runtime *runtime = substream->runtime;
1194 
1195  runtime->hw = snd_rme96_capture_spdif_info;
1196  if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1197  (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1198  {
1199  if (isadat) {
1200  return -EIO;
1201  }
1202  runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1203  runtime->hw.rate_min = rate;
1204  runtime->hw.rate_max = rate;
1205  }
1206 
1207  spin_lock_irq(&rme96->lock);
1208  if (rme96->capture_substream != NULL) {
1209  spin_unlock_irq(&rme96->lock);
1210  return -EBUSY;
1211  }
1212  rme96->capture_substream = substream;
1213  spin_unlock_irq(&rme96->lock);
1214 
1215  rme96_set_buffer_size_constraint(rme96, runtime);
1216  return 0;
1217 }
1218 
1219 static int
1220 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1221 {
1222  int rate, dummy;
1223  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1224  struct snd_pcm_runtime *runtime = substream->runtime;
1225 
1226  spin_lock_irq(&rme96->lock);
1227  if (rme96->playback_substream != NULL) {
1228  spin_unlock_irq(&rme96->lock);
1229  return -EBUSY;
1230  }
1231  rme96->wcreg |= RME96_WCR_ADAT;
1232  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1233  rme96->playback_substream = substream;
1234  spin_unlock_irq(&rme96->lock);
1235 
1236  runtime->hw = snd_rme96_playback_adat_info;
1237  if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1238  snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1239  (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1240  {
1241  /* slave clock */
1242  runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1243  runtime->hw.rate_min = rate;
1244  runtime->hw.rate_max = rate;
1245  }
1246  rme96_set_buffer_size_constraint(rme96, runtime);
1247  return 0;
1248 }
1249 
1250 static int
1251 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1252 {
1253  int isadat, rate;
1254  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1255  struct snd_pcm_runtime *runtime = substream->runtime;
1256 
1257  runtime->hw = snd_rme96_capture_adat_info;
1258  if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1259  /* makes no sense to use analog input. Note that analog
1260  expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1261  return -EIO;
1262  }
1263  if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1264  if (!isadat) {
1265  return -EIO;
1266  }
1267  runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1268  runtime->hw.rate_min = rate;
1269  runtime->hw.rate_max = rate;
1270  }
1271 
1272  spin_lock_irq(&rme96->lock);
1273  if (rme96->capture_substream != NULL) {
1274  spin_unlock_irq(&rme96->lock);
1275  return -EBUSY;
1276  }
1277  rme96->capture_substream = substream;
1278  spin_unlock_irq(&rme96->lock);
1279 
1280  rme96_set_buffer_size_constraint(rme96, runtime);
1281  return 0;
1282 }
1283 
1284 static int
1285 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1286 {
1287  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1288  int spdif = 0;
1289 
1290  spin_lock_irq(&rme96->lock);
1291  if (RME96_ISPLAYING(rme96)) {
1292  snd_rme96_playback_stop(rme96);
1293  }
1294  rme96->playback_substream = NULL;
1295  rme96->playback_periodsize = 0;
1296  spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1297  spin_unlock_irq(&rme96->lock);
1298  if (spdif) {
1299  rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1300  snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1301  SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1302  }
1303  return 0;
1304 }
1305 
1306 static int
1307 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1308 {
1309  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1310 
1311  spin_lock_irq(&rme96->lock);
1312  if (RME96_ISRECORDING(rme96)) {
1313  snd_rme96_capture_stop(rme96);
1314  }
1315  rme96->capture_substream = NULL;
1316  rme96->capture_periodsize = 0;
1317  spin_unlock_irq(&rme96->lock);
1318  return 0;
1319 }
1320 
1321 static int
1322 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1323 {
1324  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1325 
1326  spin_lock_irq(&rme96->lock);
1327  if (RME96_ISPLAYING(rme96)) {
1328  snd_rme96_playback_stop(rme96);
1329  }
1330  writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1331  spin_unlock_irq(&rme96->lock);
1332  return 0;
1333 }
1334 
1335 static int
1336 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1337 {
1338  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1339 
1340  spin_lock_irq(&rme96->lock);
1341  if (RME96_ISRECORDING(rme96)) {
1342  snd_rme96_capture_stop(rme96);
1343  }
1344  writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1345  spin_unlock_irq(&rme96->lock);
1346  return 0;
1347 }
1348 
1349 static int
1350 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1351  int cmd)
1352 {
1353  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1354 
1355  switch (cmd) {
1356  case SNDRV_PCM_TRIGGER_START:
1357  if (!RME96_ISPLAYING(rme96)) {
1358  if (substream != rme96->playback_substream) {
1359  return -EBUSY;
1360  }
1361  snd_rme96_playback_start(rme96, 0);
1362  }
1363  break;
1364 
1365  case SNDRV_PCM_TRIGGER_STOP:
1366  if (RME96_ISPLAYING(rme96)) {
1367  if (substream != rme96->playback_substream) {
1368  return -EBUSY;
1369  }
1370  snd_rme96_playback_stop(rme96);
1371  }
1372  break;
1373 
1374  case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1375  if (RME96_ISPLAYING(rme96)) {
1376  snd_rme96_playback_stop(rme96);
1377  }
1378  break;
1379 
1380  case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1381  if (!RME96_ISPLAYING(rme96)) {
1382  snd_rme96_playback_start(rme96, 1);
1383  }
1384  break;
1385 
1386  default:
1387  return -EINVAL;
1388  }
1389  return 0;
1390 }
1391 
1392 static int
1393 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1394  int cmd)
1395 {
1396  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1397 
1398  switch (cmd) {
1399  case SNDRV_PCM_TRIGGER_START:
1400  if (!RME96_ISRECORDING(rme96)) {
1401  if (substream != rme96->capture_substream) {
1402  return -EBUSY;
1403  }
1404  snd_rme96_capture_start(rme96, 0);
1405  }
1406  break;
1407 
1408  case SNDRV_PCM_TRIGGER_STOP:
1409  if (RME96_ISRECORDING(rme96)) {
1410  if (substream != rme96->capture_substream) {
1411  return -EBUSY;
1412  }
1413  snd_rme96_capture_stop(rme96);
1414  }
1415  break;
1416 
1417  case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1418  if (RME96_ISRECORDING(rme96)) {
1419  snd_rme96_capture_stop(rme96);
1420  }
1421  break;
1422 
1423  case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1424  if (!RME96_ISRECORDING(rme96)) {
1425  snd_rme96_capture_start(rme96, 1);
1426  }
1427  break;
1428 
1429  default:
1430  return -EINVAL;
1431  }
1432 
1433  return 0;
1434 }
1435 
1436 static snd_pcm_uframes_t
1437 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1438 {
1439  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1440  return snd_rme96_playback_ptr(rme96);
1441 }
1442 
1443 static snd_pcm_uframes_t
1444 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1445 {
1446  struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1447  return snd_rme96_capture_ptr(rme96);
1448 }
1449 
1450 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1451  .open = snd_rme96_playback_spdif_open,
1452  .close = snd_rme96_playback_close,
1453  .ioctl = snd_pcm_lib_ioctl,
1454  .hw_params = snd_rme96_playback_hw_params,
1455  .prepare = snd_rme96_playback_prepare,
1456  .trigger = snd_rme96_playback_trigger,
1457  .pointer = snd_rme96_playback_pointer,
1458  .copy = snd_rme96_playback_copy,
1459  .silence = snd_rme96_playback_silence,
1460  .mmap = snd_pcm_lib_mmap_iomem,
1461 };
1462 
1463 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1464  .open = snd_rme96_capture_spdif_open,
1465  .close = snd_rme96_capture_close,
1466  .ioctl = snd_pcm_lib_ioctl,
1467  .hw_params = snd_rme96_capture_hw_params,
1468  .prepare = snd_rme96_capture_prepare,
1469  .trigger = snd_rme96_capture_trigger,
1470  .pointer = snd_rme96_capture_pointer,
1471  .copy = snd_rme96_capture_copy,
1472  .mmap = snd_pcm_lib_mmap_iomem,
1473 };
1474 
1475 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1476  .open = snd_rme96_playback_adat_open,
1477  .close = snd_rme96_playback_close,
1478  .ioctl = snd_pcm_lib_ioctl,
1479  .hw_params = snd_rme96_playback_hw_params,
1480  .prepare = snd_rme96_playback_prepare,
1481  .trigger = snd_rme96_playback_trigger,
1482  .pointer = snd_rme96_playback_pointer,
1483  .copy = snd_rme96_playback_copy,
1484  .silence = snd_rme96_playback_silence,
1485  .mmap = snd_pcm_lib_mmap_iomem,
1486 };
1487 
1488 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1489  .open = snd_rme96_capture_adat_open,
1490  .close = snd_rme96_capture_close,
1491  .ioctl = snd_pcm_lib_ioctl,
1492  .hw_params = snd_rme96_capture_hw_params,
1493  .prepare = snd_rme96_capture_prepare,
1494  .trigger = snd_rme96_capture_trigger,
1495  .pointer = snd_rme96_capture_pointer,
1496  .copy = snd_rme96_capture_copy,
1497  .mmap = snd_pcm_lib_mmap_iomem,
1498 };
1499 
1500 static void
1501 snd_rme96_free(void *private_data)
1502 {
1503  struct rme96 *rme96 = (struct rme96 *)private_data;
1504 
1505  if (rme96 == NULL) {
1506  return;
1507  }
1508  if (rme96->irq >= 0) {
1509  snd_rme96_playback_stop(rme96);
1510  snd_rme96_capture_stop(rme96);
1511  rme96->areg &= ~RME96_AR_DAC_EN;
1512  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1513  free_irq(rme96->irq, (void *)rme96);
1514  rme96->irq = -1;
1515  }
1516  if (rme96->iobase) {
1517  iounmap(rme96->iobase);
1518  rme96->iobase = NULL;
1519  }
1520  if (rme96->port) {
1521  pci_release_regions(rme96->pci);
1522  rme96->port = 0;
1523  }
1524  pci_disable_device(rme96->pci);
1525 }
1526 
1527 static void
1528 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1529 {
1530  struct rme96 *rme96 = pcm->private_data;
1531  rme96->spdif_pcm = NULL;
1532 }
1533 
1534 static void
1535 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1536 {
1537  struct rme96 *rme96 = pcm->private_data;
1538  rme96->adat_pcm = NULL;
1539 }
1540 
1541 static int __devinit
1542 snd_rme96_create(struct rme96 *rme96)
1543 {
1544  struct pci_dev *pci = rme96->pci;
1545  int err;
1546 
1547  rme96->irq = -1;
1548  spin_lock_init(&rme96->lock);
1549 
1550  if ((err = pci_enable_device(pci)) < 0)
1551  return err;
1552 
1553  if ((err = pci_request_regions(pci, "RME96")) < 0)
1554  return err;
1555  rme96->port = pci_resource_start(rme96->pci, 0);
1556 
1557  rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1558  if (!rme96->iobase) {
1559  snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1560  return -ENOMEM;
1561  }
1562 
1563  if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1564  KBUILD_MODNAME, rme96)) {
1565  snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1566  return -EBUSY;
1567  }
1568  rme96->irq = pci->irq;
1569 
1570  /* read the card's revision number */
1571  pci_read_config_byte(pci, 8, &rme96->rev);
1572 
1573  /* set up ALSA pcm device for S/PDIF */
1574  if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1575  1, 1, &rme96->spdif_pcm)) < 0)
1576  {
1577  return err;
1578  }
1579  rme96->spdif_pcm->private_data = rme96;
1580  rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1581  strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1582  snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1583  snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1584 
1585  rme96->spdif_pcm->info_flags = 0;
1586 
1587  /* set up ALSA pcm device for ADAT */
1588  if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1589  /* ADAT is not available on the base model */
1590  rme96->adat_pcm = NULL;
1591  } else {
1592  if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1593  1, 1, &rme96->adat_pcm)) < 0)
1594  {
1595  return err;
1596  }
1597  rme96->adat_pcm->private_data = rme96;
1598  rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1599  strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1600  snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1601  snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1602 
1603  rme96->adat_pcm->info_flags = 0;
1604  }
1605 
1606  rme96->playback_periodsize = 0;
1607  rme96->capture_periodsize = 0;
1608 
1609  /* make sure playback/capture is stopped, if by some reason active */
1610  snd_rme96_playback_stop(rme96);
1611  snd_rme96_capture_stop(rme96);
1612 
1613  /* set default values in registers */
1614  rme96->wcreg =
1615  RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1616  RME96_WCR_SEL | /* normal playback */
1617  RME96_WCR_MASTER | /* set to master clock mode */
1618  RME96_WCR_INP_0; /* set coaxial input */
1619 
1620  rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1621 
1622  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1623  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1624 
1625  /* reset the ADC */
1626  writel(rme96->areg | RME96_AR_PD2,
1627  rme96->iobase + RME96_IO_ADDITIONAL_REG);
1628  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1629 
1630  /* reset and enable the DAC (order is important). */
1631  snd_rme96_reset_dac(rme96);
1632  rme96->areg |= RME96_AR_DAC_EN;
1633  writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1634 
1635  /* reset playback and record buffer pointers */
1636  writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1637  writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1638 
1639  /* reset volume */
1640  rme96->vol[0] = rme96->vol[1] = 0;
1641  if (RME96_HAS_ANALOG_OUT(rme96)) {
1642  snd_rme96_apply_dac_volume(rme96);
1643  }
1644 
1645  /* init switch interface */
1646  if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1647  return err;
1648  }
1649 
1650  /* init proc interface */
1651  snd_rme96_proc_init(rme96);
1652 
1653  return 0;
1654 }
1655 
1656 /*
1657  * proc interface
1658  */
1659 
1660 static void
1661 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1662 {
1663  int n;
1664  struct rme96 *rme96 = entry->private_data;
1665 
1666  rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1667 
1668  snd_iprintf(buffer, rme96->card->longname);
1669  snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1670 
1671  snd_iprintf(buffer, "\nGeneral settings\n");
1672  if (rme96->wcreg & RME96_WCR_IDIS) {
1673  snd_iprintf(buffer, " period size: N/A (interrupts "
1674  "disabled)\n");
1675  } else if (rme96->wcreg & RME96_WCR_ISEL) {
1676  snd_iprintf(buffer, " period size: 2048 bytes\n");
1677  } else {
1678  snd_iprintf(buffer, " period size: 8192 bytes\n");
1679  }
1680  snd_iprintf(buffer, "\nInput settings\n");
1681  switch (snd_rme96_getinputtype(rme96)) {
1682  case RME96_INPUT_OPTICAL:
1683  snd_iprintf(buffer, " input: optical");
1684  break;
1685  case RME96_INPUT_COAXIAL:
1686  snd_iprintf(buffer, " input: coaxial");
1687  break;
1688  case RME96_INPUT_INTERNAL:
1689  snd_iprintf(buffer, " input: internal");
1690  break;
1691  case RME96_INPUT_XLR:
1692  snd_iprintf(buffer, " input: XLR");
1693  break;
1694  case RME96_INPUT_ANALOG:
1695  snd_iprintf(buffer, " input: analog");
1696  break;
1697  }
1698  if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1699  snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1700  } else {
1701  if (n) {
1702  snd_iprintf(buffer, " (8 channels)\n");
1703  } else {
1704  snd_iprintf(buffer, " (2 channels)\n");
1705  }
1706  snd_iprintf(buffer, " sample rate: %d Hz\n",
1707  snd_rme96_capture_getrate(rme96, &n));
1708  }
1709  if (rme96->wcreg & RME96_WCR_MODE24_2) {
1710  snd_iprintf(buffer, " sample format: 24 bit\n");
1711  } else {
1712  snd_iprintf(buffer, " sample format: 16 bit\n");
1713  }
1714 
1715  snd_iprintf(buffer, "\nOutput settings\n");
1716  if (rme96->wcreg & RME96_WCR_SEL) {
1717  snd_iprintf(buffer, " output signal: normal playback\n");
1718  } else {
1719  snd_iprintf(buffer, " output signal: same as input\n");
1720  }
1721  snd_iprintf(buffer, " sample rate: %d Hz\n",
1722  snd_rme96_playback_getrate(rme96));
1723  if (rme96->wcreg & RME96_WCR_MODE24) {
1724  snd_iprintf(buffer, " sample format: 24 bit\n");
1725  } else {
1726  snd_iprintf(buffer, " sample format: 16 bit\n");
1727  }
1728  if (rme96->areg & RME96_AR_WSEL) {
1729  snd_iprintf(buffer, " sample clock source: word clock\n");
1730  } else if (rme96->wcreg & RME96_WCR_MASTER) {
1731  snd_iprintf(buffer, " sample clock source: internal\n");
1732  } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1733  snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1734  } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1735  snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1736  } else {
1737  snd_iprintf(buffer, " sample clock source: autosync\n");
1738  }
1739  if (rme96->wcreg & RME96_WCR_PRO) {
1740  snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1741  } else {
1742  snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1743  }
1744  if (rme96->wcreg & RME96_WCR_EMP) {
1745  snd_iprintf(buffer, " emphasis: on\n");
1746  } else {
1747  snd_iprintf(buffer, " emphasis: off\n");
1748  }
1749  if (rme96->wcreg & RME96_WCR_DOLBY) {
1750  snd_iprintf(buffer, " non-audio (dolby): on\n");
1751  } else {
1752  snd_iprintf(buffer, " non-audio (dolby): off\n");
1753  }
1754  if (RME96_HAS_ANALOG_IN(rme96)) {
1755  snd_iprintf(buffer, "\nAnalog output settings\n");
1756  switch (snd_rme96_getmontracks(rme96)) {
1757  case RME96_MONITOR_TRACKS_1_2:
1758  snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1759  break;
1760  case RME96_MONITOR_TRACKS_3_4:
1761  snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1762  break;
1763  case RME96_MONITOR_TRACKS_5_6:
1764  snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1765  break;
1766  case RME96_MONITOR_TRACKS_7_8:
1767  snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1768  break;
1769  }
1770  switch (snd_rme96_getattenuation(rme96)) {
1771  case RME96_ATTENUATION_0:
1772  snd_iprintf(buffer, " attenuation: 0 dB\n");
1773  break;
1774  case RME96_ATTENUATION_6:
1775  snd_iprintf(buffer, " attenuation: -6 dB\n");
1776  break;
1777  case RME96_ATTENUATION_12:
1778  snd_iprintf(buffer, " attenuation: -12 dB\n");
1779  break;
1780  case RME96_ATTENUATION_18:
1781  snd_iprintf(buffer, " attenuation: -18 dB\n");
1782  break;
1783  }
1784  snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1785  snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1786  }
1787 }
1788 
1789 static void __devinit
1790 snd_rme96_proc_init(struct rme96 *rme96)
1791 {
1792  struct snd_info_entry *entry;
1793 
1794  if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1795  snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1796 }
1797 
1798 /*
1799  * control interface
1800  */
1801 
1802 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1803 
1804 static int
1805 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1806 {
1807  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1808 
1809  spin_lock_irq(&rme96->lock);
1810  ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1811  spin_unlock_irq(&rme96->lock);
1812  return 0;
1813 }
1814 static int
1815 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1816 {
1817  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1818  unsigned int val;
1819  int change;
1820 
1821  val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1822  spin_lock_irq(&rme96->lock);
1823  val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1824  change = val != rme96->wcreg;
1825  rme96->wcreg = val;
1826  writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1827  spin_unlock_irq(&rme96->lock);
1828  return change;
1829 }
1830 
1831 static int
1832 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1833 {
1834  static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1835  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1836  char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1837 
1838  uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1839  uinfo->count = 1;
1840  switch (rme96->pci->device) {
1841  case PCI_DEVICE_ID_RME_DIGI96:
1842  case PCI_DEVICE_ID_RME_DIGI96_8:
1843  uinfo->value.enumerated.items = 3;
1844  break;
1845  case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1846  uinfo->value.enumerated.items = 4;
1847  break;
1848  case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1849  if (rme96->rev > 4) {
1850  /* PST */
1851  uinfo->value.enumerated.items = 4;
1852  texts[3] = _texts[4]; /* Analog instead of XLR */
1853  } else {
1854  /* PAD */
1855  uinfo->value.enumerated.items = 5;
1856  }
1857  break;
1858  default:
1859  snd_BUG();
1860  break;
1861  }
1862  if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1863  uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1864  }
1865  strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1866  return 0;
1867 }
1868 static int
1869 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1870 {
1871  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1872  unsigned int items = 3;
1873 
1874  spin_lock_irq(&rme96->lock);
1875  ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1876 
1877  switch (rme96->pci->device) {
1878  case PCI_DEVICE_ID_RME_DIGI96:
1879  case PCI_DEVICE_ID_RME_DIGI96_8:
1880  items = 3;
1881  break;
1882  case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1883  items = 4;
1884  break;
1885  case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1886  if (rme96->rev > 4) {
1887  /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1888  if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1889  ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1890  }
1891  items = 4;
1892  } else {
1893  items = 5;
1894  }
1895  break;
1896  default:
1897  snd_BUG();
1898  break;
1899  }
1900  if (ucontrol->value.enumerated.item[0] >= items) {
1901  ucontrol->value.enumerated.item[0] = items - 1;
1902  }
1903 
1904  spin_unlock_irq(&rme96->lock);
1905  return 0;
1906 }
1907 static int
1908 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1909 {
1910  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1911  unsigned int val;
1912  int change, items = 3;
1913 
1914  switch (rme96->pci->device) {
1915  case PCI_DEVICE_ID_RME_DIGI96:
1916  case PCI_DEVICE_ID_RME_DIGI96_8:
1917  items = 3;
1918  break;
1919  case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1920  items = 4;
1921  break;
1922  case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1923  if (rme96->rev > 4) {
1924  items = 4;
1925  } else {
1926  items = 5;
1927  }
1928  break;
1929  default:
1930  snd_BUG();
1931  break;
1932  }
1933  val = ucontrol->value.enumerated.item[0] % items;
1934 
1935  /* special case for PST */
1936  if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1937  if (val == RME96_INPUT_XLR) {
1938  val = RME96_INPUT_ANALOG;
1939  }
1940  }
1941 
1942  spin_lock_irq(&rme96->lock);
1943  change = (int)val != snd_rme96_getinputtype(rme96);
1944  snd_rme96_setinputtype(rme96, val);
1945  spin_unlock_irq(&rme96->lock);
1946  return change;
1947 }
1948 
1949 static int
1950 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1951 {
1952  static char *texts[3] = { "AutoSync", "Internal", "Word" };
1953 
1954  uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1955  uinfo->count = 1;
1956  uinfo->value.enumerated.items = 3;
1957  if (uinfo->value.enumerated.item > 2) {
1958  uinfo->value.enumerated.item = 2;
1959  }
1960  strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1961  return 0;
1962 }
1963 static int
1964 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1965 {
1966  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1967 
1968  spin_lock_irq(&rme96->lock);
1969  ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1970  spin_unlock_irq(&rme96->lock);
1971  return 0;
1972 }
1973 static int
1974 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1975 {
1976  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1977  unsigned int val;
1978  int change;
1979 
1980  val = ucontrol->value.enumerated.item[0] % 3;
1981  spin_lock_irq(&rme96->lock);
1982  change = (int)val != snd_rme96_getclockmode(rme96);
1983  snd_rme96_setclockmode(rme96, val);
1984  spin_unlock_irq(&rme96->lock);
1985  return change;
1986 }
1987 
1988 static int
1989 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1990 {
1991  static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
1992 
1993  uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1994  uinfo->count = 1;
1995  uinfo->value.enumerated.items = 4;
1996  if (uinfo->value.enumerated.item > 3) {
1997  uinfo->value.enumerated.item = 3;
1998  }
1999  strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2000  return 0;
2001 }
2002 static int
2003 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2004 {
2005  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2006 
2007  spin_lock_irq(&rme96->lock);
2008  ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2009  spin_unlock_irq(&rme96->lock);
2010  return 0;
2011 }
2012 static int
2013 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2014 {
2015  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2016  unsigned int val;
2017  int change;
2018 
2019  val = ucontrol->value.enumerated.item[0] % 4;
2020  spin_lock_irq(&rme96->lock);
2021 
2022  change = (int)val != snd_rme96_getattenuation(rme96);
2023  snd_rme96_setattenuation(rme96, val);
2024  spin_unlock_irq(&rme96->lock);
2025  return change;
2026 }
2027 
2028 static int
2029 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2030 {
2031  static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2032 
2033  uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2034  uinfo->count = 1;
2035  uinfo->value.enumerated.items = 4;
2036  if (uinfo->value.enumerated.item > 3) {
2037  uinfo->value.enumerated.item = 3;
2038  }
2039  strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2040  return 0;
2041 }
2042 static int
2043 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2044 {
2045  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2046 
2047  spin_lock_irq(&rme96->lock);
2048  ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2049  spin_unlock_irq(&rme96->lock);
2050  return 0;
2051 }
2052 static int
2053 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2054 {
2055  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2056  unsigned int val;
2057  int change;
2058 
2059  val = ucontrol->value.enumerated.item[0] % 4;
2060  spin_lock_irq(&rme96->lock);
2061  change = (int)val != snd_rme96_getmontracks(rme96);
2062  snd_rme96_setmontracks(rme96, val);
2063  spin_unlock_irq(&rme96->lock);
2064  return change;
2065 }
2066 
2067 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2068 {
2069  u32 val = 0;
2070  val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2071  val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2072  if (val & RME96_WCR_PRO)
2073  val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2074  else
2075  val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2076  return val;
2077 }
2078 
2079 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2080 {
2081  aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2082  ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2083  if (val & RME96_WCR_PRO)
2084  aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2085  else
2086  aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2087 }
2088 
2089 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2090 {
2091  uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2092  uinfo->count = 1;
2093  return 0;
2094 }
2095 
2096 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2097 {
2098  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2099 
2100  snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2101  return 0;
2102 }
2103 
2104 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2105 {
2106  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2107  int change;
2108  u32 val;
2109 
2110  val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2111  spin_lock_irq(&rme96->lock);
2112  change = val != rme96->wcreg_spdif;
2113  rme96->wcreg_spdif = val;
2114  spin_unlock_irq(&rme96->lock);
2115  return change;
2116 }
2117 
2118 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2119 {
2120  uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2121  uinfo->count = 1;
2122  return 0;
2123 }
2124 
2125 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2126 {
2127  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2128 
2129  snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2130  return 0;
2131 }
2132 
2133 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2134 {
2135  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2136  int change;
2137  u32 val;
2138 
2139  val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2140  spin_lock_irq(&rme96->lock);
2141  change = val != rme96->wcreg_spdif_stream;
2142  rme96->wcreg_spdif_stream = val;
2143  rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2144  rme96->wcreg |= val;
2145  writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2146  spin_unlock_irq(&rme96->lock);
2147  return change;
2148 }
2149 
2150 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2151 {
2152  uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2153  uinfo->count = 1;
2154  return 0;
2155 }
2156 
2157 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2158 {
2159  ucontrol->value.iec958.status[0] = kcontrol->private_value;
2160  return 0;
2161 }
2162 
2163 static int
2164 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2165 {
2166  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2167 
2168  uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2169  uinfo->count = 2;
2170  uinfo->value.integer.min = 0;
2171  uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2172  return 0;
2173 }
2174 
2175 static int
2176 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2177 {
2178  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2179 
2180  spin_lock_irq(&rme96->lock);
2181  u->value.integer.value[0] = rme96->vol[0];
2182  u->value.integer.value[1] = rme96->vol[1];
2183  spin_unlock_irq(&rme96->lock);
2184 
2185  return 0;
2186 }
2187 
2188 static int
2189 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2190 {
2191  struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2192  int change = 0;
2193  unsigned int vol, maxvol;
2194 
2195 
2196  if (!RME96_HAS_ANALOG_OUT(rme96))
2197  return -EINVAL;
2198  maxvol = RME96_185X_MAX_OUT(rme96);
2199  spin_lock_irq(&rme96->lock);
2200  vol = u->value.integer.value[0];
2201  if (vol != rme96->vol[0] && vol <= maxvol) {
2202  rme96->vol[0] = vol;
2203  change = 1;
2204  }
2205  vol = u->value.integer.value[1];
2206  if (vol != rme96->vol[1] && vol <= maxvol) {
2207  rme96->vol[1] = vol;
2208  change = 1;
2209  }
2210  if (change)
2211  snd_rme96_apply_dac_volume(rme96);
2212  spin_unlock_irq(&rme96->lock);
2213 
2214  return change;
2215 }
2216 
2217 static struct snd_kcontrol_new snd_rme96_controls[] = {
2218 {
2219  .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2220  .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2221  .info = snd_rme96_control_spdif_info,
2222  .get = snd_rme96_control_spdif_get,
2223  .put = snd_rme96_control_spdif_put
2224 },
2225 {
2226  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2227  .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2228  .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2229  .info = snd_rme96_control_spdif_stream_info,
2230  .get = snd_rme96_control_spdif_stream_get,
2231  .put = snd_rme96_control_spdif_stream_put
2232 },
2233 {
2234  .access = SNDRV_CTL_ELEM_ACCESS_READ,
2235  .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2236  .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2237  .info = snd_rme96_control_spdif_mask_info,
2238  .get = snd_rme96_control_spdif_mask_get,
2239  .private_value = IEC958_AES0_NONAUDIO |
2240  IEC958_AES0_PROFESSIONAL |
2241  IEC958_AES0_CON_EMPHASIS
2242 },
2243 {
2244  .access = SNDRV_CTL_ELEM_ACCESS_READ,
2245  .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2246  .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2247  .info = snd_rme96_control_spdif_mask_info,
2248  .get = snd_rme96_control_spdif_mask_get,
2249  .private_value = IEC958_AES0_NONAUDIO |
2250  IEC958_AES0_PROFESSIONAL |
2251  IEC958_AES0_PRO_EMPHASIS
2252 },
2253 {
2254  .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2255  .name = "Input Connector",
2256  .info = snd_rme96_info_inputtype_control,
2257  .get = snd_rme96_get_inputtype_control,
2258  .put = snd_rme96_put_inputtype_control
2259 },
2260 {
2261  .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2262  .name = "Loopback Input",
2263  .info = snd_rme96_info_loopback_control,
2264  .get = snd_rme96_get_loopback_control,
2265  .put = snd_rme96_put_loopback_control
2266 },
2267 {
2268  .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2269  .name = "Sample Clock Source",
2270  .info = snd_rme96_info_clockmode_control,
2271  .get = snd_rme96_get_clockmode_control,
2272  .put = snd_rme96_put_clockmode_control
2273 },
2274 {
2275  .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2276  .name = "Monitor Tracks",
2277  .info = snd_rme96_info_montracks_control,
2278  .get = snd_rme96_get_montracks_control,
2279  .put = snd_rme96_put_montracks_control
2280 },
2281 {
2282  .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2283  .name = "Attenuation",
2284  .info = snd_rme96_info_attenuation_control,
2285  .get = snd_rme96_get_attenuation_control,
2286  .put = snd_rme96_put_attenuation_control
2287 },
2288 {
2289  .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2290  .name = "DAC Playback Volume",
2291  .info = snd_rme96_dac_volume_info,
2292  .get = snd_rme96_dac_volume_get,
2293  .put = snd_rme96_dac_volume_put
2294 }
2295 };
2296 
2297 static int
2298 snd_rme96_create_switches(struct snd_card *card,
2299  struct rme96 *rme96)
2300 {
2301  int idx, err;
2302  struct snd_kcontrol *kctl;
2303 
2304  for (idx = 0; idx < 7; idx++) {
2305  if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2306  return err;
2307  if (idx == 1) /* IEC958 (S/PDIF) Stream */
2308  rme96->spdif_ctl = kctl;
2309  }
2310 
2311  if (RME96_HAS_ANALOG_OUT(rme96)) {
2312  for (idx = 7; idx < 10; idx++)
2313  if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2314  return err;
2315  }
2316 
2317  return 0;
2318 }
2319 
2320 /*
2321  * Card initialisation
2322  */
2323 
2324 static void snd_rme96_card_free(struct snd_card *card)
2325 {
2326  snd_rme96_free(card->private_data);
2327 }
2328 
2329 static int __devinit
2330 snd_rme96_probe(struct pci_dev *pci,
2331  const struct pci_device_id *pci_id)
2332 {
2333  static int dev;
2334  struct rme96 *rme96;
2335  struct snd_card *card;
2336  int err;
2337  u8 val;
2338 
2339  if (dev >= SNDRV_CARDS) {
2340  return -ENODEV;
2341  }
2342  if (!enable[dev]) {
2343  dev++;
2344  return -ENOENT;
2345  }
2346  err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2347  sizeof(struct rme96), &card);
2348  if (err < 0)
2349  return err;
2350  card->private_free = snd_rme96_card_free;
2351  rme96 = card->private_data;
2352  rme96->card = card;
2353  rme96->pci = pci;
2354  snd_card_set_dev(card, &pci->dev);
2355  if ((err = snd_rme96_create(rme96)) < 0) {
2356  snd_card_free(card);
2357  return err;
2358  }
2359 
2360  strcpy(card->driver, "Digi96");
2361  switch (rme96->pci->device) {
2362  case PCI_DEVICE_ID_RME_DIGI96:
2363  strcpy(card->shortname, "RME Digi96");
2364  break;
2365  case PCI_DEVICE_ID_RME_DIGI96_8:
2366  strcpy(card->shortname, "RME Digi96/8");
2367  break;
2368  case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2369  strcpy(card->shortname, "RME Digi96/8 PRO");
2370  break;
2371  case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2372  pci_read_config_byte(rme96->pci, 8, &val);
2373  if (val < 5) {
2374  strcpy(card->shortname, "RME Digi96/8 PAD");
2375  } else {
2376  strcpy(card->shortname, "RME Digi96/8 PST");
2377  }
2378  break;
2379  }
2380  sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2381  rme96->port, rme96->irq);
2382 
2383  if ((err = snd_card_register(card)) < 0) {
2384  snd_card_free(card);
2385  return err;
2386  }
2387  pci_set_drvdata(pci, card);
2388  dev++;
2389  return 0;
2390 }
2391 
2392 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2393 {
2394  snd_card_free(pci_get_drvdata(pci));
2395  pci_set_drvdata(pci, NULL);
2396 }
2397 
2398 static struct pci_driver rme96_driver = {
2399  .name = KBUILD_MODNAME,
2400  .id_table = snd_rme96_ids,
2401  .probe = snd_rme96_probe,
2402  .remove = __devexit_p(snd_rme96_remove),
2403 };
2404 
2405 module_pci_driver(rme96_driver);
Generated on Thu Jan 10 2013 15:07:04 for Linux Kernel by   doxygen 1.8.2