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s3c-hsudc.c
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1 /* linux/drivers/usb/gadget/s3c-hsudc.c
2  *
3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4  * http://www.samsung.com/
5  *
6  * S3C24XX USB 2.0 High-speed USB controller gadget driver
7  *
8  * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
9  * Each endpoint can be configured as either in or out endpoint. Endpoints
10  * can be configured for Bulk or Interrupt transfer mode.
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15 */
16 
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/delay.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/otg.h>
31 #include <linux/prefetch.h>
34 #include <linux/pm_runtime.h>
35 
37 
38 #define S3C_HSUDC_REG(x) (x)
39 
40 /* Non-Indexed Registers */
41 #define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
42 #define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
43 #define S3C_EIR_EP0 (1<<0)
44 #define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
45 #define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
46 #define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
47 #define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
48 #define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
49 #define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
50 #define S3C_SSR_DTZIEN_EN (0xff8f)
51 #define S3C_SSR_ERR (0xff80)
52 #define S3C_SSR_VBUSON (1 << 8)
53 #define S3C_SSR_HSP (1 << 4)
54 #define S3C_SSR_SDE (1 << 3)
55 #define S3C_SSR_RESUME (1 << 2)
56 #define S3C_SSR_SUSPEND (1 << 1)
57 #define S3C_SSR_RESET (1 << 0)
58 #define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
59 #define S3C_SCR_DTZIEN_EN (1 << 14)
60 #define S3C_SCR_RRD_EN (1 << 5)
61 #define S3C_SCR_SUS_EN (1 << 1)
62 #define S3C_SCR_RST_EN (1 << 0)
63 #define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
64 #define S3C_EP0SR_EP0_LWO (1 << 6)
65 #define S3C_EP0SR_STALL (1 << 4)
66 #define S3C_EP0SR_TX_SUCCESS (1 << 1)
67 #define S3C_EP0SR_RX_SUCCESS (1 << 0)
68 #define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
69 #define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
70 
71 /* Indexed Registers */
72 #define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
73 #define S3C_ESR_FLUSH (1 << 6)
74 #define S3C_ESR_STALL (1 << 5)
75 #define S3C_ESR_LWO (1 << 4)
76 #define S3C_ESR_PSIF_ONE (1 << 2)
77 #define S3C_ESR_PSIF_TWO (2 << 2)
78 #define S3C_ESR_TX_SUCCESS (1 << 1)
79 #define S3C_ESR_RX_SUCCESS (1 << 0)
80 #define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
81 #define S3C_ECR_DUEN (1 << 7)
82 #define S3C_ECR_FLUSH (1 << 6)
83 #define S3C_ECR_STALL (1 << 1)
84 #define S3C_ECR_IEMS (1 << 0)
85 #define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
86 #define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
87 #define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
88 
89 #define WAIT_FOR_SETUP (0)
90 #define DATA_STATE_XMIT (1)
91 #define DATA_STATE_RECV (2)
92 
93 static const char * const s3c_hsudc_supply_names[] = {
94  "vdda", /* analog phy supply, 3.3V */
95  "vddi", /* digital phy supply, 1.2V */
96  "vddosc", /* oscillator supply, 1.8V - 3.3V */
97 };
98 
110 struct s3c_hsudc_ep {
111  struct usb_ep ep;
112  char name[20];
113  struct s3c_hsudc *dev;
114  struct list_head queue;
118  void __iomem *fifo;
119 };
120 
127  struct usb_request req;
128  struct list_head queue;
129 };
130 
143 struct s3c_hsudc {
146  struct device *dev;
149  struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
151  void __iomem *regs;
152  int irq;
153  struct clk *uclk;
154  int ep0state;
155  struct s3c_hsudc_ep ep[];
156 };
157 
158 #define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
159 #define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
160 #define ep_index(_ep) ((_ep)->bEndpointAddress & \
161  USB_ENDPOINT_NUMBER_MASK)
162 
163 static const char driver_name[] = "s3c-udc";
164 static const char ep0name[] = "ep0-control";
165 
166 static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
167 {
168  return container_of(req, struct s3c_hsudc_req, req);
169 }
170 
171 static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
172 {
173  return container_of(ep, struct s3c_hsudc_ep, ep);
174 }
175 
176 static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
177 {
178  return container_of(gadget, struct s3c_hsudc, gadget);
179 }
180 
181 static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
182 {
183  ep_addr &= USB_ENDPOINT_NUMBER_MASK;
184  writel(ep_addr, hsudc->regs + S3C_IR);
185 }
186 
187 static inline void __orr32(void __iomem *ptr, u32 val)
188 {
189  writel(readl(ptr) | val, ptr);
190 }
191 
192 static void s3c_hsudc_init_phy(void)
193 {
194  u32 cfg;
195 
197  writel(cfg, S3C2443_PWRCFG);
198 
199  cfg = readl(S3C2443_URSTCON);
201  writel(cfg, S3C2443_URSTCON);
202  mdelay(1);
203 
204  cfg = readl(S3C2443_URSTCON);
206  writel(cfg, S3C2443_URSTCON);
207 
208  cfg = readl(S3C2443_PHYCTRL);
211  writel(cfg, S3C2443_PHYCTRL);
212 
213  cfg = readl(S3C2443_PHYPWR);
218  writel(cfg, S3C2443_PHYPWR);
219 
220  cfg = readl(S3C2443_UCLKCON);
223  writel(cfg, S3C2443_UCLKCON);
224 }
225 
226 static void s3c_hsudc_uninit_phy(void)
227 {
228  u32 cfg;
229 
231  writel(cfg, S3C2443_PWRCFG);
232 
234 
236  writel(cfg, S3C2443_UCLKCON);
237 }
238 
245 static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
246  struct s3c_hsudc_req *hsreq, int status)
247 {
248  unsigned int stopped = hsep->stopped;
249  struct s3c_hsudc *hsudc = hsep->dev;
250 
251  list_del_init(&hsreq->queue);
252  hsreq->req.status = status;
253 
254  if (!ep_index(hsep)) {
255  hsudc->ep0state = WAIT_FOR_SETUP;
256  hsep->bEndpointAddress &= ~USB_DIR_IN;
257  }
258 
259  hsep->stopped = 1;
260  spin_unlock(&hsudc->lock);
261  if (hsreq->req.complete != NULL)
262  hsreq->req.complete(&hsep->ep, &hsreq->req);
263  spin_lock(&hsudc->lock);
264  hsep->stopped = stopped;
265 }
266 
272 static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
273 {
274  struct s3c_hsudc_req *hsreq;
275 
276  while (!list_empty(&hsep->queue)) {
277  hsreq = list_entry(hsep->queue.next,
278  struct s3c_hsudc_req, queue);
279  s3c_hsudc_complete_request(hsep, hsreq, status);
280  }
281 }
282 
291 static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
292 {
293  struct s3c_hsudc_ep *hsep;
294  int epnum;
295 
296  hsudc->gadget.speed = USB_SPEED_UNKNOWN;
297 
298  for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
299  hsep = &hsudc->ep[epnum];
300  hsep->stopped = 1;
301  s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
302  }
303 }
304 
314 static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
315 {
316  int count;
317 
318  count = readl(hsudc->regs + S3C_BRCR);
319  while (count--)
320  *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
321 
323 }
324 
333 static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
334  struct s3c_hsudc_req *hsreq)
335 {
336  u16 *buf;
337  u32 max = ep_maxpacket(hsep);
338  u32 count, length;
339  bool is_last;
340  void __iomem *fifo = hsep->fifo;
341 
342  buf = hsreq->req.buf + hsreq->req.actual;
343  prefetch(buf);
344 
345  length = hsreq->req.length - hsreq->req.actual;
346  length = min(length, max);
347  hsreq->req.actual += length;
348 
349  writel(length, hsep->dev->regs + S3C_BWCR);
350  for (count = 0; count < length; count += 2)
351  writel(*buf++, fifo);
352 
353  if (count != max) {
354  is_last = true;
355  } else {
356  if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
357  is_last = false;
358  else
359  is_last = true;
360  }
361 
362  if (is_last) {
363  s3c_hsudc_complete_request(hsep, hsreq, 0);
364  return 1;
365  }
366 
367  return 0;
368 }
369 
379 static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
380  struct s3c_hsudc_req *hsreq)
381 {
382  struct s3c_hsudc *hsudc = hsep->dev;
383  u32 csr, offset;
384  u16 *buf, word;
385  u32 buflen, rcnt, rlen;
386  void __iomem *fifo = hsep->fifo;
387  u32 is_short = 0;
388 
389  offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
390  csr = readl(hsudc->regs + offset);
391  if (!(csr & S3C_ESR_RX_SUCCESS))
392  return -EINVAL;
393 
394  buf = hsreq->req.buf + hsreq->req.actual;
395  prefetchw(buf);
396  buflen = hsreq->req.length - hsreq->req.actual;
397 
398  rcnt = readl(hsudc->regs + S3C_BRCR);
399  rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
400 
401  hsreq->req.actual += min(rlen, buflen);
402  is_short = (rlen < hsep->ep.maxpacket);
403 
404  while (rcnt-- != 0) {
405  word = (u16)readl(fifo);
406  if (buflen) {
407  *buf++ = word;
408  buflen--;
409  } else {
410  hsreq->req.status = -EOVERFLOW;
411  }
412  }
413 
414  writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
415 
416  if (is_short || hsreq->req.actual == hsreq->req.length) {
417  s3c_hsudc_complete_request(hsep, hsreq, 0);
418  return 1;
419  }
420 
421  return 0;
422 }
423 
432 static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
433 {
434  struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
435  struct s3c_hsudc_req *hsreq;
436  u32 csr;
437 
438  csr = readl((u32)hsudc->regs + S3C_ESR);
439  if (csr & S3C_ESR_STALL) {
440  writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
441  return;
442  }
443 
444  if (csr & S3C_ESR_TX_SUCCESS) {
445  writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
446  if (list_empty(&hsep->queue))
447  return;
448 
449  hsreq = list_entry(hsep->queue.next,
450  struct s3c_hsudc_req, queue);
451  if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
452  (csr & S3C_ESR_PSIF_TWO))
453  s3c_hsudc_write_fifo(hsep, hsreq);
454  }
455 }
456 
465 static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
466 {
467  struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
468  struct s3c_hsudc_req *hsreq;
469  u32 csr;
470 
471  csr = readl((u32)hsudc->regs + S3C_ESR);
472  if (csr & S3C_ESR_STALL) {
473  writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
474  return;
475  }
476 
477  if (csr & S3C_ESR_FLUSH) {
478  __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
479  return;
480  }
481 
482  if (csr & S3C_ESR_RX_SUCCESS) {
483  if (list_empty(&hsep->queue))
484  return;
485 
486  hsreq = list_entry(hsep->queue.next,
487  struct s3c_hsudc_req, queue);
488  if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
489  (csr & S3C_ESR_PSIF_TWO))
490  s3c_hsudc_read_fifo(hsep, hsreq);
491  }
492 }
493 
502 static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
503 {
504  struct s3c_hsudc_ep *hsep = our_ep(_ep);
505  struct s3c_hsudc *hsudc = hsep->dev;
506  struct s3c_hsudc_req *hsreq;
507  unsigned long irqflags;
508  u32 ecr;
509  u32 offset;
510 
511  if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
512  return -EAGAIN;
513 
514  spin_lock_irqsave(&hsudc->lock, irqflags);
515  set_index(hsudc, ep_index(hsep));
516  offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
517  ecr = readl(hsudc->regs + offset);
518 
519  if (value) {
520  ecr |= S3C_ECR_STALL;
521  if (ep_index(hsep))
522  ecr |= S3C_ECR_FLUSH;
523  hsep->stopped = 1;
524  } else {
525  ecr &= ~S3C_ECR_STALL;
526  hsep->stopped = hsep->wedge = 0;
527  }
528  writel(ecr, hsudc->regs + offset);
529 
530  if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
531  hsreq = list_entry(hsep->queue.next,
532  struct s3c_hsudc_req, queue);
533  if (hsreq)
534  s3c_hsudc_write_fifo(hsep, hsreq);
535  }
536 
537  spin_unlock_irqrestore(&hsudc->lock, irqflags);
538  return 0;
539 }
540 
546 static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
547 {
548  struct s3c_hsudc_ep *hsep = our_ep(_ep);
549 
550  if (!hsep)
551  return -EINVAL;
552 
553  hsep->wedge = 1;
554  return usb_ep_set_halt(_ep);
555 }
556 
563 static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
564  struct usb_ctrlrequest *ctrl)
565 {
566  struct s3c_hsudc_ep *hsep;
567  bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
568  u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
569 
570  if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
571  hsep = &hsudc->ep[ep_num];
572  switch (le16_to_cpu(ctrl->wValue)) {
573  case USB_ENDPOINT_HALT:
574  if (set || (!set && !hsep->wedge))
575  s3c_hsudc_set_halt(&hsep->ep, set);
576  return 0;
577  }
578  }
579 
580  return -ENOENT;
581 }
582 
590 static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
591  struct usb_ctrlrequest *ctrl)
592 {
593  struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
594  struct s3c_hsudc_req hsreq;
595  struct s3c_hsudc_ep *hsep;
596  __le16 reply;
597  u8 epnum;
598 
599  switch (ctrl->bRequestType & USB_RECIP_MASK) {
600  case USB_RECIP_DEVICE:
601  reply = cpu_to_le16(0);
602  break;
603 
604  case USB_RECIP_INTERFACE:
605  reply = cpu_to_le16(0);
606  break;
607 
608  case USB_RECIP_ENDPOINT:
610  hsep = &hsudc->ep[epnum];
611  reply = cpu_to_le16(hsep->stopped ? 1 : 0);
612  break;
613  }
614 
615  INIT_LIST_HEAD(&hsreq.queue);
616  hsreq.req.length = 2;
617  hsreq.req.buf = &reply;
618  hsreq.req.actual = 0;
619  hsreq.req.complete = NULL;
620  s3c_hsudc_write_fifo(hsep0, &hsreq);
621 }
622 
630 static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
631 {
632  struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
633  struct usb_ctrlrequest ctrl = {0};
634  int ret;
635 
636  s3c_hsudc_nuke_ep(hsep, -EPROTO);
637  s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
638 
639  if (ctrl.bRequestType & USB_DIR_IN) {
640  hsep->bEndpointAddress |= USB_DIR_IN;
641  hsudc->ep0state = DATA_STATE_XMIT;
642  } else {
643  hsep->bEndpointAddress &= ~USB_DIR_IN;
644  hsudc->ep0state = DATA_STATE_RECV;
645  }
646 
647  switch (ctrl.bRequest) {
648  case USB_REQ_SET_ADDRESS:
650  break;
651  hsudc->ep0state = WAIT_FOR_SETUP;
652  return;
653 
654  case USB_REQ_GET_STATUS:
656  break;
657  s3c_hsudc_process_req_status(hsudc, &ctrl);
658  return;
659 
660  case USB_REQ_SET_FEATURE:
663  break;
664  s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
665  hsudc->ep0state = WAIT_FOR_SETUP;
666  return;
667  }
668 
669  if (hsudc->driver) {
670  spin_unlock(&hsudc->lock);
671  ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
672  spin_lock(&hsudc->lock);
673 
674  if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
675  hsep->bEndpointAddress &= ~USB_DIR_IN;
676  hsudc->ep0state = WAIT_FOR_SETUP;
677  }
678 
679  if (ret < 0) {
680  dev_err(hsudc->dev, "setup failed, returned %d\n",
681  ret);
682  s3c_hsudc_set_halt(&hsep->ep, 1);
683  hsudc->ep0state = WAIT_FOR_SETUP;
684  hsep->bEndpointAddress &= ~USB_DIR_IN;
685  }
686  }
687 }
688 
696 static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
697 {
698  struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
699  struct s3c_hsudc_req *hsreq;
700  u32 csr = readl(hsudc->regs + S3C_EP0SR);
701  u32 ecr;
702 
703  if (csr & S3C_EP0SR_STALL) {
704  ecr = readl(hsudc->regs + S3C_EP0CR);
705  ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
706  writel(ecr, hsudc->regs + S3C_EP0CR);
707 
708  writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
709  hsep->stopped = 0;
710 
711  s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
712  hsudc->ep0state = WAIT_FOR_SETUP;
713  hsep->bEndpointAddress &= ~USB_DIR_IN;
714  return;
715  }
716 
717  if (csr & S3C_EP0SR_TX_SUCCESS) {
718  writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
719  if (ep_is_in(hsep)) {
720  if (list_empty(&hsep->queue))
721  return;
722 
723  hsreq = list_entry(hsep->queue.next,
724  struct s3c_hsudc_req, queue);
725  s3c_hsudc_write_fifo(hsep, hsreq);
726  }
727  }
728 
729  if (csr & S3C_EP0SR_RX_SUCCESS) {
730  if (hsudc->ep0state == WAIT_FOR_SETUP)
731  s3c_hsudc_process_setup(hsudc);
732  else {
733  if (!ep_is_in(hsep)) {
734  if (list_empty(&hsep->queue))
735  return;
736  hsreq = list_entry(hsep->queue.next,
737  struct s3c_hsudc_req, queue);
738  s3c_hsudc_read_fifo(hsep, hsreq);
739  }
740  }
741  }
742 }
743 
753 static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
754  const struct usb_endpoint_descriptor *desc)
755 {
756  struct s3c_hsudc_ep *hsep;
757  struct s3c_hsudc *hsudc;
758  unsigned long flags;
759  u32 ecr = 0;
760 
761  hsep = our_ep(_ep);
762  if (!_ep || !desc || _ep->name == ep0name
763  || desc->bDescriptorType != USB_DT_ENDPOINT
764  || hsep->bEndpointAddress != desc->bEndpointAddress
765  || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
766  return -EINVAL;
767 
769  && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
770  || !desc->wMaxPacketSize)
771  return -ERANGE;
772 
773  hsudc = hsep->dev;
774  if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
775  return -ESHUTDOWN;
776 
777  spin_lock_irqsave(&hsudc->lock, flags);
778 
779  set_index(hsudc, hsep->bEndpointAddress);
780  ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
781  writel(ecr, hsudc->regs + S3C_ECR);
782 
783  hsep->stopped = hsep->wedge = 0;
784  hsep->ep.desc = desc;
785  hsep->ep.maxpacket = usb_endpoint_maxp(desc);
786 
787  s3c_hsudc_set_halt(_ep, 0);
788  __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
789 
790  spin_unlock_irqrestore(&hsudc->lock, flags);
791  return 0;
792 }
793 
801 static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
802 {
803  struct s3c_hsudc_ep *hsep = our_ep(_ep);
804  struct s3c_hsudc *hsudc = hsep->dev;
805  unsigned long flags;
806 
807  if (!_ep || !hsep->ep.desc)
808  return -EINVAL;
809 
810  spin_lock_irqsave(&hsudc->lock, flags);
811 
812  set_index(hsudc, hsep->bEndpointAddress);
813  __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
814 
815  s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
816 
817  hsep->ep.desc = NULL;
818  hsep->stopped = 1;
819 
820  spin_unlock_irqrestore(&hsudc->lock, flags);
821  return 0;
822 }
823 
831 static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
832  gfp_t gfp_flags)
833 {
834  struct s3c_hsudc_req *hsreq;
835 
836  hsreq = kzalloc(sizeof(*hsreq), gfp_flags);
837  if (!hsreq)
838  return NULL;
839 
840  INIT_LIST_HEAD(&hsreq->queue);
841  return &hsreq->req;
842 }
843 
851 static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
852 {
853  struct s3c_hsudc_req *hsreq;
854 
855  hsreq = our_req(_req);
856  WARN_ON(!list_empty(&hsreq->queue));
857  kfree(hsreq);
858 }
859 
868 static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
869  gfp_t gfp_flags)
870 {
871  struct s3c_hsudc_req *hsreq;
872  struct s3c_hsudc_ep *hsep;
873  struct s3c_hsudc *hsudc;
874  unsigned long flags;
875  u32 offset;
876  u32 csr;
877 
878  hsreq = our_req(_req);
879  if ((!_req || !_req->complete || !_req->buf ||
880  !list_empty(&hsreq->queue)))
881  return -EINVAL;
882 
883  hsep = our_ep(_ep);
884  hsudc = hsep->dev;
885  if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
886  return -ESHUTDOWN;
887 
888  spin_lock_irqsave(&hsudc->lock, flags);
889  set_index(hsudc, hsep->bEndpointAddress);
890 
891  _req->status = -EINPROGRESS;
892  _req->actual = 0;
893 
894  if (!ep_index(hsep) && _req->length == 0) {
895  hsudc->ep0state = WAIT_FOR_SETUP;
896  s3c_hsudc_complete_request(hsep, hsreq, 0);
897  spin_unlock_irqrestore(&hsudc->lock, flags);
898  return 0;
899  }
900 
901  if (list_empty(&hsep->queue) && !hsep->stopped) {
902  offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
903  if (ep_is_in(hsep)) {
904  csr = readl((u32)hsudc->regs + offset);
905  if (!(csr & S3C_ESR_TX_SUCCESS) &&
906  (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
907  hsreq = NULL;
908  } else {
909  csr = readl((u32)hsudc->regs + offset);
910  if ((csr & S3C_ESR_RX_SUCCESS)
911  && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
912  hsreq = NULL;
913  }
914  }
915 
916  if (hsreq)
917  list_add_tail(&hsreq->queue, &hsep->queue);
918 
919  spin_unlock_irqrestore(&hsudc->lock, flags);
920  return 0;
921 }
922 
930 static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
931 {
932  struct s3c_hsudc_ep *hsep = our_ep(_ep);
933  struct s3c_hsudc *hsudc = hsep->dev;
934  struct s3c_hsudc_req *hsreq;
935  unsigned long flags;
936 
937  hsep = our_ep(_ep);
938  if (!_ep || hsep->ep.name == ep0name)
939  return -EINVAL;
940 
941  spin_lock_irqsave(&hsudc->lock, flags);
942 
943  list_for_each_entry(hsreq, &hsep->queue, queue) {
944  if (&hsreq->req == _req)
945  break;
946  }
947  if (&hsreq->req != _req) {
948  spin_unlock_irqrestore(&hsudc->lock, flags);
949  return -EINVAL;
950  }
951 
952  set_index(hsudc, hsep->bEndpointAddress);
953  s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
954 
955  spin_unlock_irqrestore(&hsudc->lock, flags);
956  return 0;
957 }
958 
959 static struct usb_ep_ops s3c_hsudc_ep_ops = {
960  .enable = s3c_hsudc_ep_enable,
961  .disable = s3c_hsudc_ep_disable,
962  .alloc_request = s3c_hsudc_alloc_request,
963  .free_request = s3c_hsudc_free_request,
964  .queue = s3c_hsudc_queue,
965  .dequeue = s3c_hsudc_dequeue,
966  .set_halt = s3c_hsudc_set_halt,
967  .set_wedge = s3c_hsudc_set_wedge,
968 };
969 
978 static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
979  struct s3c_hsudc_ep *hsep, int epnum)
980 {
981  char *dir;
982 
983  if ((epnum % 2) == 0) {
984  dir = "out";
985  } else {
986  dir = "in";
988  }
989 
990  hsep->bEndpointAddress |= epnum;
991  if (epnum)
992  snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
993  else
994  snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
995 
996  INIT_LIST_HEAD(&hsep->queue);
997  INIT_LIST_HEAD(&hsep->ep.ep_list);
998  if (epnum)
999  list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
1000 
1001  hsep->dev = hsudc;
1002  hsep->ep.name = hsep->name;
1003  hsep->ep.maxpacket = epnum ? 512 : 64;
1004  hsep->ep.ops = &s3c_hsudc_ep_ops;
1005  hsep->fifo = hsudc->regs + S3C_BR(epnum);
1006  hsep->ep.desc = NULL;
1007  hsep->stopped = 0;
1008  hsep->wedge = 0;
1009 
1010  set_index(hsudc, epnum);
1011  writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
1012 }
1013 
1020 static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
1021 {
1022  int epnum;
1023 
1024  hsudc->ep0state = WAIT_FOR_SETUP;
1025  INIT_LIST_HEAD(&hsudc->gadget.ep_list);
1026  for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
1027  s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
1028 }
1029 
1036 static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1037 {
1038  writel(0xAA, hsudc->regs + S3C_EDR);
1039  writel(1, hsudc->regs + S3C_EIER);
1040  writel(0, hsudc->regs + S3C_TR);
1042  S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1043  writel(0, hsudc->regs + S3C_EP0CR);
1044 
1045  s3c_hsudc_setup_ep(hsudc);
1046 }
1047 
1056 static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1057 {
1058  struct s3c_hsudc *hsudc = _dev;
1059  struct s3c_hsudc_ep *hsep;
1060  u32 ep_intr;
1061  u32 sys_status;
1062  u32 ep_idx;
1063 
1064  spin_lock(&hsudc->lock);
1065 
1066  sys_status = readl(hsudc->regs + S3C_SSR);
1067  ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1068 
1069  if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1070  spin_unlock(&hsudc->lock);
1071  return IRQ_HANDLED;
1072  }
1073 
1074  if (sys_status) {
1075  if (sys_status & S3C_SSR_VBUSON)
1076  writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1077 
1078  if (sys_status & S3C_SSR_ERR)
1079  writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1080 
1081  if (sys_status & S3C_SSR_SDE) {
1082  writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1083  hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1085  }
1086 
1087  if (sys_status & S3C_SSR_SUSPEND) {
1088  writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1089  if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1090  && hsudc->driver && hsudc->driver->suspend)
1091  hsudc->driver->suspend(&hsudc->gadget);
1092  }
1093 
1094  if (sys_status & S3C_SSR_RESUME) {
1095  writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1096  if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1097  && hsudc->driver && hsudc->driver->resume)
1098  hsudc->driver->resume(&hsudc->gadget);
1099  }
1100 
1101  if (sys_status & S3C_SSR_RESET) {
1102  writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1103  for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1104  hsep = &hsudc->ep[ep_idx];
1105  hsep->stopped = 1;
1106  s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1107  }
1108  s3c_hsudc_reconfig(hsudc);
1109  hsudc->ep0state = WAIT_FOR_SETUP;
1110  }
1111  }
1112 
1113  if (ep_intr & S3C_EIR_EP0) {
1114  writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1115  set_index(hsudc, 0);
1116  s3c_hsudc_handle_ep0_intr(hsudc);
1117  }
1118 
1119  ep_intr >>= 1;
1120  ep_idx = 1;
1121  while (ep_intr) {
1122  if (ep_intr & 1) {
1123  hsep = &hsudc->ep[ep_idx];
1124  set_index(hsudc, ep_idx);
1125  writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1126  if (ep_is_in(hsep))
1127  s3c_hsudc_epin_intr(hsudc, ep_idx);
1128  else
1129  s3c_hsudc_epout_intr(hsudc, ep_idx);
1130  }
1131  ep_intr >>= 1;
1132  ep_idx++;
1133  }
1134 
1135  spin_unlock(&hsudc->lock);
1136  return IRQ_HANDLED;
1137 }
1138 
1139 static int s3c_hsudc_start(struct usb_gadget *gadget,
1140  struct usb_gadget_driver *driver)
1141 {
1142  struct s3c_hsudc *hsudc = to_hsudc(gadget);
1143  int ret;
1144 
1145  if (!driver
1146  || driver->max_speed < USB_SPEED_FULL
1147  || !driver->setup)
1148  return -EINVAL;
1149 
1150  if (!hsudc)
1151  return -ENODEV;
1152 
1153  if (hsudc->driver)
1154  return -EBUSY;
1155 
1156  hsudc->driver = driver;
1157  hsudc->gadget.dev.driver = &driver->driver;
1158 
1160  hsudc->supplies);
1161  if (ret != 0) {
1162  dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
1163  goto err_supplies;
1164  }
1165 
1166  /* connect to bus through transceiver */
1167  if (!IS_ERR_OR_NULL(hsudc->transceiver)) {
1168  ret = otg_set_peripheral(hsudc->transceiver->otg,
1169  &hsudc->gadget);
1170  if (ret) {
1171  dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1172  hsudc->gadget.name);
1173  goto err_otg;
1174  }
1175  }
1176 
1177  enable_irq(hsudc->irq);
1178  dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
1179 
1180  s3c_hsudc_reconfig(hsudc);
1181 
1182  pm_runtime_get_sync(hsudc->dev);
1183 
1184  s3c_hsudc_init_phy();
1185  if (hsudc->pd->gpio_init)
1186  hsudc->pd->gpio_init();
1187 
1188  return 0;
1189 err_otg:
1191 err_supplies:
1192  hsudc->driver = NULL;
1193  hsudc->gadget.dev.driver = NULL;
1194  return ret;
1195 }
1196 
1197 static int s3c_hsudc_stop(struct usb_gadget *gadget,
1198  struct usb_gadget_driver *driver)
1199 {
1200  struct s3c_hsudc *hsudc = to_hsudc(gadget);
1201  unsigned long flags;
1202 
1203  if (!hsudc)
1204  return -ENODEV;
1205 
1206  if (!driver || driver != hsudc->driver)
1207  return -EINVAL;
1208 
1209  spin_lock_irqsave(&hsudc->lock, flags);
1210  hsudc->driver = NULL;
1211  hsudc->gadget.dev.driver = NULL;
1212  hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1213  s3c_hsudc_uninit_phy();
1214 
1215  pm_runtime_put(hsudc->dev);
1216 
1217  if (hsudc->pd->gpio_uninit)
1218  hsudc->pd->gpio_uninit();
1219  s3c_hsudc_stop_activity(hsudc);
1220  spin_unlock_irqrestore(&hsudc->lock, flags);
1221 
1222  if (!IS_ERR_OR_NULL(hsudc->transceiver))
1223  (void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
1224 
1225  disable_irq(hsudc->irq);
1226 
1228 
1229  dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
1230  driver->driver.name);
1231  return 0;
1232 }
1233 
1234 static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1235 {
1236  return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1237 }
1238 
1239 static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1240 {
1241  return s3c_hsudc_read_frameno(to_hsudc(gadget));
1242 }
1243 
1244 static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1245 {
1246  struct s3c_hsudc *hsudc = to_hsudc(gadget);
1247 
1248  if (!hsudc)
1249  return -ENODEV;
1250 
1251  if (!IS_ERR_OR_NULL(hsudc->transceiver))
1252  return usb_phy_set_power(hsudc->transceiver, mA);
1253 
1254  return -EOPNOTSUPP;
1255 }
1256 
1257 static struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1258  .get_frame = s3c_hsudc_gadget_getframe,
1259  .udc_start = s3c_hsudc_start,
1260  .udc_stop = s3c_hsudc_stop,
1261  .vbus_draw = s3c_hsudc_vbus_draw,
1262 };
1263 
1264 static int __devinit s3c_hsudc_probe(struct platform_device *pdev)
1265 {
1266  struct device *dev = &pdev->dev;
1267  struct resource *res;
1268  struct s3c_hsudc *hsudc;
1269  struct s3c24xx_hsudc_platdata *pd = pdev->dev.platform_data;
1270  int ret, i;
1271 
1272  hsudc = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsudc) +
1273  sizeof(struct s3c_hsudc_ep) * pd->epnum,
1274  GFP_KERNEL);
1275  if (!hsudc) {
1276  dev_err(dev, "cannot allocate memory\n");
1277  return -ENOMEM;
1278  }
1279 
1280  platform_set_drvdata(pdev, dev);
1281  hsudc->dev = dev;
1282  hsudc->pd = pdev->dev.platform_data;
1283 
1285 
1286  for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
1287  hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
1288 
1289  ret = regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
1290  hsudc->supplies);
1291  if (ret != 0) {
1292  dev_err(dev, "failed to request supplies: %d\n", ret);
1293  goto err_supplies;
1294  }
1295 
1296  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 
1298  hsudc->regs = devm_request_and_ioremap(&pdev->dev, res);
1299  if (!hsudc->regs) {
1300  dev_err(dev, "error mapping device register area\n");
1301  ret = -EBUSY;
1302  goto err_res;
1303  }
1304 
1305  spin_lock_init(&hsudc->lock);
1306 
1307  dev_set_name(&hsudc->gadget.dev, "gadget");
1308 
1309  hsudc->gadget.max_speed = USB_SPEED_HIGH;
1310  hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1311  hsudc->gadget.name = dev_name(dev);
1312  hsudc->gadget.dev.parent = dev;
1313  hsudc->gadget.dev.dma_mask = dev->dma_mask;
1314  hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1315 
1316  hsudc->gadget.is_otg = 0;
1317  hsudc->gadget.is_a_peripheral = 0;
1318  hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1319 
1320  s3c_hsudc_setup_ep(hsudc);
1321 
1322  ret = platform_get_irq(pdev, 0);
1323  if (ret < 0) {
1324  dev_err(dev, "unable to obtain IRQ number\n");
1325  goto err_res;
1326  }
1327  hsudc->irq = ret;
1328 
1329  ret = devm_request_irq(&pdev->dev, hsudc->irq, s3c_hsudc_irq, 0,
1330  driver_name, hsudc);
1331  if (ret < 0) {
1332  dev_err(dev, "irq request failed\n");
1333  goto err_res;
1334  }
1335 
1336  hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device");
1337  if (IS_ERR(hsudc->uclk)) {
1338  dev_err(dev, "failed to find usb-device clock source\n");
1339  ret = PTR_ERR(hsudc->uclk);
1340  goto err_res;
1341  }
1342  clk_enable(hsudc->uclk);
1343 
1345 
1346  disable_irq(hsudc->irq);
1347  local_irq_enable();
1348 
1349  ret = device_register(&hsudc->gadget.dev);
1350  if (ret) {
1351  put_device(&hsudc->gadget.dev);
1352  goto err_add_device;
1353  }
1354 
1355  ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1356  if (ret)
1357  goto err_add_udc;
1358 
1359  pm_runtime_enable(dev);
1360 
1361  return 0;
1362 err_add_udc:
1363  device_unregister(&hsudc->gadget.dev);
1364 err_add_device:
1365  clk_disable(hsudc->uclk);
1366 err_res:
1367  if (!IS_ERR_OR_NULL(hsudc->transceiver))
1368  usb_put_phy(hsudc->transceiver);
1369 
1371 err_supplies:
1372  return ret;
1373 }
1374 
1375 static struct platform_driver s3c_hsudc_driver = {
1376  .driver = {
1377  .owner = THIS_MODULE,
1378  .name = "s3c-hsudc",
1379  },
1380  .probe = s3c_hsudc_probe,
1381 };
1382 
1383 module_platform_driver(s3c_hsudc_driver);
1384 
1385 MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1386 MODULE_AUTHOR("Thomas Abraham <[email protected]>");
1387 MODULE_LICENSE("GPL");
1388 MODULE_ALIAS("platform:s3c-hsudc");