26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/ptrace.h>
29 #include <linux/slab.h>
30 #include <linux/wait.h>
41 #include <asm/kexec.h>
85 struct spu_priv2 __iomem *priv2 = spu->priv2;
89 if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
90 out_be64(&priv2->slb_invalidate_all_W, 0
UL);
91 spin_unlock_irqrestore(&spu->register_lock, flags);
108 spin_unlock_irqrestore(&spu_full_list_lock, flags);
114 static inline void mm_needs_global_tlbie(
struct mm_struct *mm)
128 spin_unlock_irqrestore(&spu_full_list_lock, flags);
130 mm_needs_global_tlbie(mm);
140 static void spu_restart_dma(
struct spu *spu)
142 struct spu_priv2
__iomem *priv2 = spu->priv2;
144 if (!
test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
145 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
147 set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags);
152 static inline void spu_load_slb(
struct spu *spu,
int slbe,
struct spu_slb *slb)
154 struct spu_priv2
__iomem *priv2 = spu->priv2;
156 pr_debug(
"%s: adding SLB[%d] 0x%016llx 0x%016llx\n",
157 __func__, slbe, slb->
vsid, slb->
esid);
159 out_be64(&priv2->slb_index_W, slbe);
161 out_be64(&priv2->slb_esid_RW, 0);
163 out_be64(&priv2->slb_vsid_RW, slb->
vsid);
165 out_be64(&priv2->slb_esid_RW, slb->
esid);
168 static int __spu_trap_data_seg(
struct spu *spu,
unsigned long ea)
180 #ifdef CONFIG_PPC_MM_SLICES
205 pr_debug(
"invalid region access at %016lx\n", ea);
210 spu_load_slb(spu, spu->slb_replace, &slb);
213 if (spu->slb_replace >= 8)
214 spu->slb_replace = 0;
216 spu_restart_dma(spu);
217 spu->stats.slb_flt++;
222 static int __spu_trap_data_map(
struct spu *spu,
unsigned long ea,
u64 dsisr)
226 pr_debug(
"%s, %llx, %lx\n", __func__, dsisr, ea);
232 if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) &&
235 spin_unlock(&spu->register_lock);
237 spin_lock(&spu->register_lock);
240 spu_restart_dma(spu);
245 spu->class_1_dar =
ea;
246 spu->class_1_dsisr = dsisr;
248 spu->stop_callback(spu, 1);
250 spu->class_1_dar = 0;
251 spu->class_1_dsisr = 0;
256 static void __spu_kernel_slb(
void *
addr,
struct spu_slb *slb)
258 unsigned long ea = (
unsigned long)addr;
275 static inline int __slb_present(
struct spu_slb *slbs,
int nr_slbs,
278 unsigned long ea = (
unsigned long)new_addr;
281 for (i = 0; i < nr_slbs; i++)
298 void *
code,
int code_size)
304 lscsa, (
void *)lscsa +
sizeof(*lscsa) - 1,
305 code, code + code_size - 1
311 if (__slb_present(slbs, nr_slbs, addrs[i]))
314 __spu_kernel_slb(addrs[i], &slbs[nr_slbs]);
318 spin_lock_irq(&spu->register_lock);
320 for (i = 0; i < nr_slbs; i++)
321 spu_load_slb(spu, i, &slbs[i]);
322 spin_unlock_irq(&spu->register_lock);
327 spu_irq_class_0(
int irq,
void *
data)
334 spin_lock(&spu->register_lock);
335 mask = spu_int_mask_get(spu, 0);
336 stat = spu_int_stat_get(spu, 0) &
mask;
338 spu->class_0_pending |=
stat;
339 spu->class_0_dar = spu_mfc_dar_get(spu);
340 spu->stop_callback(spu, 0);
341 spu->class_0_pending = 0;
342 spu->class_0_dar = 0;
344 spu_int_stat_clear(spu, 0, stat);
345 spin_unlock(&spu->register_lock);
351 spu_irq_class_1(
int irq,
void *data)
359 spin_lock(&spu->register_lock);
360 mask = spu_int_mask_get(spu, 1);
361 stat = spu_int_stat_get(spu, 1) &
mask;
362 dar = spu_mfc_dar_get(spu);
363 dsisr = spu_mfc_dsisr_get(spu);
364 if (stat & CLASS1_STORAGE_FAULT_INTR)
365 spu_mfc_dsisr_set(spu, 0ul);
366 spu_int_stat_clear(spu, 1, stat);
368 pr_debug(
"%s: %lx %lx %lx %lx\n", __func__, mask, stat,
371 if (stat & CLASS1_SEGMENT_FAULT_INTR)
372 __spu_trap_data_seg(spu, dar);
374 if (stat & CLASS1_STORAGE_FAULT_INTR)
375 __spu_trap_data_map(spu, dar, dsisr);
377 if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR)
380 if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR)
383 spu->class_1_dsisr = 0;
384 spu->class_1_dar = 0;
386 spin_unlock(&spu->register_lock);
392 spu_irq_class_2(
int irq,
void *data)
397 const int mailbox_intrs =
398 CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR;
401 spin_lock(&spu->register_lock);
402 stat = spu_int_stat_get(spu, 2);
403 mask = spu_int_mask_get(spu, 2);
408 if (stat & mailbox_intrs)
409 spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs));
411 spu_int_stat_clear(spu, 2, stat);
413 pr_debug(
"class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
415 if (stat & CLASS2_MAILBOX_INTR)
416 spu->ibox_callback(spu);
418 if (stat & CLASS2_SPU_STOP_INTR)
419 spu->stop_callback(spu, 2);
421 if (stat & CLASS2_SPU_HALT_INTR)
422 spu->stop_callback(spu, 2);
424 if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR)
425 spu->mfc_callback(spu);
427 if (stat & CLASS2_MAILBOX_THRESHOLD_INTR)
428 spu->wbox_callback(spu);
430 spu->stats.class2_intr++;
432 spin_unlock(&spu->register_lock);
437 static int spu_request_irqs(
struct spu *spu)
441 if (spu->irqs[0] !=
NO_IRQ) {
445 0, spu->irq_c0, spu);
449 if (spu->irqs[1] !=
NO_IRQ) {
453 0, spu->irq_c1, spu);
457 if (spu->irqs[2] !=
NO_IRQ) {
461 0, spu->irq_c2, spu);
468 if (spu->irqs[1] !=
NO_IRQ)
471 if (spu->irqs[0] !=
NO_IRQ)
477 static void spu_free_irqs(
struct spu *spu)
479 if (spu->irqs[0] !=
NO_IRQ)
481 if (spu->irqs[1] !=
NO_IRQ)
483 if (spu->irqs[2] !=
NO_IRQ)
489 static const struct {
493 { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
494 { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
496 { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
497 { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
498 { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
500 struct spu_priv2 __iomem *priv2;
509 out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
510 for (count = 0; count < zero_list[
i].count; count++)
511 out_be64(&priv2->spu_chnldata_RW, 0);
515 for (i = 0; i <
ARRAY_SIZE(count_list); i++) {
516 out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
517 out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
522 static struct bus_type spu_subsys = {
552 __func__, attrs->
name);
555 &spu_full_list, full_list)
590 static int spu_create_dev(
struct spu *spu)
594 spu->dev.id = spu->number;
595 spu->dev.bus = &spu_subsys;
603 sysfs_add_device_to_node(&spu->dev, spu->node);
608 static int __init create_spu(
void *data)
621 spu->alloc_state = SPU_FREE;
624 spin_lock(&spu_lock);
625 spu->number = number++;
626 spin_unlock(&spu_lock);
628 ret = spu_create_spu(spu, data);
633 spu_mfc_sdr_setup(spu);
634 spu_mfc_sr1_set(spu, 0x33);
635 ret = spu_request_irqs(spu);
639 ret = spu_create_dev(spu);
644 list_add(&spu->cbe_list, &
cbe_spu_info[spu->node].spus);
650 list_add(&spu->full_list, &spu_full_list);
651 spin_unlock_irqrestore(&spu_full_list_lock, flags);
654 spu->stats.util_state = SPU_UTIL_IDLE_LOADED;
656 spu->stats.tstamp = timespec_to_ns(&
ts);
658 INIT_LIST_HEAD(&spu->aff_list);
665 spu_destroy_spu(spu);
672 static const char *spu_state_names[] = {
673 "user",
"system",
"iowait",
"idle"
676 static unsigned long long spu_acct_time(
struct spu *spu,
677 enum spu_utilization_state
state)
680 unsigned long long time = spu->stats.times[
state];
687 if (spu->stats.util_state == state) {
689 time += timespec_to_ns(&
ts) - spu->stats.tstamp;
701 return sprintf(buf,
"%s %llu %llu %llu %llu "
702 "%llu %llu %llu %llu %llu %llu %llu %llu\n",
703 spu_state_names[spu->stats.util_state],
704 spu_acct_time(spu, SPU_UTIL_USER),
705 spu_acct_time(spu, SPU_UTIL_SYSTEM),
706 spu_acct_time(spu, SPU_UTIL_IOWAIT),
707 spu_acct_time(spu, SPU_UTIL_IDLE_LOADED),
708 spu->stats.vol_ctx_switch,
709 spu->stats.invol_ctx_switch,
714 spu->stats.class2_intr,
715 spu->stats.libassist);
722 struct crash_spu_info {
724 u32 saved_spu_runcntl_RW;
725 u32 saved_spu_status_R;
726 u32 saved_spu_npc_RW;
727 u64 saved_mfc_sr1_RW;
732 #define CRASH_NUM_SPUS 16
733 static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS];
735 static void crash_kexec_stop_spus(
void)
741 for (i = 0; i < CRASH_NUM_SPUS; i++) {
742 if (!crash_spu_info[i].spu)
745 spu = crash_spu_info[
i].spu;
747 crash_spu_info[
i].saved_spu_runcntl_RW =
748 in_be32(&spu->problem->spu_runcntl_RW);
749 crash_spu_info[
i].saved_spu_status_R =
750 in_be32(&spu->problem->spu_status_R);
751 crash_spu_info[
i].saved_spu_npc_RW =
752 in_be32(&spu->problem->spu_npc_RW);
754 crash_spu_info[
i].saved_mfc_dar = spu_mfc_dar_get(spu);
755 crash_spu_info[
i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu);
756 tmp = spu_mfc_sr1_get(spu);
757 crash_spu_info[
i].saved_mfc_sr1_RW =
tmp;
759 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
760 spu_mfc_sr1_set(spu, tmp);
772 if (
WARN_ON(spu->number >= CRASH_NUM_SPUS))
775 crash_spu_info[spu->number].spu = spu;
784 static inline void crash_register_spus(
struct list_head *list)
789 static void spu_shutdown(
void)
796 spu_destroy_spu(spu);
802 .shutdown = spu_shutdown,
805 static int __init init_spu_base(
void)
822 ret = spu_enumerate_spus(create_spu);
827 goto out_unregister_subsys;
831 fb_append_extra_logo(&logo_spe_clut224, ret);
834 xmon_register_spus(&spu_full_list);
835 crash_register_spus(&spu_full_list);
844 out_unregister_subsys: