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Linux Kernel
3.7.1
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#include <linux/module.h>#include <linux/stddef.h>#include <linux/kernel.h>#include <linux/string.h>#include <linux/errno.h>#include <linux/interrupt.h>#include <linux/init.h>#include <linux/ioport.h>#include <linux/delay.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/skbuff.h>#include <linux/bitops.h>#include <asm/cacheflush.h>#include <asm/setup.h>#include <asm/irq.h>#include <asm/io.h>#include <asm/pgtable.h>#include <asm/dvma.h>#include <asm/idprom.h>#include <asm/machines.h>#include <asm/sun3xprom.h>Go to the source code of this file.
Data Structures | |
| struct | lance_rx_head |
| struct | lance_tx_head |
| struct | lance_init_block |
| struct | lance_memory |
| struct | lance_private |
Macros | |
| #define | LANCE_OBIO 0x120000 |
| #define | LANCE_IRQ IRQ_AUTO_3 |
| #define | LANCE_DEBUG 0 |
| #define | DPRINTK(n, a) |
| #define | TX_LOG_RING_SIZE 3 |
| #define | RX_LOG_RING_SIZE 5 |
| #define | TX_RING_SIZE (1 << TX_LOG_RING_SIZE) |
| #define | TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5) |
| #define | TX_RING_MOD_MASK (TX_RING_SIZE - 1) |
| #define | RX_RING_SIZE (1 << RX_LOG_RING_SIZE) |
| #define | RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5) |
| #define | RX_RING_MOD_MASK (RX_RING_SIZE - 1) |
| #define | PKT_BUF_SZ 1544 |
| #define | PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base) |
| #define | MEM lp->mem |
| #define | DREG lp->iobase[0] |
| #define | AREG lp->iobase[1] |
| #define | REGA(a) (*( AREG = (a), &DREG )) |
| #define | TMD1_ENP 0x01 /* end of packet */ |
| #define | TMD1_STP 0x02 /* start of packet */ |
| #define | TMD1_DEF 0x04 /* deferred */ |
| #define | TMD1_ONE 0x08 /* one retry needed */ |
| #define | TMD1_MORE 0x10 /* more than one retry needed */ |
| #define | TMD1_ERR 0x40 /* error summary */ |
| #define | TMD1_OWN 0x80 /* ownership (set: chip owns) */ |
| #define | TMD1_OWN_CHIP TMD1_OWN |
| #define | TMD1_OWN_HOST 0 |
| #define | TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */ |
| #define | TMD3_RTRY 0x0400 /* failed after 16 retries */ |
| #define | TMD3_LCAR 0x0800 /* carrier lost */ |
| #define | TMD3_LCOL 0x1000 /* late collision */ |
| #define | TMD3_UFLO 0x4000 /* underflow (late memory) */ |
| #define | TMD3_BUFF 0x8000 /* buffering error (no ENP) */ |
| #define | RMD1_ENP 0x01 /* end of packet */ |
| #define | RMD1_STP 0x02 /* start of packet */ |
| #define | RMD1_BUFF 0x04 /* buffer error */ |
| #define | RMD1_CRC 0x08 /* CRC error */ |
| #define | RMD1_OFLO 0x10 /* overflow */ |
| #define | RMD1_FRAM 0x20 /* framing error */ |
| #define | RMD1_ERR 0x40 /* error summary */ |
| #define | RMD1_OWN 0x80 /* ownership (set: ship owns) */ |
| #define | RMD1_OWN_CHIP RMD1_OWN |
| #define | RMD1_OWN_HOST 0 |
| #define | CSR0 0 /* mode/status */ |
| #define | CSR1 1 /* init block addr (low) */ |
| #define | CSR2 2 /* init block addr (high) */ |
| #define | CSR3 3 /* misc */ |
| #define | CSR8 8 /* address filter */ |
| #define | CSR15 15 /* promiscuous mode */ |
| #define | CSR0_INIT 0x0001 /* initialize (RS) */ |
| #define | CSR0_STRT 0x0002 /* start (RS) */ |
| #define | CSR0_STOP 0x0004 /* stop (RS) */ |
| #define | CSR0_TDMD 0x0008 /* transmit demand (RS) */ |
| #define | CSR0_TXON 0x0010 /* transmitter on (R) */ |
| #define | CSR0_RXON 0x0020 /* receiver on (R) */ |
| #define | CSR0_INEA 0x0040 /* interrupt enable (RW) */ |
| #define | CSR0_INTR 0x0080 /* interrupt active (R) */ |
| #define | CSR0_IDON 0x0100 /* initialization done (RC) */ |
| #define | CSR0_TINT 0x0200 /* transmitter interrupt (RC) */ |
| #define | CSR0_RINT 0x0400 /* receiver interrupt (RC) */ |
| #define | CSR0_MERR 0x0800 /* memory error (RC) */ |
| #define | CSR0_MISS 0x1000 /* missed frame (RC) */ |
| #define | CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */ |
| #define | CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */ |
| #define | CSR0_ERR 0x8000 /* error (RC) */ |
| #define | CSR3_BCON 0x0001 /* byte control */ |
| #define | CSR3_ACON 0x0002 /* ALE control */ |
| #define | CSR3_BSWP 0x0004 /* byte swap (1=big endian) */ |
Functions | |
| module_param (lance_debug, int, 0) | |
| MODULE_PARM_DESC (lance_debug,"SUN3 Lance debug level (0-3)") | |
| MODULE_LICENSE ("GPL") | |
| struct net_device *__init | sun3lance_probe (int unit) |
Definition at line 163 of file sun3lance.c.
Definition at line 202 of file sun3lance.c.
| #define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */ |
Definition at line 225 of file sun3lance.c.
| #define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */ |
Definition at line 224 of file sun3lance.c.
| #define CSR0_ERR 0x8000 /* error (RC) */ |
Definition at line 226 of file sun3lance.c.
| #define CSR0_IDON 0x0100 /* initialization done (RC) */ |
Definition at line 219 of file sun3lance.c.
| #define CSR0_INEA 0x0040 /* interrupt enable (RW) */ |
Definition at line 217 of file sun3lance.c.
| #define CSR0_INIT 0x0001 /* initialize (RS) */ |
Definition at line 211 of file sun3lance.c.
| #define CSR0_INTR 0x0080 /* interrupt active (R) */ |
Definition at line 218 of file sun3lance.c.
| #define CSR0_MERR 0x0800 /* memory error (RC) */ |
Definition at line 222 of file sun3lance.c.
| #define CSR0_MISS 0x1000 /* missed frame (RC) */ |
Definition at line 223 of file sun3lance.c.
| #define CSR0_RINT 0x0400 /* receiver interrupt (RC) */ |
Definition at line 221 of file sun3lance.c.
| #define CSR0_RXON 0x0020 /* receiver on (R) */ |
Definition at line 216 of file sun3lance.c.
| #define CSR0_STOP 0x0004 /* stop (RS) */ |
Definition at line 213 of file sun3lance.c.
| #define CSR0_STRT 0x0002 /* start (RS) */ |
Definition at line 212 of file sun3lance.c.
| #define CSR0_TDMD 0x0008 /* transmit demand (RS) */ |
Definition at line 214 of file sun3lance.c.
| #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */ |
Definition at line 220 of file sun3lance.c.
| #define CSR0_TXON 0x0010 /* transmitter on (R) */ |
Definition at line 215 of file sun3lance.c.
| #define CSR15 15 /* promiscuous mode */ |
Definition at line 207 of file sun3lance.c.
| #define CSR3 3 /* misc */ |
Definition at line 205 of file sun3lance.c.
| #define CSR3_ACON 0x0002 /* ALE control */ |
Definition at line 230 of file sun3lance.c.
| #define CSR3_BCON 0x0001 /* byte control */ |
Definition at line 229 of file sun3lance.c.
| #define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */ |
Definition at line 231 of file sun3lance.c.
Definition at line 206 of file sun3lance.c.
Definition at line 78 of file sun3lance.c.
Definition at line 162 of file sun3lance.c.
| #define LANCE_DEBUG 0 |
Definition at line 67 of file sun3lance.c.
| #define LANCE_IRQ IRQ_AUTO_3 |
Definition at line 58 of file sun3lance.c.
| #define LANCE_OBIO 0x120000 |
Definition at line 57 of file sun3lance.c.
Definition at line 161 of file sun3lance.c.
| #define PKT_BUF_SZ 1544 |
Definition at line 102 of file sun3lance.c.
Definition at line 105 of file sun3lance.c.
| #define RMD1_BUFF 0x04 /* buffer error */ |
Definition at line 191 of file sun3lance.c.
| #define RMD1_CRC 0x08 /* CRC error */ |
Definition at line 192 of file sun3lance.c.
| #define RMD1_ENP 0x01 /* end of packet */ |
Definition at line 189 of file sun3lance.c.
| #define RMD1_ERR 0x40 /* error summary */ |
Definition at line 195 of file sun3lance.c.
| #define RMD1_FRAM 0x20 /* framing error */ |
Definition at line 194 of file sun3lance.c.
| #define RMD1_OFLO 0x10 /* overflow */ |
Definition at line 193 of file sun3lance.c.
| #define RMD1_OWN 0x80 /* ownership (set: ship owns) */ |
Definition at line 196 of file sun3lance.c.
| #define RMD1_OWN_CHIP RMD1_OWN |
Definition at line 198 of file sun3lance.c.
| #define RMD1_OWN_HOST 0 |
Definition at line 199 of file sun3lance.c.
| #define RMD1_STP 0x02 /* start of packet */ |
Definition at line 190 of file sun3lance.c.
| #define RX_LOG_RING_SIZE 5 |
Definition at line 89 of file sun3lance.c.
| #define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5) |
Definition at line 98 of file sun3lance.c.
| #define RX_RING_MOD_MASK (RX_RING_SIZE - 1) |
Definition at line 99 of file sun3lance.c.
| #define RX_RING_SIZE (1 << RX_LOG_RING_SIZE) |
Definition at line 97 of file sun3lance.c.
| #define TMD1_DEF 0x04 /* deferred */ |
Definition at line 171 of file sun3lance.c.
| #define TMD1_ENP 0x01 /* end of packet */ |
Definition at line 169 of file sun3lance.c.
| #define TMD1_ERR 0x40 /* error summary */ |
Definition at line 174 of file sun3lance.c.
| #define TMD1_MORE 0x10 /* more than one retry needed */ |
Definition at line 173 of file sun3lance.c.
| #define TMD1_ONE 0x08 /* one retry needed */ |
Definition at line 172 of file sun3lance.c.
| #define TMD1_OWN 0x80 /* ownership (set: chip owns) */ |
Definition at line 175 of file sun3lance.c.
| #define TMD1_OWN_CHIP TMD1_OWN |
Definition at line 177 of file sun3lance.c.
| #define TMD1_OWN_HOST 0 |
Definition at line 178 of file sun3lance.c.
| #define TMD1_STP 0x02 /* start of packet */ |
Definition at line 170 of file sun3lance.c.
| #define TMD3_BUFF 0x8000 /* buffering error (no ENP) */ |
Definition at line 186 of file sun3lance.c.
| #define TMD3_LCAR 0x0800 /* carrier lost */ |
Definition at line 183 of file sun3lance.c.
| #define TMD3_LCOL 0x1000 /* late collision */ |
Definition at line 184 of file sun3lance.c.
| #define TMD3_RTRY 0x0400 /* failed after 16 retries */ |
Definition at line 182 of file sun3lance.c.
| #define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */ |
Definition at line 181 of file sun3lance.c.
| #define TMD3_UFLO 0x4000 /* underflow (late memory) */ |
Definition at line 185 of file sun3lance.c.
| #define TX_LOG_RING_SIZE 3 |
Definition at line 88 of file sun3lance.c.
| #define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5) |
Definition at line 94 of file sun3lance.c.
| #define TX_RING_MOD_MASK (TX_RING_SIZE - 1) |
Definition at line 95 of file sun3lance.c.
| #define TX_RING_SIZE (1 << TX_LOG_RING_SIZE) |
Definition at line 93 of file sun3lance.c.
| MODULE_LICENSE | ( | "GPL" | ) |
| module_param | ( | lance_debug | , |
| int | , | ||
| 0 | |||
| ) |
|
read |
Definition at line 246 of file sun3lance.c.
1.8.2