15 #include <linux/kernel.h>
16 #include <linux/types.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
21 #include <linux/bitops.h>
23 #include <asm/ptrace.h>
26 #include <asm/mmu_context.h>
28 #include <asm/pgtable.h>
31 #include <asm/tlbflush.h>
40 static unsigned long cached_irq_mask;
42 static unsigned long cpu_irq_affinity[4] = { 0
UL, 0
UL, 0
UL, 0UL };
47 tsunami_update_irq_hw(
unsigned long mask)
50 unsigned long isa_enable = 1
UL << 55;
54 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
55 unsigned long mask0, mask1, mask2, mask3,
dummy;
58 mask0 = mask & cpu_irq_affinity[0];
59 mask1 = mask & cpu_irq_affinity[1];
60 mask2 = mask & cpu_irq_affinity[2];
61 mask3 = mask & cpu_irq_affinity[3];
63 if (bcpu == 0) mask0 |= isa_enable;
64 else if (bcpu == 1) mask1 |= isa_enable;
65 else if (bcpu == 2) mask2 |= isa_enable;
66 else mask3 |= isa_enable;
68 dim0 = &cchip->
dim0.csr;
69 dim1 = &cchip->
dim1.csr;
70 dim2 = &cchip->
dim2.csr;
71 dim3 = &cchip->
dim3.csr;
87 volatile unsigned long *dimB;
88 if (bcpu == 0) dimB = &cchip->
dim0.csr;
89 else if (bcpu == 1) dimB = &cchip->
dim1.csr;
90 else if (bcpu == 2) dimB = &cchip->
dim2.csr;
91 else dimB = &cchip->
dim3.csr;
93 *dimB = mask | isa_enable;
102 spin_lock(&dp264_irq_lock);
103 cached_irq_mask |= 1
UL << d->
irq;
104 tsunami_update_irq_hw(cached_irq_mask);
105 spin_unlock(&dp264_irq_lock);
111 spin_lock(&dp264_irq_lock);
112 cached_irq_mask &= ~(1
UL << d->
irq);
113 tsunami_update_irq_hw(cached_irq_mask);
114 spin_unlock(&dp264_irq_lock);
120 spin_lock(&dp264_irq_lock);
121 cached_irq_mask |= 1
UL << (d->
irq - 16);
122 tsunami_update_irq_hw(cached_irq_mask);
123 spin_unlock(&dp264_irq_lock);
129 spin_lock(&dp264_irq_lock);
130 cached_irq_mask &= ~(1
UL << (d->
irq - 16));
131 tsunami_update_irq_hw(cached_irq_mask);
132 spin_unlock(&dp264_irq_lock);
140 for (cpu = 0; cpu < 4; cpu++) {
141 unsigned long aff = cpu_irq_affinity[
cpu];
145 aff &= ~(1
UL << irq);
146 cpu_irq_affinity[
cpu] = aff;
154 spin_lock(&dp264_irq_lock);
155 cpu_set_irq_affinity(d->
irq, *affinity);
156 tsunami_update_irq_hw(cached_irq_mask);
157 spin_unlock(&dp264_irq_lock);
166 spin_lock(&dp264_irq_lock);
167 cpu_set_irq_affinity(d->
irq - 16, *affinity);
168 tsunami_update_irq_hw(cached_irq_mask);
169 spin_unlock(&dp264_irq_lock);
174 static struct irq_chip dp264_irq_type = {
176 .irq_unmask = dp264_enable_irq,
177 .irq_mask = dp264_disable_irq,
178 .irq_mask_ack = dp264_disable_irq,
179 .irq_set_affinity = dp264_set_affinity,
182 static struct irq_chip clipper_irq_type = {
184 .irq_unmask = clipper_enable_irq,
185 .irq_mask = clipper_disable_irq,
186 .irq_mask_ack = clipper_disable_irq,
187 .irq_set_affinity = clipper_set_affinity,
191 dp264_device_interrupt(
unsigned long vector)
194 printk(
"dp264_device_interrupt: NOT IMPLEMENTED YET!!\n");
222 dp264_srm_device_interrupt(
unsigned long vector)
226 irq = (vector - 0x800) >> 4;
246 clipper_srm_device_interrupt(
unsigned long vector)
250 irq = (vector - 0x800) >> 4;
268 init_tsunami_irqs(
struct irq_chip * ops,
int imin,
int imax)
271 for (i = imin; i <= imax; ++
i) {
286 alpha_mv.device_interrupt = dp264_srm_device_interrupt;
288 tsunami_update_irq_hw(0);
291 init_tsunami_irqs(&dp264_irq_type, 16, 47);
295 clipper_init_irq(
void)
303 alpha_mv.device_interrupt = clipper_srm_device_interrupt;
305 tsunami_update_irq_hw(0);
308 init_tsunami_irqs(&clipper_irq_type, 24, 63);
368 isa_irq_fixup(
const struct pci_dev *
dev,
int irq)
388 { -1, -1, -1, -1, -1},
389 { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2},
390 { 16+15, 16+15, 16+14, 16+13, 16+12},
391 { 16+11, 16+11, 16+10, 16+ 9, 16+ 8},
392 { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4},
393 { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0}
395 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
400 irq += 16 * hose->
index;
402 return isa_irq_fixup(dev, irq);
406 monet_map_irq(
const struct pci_dev *dev,
u8 slot,
u8 pin)
408 static char irq_tab[13][5] __initdata = {
410 { 45, 45, 45, 45, 45},
411 { -1, -1, -1, -1, -1},
412 { -1, -1, -1, -1, -1},
413 { 47, 47, 47, 47, 47},
414 { -1, -1, -1, -1, -1},
415 { -1, -1, -1, -1, -1},
417 { 28, 28, 29, 30, 31},
418 { 24, 24, 25, 26, 27},
420 { -1, -1, -1, -1, -1},
421 { -1, -1, -1, -1, -1},
423 { 40, 40, 41, 42, 43},
424 { 36, 36, 37, 38, 39},
425 { 32, 32, 33, 34, 35},
426 { 28, 28, 29, 30, 31},
427 { 24, 24, 25, 26, 27}
429 const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
435 monet_swizzle(
struct pci_dev *dev,
u8 *pinp)
438 int slot, pin = *pinp;
440 if (!dev->
bus->parent) {
450 if (hose->
index == 1 &&
458 dev = dev->
bus->self;
461 }
while (dev->
bus->self);
468 webbrick_map_irq(
const struct pci_dev *dev,
u8 slot,
u8 pin)
470 static char irq_tab[13][5] __initdata = {
472 { -1, -1, -1, -1, -1},
473 { -1, -1, -1, -1, -1},
474 { 29, 29, 29, 29, 29},
475 { -1, -1, -1, -1, -1},
476 { 30, 30, 30, 30, 30},
477 { -1, -1, -1, -1, -1},
478 { -1, -1, -1, -1, -1},
479 { 35, 35, 34, 33, 32},
480 { 39, 39, 38, 37, 36},
481 { 43, 43, 42, 41, 40},
482 { 47, 47, 46, 45, 44},
484 const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
490 clipper_map_irq(
const struct pci_dev *dev,
u8 slot,
u8 pin)
492 static char irq_tab[7][5] __initdata = {
494 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11},
495 { 16+12, 16+12, 16+13, 16+14, 16+15},
496 { 16+16, 16+16, 16+17, 16+18, 16+19},
497 { 16+20, 16+20, 16+21, 16+22, 16+23},
498 { 16+24, 16+24, 16+25, 16+26, 16+27},
499 { 16+28, 16+28, 16+29, 16+30, 16+31},
500 { -1, -1, -1, -1, -1}
502 const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
507 irq += 16 * hose->
index;
509 return isa_irq_fixup(dev, irq);
517 locate_and_init_vga(
NULL);
526 locate_and_init_vga(
NULL);
530 clipper_init_pci(
void)
533 locate_and_init_vga(
NULL);
537 webbrick_init_arch(
void)
552 .vector_name =
"DP264",
563 .device_interrupt = dp264_device_interrupt,
566 .init_irq = dp264_init_irq,
568 .init_pci = dp264_init_pci,
570 .pci_map_irq = dp264_map_irq,
575 struct alpha_machine_vector monet_mv __initmv = {
576 .vector_name =
"Monet",
587 .device_interrupt = dp264_device_interrupt,
590 .init_irq = dp264_init_irq,
592 .init_pci = monet_init_pci,
594 .pci_map_irq = monet_map_irq,
595 .pci_swizzle = monet_swizzle,
598 struct alpha_machine_vector webbrick_mv __initmv = {
599 .vector_name =
"Webbrick",
610 .device_interrupt = dp264_device_interrupt,
612 .init_arch = webbrick_init_arch,
613 .init_irq = dp264_init_irq,
617 .pci_map_irq = webbrick_map_irq,
621 struct alpha_machine_vector clipper_mv __initmv = {
622 .vector_name =
"Clipper",
633 .device_interrupt = dp264_device_interrupt,
636 .init_irq = clipper_init_irq,
638 .init_pci = clipper_init_pci,
640 .pci_map_irq = clipper_map_irq,
649 struct alpha_machine_vector shark_mv __initmv = {
650 .vector_name =
"Shark",
661 .device_interrupt = dp264_device_interrupt,
664 .init_irq = clipper_init_irq,
668 .pci_map_irq = clipper_map_irq,