|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Data Structures | |
| struct | axidma_bd |
| struct | axienet_local |
| struct | axienet_option |
Macros | |
| #define | XAE_HDR_SIZE 14 /* Size of Ethernet header */ |
| #define | XAE_HDR_VLAN_SIZE 18 /* Size of an Ethernet hdr + VLAN */ |
| #define | XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */ |
| #define | XAE_MTU 1500 /* Max MTU of an Ethernet frame */ |
| #define | XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */ |
| #define | XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) |
| #define | XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + XAE_HDR_VLAN_SIZE + XAE_TRL_SIZE) |
| #define | XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) |
| #define | XAE_OPTION_PROMISC (1 << 0) |
| #define | XAE_OPTION_JUMBO (1 << 1) |
| #define | XAE_OPTION_VLAN (1 << 2) |
| #define | XAE_OPTION_FLOW_CONTROL (1 << 4) |
| #define | XAE_OPTION_FCS_STRIP (1 << 5) |
| #define | XAE_OPTION_FCS_INSERT (1 << 6) |
| #define | XAE_OPTION_LENTYPE_ERR (1 << 7) |
| #define | XAE_OPTION_TXEN (1 << 11) |
| #define | XAE_OPTION_RXEN (1 << 12) |
| #define | XAE_OPTION_DEFAULTS |
| #define | XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */ |
| #define | XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */ |
| #define | XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */ |
| #define | XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */ |
| #define | XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */ |
| #define | XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */ |
| #define | XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */ |
| #define | XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */ |
| #define | XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ |
| #define | XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ |
| #define | XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */ |
| #define | XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */ |
| #define | XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */ |
| #define | XAXIDMA_BD_STS_OFFSET 0x1C /* Status */ |
| #define | XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */ |
| #define | XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */ |
| #define | XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */ |
| #define | XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */ |
| #define | XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */ |
| #define | XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */ |
| #define | XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */ |
| #define | XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */ |
| #define | XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */ |
| #define | XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */ |
| #define | XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */ |
| #define | XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */ |
| #define | XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ |
| #define | XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ |
| #define | XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ |
| #define | XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */ |
| #define | XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */ |
| #define | XAXIDMA_DELAY_SHIFT 24 |
| #define | XAXIDMA_COALESCE_SHIFT 16 |
| #define | XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ |
| #define | XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ |
| #define | XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */ |
| #define | XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ |
| #define | XAXIDMA_DFT_TX_THRESHOLD 24 |
| #define | XAXIDMA_DFT_TX_WAITBOUND 254 |
| #define | XAXIDMA_DFT_RX_THRESHOLD 24 |
| #define | XAXIDMA_DFT_RX_WAITBOUND 254 |
| #define | XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ |
| #define | XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ |
| #define | XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ |
| #define | XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */ |
| #define | XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */ |
| #define | XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */ |
| #define | XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */ |
| #define | XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */ |
| #define | XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */ |
| #define | XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */ |
| #define | XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */ |
| #define | XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */ |
| #define | XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40 |
| #define | XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */ |
| #define | XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */ |
| #define | XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/ |
| #define | XAE_IS_OFFSET 0x0000000C /* Interrupt status */ |
| #define | XAE_IP_OFFSET 0x00000010 /* Interrupt pending */ |
| #define | XAE_IE_OFFSET 0x00000014 /* Interrupt enable */ |
| #define | XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */ |
| #define | XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */ |
| #define | XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */ |
| #define | XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */ |
| #define | XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */ |
| #define | XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */ |
| #define | XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */ |
| #define | XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */ |
| #define | XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */ |
| #define | XAE_TC_OFFSET 0x00000408 /* Tx Configuration */ |
| #define | XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */ |
| #define | XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */ |
| #define | XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */ |
| #define | XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */ |
| #define | XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */ |
| #define | XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */ |
| #define | XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */ |
| #define | XAE_MDIO_MIS_OFFSET 0x00000600 /* MII Management Interrupt Status */ |
| #define | XAE_MDIO_MIP_OFFSET |
| #define | XAE_MDIO_MIE_OFFSET |
| #define | XAE_MDIO_MIC_OFFSET |
| #define | XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */ |
| #define | XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */ |
| #define | XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */ |
| #define | XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */ |
| #define | XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */ |
| #define | XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */ |
| #define | XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */ |
| #define | XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */ |
| #define | XAE_RAF_MCSTREJ_MASK |
| #define | XAE_RAF_BCSTREJ_MASK |
| #define | XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */ |
| #define | XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */ |
| #define | XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */ |
| #define | XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */ |
| #define | XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */ |
| #define | XAE_RAF_EMULTIFLTRENBL_MASK |
| #define | XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */ |
| #define | XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */ |
| #define | XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */ |
| #define | XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */ |
| #define | XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/ |
| #define | XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/ |
| #define | XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */ |
| #define | XAE_IFGP0_IFGP_MASK |
| #define | XAE_INT_HARDACSCMPLT_MASK |
| #define | XAE_INT_AUTONEG_MASK |
| #define | XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */ |
| #define | XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ |
| #define | XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */ |
| #define | XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */ |
| #define | XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */ |
| #define | XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ |
| #define | XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */ |
| #define | XAE_INT_ALL_MASK 0x0000003F /* All the ints */ |
| #define | XAE_INT_RECV_ERROR_MASK |
| #define | XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */ |
| #define | XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */ |
| #define | XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */ |
| #define | XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */ |
| #define | XAE_RCW1_RST_MASK 0x80000000 /* Reset */ |
| #define | XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */ |
| #define | XAE_RCW1_FCS_MASK |
| #define | XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ |
| #define | XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */ |
| #define | XAE_RCW1_LT_DIS_MASK |
| #define | XAE_RCW1_CL_DIS_MASK |
| #define | XAE_RCW1_PAUSEADDR_MASK |
| #define | XAE_TC_RST_MASK 0x80000000 /* Reset */ |
| #define | XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */ |
| #define | XAE_TC_FCS_MASK |
| #define | XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ |
| #define | XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */ |
| #define | XAE_TC_IFG_MASK |
| #define | XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */ |
| #define | XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */ |
| #define | XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ |
| #define | XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */ |
| #define | XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */ |
| #define | XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */ |
| #define | XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */ |
| #define | XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */ |
| #define | XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */ |
| #define | XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ |
| #define | XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ |
| #define | XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ |
| #define | XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/ |
| #define | XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */ |
| #define | XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */ |
| #define | XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */ |
| #define | XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */ |
| #define | XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */ |
| #define | XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */ |
| #define | XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */ |
| #define | XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */ |
| #define | XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */ |
| #define | XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */ |
| #define | XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */ |
| #define | XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ |
| #define | XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ |
| #define | XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ |
| #define | XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ |
| #define | XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */ |
| #define | XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */ |
| #define | XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ |
| #define | XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ |
| #define | XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ |
| #define | XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ |
| #define | XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */ |
| #define | XAE_UAW1_UNICASTADDR_MASK |
| #define | XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */ |
| #define | XAE_FMI_IND_MASK 0x00000003 /* Index Mask */ |
| #define | XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ |
| #define | XAE_PHY_TYPE_MII 0 |
| #define | XAE_PHY_TYPE_GMII 1 |
| #define | XAE_PHY_TYPE_RGMII_1_3 2 |
| #define | XAE_PHY_TYPE_RGMII_2_0 3 |
| #define | XAE_PHY_TYPE_SGMII 4 |
| #define | XAE_PHY_TYPE_1000BASE_X 5 |
| #define | XAE_MULTICAST_CAM_TABLE_NUM |
| #define | XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0) |
| #define | XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1) |
| #define | XAE_FEATURE_FULL_RX_CSUM (1 << 2) |
| #define | XAE_FEATURE_FULL_TX_CSUM (1 << 3) |
| #define | XAE_NO_CSUM_OFFLOAD 0 |
| #define | XAE_FULL_CSUM_STATUS_MASK 0x00000038 |
| #define | XAE_IP_UDP_CSUM_VALIDATED 0x00000003 |
| #define | XAE_IP_TCP_CSUM_VALIDATED 0x00000002 |
| #define | DELAY_OF_ONE_MILLISEC 1000 |
Functions | |
| int | axienet_mdio_setup (struct axienet_local *lp, struct device_node *np) |
| int | axienet_mdio_wait_until_ready (struct axienet_local *lp) |
| void | axienet_mdio_teardown (struct axienet_local *lp) |
| #define DELAY_OF_ONE_MILLISEC 1000 |
Definition at line 315 of file xilinx_axienet.h.
| #define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */ |
Definition at line 168 of file xilinx_axienet.h.
| #define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */ |
Definition at line 169 of file xilinx_axienet.h.
| #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */ |
Definition at line 245 of file xilinx_axienet.h.
| #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */ |
Definition at line 246 of file xilinx_axienet.h.
| #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ |
Definition at line 249 of file xilinx_axienet.h.
| #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ |
Definition at line 250 of file xilinx_axienet.h.
| #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ |
Definition at line 251 of file xilinx_axienet.h.
| #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ |
Definition at line 242 of file xilinx_axienet.h.
| #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */ |
Definition at line 155 of file xilinx_axienet.h.
| #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */ |
Definition at line 243 of file xilinx_axienet.h.
| #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */ |
Definition at line 248 of file xilinx_axienet.h.
| #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */ |
Definition at line 244 of file xilinx_axienet.h.
| #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */ |
Definition at line 247 of file xilinx_axienet.h.
| #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */ |
Definition at line 238 of file xilinx_axienet.h.
| #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */ |
Definition at line 239 of file xilinx_axienet.h.
| #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */ |
Definition at line 154 of file xilinx_axienet.h.
| #define XAE_FEATURE_FULL_RX_CSUM (1 << 2) |
Definition at line 306 of file xilinx_axienet.h.
| #define XAE_FEATURE_FULL_TX_CSUM (1 << 3) |
Definition at line 307 of file xilinx_axienet.h.
| #define XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0) |
Definition at line 304 of file xilinx_axienet.h.
| #define XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1) |
Definition at line 305 of file xilinx_axienet.h.
| #define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */ |
Definition at line 289 of file xilinx_axienet.h.
| #define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */ |
Definition at line 167 of file xilinx_axienet.h.
| #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */ |
Definition at line 288 of file xilinx_axienet.h.
| #define XAE_FULL_CSUM_STATUS_MASK 0x00000038 |
Definition at line 311 of file xilinx_axienet.h.
Definition at line 16 of file xilinx_axienet.h.
Definition at line 17 of file xilinx_axienet.h.
| #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */ |
Definition at line 143 of file xilinx_axienet.h.
| #define XAE_IFGP0_IFGP_MASK |
Definition at line 193 of file xilinx_axienet.h.
| #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/ |
Definition at line 140 of file xilinx_axienet.h.
| #define XAE_INT_ALL_MASK 0x0000003F /* All the ints */ |
Definition at line 206 of file xilinx_axienet.h.
| #define XAE_INT_AUTONEG_MASK |
Definition at line 198 of file xilinx_axienet.h.
| #define XAE_INT_HARDACSCMPLT_MASK |
Definition at line 197 of file xilinx_axienet.h.
| #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ |
Definition at line 204 of file xilinx_axienet.h.
| #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */ |
Definition at line 205 of file xilinx_axienet.h.
| #define XAE_INT_RECV_ERROR_MASK |
Definition at line 208 of file xilinx_axienet.h.
| #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */ |
Definition at line 199 of file xilinx_axienet.h.
| #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */ |
Definition at line 203 of file xilinx_axienet.h.
| #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */ |
Definition at line 201 of file xilinx_axienet.h.
| #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ |
Definition at line 200 of file xilinx_axienet.h.
| #define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */ |
Definition at line 202 of file xilinx_axienet.h.
| #define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */ |
Definition at line 142 of file xilinx_axienet.h.
| #define XAE_IP_TCP_CSUM_VALIDATED 0x00000002 |
Definition at line 313 of file xilinx_axienet.h.
| #define XAE_IP_UDP_CSUM_VALIDATED 0x00000003 |
Definition at line 312 of file xilinx_axienet.h.
| #define XAE_IS_OFFSET 0x0000000C /* Interrupt status */ |
Definition at line 141 of file xilinx_axienet.h.
Definition at line 20 of file xilinx_axienet.h.
| #define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) |
Definition at line 22 of file xilinx_axienet.h.
| #define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE) |
Definition at line 24 of file xilinx_axienet.h.
| #define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + XAE_HDR_VLAN_SIZE + XAE_TRL_SIZE) |
Definition at line 23 of file xilinx_axienet.h.
| #define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */ |
Definition at line 173 of file xilinx_axienet.h.
Definition at line 291 of file xilinx_axienet.h.
| #define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */ |
Definition at line 282 of file xilinx_axienet.h.
| #define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */ |
Definition at line 267 of file xilinx_axienet.h.
| #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */ |
Definition at line 266 of file xilinx_axienet.h.
| #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */ |
Definition at line 157 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ |
Definition at line 278 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */ |
Definition at line 158 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */ |
Definition at line 274 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ |
Definition at line 276 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */ |
Definition at line 275 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ |
Definition at line 277 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ |
Definition at line 270 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ |
Definition at line 271 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ |
Definition at line 279 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ |
Definition at line 272 of file xilinx_axienet.h.
| #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ |
Definition at line 273 of file xilinx_axienet.h.
| #define XAE_MDIO_MIC_OFFSET |
Definition at line 164 of file xilinx_axienet.h.
| #define XAE_MDIO_MIE_OFFSET |
Definition at line 163 of file xilinx_axienet.h.
| #define XAE_MDIO_MIP_OFFSET |
Definition at line 162 of file xilinx_axienet.h.
| #define XAE_MDIO_MIS_OFFSET 0x00000600 /* MII Management Interrupt Status */ |
Definition at line 161 of file xilinx_axienet.h.
| #define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */ |
Definition at line 160 of file xilinx_axienet.h.
| #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */ |
Definition at line 159 of file xilinx_axienet.h.
| #define XAE_MTU 1500 /* Max MTU of an Ethernet frame */ |
Definition at line 19 of file xilinx_axienet.h.
| #define XAE_MULTICAST_CAM_TABLE_NUM |
Definition at line 301 of file xilinx_axienet.h.
| #define XAE_NO_CSUM_OFFLOAD 0 |
Definition at line 309 of file xilinx_axienet.h.
| #define XAE_OPTION_DEFAULTS |
Definition at line 62 of file xilinx_axienet.h.
| #define XAE_OPTION_FCS_INSERT (1 << 6) |
Definition at line 46 of file xilinx_axienet.h.
| #define XAE_OPTION_FCS_STRIP (1 << 5) |
Definition at line 42 of file xilinx_axienet.h.
| #define XAE_OPTION_FLOW_CONTROL (1 << 4) |
Definition at line 38 of file xilinx_axienet.h.
| #define XAE_OPTION_JUMBO (1 << 1) |
Definition at line 32 of file xilinx_axienet.h.
| #define XAE_OPTION_LENTYPE_ERR (1 << 7) |
Definition at line 53 of file xilinx_axienet.h.
| #define XAE_OPTION_PROMISC (1 << 0) |
Definition at line 29 of file xilinx_axienet.h.
| #define XAE_OPTION_RXEN (1 << 12) |
Definition at line 59 of file xilinx_axienet.h.
| #define XAE_OPTION_TXEN (1 << 11) |
Definition at line 56 of file xilinx_axienet.h.
| #define XAE_OPTION_VLAN (1 << 2) |
Definition at line 35 of file xilinx_axienet.h.
| #define XAE_PHY_TYPE_1000BASE_X 5 |
Definition at line 299 of file xilinx_axienet.h.
| #define XAE_PHY_TYPE_GMII 1 |
Definition at line 295 of file xilinx_axienet.h.
| #define XAE_PHY_TYPE_MII 0 |
Definition at line 294 of file xilinx_axienet.h.
| #define XAE_PHY_TYPE_RGMII_1_3 2 |
Definition at line 296 of file xilinx_axienet.h.
| #define XAE_PHY_TYPE_RGMII_2_0 3 |
Definition at line 297 of file xilinx_axienet.h.
| #define XAE_PHY_TYPE_SGMII 4 |
Definition at line 298 of file xilinx_axienet.h.
| #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */ |
Definition at line 156 of file xilinx_axienet.h.
| #define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */ |
Definition at line 258 of file xilinx_axienet.h.
| #define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */ |
Definition at line 259 of file xilinx_axienet.h.
| #define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */ |
Definition at line 260 of file xilinx_axienet.h.
| #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */ |
Definition at line 256 of file xilinx_axienet.h.
| #define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */ |
Definition at line 257 of file xilinx_axienet.h.
| #define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */ |
Definition at line 255 of file xilinx_axienet.h.
| #define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */ |
Definition at line 261 of file xilinx_axienet.h.
| #define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */ |
Definition at line 262 of file xilinx_axienet.h.
| #define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */ |
Definition at line 263 of file xilinx_axienet.h.
| #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/ |
Definition at line 254 of file xilinx_axienet.h.
| #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */ |
Definition at line 150 of file xilinx_axienet.h.
| #define XAE_RAF_BCSTREJ_MASK |
Definition at line 177 of file xilinx_axienet.h.
| #define XAE_RAF_EMULTIFLTRENBL_MASK |
Definition at line 183 of file xilinx_axienet.h.
| #define XAE_RAF_MCSTREJ_MASK |
Definition at line 176 of file xilinx_axienet.h.
| #define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */ |
Definition at line 182 of file xilinx_axienet.h.
| #define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */ |
Definition at line 138 of file xilinx_axienet.h.
| #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */ |
Definition at line 185 of file xilinx_axienet.h.
| #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */ |
Definition at line 181 of file xilinx_axienet.h.
Definition at line 189 of file xilinx_axienet.h.
| #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */ |
Definition at line 179 of file xilinx_axienet.h.
Definition at line 187 of file xilinx_axienet.h.
| #define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */ |
Definition at line 184 of file xilinx_axienet.h.
| #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */ |
Definition at line 180 of file xilinx_axienet.h.
Definition at line 188 of file xilinx_axienet.h.
| #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */ |
Definition at line 178 of file xilinx_axienet.h.
Definition at line 186 of file xilinx_axienet.h.
| #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */ |
Definition at line 151 of file xilinx_axienet.h.
| #define XAE_RCW1_CL_DIS_MASK |
Definition at line 226 of file xilinx_axienet.h.
| #define XAE_RCW1_FCS_MASK |
Definition at line 222 of file xilinx_axienet.h.
| #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */ |
Definition at line 221 of file xilinx_axienet.h.
| #define XAE_RCW1_LT_DIS_MASK |
Definition at line 225 of file xilinx_axienet.h.
| #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */ |
Definition at line 152 of file xilinx_axienet.h.
| #define XAE_RCW1_PAUSEADDR_MASK |
Definition at line 227 of file xilinx_axienet.h.
| #define XAE_RCW1_RST_MASK 0x80000000 /* Reset */ |
Definition at line 220 of file xilinx_axienet.h.
| #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ |
Definition at line 223 of file xilinx_axienet.h.
| #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */ |
Definition at line 224 of file xilinx_axienet.h.
| #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */ |
Definition at line 145 of file xilinx_axienet.h.
| #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */ |
Definition at line 172 of file xilinx_axienet.h.
| #define XAE_TC_FCS_MASK |
Definition at line 232 of file xilinx_axienet.h.
| #define XAE_TC_IFG_MASK |
Definition at line 235 of file xilinx_axienet.h.
| #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */ |
Definition at line 231 of file xilinx_axienet.h.
| #define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */ |
Definition at line 153 of file xilinx_axienet.h.
| #define XAE_TC_RST_MASK 0x80000000 /* Reset */ |
Definition at line 230 of file xilinx_axienet.h.
| #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ |
Definition at line 233 of file xilinx_axienet.h.
| #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */ |
Definition at line 234 of file xilinx_axienet.h.
| #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */ |
Definition at line 139 of file xilinx_axienet.h.
| #define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */ |
Definition at line 192 of file xilinx_axienet.h.
| #define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */ |
Definition at line 148 of file xilinx_axienet.h.
| #define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */ |
Definition at line 149 of file xilinx_axienet.h.
| #define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */ |
Definition at line 212 of file xilinx_axienet.h.
| #define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */ |
Definition at line 213 of file xilinx_axienet.h.
| #define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */ |
Definition at line 216 of file xilinx_axienet.h.
| #define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */ |
Definition at line 217 of file xilinx_axienet.h.
Definition at line 18 of file xilinx_axienet.h.
| #define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */ |
Definition at line 144 of file xilinx_axienet.h.
| #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */ |
Definition at line 171 of file xilinx_axienet.h.
| #define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */ |
Definition at line 165 of file xilinx_axienet.h.
| #define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */ |
Definition at line 166 of file xilinx_axienet.h.
| #define XAE_UAW1_UNICASTADDR_MASK |
Definition at line 285 of file xilinx_axienet.h.
| #define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */ |
Definition at line 146 of file xilinx_axienet.h.
| #define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */ |
Definition at line 147 of file xilinx_axienet.h.
| #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */ |
Definition at line 83 of file xilinx_axienet.h.
| #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ |
Definition at line 123 of file xilinx_axienet.h.
| #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ |
Definition at line 123 of file xilinx_axienet.h.
| #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */ |
Definition at line 84 of file xilinx_axienet.h.
| #define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */ |
Definition at line 99 of file xilinx_axienet.h.
| #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ |
Definition at line 122 of file xilinx_axienet.h.
| #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ |
Definition at line 122 of file xilinx_axienet.h.
| #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ |
Definition at line 121 of file xilinx_axienet.h.
| #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ |
Definition at line 121 of file xilinx_axienet.h.
| #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */ |
Definition at line 96 of file xilinx_axienet.h.
| #define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */ |
Definition at line 93 of file xilinx_axienet.h.
| #define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */ |
Definition at line 95 of file xilinx_axienet.h.
| #define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */ |
Definition at line 92 of file xilinx_axienet.h.
| #define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */ |
Definition at line 91 of file xilinx_axienet.h.
| #define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40 |
Definition at line 135 of file xilinx_axienet.h.
| #define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */ |
Definition at line 82 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */ |
Definition at line 125 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */ |
Definition at line 130 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */ |
Definition at line 133 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */ |
Definition at line 126 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */ |
Definition at line 127 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */ |
Definition at line 129 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */ |
Definition at line 85 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */ |
Definition at line 132 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */ |
Definition at line 131 of file xilinx_axienet.h.
| #define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */ |
Definition at line 128 of file xilinx_axienet.h.
| #define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */ |
Definition at line 86 of file xilinx_axienet.h.
| #define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */ |
Definition at line 87 of file xilinx_axienet.h.
| #define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */ |
Definition at line 88 of file xilinx_axienet.h.
| #define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */ |
Definition at line 89 of file xilinx_axienet.h.
| #define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */ |
Definition at line 90 of file xilinx_axienet.h.
| #define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */ |
Definition at line 97 of file xilinx_axienet.h.
| #define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */ |
Definition at line 105 of file xilinx_axienet.h.
| #define XAXIDMA_COALESCE_SHIFT 16 |
Definition at line 108 of file xilinx_axienet.h.
| #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ |
Definition at line 80 of file xilinx_axienet.h.
| #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ |
Definition at line 79 of file xilinx_axienet.h.
| #define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */ |
Definition at line 104 of file xilinx_axienet.h.
| #define XAXIDMA_DELAY_SHIFT 24 |
Definition at line 107 of file xilinx_axienet.h.
| #define XAXIDMA_DFT_RX_THRESHOLD 24 |
Definition at line 118 of file xilinx_axienet.h.
| #define XAXIDMA_DFT_RX_WAITBOUND 254 |
Definition at line 119 of file xilinx_axienet.h.
| #define XAXIDMA_DFT_TX_THRESHOLD 24 |
Definition at line 116 of file xilinx_axienet.h.
| #define XAXIDMA_DFT_TX_WAITBOUND 254 |
Definition at line 117 of file xilinx_axienet.h.
| #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ |
Definition at line 113 of file xilinx_axienet.h.
| #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ |
Definition at line 111 of file xilinx_axienet.h.
| #define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */ |
Definition at line 112 of file xilinx_axienet.h.
| #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ |
Definition at line 110 of file xilinx_axienet.h.
| #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */ |
Definition at line 76 of file xilinx_axienet.h.
| #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */ |
Definition at line 74 of file xilinx_axienet.h.
| #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */ |
Definition at line 75 of file xilinx_axienet.h.
| #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */ |
Definition at line 77 of file xilinx_axienet.h.
| #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */ |
Definition at line 71 of file xilinx_axienet.h.
| #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */ |
Definition at line 69 of file xilinx_axienet.h.
| #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */ |
Definition at line 70 of file xilinx_axienet.h.
| #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */ |
Definition at line 72 of file xilinx_axienet.h.
| int axienet_mdio_setup | ( | struct axienet_local * | lp, |
| struct device_node * | np | ||
| ) |
axienet_mdio_setup - MDIO setup function : Pointer to axienet local data structure. : Pointer to device node
returns: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when mdiobus_alloc (to allocate memory for mii bus structure) fails.
Sets up the MDIO interface by initializing the MDIO clock and enabling the MDIO interface in hardware. Register the MDIO interface.
Definition at line 128 of file xilinx_axienet_mdio.c.
| void axienet_mdio_teardown | ( | struct axienet_local * | lp | ) |
axienet_mdio_teardown - MDIO remove function : Pointer to axienet local data structure.
Unregisters the MDIO and frees any associate memory for mii bus.
Definition at line 232 of file xilinx_axienet_mdio.c.
| int axienet_mdio_wait_until_ready | ( | struct axienet_local * | lp | ) |
Definition at line 20 of file xilinx_axienet_mdio.c.
1.8.2