Passes.cpp File Reference

#include "llvm/CodeGen/Passes.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/IR/IRPrintingPasses.h"
#include "llvm/IR/Verifier.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/PassManager.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Scalar.h"

Include dependency graph for Passes.cpp:

Go to the source code of this file.

Classes
class	llvm::PassConfigImpl
Namespaces
namespace	llvm
	List of target independent CodeGen pass IDs.
Functions
static IdentifyingPassPtr	applyDisable (IdentifyingPassPtr PassID, bool Override)
static IdentifyingPassPtr	applyOverride (IdentifyingPassPtr TargetID, cl::boolOrDefault Override, AnalysisID StandardID)
static IdentifyingPassPtr	overridePass (AnalysisID StandardID, IdentifyingPassPtr TargetID)
static FunctionPass *	useDefaultRegisterAllocator ()
Variables
static cl::opt< bool >	DisablePostRA ("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc"))
static cl::opt< bool >	DisableBranchFold ("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
static cl::opt< bool >	DisableTailDuplicate ("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
static cl::opt< bool >	DisableEarlyTailDup ("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
static cl::opt< bool >	DisableBlockPlacement ("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
static cl::opt< bool >	EnableBlockPlacementStats ("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
static cl::opt< bool >	DisableSSC ("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
static cl::opt< bool >	DisableMachineDCE ("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
static cl::opt< bool >	DisableEarlyIfConversion ("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
static cl::opt< bool >	DisableMachineLICM ("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static cl::opt< bool >	DisableMachineCSE ("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
static cl::opt< cl::boolOrDefault >	OptimizeRegAlloc ("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
static cl::opt< cl::boolOrDefault >	EnableMachineSched ("enable-misched", cl::desc("Enable the machine instruction scheduling pass."))
static cl::opt< bool >	DisablePostRAMachineLICM ("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static cl::opt< bool >	DisableMachineSink ("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
static cl::opt< bool >	DisableLSR ("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
static cl::opt< bool >	DisableConstantHoisting ("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
static cl::opt< bool >	DisableCGP ("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
static cl::opt< bool >	DisableCopyProp ("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool >	DisablePartialLibcallInlining ("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
static cl::opt< bool >	PrintLSR ("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
static cl::opt< bool >	PrintISelInput ("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
static cl::opt< bool >	PrintGCInfo ("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static cl::opt< bool >	VerifyMachineCode ("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=nullptr))
static cl::opt< std::string >	PrintMachineInstrs ("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"))
static cl::opt< bool >	MISchedPostRA ("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
static cl::opt< bool >	EarlyLiveIntervals ("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
static cl::opt< bool >	UseCFLAA ("use-cfl-aa-in-codegen", cl::init(false), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"))
static RegisterRegAlloc	defaultRegAlloc ("default","pick register allocator based on -O option", useDefaultRegisterAllocator)
static cl::opt < RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser < RegisterRegAlloc > >	RegAlloc ("regalloc", cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))

---

Function Documentation

static IdentifyingPassPtr applyDisable	(	IdentifyingPassPtr	PassID,
		bool	Override
	)		[static]

Allow standard passes to be disabled by command line options. This supports simple binary flags that either suppress the pass or do nothing. i.e. -disable-mypass=false has no effect. These should be converted to boolOrDefault in order to use applyOverride.

Definition at line 110 of file Passes.cpp.

Referenced by overridePass().

static IdentifyingPassPtr applyOverride	(	IdentifyingPassPtr	TargetID,
		cl::boolOrDefault	Override,
		AnalysisID	StandardID
	)		[static]

Allow Pass selection to be overriden by command line options. This supports flags with ternary conditions. TargetID is passed through by default. The pass is suppressed when the option is false. When the option is true, the StandardID is selected if the target provides no default.

Definition at line 121 of file Passes.cpp.

References llvm::cl::BOU_FALSE, llvm::cl::BOU_TRUE, llvm::cl::BOU_UNSET, llvm::IdentifyingPassPtr::isValid(), llvm_unreachable, and llvm::report_fatal_error().

Referenced by overridePass().

static IdentifyingPassPtr overridePass	(	AnalysisID	StandardID,
		IdentifyingPassPtr	TargetID
	)		[static]

Allow standard passes to be disabled by the command line, regardless of who is adding the pass.

StandardID is the pass identified in the standard pass pipeline and provided to addPass(). It may be a target-specific ID in the case that the target directly adds its own pass, but in that case we harmlessly fall through.

TargetID is the pass that the target has configured to override StandardID.

StandardID may be a pseudo ID. In that case TargetID is the name of the real pass to run. This allows multiple options to control a single pass depending on where in the pipeline that pass is added.

Definition at line 151 of file Passes.cpp.

References applyDisable(), applyOverride(), llvm::BranchFolderPassID, llvm::DeadMachineInstructionElimID, DisableBlockPlacement, DisableBranchFold, DisableCopyProp, DisableEarlyIfConversion, DisableEarlyTailDup, DisableMachineCSE, DisableMachineDCE, DisableMachineLICM, DisableMachineSink, DisablePostRA, DisablePostRAMachineLICM, DisableSSC, DisableTailDuplicate, llvm::EarlyIfConverterID, llvm::TargetPassConfig::EarlyTailDuplicateID, EnableMachineSched, llvm::MachineBlockPlacementID, llvm::MachineCopyPropagationID, llvm::MachineCSEID, llvm::MachineLICMID, llvm::MachineSchedulerID, llvm::MachineSinkingID, llvm::TargetPassConfig::PostRAMachineLICMID, llvm::PostRASchedulerID, llvm::StackSlotColoringID, and llvm::TailDuplicateID.

Referenced by llvm::TargetPassConfig::addPass().

static FunctionPass* useDefaultRegisterAllocator

(

)

[static]

A dummy default pass factory indicates whether the register allocator is overridden on the command line.

Definition at line 640 of file Passes.cpp.

Referenced by llvm::TargetPassConfig::createRegAllocPass().

---

Variable Documentation

RegisterRegAlloc defaultRegAlloc("default","pick register allocator based on -O option", useDefaultRegisterAllocator) [static]

cl::opt<bool> DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement")) [static]

Referenced by overridePass().

cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding")) [static]

Referenced by overridePass().

cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare")) [static]

Referenced by llvm::TargetPassConfig::addCodeGenPrepare().

cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting")) [static]

Referenced by llvm::TargetPassConfig::addIRPasses().

cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass")) [static]

Referenced by overridePass().

cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion")) [static]

Referenced by overridePass().

cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication")) [static]

Referenced by overridePass().

cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass")) [static]

Referenced by llvm::TargetPassConfig::addIRPasses().

cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination")) [static]

Referenced by overridePass().

cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination")) [static]

Referenced by overridePass().

cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM")) [static]

Referenced by overridePass().

cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking")) [static]

Referenced by overridePass().

cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining")) [static]

Referenced by llvm::TargetPassConfig::addIRPasses().

cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc")) [static]

Referenced by overridePass().

cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM")) [static]

Referenced by overridePass().

cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring")) [static]

Referenced by overridePass().

cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication")) [static]

Referenced by overridePass().

cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline")) [static]

Referenced by llvm::TargetPassConfig::addOptimizedRegAlloc().

cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats")) [static]

Referenced by llvm::TargetPassConfig::addBlockPlacement().

cl::opt<cl::boolOrDefault> EnableMachineSched("enable-misched", cl::desc("Enable the machine instruction scheduling pass.")) [static]

Referenced by overridePass().

cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)")) [static]

Referenced by llvm::TargetPassConfig::addMachinePasses().

cl::opt<cl::boolOrDefault> OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path.")) [static]

Referenced by llvm::TargetPassConfig::getOptimizeRegAlloc().

cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data")) [static]

Referenced by llvm::TargetPassConfig::addMachinePasses().

cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass")) [static]

Referenced by llvm::TargetPassConfig::addISelPrepare().

cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass")) [static]

Referenced by llvm::TargetPassConfig::addIRPasses().

cl::opt<std::string> PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified")) [static]

Referenced by llvm::TargetPassConfig::addMachinePasses().

cl::opt<RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser<RegisterRegAlloc> > RegAlloc("regalloc", cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use")) [static]

-regalloc=... command line option.

Referenced by llvm::TargetPassConfig::createRegAllocPass().

cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen", cl::init(false), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen")) [static]

Referenced by llvm::TargetPassConfig::addIRPasses().

cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=nullptr)) [static]

Referenced by llvm::TargetPassConfig::printAndVerify().