MC68328.h File Reference

Go to the source code of this file.

Data Structures
struct	__attribute__

Macros
#define	BYTE_REF(addr)   (*((volatile unsigned char*)addr))
#define	WORD_REF(addr)   (*((volatile unsigned short*)addr))
#define	LONG_REF(addr)   (*((volatile unsigned long*)addr))
#define	PUT_FIELD(field, val)   (((val) << field##_SHIFT) & field##_MASK)
#define	GET_FIELD(reg, field)   (((reg) & field##_MASK) >> field##_SHIFT)
#define	SCR_ADDR   0xfffff000
#define	SCR   BYTE_REF(SCR_ADDR)
#define	SCR_WDTH8   0x01 /* 8-Bit Width Select */
#define	SCR_DMAP   0x04 /* Double Map */
#define	SCR_SO   0x08 /* Supervisor Only */
#define	SCR_BETEN   0x10 /* Bus-Error Time-Out Enable */
#define	SCR_PRV   0x20 /* Privilege Violation */
#define	SCR_WPV   0x40 /* Write Protect Violation */
#define	SCR_BETO   0x80 /* Bus-Error TimeOut */
#define	MRR_ADDR   0xfffff004
#define	MRR   LONG_REF(MRR_ADDR)
#define	GRPBASEA_ADDR   0xfffff100
#define	GRPBASEB_ADDR   0xfffff102
#define	GRPBASEC_ADDR   0xfffff104
#define	GRPBASED_ADDR   0xfffff106
#define	GRPBASEA   WORD_REF(GRPBASEA_ADDR)
#define	GRPBASEB   WORD_REF(GRPBASEB_ADDR)
#define	GRPBASEC   WORD_REF(GRPBASEC_ADDR)
#define	GRPBASED   WORD_REF(GRPBASED_ADDR)
#define	GRPBASE_V   0x0001 /* Valid */
#define	GRPBASE_GBA_MASK   0xfff0 /* Group Base Address (bits 31-20) */
#define	GRPMASKA_ADDR   0xfffff108
#define	GRPMASKB_ADDR   0xfffff10a
#define	GRPMASKC_ADDR   0xfffff10c
#define	GRPMASKD_ADDR   0xfffff10e
#define	GRPMASKA   WORD_REF(GRPMASKA_ADDR)
#define	GRPMASKB   WORD_REF(GRPMASKB_ADDR)
#define	GRPMASKC   WORD_REF(GRPMASKC_ADDR)
#define	GRPMASKD   WORD_REF(GRPMASKD_ADDR)
#define	GRMMASK_GMA_MASK   0xfffff0 /* Group Base Mask (bits 31-20) */
#define	CSA0_ADDR   0xfffff110
#define	CSA1_ADDR   0xfffff114
#define	CSA2_ADDR   0xfffff118
#define	CSA3_ADDR   0xfffff11c
#define	CSA0   LONG_REF(CSA0_ADDR)
#define	CSA1   LONG_REF(CSA1_ADDR)
#define	CSA2   LONG_REF(CSA2_ADDR)
#define	CSA3   LONG_REF(CSA3_ADDR)
#define	CSA_WAIT_MASK   0x00000007 /* Wait State Selection */
#define	CSA_WAIT_SHIFT   0
#define	CSA_RO   0x00000008 /* Read-Only */
#define	CSA_AM_MASK   0x0000ff00 /* Address Mask (bits 23-16) */
#define	CSA_AM_SHIFT   8
#define	CSA_BUSW   0x00010000 /* Bus Width Select */
#define	CSA_AC_MASK   0xff000000 /* Address Compare (bits 23-16) */
#define	CSA_AC_SHIFT   24
#define	CSB0_ADDR   0xfffff120
#define	CSB1_ADDR   0xfffff124
#define	CSB2_ADDR   0xfffff128
#define	CSB3_ADDR   0xfffff12c
#define	CSB0   LONG_REF(CSB0_ADDR)
#define	CSB1   LONG_REF(CSB1_ADDR)
#define	CSB2   LONG_REF(CSB2_ADDR)
#define	CSB3   LONG_REF(CSB3_ADDR)
#define	CSB_WAIT_MASK   0x00000007 /* Wait State Selection */
#define	CSB_WAIT_SHIFT   0
#define	CSB_RO   0x00000008 /* Read-Only */
#define	CSB_AM_MASK   0x0000ff00 /* Address Mask (bits 23-16) */
#define	CSB_AM_SHIFT   8
#define	CSB_BUSW   0x00010000 /* Bus Width Select */
#define	CSB_AC_MASK   0xff000000 /* Address Compare (bits 23-16) */
#define	CSB_AC_SHIFT   24
#define	CSC0_ADDR   0xfffff130
#define	CSC1_ADDR   0xfffff134
#define	CSC2_ADDR   0xfffff138
#define	CSC3_ADDR   0xfffff13c
#define	CSC0   LONG_REF(CSC0_ADDR)
#define	CSC1   LONG_REF(CSC1_ADDR)
#define	CSC2   LONG_REF(CSC2_ADDR)
#define	CSC3   LONG_REF(CSC3_ADDR)
#define	CSC_WAIT_MASK   0x00000007 /* Wait State Selection */
#define	CSC_WAIT_SHIFT   0
#define	CSC_RO   0x00000008 /* Read-Only */
#define	CSC_AM_MASK   0x0000fff0 /* Address Mask (bits 23-12) */
#define	CSC_AM_SHIFT   4
#define	CSC_BUSW   0x00010000 /* Bus Width Select */
#define	CSC_AC_MASK   0xfff00000 /* Address Compare (bits 23-12) */
#define	CSC_AC_SHIFT   20
#define	CSD0_ADDR   0xfffff140
#define	CSD1_ADDR   0xfffff144
#define	CSD2_ADDR   0xfffff148
#define	CSD3_ADDR   0xfffff14c
#define	CSD0   LONG_REF(CSD0_ADDR)
#define	CSD1   LONG_REF(CSD1_ADDR)
#define	CSD2   LONG_REF(CSD2_ADDR)
#define	CSD3   LONG_REF(CSD3_ADDR)
#define	CSD_WAIT_MASK   0x00000007 /* Wait State Selection */
#define	CSD_WAIT_SHIFT   0
#define	CSD_RO   0x00000008 /* Read-Only */
#define	CSD_AM_MASK   0x0000fff0 /* Address Mask (bits 23-12) */
#define	CSD_AM_SHIFT   4
#define	CSD_BUSW   0x00010000 /* Bus Width Select */
#define	CSD_AC_MASK   0xfff00000 /* Address Compare (bits 23-12) */
#define	CSD_AC_SHIFT   20
#define	PLLCR_ADDR   0xfffff200
#define	PLLCR   WORD_REF(PLLCR_ADDR)
#define	PLLCR_DISPLL   0x0008 /* Disable PLL */
#define	PLLCR_CLKEN   0x0010 /* Clock (CLKO pin) enable */
#define	PLLCR_SYSCLK_SEL_MASK   0x0700 /* System Clock Selection */
#define	PLLCR_SYSCLK_SEL_SHIFT   8
#define	PLLCR_PIXCLK_SEL_MASK   0x3800 /* LCD Clock Selection */
#define	PLLCR_PIXCLK_SEL_SHIFT   11
#define	PLLCR_LCDCLK_SEL_MASK   PLLCR_PIXCLK_SEL_MASK
#define	PLLCR_LCDCLK_SEL_SHIFT   PLLCR_PIXCLK_SEL_SHIFT
#define	PLLFSR_ADDR   0xfffff202
#define	PLLFSR   WORD_REF(PLLFSR_ADDR)
#define	PLLFSR_PC_MASK   0x00ff /* P Count */
#define	PLLFSR_PC_SHIFT   0
#define	PLLFSR_QC_MASK   0x0f00 /* Q Count */
#define	PLLFSR_QC_SHIFT   8
#define	PLLFSR_PROT   0x4000 /* Protect P & Q */
#define	PLLFSR_CLK32   0x8000 /* Clock 32 (kHz) */
#define	PCTRL_ADDR   0xfffff207
#define	PCTRL   BYTE_REF(PCTRL_ADDR)
#define	PCTRL_WIDTH_MASK   0x1f /* CPU Clock bursts width */
#define	PCTRL_WIDTH_SHIFT   0
#define	PCTRL_STOP   0x40 /* Enter power-save mode immediately */
#define	PCTRL_PCEN   0x80 /* Power Control Enable */
#define	IVR_ADDR   0xfffff300
#define	IVR   BYTE_REF(IVR_ADDR)
#define	IVR_VECTOR_MASK   0xF8
#define	ICR_ADRR   0xfffff302
#define	ICR   WORD_REF(ICR_ADDR)
#define	ICR_ET6   0x0100 /* Edge Trigger Select for IRQ6 */
#define	ICR_ET3   0x0200 /* Edge Trigger Select for IRQ3 */
#define	ICR_ET2   0x0400 /* Edge Trigger Select for IRQ2 */
#define	ICR_ET1   0x0800 /* Edge Trigger Select for IRQ1 */
#define	ICR_POL6   0x1000 /* Polarity Control for IRQ6 */
#define	ICR_POL3   0x2000 /* Polarity Control for IRQ3 */
#define	ICR_POL2   0x4000 /* Polarity Control for IRQ2 */
#define	ICR_POL1   0x8000 /* Polarity Control for IRQ1 */
#define	IMR_ADDR   0xfffff304
#define	IMR   LONG_REF(IMR_ADDR)
#define	SPIM_IRQ_NUM   0 /* SPI Master interrupt */
#define	TMR2_IRQ_NUM   1 /* Timer 2 interrupt */
#define	UART_IRQ_NUM   2 /* UART interrupt */
#define	WDT_IRQ_NUM   3 /* Watchdog Timer interrupt */
#define	RTC_IRQ_NUM   4 /* RTC interrupt */
#define	KB_IRQ_NUM   6 /* Keyboard Interrupt */
#define	PWM_IRQ_NUM   7 /* Pulse-Width Modulator int. */
#define	INT0_IRQ_NUM   8 /* External INT0 */
#define	INT1_IRQ_NUM   9 /* External INT1 */
#define	INT2_IRQ_NUM   10 /* External INT2 */
#define	INT3_IRQ_NUM   11 /* External INT3 */
#define	INT4_IRQ_NUM   12 /* External INT4 */
#define	INT5_IRQ_NUM   13 /* External INT5 */
#define	INT6_IRQ_NUM   14 /* External INT6 */
#define	INT7_IRQ_NUM   15 /* External INT7 */
#define	IRQ1_IRQ_NUM   16 /* IRQ1 */
#define	IRQ2_IRQ_NUM   17 /* IRQ2 */
#define	IRQ3_IRQ_NUM   18 /* IRQ3 */
#define	IRQ6_IRQ_NUM   19 /* IRQ6 */
#define	PEN_IRQ_NUM   20 /* Pen Interrupt */
#define	SPIS_IRQ_NUM   21 /* SPI Slave Interrupt */
#define	TMR1_IRQ_NUM   22 /* Timer 1 interrupt */
#define	IRQ7_IRQ_NUM   23 /* IRQ7 */
#define	SPI_IRQ_NUM   SPIM_IRQ_NUM
#define	TMR_IRQ_NUM   TMR1_IRQ_NUM
#define	IMR_MSPIM   (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */
#define	IMR_MTMR2   (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
#define	IMR_MUART   (1 << UART_IRQ_NUM) /* Mask UART interrupt */
#define	IMR_MWDT   (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
#define	IMR_MRTC   (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
#define	IMR_MKB   (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
#define	IMR_MPWM   (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
#define	IMR_MINT0   (1 << INT0_IRQ_NUM) /* Mask External INT0 */
#define	IMR_MINT1   (1 << INT1_IRQ_NUM) /* Mask External INT1 */
#define	IMR_MINT2   (1 << INT2_IRQ_NUM) /* Mask External INT2 */
#define	IMR_MINT3   (1 << INT3_IRQ_NUM) /* Mask External INT3 */
#define	IMR_MINT4   (1 << INT4_IRQ_NUM) /* Mask External INT4 */
#define	IMR_MINT5   (1 << INT5_IRQ_NUM) /* Mask External INT5 */
#define	IMR_MINT6   (1 << INT6_IRQ_NUM) /* Mask External INT6 */
#define	IMR_MINT7   (1 << INT7_IRQ_NUM) /* Mask External INT7 */
#define	IMR_MIRQ1   (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
#define	IMR_MIRQ2   (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
#define	IMR_MIRQ3   (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
#define	IMR_MIRQ6   (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
#define	IMR_MPEN   (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */
#define	IMR_MSPIS   (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */
#define	IMR_MTMR1   (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */
#define	IMR_MIRQ7   (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */
#define	IMR_MSPI   IMR_MSPIM
#define	IMR_MTMR   IMR_MTMR1
#define	IWR_ADDR   0xfffff308
#define	IWR   LONG_REF(IWR_ADDR)
#define	IWR_SPIM   (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
#define	IWR_TMR2   (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define	IWR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */
#define	IWR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define	IWR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define	IWR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define	IWR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
#define	IWR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */
#define	IWR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */
#define	IWR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */
#define	IWR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */
#define	IWR_INT4   (1 << INT4_IRQ_NUM) /* External INT4 */
#define	IWR_INT5   (1 << INT5_IRQ_NUM) /* External INT5 */
#define	IWR_INT6   (1 << INT6_IRQ_NUM) /* External INT6 */
#define	IWR_INT7   (1 << INT7_IRQ_NUM) /* External INT7 */
#define	IWR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define	IWR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define	IWR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define	IWR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define	IWR_PEN   (1 << PEN_IRQ_NUM) /* Pen Interrupt */
#define	IWR_SPIS   (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
#define	IWR_TMR1   (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
#define	IWR_IRQ7   (1 << IRQ7_IRQ_NUM) /* IRQ7 */
#define	ISR_ADDR   0xfffff30c
#define	ISR   LONG_REF(ISR_ADDR)
#define	ISR_SPIM   (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
#define	ISR_TMR2   (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define	ISR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */
#define	ISR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define	ISR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define	ISR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define	ISR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
#define	ISR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */
#define	ISR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */
#define	ISR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */
#define	ISR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */
#define	ISR_INT4   (1 << INT4_IRQ_NUM) /* External INT4 */
#define	ISR_INT5   (1 << INT5_IRQ_NUM) /* External INT5 */
#define	ISR_INT6   (1 << INT6_IRQ_NUM) /* External INT6 */
#define	ISR_INT7   (1 << INT7_IRQ_NUM) /* External INT7 */
#define	ISR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define	ISR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define	ISR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define	ISR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define	ISR_PEN   (1 << PEN_IRQ_NUM) /* Pen Interrupt */
#define	ISR_SPIS   (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
#define	ISR_TMR1   (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
#define	ISR_IRQ7   (1 << IRQ7_IRQ_NUM) /* IRQ7 */
#define	ISR_SPI   ISR_SPIM
#define	ISR_TMR   ISR_TMR1
#define	IPR_ADDR   0xfffff310
#define	IPR   LONG_REF(IPR_ADDR)
#define	IPR_SPIM   (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
#define	IPR_TMR2   (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define	IPR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */
#define	IPR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define	IPR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define	IPR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define	IPR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
#define	IPR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */
#define	IPR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */
#define	IPR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */
#define	IPR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */
#define	IPR_INT4   (1 << INT4_IRQ_NUM) /* External INT4 */
#define	IPR_INT5   (1 << INT5_IRQ_NUM) /* External INT5 */
#define	IPR_INT6   (1 << INT6_IRQ_NUM) /* External INT6 */
#define	IPR_INT7   (1 << INT7_IRQ_NUM) /* External INT7 */
#define	IPR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define	IPR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define	IPR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define	IPR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define	IPR_PEN   (1 << PEN_IRQ_NUM) /* Pen Interrupt */
#define	IPR_SPIS   (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
#define	IPR_TMR1   (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
#define	IPR_IRQ7   (1 << IRQ7_IRQ_NUM) /* IRQ7 */
#define	IPR_SPI   IPR_SPIM
#define	IPR_TMR   IPR_TMR1
#define	PADIR_ADDR   0xfffff400 /* Port A direction reg */
#define	PADATA_ADDR   0xfffff401 /* Port A data register */
#define	PASEL_ADDR   0xfffff403 /* Port A Select register */
#define	PADIR   BYTE_REF(PADIR_ADDR)
#define	PADATA   BYTE_REF(PADATA_ADDR)
#define	PASEL   BYTE_REF(PASEL_ADDR)
#define	PA(x)   (1 << (x))
#define	PA_A(x)   PA((x) - 16) /* This is specific to PA only! */
#define	PA_A16   PA(0) /* Use A16 as PA(0) */
#define	PA_A17   PA(1) /* Use A17 as PA(1) */
#define	PA_A18   PA(2) /* Use A18 as PA(2) */
#define	PA_A19   PA(3) /* Use A19 as PA(3) */
#define	PA_A20   PA(4) /* Use A20 as PA(4) */
#define	PA_A21   PA(5) /* Use A21 as PA(5) */
#define	PA_A22   PA(6) /* Use A22 as PA(6) */
#define	PA_A23   PA(7) /* Use A23 as PA(7) */
#define	PBDIR_ADDR   0xfffff408 /* Port B direction reg */
#define	PBDATA_ADDR   0xfffff409 /* Port B data register */
#define	PBSEL_ADDR   0xfffff40b /* Port B Select Register */
#define	PBDIR   BYTE_REF(PBDIR_ADDR)
#define	PBDATA   BYTE_REF(PBDATA_ADDR)
#define	PBSEL   BYTE_REF(PBSEL_ADDR)
#define	PB(x)   (1 << (x))
#define	PB_D(x)   PB(x) /* This is specific to port B only */
#define	PB_D0   PB(0) /* Use D0 as PB(0) */
#define	PB_D1   PB(1) /* Use D1 as PB(1) */
#define	PB_D2   PB(2) /* Use D2 as PB(2) */
#define	PB_D3   PB(3) /* Use D3 as PB(3) */
#define	PB_D4   PB(4) /* Use D4 as PB(4) */
#define	PB_D5   PB(5) /* Use D5 as PB(5) */
#define	PB_D6   PB(6) /* Use D6 as PB(6) */
#define	PB_D7   PB(7) /* Use D7 as PB(7) */
#define	PCDIR_ADDR   0xfffff410 /* Port C direction reg */
#define	PCDATA_ADDR   0xfffff411 /* Port C data register */
#define	PCSEL_ADDR   0xfffff413 /* Port C Select Register */
#define	PCDIR   BYTE_REF(PCDIR_ADDR)
#define	PCDATA   BYTE_REF(PCDATA_ADDR)
#define	PCSEL   BYTE_REF(PCSEL_ADDR)
#define	PC(x)   (1 << (x))
#define	PC_WE   PC(6) /* Use WE as PC(6) */
#define	PC_DTACK   PC(5) /* Use DTACK as PC(5) */
#define	PC_IRQ7   PC(4) /* Use IRQ7 as PC(4) */
#define	PC_LDS   PC(2) /* Use LDS as PC(2) */
#define	PC_UDS   PC(1) /* Use UDS as PC(1) */
#define	PC_MOCLK   PC(0) /* Use MOCLK as PC(0) */
#define	PDDIR_ADDR   0xfffff418 /* Port D direction reg */
#define	PDDATA_ADDR   0xfffff419 /* Port D data register */
#define	PDPUEN_ADDR   0xfffff41a /* Port D Pull-Up enable reg */
#define	PDPOL_ADDR   0xfffff41c /* Port D Polarity Register */
#define	PDIRQEN_ADDR   0xfffff41d /* Port D IRQ enable register */
#define	PDIQEG_ADDR   0xfffff41f /* Port D IRQ Edge Register */
#define	PDDIR   BYTE_REF(PDDIR_ADDR)
#define	PDDATA   BYTE_REF(PDDATA_ADDR)
#define	PDPUEN   BYTE_REF(PDPUEN_ADDR)
#define	PDPOL   BYTE_REF(PDPOL_ADDR)
#define	PDIRQEN   BYTE_REF(PDIRQEN_ADDR)
#define	PDIQEG   BYTE_REF(PDIQEG_ADDR)
#define	PD(x)   (1 << (x))
#define	PD_KB(x)   PD(x) /* This is specific for Port D only */
#define	PD_KB0   PD(0) /* Use KB0 as PD(0) */
#define	PD_KB1   PD(1) /* Use KB1 as PD(1) */
#define	PD_KB2   PD(2) /* Use KB2 as PD(2) */
#define	PD_KB3   PD(3) /* Use KB3 as PD(3) */
#define	PD_KB4   PD(4) /* Use KB4 as PD(4) */
#define	PD_KB5   PD(5) /* Use KB5 as PD(5) */
#define	PD_KB6   PD(6) /* Use KB6 as PD(6) */
#define	PD_KB7   PD(7) /* Use KB7 as PD(7) */
#define	PEDIR_ADDR   0xfffff420 /* Port E direction reg */
#define	PEDATA_ADDR   0xfffff421 /* Port E data register */
#define	PEPUEN_ADDR   0xfffff422 /* Port E Pull-Up enable reg */
#define	PESEL_ADDR   0xfffff423 /* Port E Select Register */
#define	PEDIR   BYTE_REF(PEDIR_ADDR)
#define	PEDATA   BYTE_REF(PEDATA_ADDR)
#define	PEPUEN   BYTE_REF(PEPUEN_ADDR)
#define	PESEL   BYTE_REF(PESEL_ADDR)
#define	PE(x)   (1 << (x))
#define	PE_CSA1   PE(1) /* Use CSA1 as PE(1) */
#define	PE_CSA2   PE(2) /* Use CSA2 as PE(2) */
#define	PE_CSA3   PE(3) /* Use CSA3 as PE(3) */
#define	PE_CSB0   PE(4) /* Use CSB0 as PE(4) */
#define	PE_CSB1   PE(5) /* Use CSB1 as PE(5) */
#define	PE_CSB2   PE(6) /* Use CSB2 as PE(6) */
#define	PE_CSB3   PE(7) /* Use CSB3 as PE(7) */
#define	PFDIR_ADDR   0xfffff428 /* Port F direction reg */
#define	PFDATA_ADDR   0xfffff429 /* Port F data register */
#define	PFPUEN_ADDR   0xfffff42a /* Port F Pull-Up enable reg */
#define	PFSEL_ADDR   0xfffff42b /* Port F Select Register */
#define	PFDIR   BYTE_REF(PFDIR_ADDR)
#define	PFDATA   BYTE_REF(PFDATA_ADDR)
#define	PFPUEN   BYTE_REF(PFPUEN_ADDR)
#define	PFSEL   BYTE_REF(PFSEL_ADDR)
#define	PF(x)   (1 << (x))
#define	PF_A(x)   PF((x) - 24) /* This is Port F specific only */
#define	PF_A24   PF(0) /* Use A24 as PF(0) */
#define	PF_A25   PF(1) /* Use A25 as PF(1) */
#define	PF_A26   PF(2) /* Use A26 as PF(2) */
#define	PF_A27   PF(3) /* Use A27 as PF(3) */
#define	PF_A28   PF(4) /* Use A28 as PF(4) */
#define	PF_A29   PF(5) /* Use A29 as PF(5) */
#define	PF_A30   PF(6) /* Use A30 as PF(6) */
#define	PF_A31   PF(7) /* Use A31 as PF(7) */
#define	PGDIR_ADDR   0xfffff430 /* Port G direction reg */
#define	PGDATA_ADDR   0xfffff431 /* Port G data register */
#define	PGPUEN_ADDR   0xfffff432 /* Port G Pull-Up enable reg */
#define	PGSEL_ADDR   0xfffff433 /* Port G Select Register */
#define	PGDIR   BYTE_REF(PGDIR_ADDR)
#define	PGDATA   BYTE_REF(PGDATA_ADDR)
#define	PGPUEN   BYTE_REF(PGPUEN_ADDR)
#define	PGSEL   BYTE_REF(PGSEL_ADDR)
#define	PG(x)   (1 << (x))
#define	PG_UART_TXD   PG(0) /* Use UART_TXD as PG(0) */
#define	PG_UART_RXD   PG(1) /* Use UART_RXD as PG(1) */
#define	PG_PWMOUT   PG(2) /* Use PWMOUT as PG(2) */
#define	PG_TOUT2   PG(3) /* Use TOUT2 as PG(3) */
#define	PG_TIN2   PG(4) /* Use TIN2 as PG(4) */
#define	PG_TOUT1   PG(5) /* Use TOUT1 as PG(5) */
#define	PG_TIN1   PG(6) /* Use TIN1 as PG(6) */
#define	PG_RTCOUT   PG(7) /* Use RTCOUT as PG(7) */
#define	PJDIR_ADDR   0xfffff438 /* Port J direction reg */
#define	PJDATA_ADDR   0xfffff439 /* Port J data register */
#define	PJSEL_ADDR   0xfffff43b /* Port J Select Register */
#define	PJDIR   BYTE_REF(PJDIR_ADDR)
#define	PJDATA   BYTE_REF(PJDATA_ADDR)
#define	PJSEL   BYTE_REF(PJSEL_ADDR)
#define	PJ(x)   (1 << (x))
#define	PJ_CSD3   PJ(7) /* Use CSD3 as PJ(7) */
#define	PKDIR_ADDR   0xfffff440 /* Port K direction reg */
#define	PKDATA_ADDR   0xfffff441 /* Port K data register */
#define	PKPUEN_ADDR   0xfffff442 /* Port K Pull-Up enable reg */
#define	PKSEL_ADDR   0xfffff443 /* Port K Select Register */
#define	PKDIR   BYTE_REF(PKDIR_ADDR)
#define	PKDATA   BYTE_REF(PKDATA_ADDR)
#define	PKPUEN   BYTE_REF(PKPUEN_ADDR)
#define	PKSEL   BYTE_REF(PKSEL_ADDR)
#define	PK(x)   (1 << (x))
#define	PMDIR_ADDR   0xfffff438 /* Port M direction reg */
#define	PMDATA_ADDR   0xfffff439 /* Port M data register */
#define	PMPUEN_ADDR   0xfffff43a /* Port M Pull-Up enable reg */
#define	PMSEL_ADDR   0xfffff43b /* Port M Select Register */
#define	PMDIR   BYTE_REF(PMDIR_ADDR)
#define	PMDATA   BYTE_REF(PMDATA_ADDR)
#define	PMPUEN   BYTE_REF(PMPUEN_ADDR)
#define	PMSEL   BYTE_REF(PMSEL_ADDR)
#define	PM(x)   (1 << (x))
#define	PWMC_ADDR   0xfffff500
#define	PWMC   WORD_REF(PWMC_ADDR)
#define	PWMC_CLKSEL_MASK   0x0007 /* Clock Selection */
#define	PWMC_CLKSEL_SHIFT   0
#define	PWMC_PWMEN   0x0010 /* Enable PWM */
#define	PMNC_POL   0x0020 /* PWM Output Bit Polarity */
#define	PWMC_PIN   0x0080 /* Current PWM output pin status */
#define	PWMC_LOAD   0x0100 /* Force a new period */
#define	PWMC_IRQEN   0x4000 /* Interrupt Request Enable */
#define	PWMC_CLKSRC   0x8000 /* Clock Source Select */
#define	PWMC_EN   PWMC_PWMEN
#define	PWMP_ADDR   0xfffff502
#define	PWMP   WORD_REF(PWMP_ADDR)
#define	PWMW_ADDR   0xfffff504
#define	PWMW   WORD_REF(PWMW_ADDR)
#define	PWMCNT_ADDR   0xfffff506
#define	PWMCNT   WORD_REF(PWMCNT_ADDR)
#define	TCTL1_ADDR   0xfffff600
#define	TCTL1   WORD_REF(TCTL1_ADDR)
#define	TCTL2_ADDR   0xfffff60c
#define	TCTL2   WORD_REF(TCTL2_ADDR)
#define	TCTL_TEN   0x0001 /* Timer Enable */
#define	TCTL_CLKSOURCE_MASK   0x000e /* Clock Source: */
#define	TCTL_CLKSOURCE_STOP   0x0000 /* Stop count (disabled) */
#define	TCTL_CLKSOURCE_SYSCLK   0x0002 /* SYSCLK to prescaler */
#define	TCTL_CLKSOURCE_SYSCLK_16   0x0004 /* SYSCLK/16 to prescaler */
#define	TCTL_CLKSOURCE_TIN   0x0006 /* TIN to prescaler */
#define	TCTL_CLKSOURCE_32KHZ   0x0008 /* 32kHz clock to prescaler */
#define	TCTL_IRQEN   0x0010 /* IRQ Enable */
#define	TCTL_OM   0x0020 /* Output Mode */
#define	TCTL_CAP_MASK   0x00c0 /* Capture Edge: */
#define	TCTL_CAP_RE   0x0040 /* Capture on rizing edge */
#define	TCTL_CAP_FE   0x0080 /* Capture on falling edge */
#define	TCTL_FRR   0x0010 /* Free-Run Mode */
#define	TCTL_ADDR   TCTL1_ADDR
#define	TCTL   TCTL1
#define	TPRER1_ADDR   0xfffff602
#define	TPRER1   WORD_REF(TPRER1_ADDR)
#define	TPRER2_ADDR   0xfffff60e
#define	TPRER2   WORD_REF(TPRER2_ADDR)
#define	TPRER_ADDR   TPRER1_ADDR
#define	TPRER   TPRER1
#define	TCMP1_ADDR   0xfffff604
#define	TCMP1   WORD_REF(TCMP1_ADDR)
#define	TCMP2_ADDR   0xfffff610
#define	TCMP2   WORD_REF(TCMP2_ADDR)
#define	TCMP_ADDR   TCMP1_ADDR
#define	TCMP   TCMP1
#define	TCR1_ADDR   0xfffff606
#define	TCR1   WORD_REF(TCR1_ADDR)
#define	TCR2_ADDR   0xfffff612
#define	TCR2   WORD_REF(TCR2_ADDR)
#define	TCR_ADDR   TCR1_ADDR
#define	TCR   TCR1
#define	TCN1_ADDR   0xfffff608
#define	TCN1   WORD_REF(TCN1_ADDR)
#define	TCN2_ADDR   0xfffff614
#define	TCN2   WORD_REF(TCN2_ADDR)
#define	TCN_ADDR   TCN1_ADDR
#define	TCN   TCN
#define	TSTAT1_ADDR   0xfffff60a
#define	TSTAT1   WORD_REF(TSTAT1_ADDR)
#define	TSTAT2_ADDR   0xfffff616
#define	TSTAT2   WORD_REF(TSTAT2_ADDR)
#define	TSTAT_COMP   0x0001 /* Compare Event occurred */
#define	TSTAT_CAPT   0x0001 /* Capture Event occurred */
#define	TSTAT_ADDR   TSTAT1_ADDR
#define	TSTAT   TSTAT1
#define	WRR_ADDR   0xfffff61a
#define	WRR   WORD_REF(WRR_ADDR)
#define	WCN_ADDR   0xfffff61c
#define	WCN   WORD_REF(WCN_ADDR)
#define	WCSR_ADDR   0xfffff618
#define	WCSR   WORD_REF(WCSR_ADDR)
#define	WCSR_WDEN   0x0001 /* Watchdog Enable */
#define	WCSR_FI   0x0002 /* Forced Interrupt (instead of SW reset)*/
#define	WCSR_WRST   0x0004 /* Watchdog Reset */
#define	SPISR_ADDR   0xfffff700
#define	SPISR   WORD_REF(SPISR_ADDR)
#define	SPISR_DATA_ADDR   0xfffff701
#define	SPISR_DATA   BYTE_REF(SPISR_DATA_ADDR)
#define	SPISR_DATA_MASK   0x00ff /* Shifted data from the external device */
#define	SPISR_DATA_SHIFT   0
#define	SPISR_SPISEN   0x0100 /* SPIS module enable */
#define	SPISR_POL   0x0200 /* SPSCLK polarity control */
#define	SPISR_PHA   0x0400 /* Phase relationship between SPSCLK & SPSRxD */
#define	SPISR_OVWR   0x0800 /* Data buffer has been overwritten */
#define	SPISR_DATARDY   0x1000 /* Data ready */
#define	SPISR_ENPOL   0x2000 /* Enable Polarity */
#define	SPISR_IRQEN   0x4000 /* SPIS IRQ Enable */
#define	SPISR_SPISIRQ   0x8000 /* SPIS IRQ posted */
#define	SPIMDATA_ADDR   0xfffff800
#define	SPIMDATA   WORD_REF(SPIMDATA_ADDR)
#define	SPIMCONT_ADDR   0xfffff802
#define	SPIMCONT   WORD_REF(SPIMCONT_ADDR)
#define	SPIMCONT_BIT_COUNT_MASK   0x000f /* Transfer Length in Bytes */
#define	SPIMCONT_BIT_COUNT_SHIFT   0
#define	SPIMCONT_POL   0x0010 /* SPMCLK Signel Polarity */
#define	SPIMCONT_PHA   0x0020 /* Clock/Data phase relationship */
#define	SPIMCONT_IRQEN   0x0040 /* IRQ Enable */
#define	SPIMCONT_SPIMIRQ   0x0080 /* Interrupt Request */
#define	SPIMCONT_XCH   0x0100 /* Exchange */
#define	SPIMCONT_RSPIMEN   0x0200 /* Enable SPIM */
#define	SPIMCONT_DATA_RATE_MASK   0xe000 /* SPIM Data Rate */
#define	SPIMCONT_DATA_RATE_SHIFT   13
#define	SPIMCONT_IRQ   SPIMCONT_SPIMIRQ
#define	SPIMCONT_ENABLE   SPIMCONT_SPIMEN
#define	USTCNT_ADDR   0xfffff900
#define	USTCNT   WORD_REF(USTCNT_ADDR)
#define	USTCNT_TXAVAILEN   0x0001 /* Transmitter Available Int Enable */
#define	USTCNT_TXHALFEN   0x0002 /* Transmitter Half Empty Int Enable */
#define	USTCNT_TXEMPTYEN   0x0004 /* Transmitter Empty Int Enable */
#define	USTCNT_RXREADYEN   0x0008 /* Receiver Ready Interrupt Enable */
#define	USTCNT_RXHALFEN   0x0010 /* Receiver Half-Full Int Enable */
#define	USTCNT_RXFULLEN   0x0020 /* Receiver Full Interrupt Enable */
#define	USTCNT_CTSDELTAEN   0x0040 /* CTS Delta Interrupt Enable */
#define	USTCNT_GPIODELTAEN   0x0080 /* Old Data Interrupt Enable */
#define	USTCNT_8_7   0x0100 /* Eight or seven-bit transmission */
#define	USTCNT_STOP   0x0200 /* Stop bit transmission */
#define	USTCNT_ODD_EVEN   0x0400 /* Odd Parity */
#define	USTCNT_PARITYEN   0x0800 /* Parity Enable */
#define	USTCNT_CLKMODE   0x1000 /* Clock Mode Select */
#define	USTCNT_TXEN   0x2000 /* Transmitter Enable */
#define	USTCNT_RXEN   0x4000 /* Receiver Enable */
#define	USTCNT_UARTEN   0x8000 /* UART Enable */
#define	USTCNT_TXAE   USTCNT_TXAVAILEN
#define	USTCNT_TXHE   USTCNT_TXHALFEN
#define	USTCNT_TXEE   USTCNT_TXEMPTYEN
#define	USTCNT_RXRE   USTCNT_RXREADYEN
#define	USTCNT_RXHE   USTCNT_RXHALFEN
#define	USTCNT_RXFE   USTCNT_RXFULLEN
#define	USTCNT_CTSD   USTCNT_CTSDELTAEN
#define	USTCNT_ODD   USTCNT_ODD_EVEN
#define	USTCNT_PEN   USTCNT_PARITYEN
#define	USTCNT_CLKM   USTCNT_CLKMODE
#define	USTCNT_UEN   USTCNT_UARTEN
#define	UBAUD_ADDR   0xfffff902
#define	UBAUD   WORD_REF(UBAUD_ADDR)
#define	UBAUD_PRESCALER_MASK   0x003f /* Actual divisor is 65 - PRESCALER */
#define	UBAUD_PRESCALER_SHIFT   0
#define	UBAUD_DIVIDE_MASK   0x0700 /* Baud Rate freq. divizor */
#define	UBAUD_DIVIDE_SHIFT   8
#define	UBAUD_BAUD_SRC   0x0800 /* Baud Rate Source */
#define	UBAUD_GPIOSRC   0x1000 /* GPIO source */
#define	UBAUD_GPIODIR   0x2000 /* GPIO Direction */
#define	UBAUD_GPIO   0x4000 /* Current GPIO pin status */
#define	UBAUD_GPIODELTA   0x8000 /* GPIO pin value changed */
#define	URX_ADDR   0xfffff904
#define	URX   WORD_REF(URX_ADDR)
#define	URX_RXDATA_ADDR   0xfffff905
#define	URX_RXDATA   BYTE_REF(URX_RXDATA_ADDR)
#define	URX_RXDATA_MASK   0x00ff /* Received data */
#define	URX_RXDATA_SHIFT   0
#define	URX_PARITY_ERROR   0x0100 /* Parity Error */
#define	URX_BREAK   0x0200 /* Break Detected */
#define	URX_FRAME_ERROR   0x0400 /* Framing Error */
#define	URX_OVRUN   0x0800 /* Serial Overrun */
#define	URX_DATA_READY   0x2000 /* Data Ready (FIFO not empty) */
#define	URX_FIFO_HALF   0x4000 /* FIFO is Half-Full */
#define	URX_FIFO_FULL   0x8000 /* FIFO is Full */
#define	UTX_ADDR   0xfffff906
#define	UTX   WORD_REF(UTX_ADDR)
#define	UTX_TXDATA_ADDR   0xfffff907
#define	UTX_TXDATA   BYTE_REF(UTX_TXDATA_ADDR)
#define	UTX_TXDATA_MASK   0x00ff /* Data to be transmitted */
#define	UTX_TXDATA_SHIFT   0
#define	UTX_CTS_DELTA   0x0100 /* CTS changed */
#define	UTX_CTS_STATUS   0x0200 /* CTS State */
#define	UTX_IGNORE_CTS   0x0800 /* Ignore CTS */
#define	UTX_SEND_BREAK   0x1000 /* Send a BREAK */
#define	UTX_TX_AVAIL   0x2000 /* Transmit FIFO has a slot available */
#define	UTX_FIFO_HALF   0x4000 /* Transmit FIFO is half empty */
#define	UTX_FIFO_EMPTY   0x8000 /* Transmit FIFO is empty */
#define	UTX_CTS_STAT   UTX_CTS_STATUS
#define	UTX_NOCTS   UTX_IGNORE_CTS
#define	UMISC_ADDR   0xfffff908
#define	UMISC   WORD_REF(UMISC_ADDR)
#define	UMISC_TX_POL   0x0004 /* Transmit Polarity */
#define	UMISC_RX_POL   0x0008 /* Receive Polarity */
#define	UMISC_IRDA_LOOP   0x0010 /* IrDA Loopback Enable */
#define	UMISC_IRDA_EN   0x0020 /* Infra-Red Enable */
#define	UMISC_RTS   0x0040 /* Set RTS status */
#define	UMISC_RTSCONT   0x0080 /* Choose RTS control */
#define	UMISC_LOOP   0x1000 /* Serial Loopback Enable */
#define	UMISC_FORCE_PERR   0x2000 /* Force Parity Error */
#define	UMISC_CLKSRC   0x4000 /* Clock Source */
#define	LSSA_ADDR   0xfffffa00
#define	LSSA   LONG_REF(LSSA_ADDR)
#define	LSSA_SSA_MASK   0xfffffffe /* Bit 0 is reserved */
#define	LVPW_ADDR   0xfffffa05
#define	LVPW   BYTE_REF(LVPW_ADDR)
#define	LXMAX_ADDR   0xfffffa08
#define	LXMAX   WORD_REF(LXMAX_ADDR)
#define	LXMAX_XM_MASK   0x02ff /* Bits 0-3 are reserved */
#define	LYMAX_ADDR   0xfffffa0a
#define	LYMAX   WORD_REF(LYMAX_ADDR)
#define	LYMAX_YM_MASK   0x02ff /* Bits 10-15 are reserved */
#define	LCXP_ADDR   0xfffffa18
#define	LCXP   WORD_REF(LCXP_ADDR)
#define	LCXP_CC_MASK   0xc000 /* Cursor Control */
#define	LCXP_CC_TRAMSPARENT   0x0000
#define	LCXP_CC_BLACK   0x4000
#define	LCXP_CC_REVERSED   0x8000
#define	LCXP_CC_WHITE   0xc000
#define	LCXP_CXP_MASK   0x02ff /* Cursor X position */
#define	LCYP_ADDR   0xfffffa1a
#define	LCYP   WORD_REF(LCYP_ADDR)
#define	LCYP_CYP_MASK   0x01ff /* Cursor Y Position */
#define	LCWCH_ADDR   0xfffffa1c
#define	LCWCH   WORD_REF(LCWCH_ADDR)
#define	LCWCH_CH_MASK   0x001f /* Cursor Height */
#define	LCWCH_CH_SHIFT   0
#define	LCWCH_CW_MASK   0x1f00 /* Cursor Width */
#define	LCWCH_CW_SHIFT   8
#define	LBLKC_ADDR   0xfffffa1f
#define	LBLKC   BYTE_REF(LBLKC_ADDR)
#define	LBLKC_BD_MASK   0x7f /* Blink Divisor */
#define	LBLKC_BD_SHIFT   0
#define	LBLKC_BKEN   0x80 /* Blink Enabled */
#define	LPICF_ADDR   0xfffffa20
#define	LPICF   BYTE_REF(LPICF_ADDR)
#define	LPICF_GS_MASK   0x01 /* Gray-Scale Mode */
#define	LPICF_GS_BW   0x00
#define	LPICF_GS_GRAY_4   0x01
#define	LPICF_PBSIZ_MASK   0x06 /* Panel Bus Width */
#define	LPICF_PBSIZ_1   0x00
#define	LPICF_PBSIZ_2   0x02
#define	LPICF_PBSIZ_4   0x04
#define	LPOLCF_ADDR   0xfffffa21
#define	LPOLCF   BYTE_REF(LPOLCF_ADDR)
#define	LPOLCF_PIXPOL   0x01 /* Pixel Polarity */
#define	LPOLCF_LPPOL   0x02 /* Line Pulse Polarity */
#define	LPOLCF_FLMPOL   0x04 /* Frame Marker Polarity */
#define	LPOLCF_LCKPOL   0x08 /* LCD Shift Lock Polarity */
#define	LACDRC_ADDR   0xfffffa23
#define	LACDRC   BYTE_REF(LACDRC_ADDR)
#define	LACDRC_ACD_MASK   0x0f /* Alternate Crystal Direction Control */
#define	LACDRC_ACD_SHIFT   0
#define	LPXCD_ADDR   0xfffffa25
#define	LPXCD   BYTE_REF(LPXCD_ADDR)
#define	LPXCD_PCD_MASK   0x3f /* Pixel Clock Divider */
#define	LPXCD_PCD_SHIFT   0
#define	LCKCON_ADDR   0xfffffa27
#define	LCKCON   BYTE_REF(LCKCON_ADDR)
#define	LCKCON_PCDS   0x01 /* Pixel Clock Divider Source Select */
#define	LCKCON_DWIDTH   0x02 /* Display Memory Width */
#define	LCKCON_DWS_MASK   0x3c /* Display Wait-State */
#define	LCKCON_DWS_SHIFT   2
#define	LCKCON_DMA16   0x40 /* DMA burst length */
#define	LCKCON_LCDON   0x80 /* Enable LCD Controller */
#define	LCKCON_DW_MASK   LCKCON_DWS_MASK
#define	LCKCON_DW_SHIFT   LCKCON_DWS_SHIFT
#define	LLBAR_ADDR   0xfffffa29
#define	LLBAR   BYTE_REF(LLBAR_ADDR)
#define	LLBAR_LBAR_MASK   0x7f /* Number of memory words to fill 1 line */
#define	LLBAR_LBAR_SHIFT   0
#define	LOTCR_ADDR   0xfffffa2b
#define	LOTCR   BYTE_REF(LOTCR_ADDR)
#define	LPOSR_ADDR   0xfffffa2d
#define	LPOSR   BYTE_REF(LPOSR_ADDR)
#define	LPOSR_BOS   0x08 /* Byte offset (for B/W mode only */
#define	LPOSR_POS_MASK   0x07 /* Pixel Offset Code */
#define	LPOSR_POS_SHIFT   0
#define	LFRCM_ADDR   0xfffffa31
#define	LFRCM   BYTE_REF(LFRCM_ADDR)
#define	LFRCM_YMOD_MASK   0x0f /* Vertical Modulation */
#define	LFRCM_YMOD_SHIFT   0
#define	LFRCM_XMOD_MASK   0xf0 /* Horizontal Modulation */
#define	LFRCM_XMOD_SHIFT   4
#define	LGPMR_ADDR   0xfffffa32
#define	LGPMR   WORD_REF(LGPMR_ADDR)
#define	LGPMR_GLEVEL3_MASK   0x000f
#define	LGPMR_GLEVEL3_SHIFT   0
#define	LGPMR_GLEVEL2_MASK   0x00f0
#define	LGPMR_GLEVEL2_SHIFT   4
#define	LGPMR_GLEVEL0_MASK   0x0f00
#define	LGPMR_GLEVEL0_SHIFT   8
#define	LGPMR_GLEVEL1_MASK   0xf000
#define	LGPMR_GLEVEL1_SHIFT   12
#define	RTCTIME_ADDR   0xfffffb00
#define	RTCTIME   LONG_REF(RTCTIME_ADDR)
#define	RTCTIME_SECONDS_MASK   0x0000003f /* Seconds */
#define	RTCTIME_SECONDS_SHIFT   0
#define	RTCTIME_MINUTES_MASK   0x003f0000 /* Minutes */
#define	RTCTIME_MINUTES_SHIFT   16
#define	RTCTIME_HOURS_MASK   0x1f000000 /* Hours */
#define	RTCTIME_HOURS_SHIFT   24
#define	RTCALRM_ADDR   0xfffffb04
#define	RTCALRM   LONG_REF(RTCALRM_ADDR)
#define	RTCALRM_SECONDS_MASK   0x0000003f /* Seconds */
#define	RTCALRM_SECONDS_SHIFT   0
#define	RTCALRM_MINUTES_MASK   0x003f0000 /* Minutes */
#define	RTCALRM_MINUTES_SHIFT   16
#define	RTCALRM_HOURS_MASK   0x1f000000 /* Hours */
#define	RTCALRM_HOURS_SHIFT   24
#define	RTCCTL_ADDR   0xfffffb0c
#define	RTCCTL   WORD_REF(RTCCTL_ADDR)
#define	RTCCTL_384   0x0020 /* Crystal Selection */
#define	RTCCTL_ENABLE   0x0080 /* RTC Enable */
#define	RTCCTL_XTL   RTCCTL_384
#define	RTCCTL_EN   RTCCTL_ENABLE
#define	RTCISR_ADDR   0xfffffb0e
#define	RTCISR   WORD_REF(RTCISR_ADDR)
#define	RTCISR_SW   0x0001 /* Stopwatch timed out */
#define	RTCISR_MIN   0x0002 /* 1-minute interrupt has occurred */
#define	RTCISR_ALM   0x0004 /* Alarm interrupt has occurred */
#define	RTCISR_DAY   0x0008 /* 24-hour rollover interrupt has occurred */
#define	RTCISR_1HZ   0x0010 /* 1Hz interrupt has occurred */
#define	RTCIENR_ADDR   0xfffffb10
#define	RTCIENR   WORD_REF(RTCIENR_ADDR)
#define	RTCIENR_SW   0x0001 /* Stopwatch interrupt enable */
#define	RTCIENR_MIN   0x0002 /* 1-minute interrupt enable */
#define	RTCIENR_ALM   0x0004 /* Alarm interrupt enable */
#define	RTCIENR_DAY   0x0008 /* 24-hour rollover interrupt enable */
#define	RTCIENR_1HZ   0x0010 /* 1Hz interrupt enable */
#define	STPWCH_ADDR   0xfffffb12
#define	STPWCH   WORD_REF(STPWCH)
#define	STPWCH_CNT_MASK   0x00ff /* Stopwatch countdown value */
#define	SPTWCH_CNT_SHIFT   0

Macro Definition Documentation

#define BYTE_REF

(

addr

)

(*((volatile unsigned char*)addr))

Definition at line 15 of file MC68328.h.

#define CSA0   LONG_REF(CSA0_ADDR)

Definition at line 99 of file MC68328.h.

#define CSA0_ADDR   0xfffff110

Definition at line 94 of file MC68328.h.

#define CSA1   LONG_REF(CSA1_ADDR)

Definition at line 100 of file MC68328.h.

#define CSA1_ADDR   0xfffff114

Definition at line 95 of file MC68328.h.

#define CSA2   LONG_REF(CSA2_ADDR)

Definition at line 101 of file MC68328.h.

#define CSA2_ADDR   0xfffff118

Definition at line 96 of file MC68328.h.

#define CSA3   LONG_REF(CSA3_ADDR)

Definition at line 102 of file MC68328.h.

#define CSA3_ADDR   0xfffff11c

Definition at line 97 of file MC68328.h.

#define CSA_AC_MASK   0xff000000 /* Address Compare (bits 23-16) */

Definition at line 110 of file MC68328.h.

#define CSA_AC_SHIFT   24

Definition at line 111 of file MC68328.h.

#define CSA_AM_MASK   0x0000ff00 /* Address Mask (bits 23-16) */

Definition at line 107 of file MC68328.h.

#define CSA_AM_SHIFT   8

Definition at line 108 of file MC68328.h.

#define CSA_BUSW   0x00010000 /* Bus Width Select */

Definition at line 109 of file MC68328.h.

#define CSA_RO   0x00000008 /* Read-Only */

Definition at line 106 of file MC68328.h.

#define CSA_WAIT_MASK   0x00000007 /* Wait State Selection */

Definition at line 104 of file MC68328.h.

#define CSA_WAIT_SHIFT   0

Definition at line 105 of file MC68328.h.

#define CSB0   LONG_REF(CSB0_ADDR)

Definition at line 121 of file MC68328.h.

#define CSB0_ADDR   0xfffff120

Definition at line 116 of file MC68328.h.

#define CSB1   LONG_REF(CSB1_ADDR)

Definition at line 122 of file MC68328.h.

#define CSB1_ADDR   0xfffff124

Definition at line 117 of file MC68328.h.

#define CSB2   LONG_REF(CSB2_ADDR)

Definition at line 123 of file MC68328.h.

#define CSB2_ADDR   0xfffff128

Definition at line 118 of file MC68328.h.

#define CSB3   LONG_REF(CSB3_ADDR)

Definition at line 124 of file MC68328.h.

#define CSB3_ADDR   0xfffff12c

Definition at line 119 of file MC68328.h.

#define CSB_AC_MASK   0xff000000 /* Address Compare (bits 23-16) */

Definition at line 132 of file MC68328.h.

#define CSB_AC_SHIFT   24

Definition at line 133 of file MC68328.h.

#define CSB_AM_MASK   0x0000ff00 /* Address Mask (bits 23-16) */

Definition at line 129 of file MC68328.h.

#define CSB_AM_SHIFT   8

Definition at line 130 of file MC68328.h.

#define CSB_BUSW   0x00010000 /* Bus Width Select */

Definition at line 131 of file MC68328.h.

#define CSB_RO   0x00000008 /* Read-Only */

Definition at line 128 of file MC68328.h.

#define CSB_WAIT_MASK   0x00000007 /* Wait State Selection */

Definition at line 126 of file MC68328.h.

#define CSB_WAIT_SHIFT   0

Definition at line 127 of file MC68328.h.

#define CSC0   LONG_REF(CSC0_ADDR)

Definition at line 143 of file MC68328.h.

#define CSC0_ADDR   0xfffff130

Definition at line 138 of file MC68328.h.

#define CSC1   LONG_REF(CSC1_ADDR)

Definition at line 144 of file MC68328.h.

#define CSC1_ADDR   0xfffff134

Definition at line 139 of file MC68328.h.

#define CSC2   LONG_REF(CSC2_ADDR)

Definition at line 145 of file MC68328.h.

#define CSC2_ADDR   0xfffff138

Definition at line 140 of file MC68328.h.

#define CSC3   LONG_REF(CSC3_ADDR)

Definition at line 146 of file MC68328.h.

#define CSC3_ADDR   0xfffff13c

Definition at line 141 of file MC68328.h.

#define CSC_AC_MASK   0xfff00000 /* Address Compare (bits 23-12) */

Definition at line 154 of file MC68328.h.

#define CSC_AC_SHIFT   20

Definition at line 155 of file MC68328.h.

#define CSC_AM_MASK   0x0000fff0 /* Address Mask (bits 23-12) */

Definition at line 151 of file MC68328.h.

#define CSC_AM_SHIFT   4

Definition at line 152 of file MC68328.h.

#define CSC_BUSW   0x00010000 /* Bus Width Select */

Definition at line 153 of file MC68328.h.

#define CSC_RO   0x00000008 /* Read-Only */

Definition at line 150 of file MC68328.h.

#define CSC_WAIT_MASK   0x00000007 /* Wait State Selection */

Definition at line 148 of file MC68328.h.

#define CSC_WAIT_SHIFT   0

Definition at line 149 of file MC68328.h.

#define CSD0   LONG_REF(CSD0_ADDR)

Definition at line 165 of file MC68328.h.

#define CSD0_ADDR   0xfffff140

Definition at line 160 of file MC68328.h.

#define CSD1   LONG_REF(CSD1_ADDR)

Definition at line 166 of file MC68328.h.

#define CSD1_ADDR   0xfffff144

Definition at line 161 of file MC68328.h.

#define CSD2   LONG_REF(CSD2_ADDR)

Definition at line 167 of file MC68328.h.

#define CSD2_ADDR   0xfffff148

Definition at line 162 of file MC68328.h.

#define CSD3   LONG_REF(CSD3_ADDR)

Definition at line 168 of file MC68328.h.

#define CSD3_ADDR   0xfffff14c

Definition at line 163 of file MC68328.h.

#define CSD_AC_MASK   0xfff00000 /* Address Compare (bits 23-12) */

Definition at line 176 of file MC68328.h.

#define CSD_AC_SHIFT   20

Definition at line 177 of file MC68328.h.

#define CSD_AM_MASK   0x0000fff0 /* Address Mask (bits 23-12) */

Definition at line 173 of file MC68328.h.

#define CSD_AM_SHIFT   4

Definition at line 174 of file MC68328.h.

#define CSD_BUSW   0x00010000 /* Bus Width Select */

Definition at line 175 of file MC68328.h.

#define CSD_RO   0x00000008 /* Read-Only */

Definition at line 172 of file MC68328.h.

#define CSD_WAIT_MASK   0x00000007 /* Wait State Selection */

Definition at line 170 of file MC68328.h.

#define CSD_WAIT_SHIFT   0

Definition at line 171 of file MC68328.h.

#define GET_FIELD	(		reg,
			field
	)		(((reg) & field##_MASK) >> field##_SHIFT)

Definition at line 20 of file MC68328.h.

#define GRMMASK_GMA_MASK   0xfffff0 /* Group Base Mask (bits 31-20) */

Definition at line 89 of file MC68328.h.

#define GRPBASE_GBA_MASK   0xfff0 /* Group Base Address (bits 31-20) */

Definition at line 74 of file MC68328.h.

#define GRPBASE_V   0x0001 /* Valid */

Definition at line 73 of file MC68328.h.

#define GRPBASEA   WORD_REF(GRPBASEA_ADDR)

Definition at line 68 of file MC68328.h.

#define GRPBASEA_ADDR   0xfffff100

Definition at line 63 of file MC68328.h.

#define GRPBASEB   WORD_REF(GRPBASEB_ADDR)

Definition at line 69 of file MC68328.h.

#define GRPBASEB_ADDR   0xfffff102

Definition at line 64 of file MC68328.h.

#define GRPBASEC   WORD_REF(GRPBASEC_ADDR)

Definition at line 70 of file MC68328.h.

#define GRPBASEC_ADDR   0xfffff104

Definition at line 65 of file MC68328.h.

#define GRPBASED   WORD_REF(GRPBASED_ADDR)

Definition at line 71 of file MC68328.h.

#define GRPBASED_ADDR   0xfffff106

Definition at line 66 of file MC68328.h.

#define GRPMASKA   WORD_REF(GRPMASKA_ADDR)

Definition at line 84 of file MC68328.h.

#define GRPMASKA_ADDR   0xfffff108

Definition at line 79 of file MC68328.h.

#define GRPMASKB   WORD_REF(GRPMASKB_ADDR)

Definition at line 85 of file MC68328.h.

#define GRPMASKB_ADDR   0xfffff10a

Definition at line 80 of file MC68328.h.

#define GRPMASKC   WORD_REF(GRPMASKC_ADDR)

Definition at line 86 of file MC68328.h.

#define GRPMASKC_ADDR   0xfffff10c

Definition at line 81 of file MC68328.h.

#define GRPMASKD   WORD_REF(GRPMASKD_ADDR)

Definition at line 87 of file MC68328.h.

#define GRPMASKD_ADDR   0xfffff10e

Definition at line 82 of file MC68328.h.

#define ICR   WORD_REF(ICR_ADDR)

Definition at line 244 of file MC68328.h.

#define ICR_ADRR   0xfffff302

Definition at line 243 of file MC68328.h.

#define ICR_ET1   0x0800 /* Edge Trigger Select for IRQ1 */

Definition at line 249 of file MC68328.h.

#define ICR_ET2   0x0400 /* Edge Trigger Select for IRQ2 */

Definition at line 248 of file MC68328.h.

#define ICR_ET3   0x0200 /* Edge Trigger Select for IRQ3 */

Definition at line 247 of file MC68328.h.

#define ICR_ET6   0x0100 /* Edge Trigger Select for IRQ6 */

Definition at line 246 of file MC68328.h.

#define ICR_POL1   0x8000 /* Polarity Control for IRQ1 */

Definition at line 253 of file MC68328.h.

#define ICR_POL2   0x4000 /* Polarity Control for IRQ2 */

Definition at line 252 of file MC68328.h.

#define ICR_POL3   0x2000 /* Polarity Control for IRQ3 */

Definition at line 251 of file MC68328.h.

#define ICR_POL6   0x1000 /* Polarity Control for IRQ6 */

Definition at line 250 of file MC68328.h.

#define IMR   LONG_REF(IMR_ADDR)

Definition at line 259 of file MC68328.h.

#define IMR_ADDR   0xfffff304

Definition at line 258 of file MC68328.h.

#define IMR_MINT0   (1 << INT0_IRQ_NUM) /* Mask External INT0 */

Definition at line 303 of file MC68328.h.

#define IMR_MINT1   (1 << INT1_IRQ_NUM) /* Mask External INT1 */

Definition at line 304 of file MC68328.h.

#define IMR_MINT2   (1 << INT2_IRQ_NUM) /* Mask External INT2 */

Definition at line 305 of file MC68328.h.

#define IMR_MINT3   (1 << INT3_IRQ_NUM) /* Mask External INT3 */

Definition at line 306 of file MC68328.h.

#define IMR_MINT4   (1 << INT4_IRQ_NUM) /* Mask External INT4 */

Definition at line 307 of file MC68328.h.

#define IMR_MINT5   (1 << INT5_IRQ_NUM) /* Mask External INT5 */

Definition at line 308 of file MC68328.h.

#define IMR_MINT6   (1 << INT6_IRQ_NUM) /* Mask External INT6 */

Definition at line 309 of file MC68328.h.

#define IMR_MINT7   (1 << INT7_IRQ_NUM) /* Mask External INT7 */

Definition at line 310 of file MC68328.h.

#define IMR_MIRQ1   (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */

Definition at line 311 of file MC68328.h.

#define IMR_MIRQ2   (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */

Definition at line 312 of file MC68328.h.

#define IMR_MIRQ3   (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */

Definition at line 313 of file MC68328.h.

#define IMR_MIRQ6   (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */

Definition at line 314 of file MC68328.h.

#define IMR_MIRQ7   (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */

Definition at line 318 of file MC68328.h.

#define IMR_MKB   (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */

Definition at line 301 of file MC68328.h.

#define IMR_MPEN   (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */

Definition at line 315 of file MC68328.h.

#define IMR_MPWM   (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */

Definition at line 302 of file MC68328.h.

#define IMR_MRTC   (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */

Definition at line 300 of file MC68328.h.

#define IMR_MSPI   IMR_MSPIM

Definition at line 321 of file MC68328.h.

#define IMR_MSPIM   (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */

Definition at line 296 of file MC68328.h.

#define IMR_MSPIS   (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */

Definition at line 316 of file MC68328.h.

#define IMR_MTMR   IMR_MTMR1

Definition at line 322 of file MC68328.h.

#define IMR_MTMR1   (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */

Definition at line 317 of file MC68328.h.

#define IMR_MTMR2   (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */

Definition at line 297 of file MC68328.h.

#define IMR_MUART   (1 << UART_IRQ_NUM) /* Mask UART interrupt */

Definition at line 298 of file MC68328.h.

#define IMR_MWDT   (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */

Definition at line 299 of file MC68328.h.

#define INT0_IRQ_NUM   8 /* External INT0 */

Definition at line 272 of file MC68328.h.

#define INT1_IRQ_NUM   9 /* External INT1 */

Definition at line 273 of file MC68328.h.

#define INT2_IRQ_NUM   10 /* External INT2 */

Definition at line 274 of file MC68328.h.

#define INT3_IRQ_NUM   11 /* External INT3 */

Definition at line 275 of file MC68328.h.

#define INT4_IRQ_NUM   12 /* External INT4 */

Definition at line 276 of file MC68328.h.

#define INT5_IRQ_NUM   13 /* External INT5 */

Definition at line 277 of file MC68328.h.

#define INT6_IRQ_NUM   14 /* External INT6 */

Definition at line 278 of file MC68328.h.

#define INT7_IRQ_NUM   15 /* External INT7 */

Definition at line 279 of file MC68328.h.

#define IPR   LONG_REF(IPR_ADDR)

Definition at line 392 of file MC68328.h.

#define IPR_ADDR   0xfffff310

Definition at line 391 of file MC68328.h.

#define IPR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */

Definition at line 401 of file MC68328.h.

#define IPR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */

Definition at line 402 of file MC68328.h.

#define IPR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */

Definition at line 403 of file MC68328.h.

#define IPR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */

Definition at line 404 of file MC68328.h.

#define IPR_INT4   (1 << INT4_IRQ_NUM) /* External INT4 */

Definition at line 405 of file MC68328.h.

#define IPR_INT5   (1 << INT5_IRQ_NUM) /* External INT5 */

Definition at line 406 of file MC68328.h.

#define IPR_INT6   (1 << INT6_IRQ_NUM) /* External INT6 */

Definition at line 407 of file MC68328.h.

#define IPR_INT7   (1 << INT7_IRQ_NUM) /* External INT7 */

Definition at line 408 of file MC68328.h.

#define IPR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */

Definition at line 409 of file MC68328.h.

#define IPR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */

Definition at line 410 of file MC68328.h.

#define IPR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */

Definition at line 411 of file MC68328.h.

#define IPR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */

Definition at line 412 of file MC68328.h.

#define IPR_IRQ7   (1 << IRQ7_IRQ_NUM) /* IRQ7 */

Definition at line 416 of file MC68328.h.

#define IPR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */

Definition at line 399 of file MC68328.h.

#define IPR_PEN   (1 << PEN_IRQ_NUM) /* Pen Interrupt */

Definition at line 413 of file MC68328.h.

#define IPR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */

Definition at line 400 of file MC68328.h.

#define IPR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */

Definition at line 398 of file MC68328.h.

#define IPR_SPI   IPR_SPIM

Definition at line 419 of file MC68328.h.

#define IPR_SPIM   (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */

Definition at line 394 of file MC68328.h.

#define IPR_SPIS   (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */

Definition at line 414 of file MC68328.h.

#define IPR_TMR   IPR_TMR1

Definition at line 420 of file MC68328.h.

#define IPR_TMR1   (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */

Definition at line 415 of file MC68328.h.

#define IPR_TMR2   (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */

Definition at line 395 of file MC68328.h.

#define IPR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */

Definition at line 396 of file MC68328.h.

#define IPR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */

Definition at line 397 of file MC68328.h.

#define IRQ1_IRQ_NUM   16 /* IRQ1 */

Definition at line 280 of file MC68328.h.

#define IRQ2_IRQ_NUM   17 /* IRQ2 */

Definition at line 281 of file MC68328.h.

#define IRQ3_IRQ_NUM   18 /* IRQ3 */

Definition at line 282 of file MC68328.h.

#define IRQ6_IRQ_NUM   19 /* IRQ6 */

Definition at line 283 of file MC68328.h.

#define IRQ7_IRQ_NUM   23 /* IRQ7 */

Definition at line 287 of file MC68328.h.

#define ISR   LONG_REF(ISR_ADDR)

Definition at line 358 of file MC68328.h.

#define ISR_ADDR   0xfffff30c

Definition at line 357 of file MC68328.h.

#define ISR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */

Definition at line 367 of file MC68328.h.

#define ISR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */

Definition at line 368 of file MC68328.h.

#define ISR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */

Definition at line 369 of file MC68328.h.

#define ISR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */

Definition at line 370 of file MC68328.h.

#define ISR_INT4   (1 << INT4_IRQ_NUM) /* External INT4 */

Definition at line 371 of file MC68328.h.

#define ISR_INT5   (1 << INT5_IRQ_NUM) /* External INT5 */

Definition at line 372 of file MC68328.h.

#define ISR_INT6   (1 << INT6_IRQ_NUM) /* External INT6 */

Definition at line 373 of file MC68328.h.

#define ISR_INT7   (1 << INT7_IRQ_NUM) /* External INT7 */

Definition at line 374 of file MC68328.h.

#define ISR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */

Definition at line 375 of file MC68328.h.

#define ISR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */

Definition at line 376 of file MC68328.h.

#define ISR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */

Definition at line 377 of file MC68328.h.

#define ISR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */

Definition at line 378 of file MC68328.h.

#define ISR_IRQ7   (1 << IRQ7_IRQ_NUM) /* IRQ7 */

Definition at line 382 of file MC68328.h.

#define ISR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */

Definition at line 365 of file MC68328.h.

#define ISR_PEN   (1 << PEN_IRQ_NUM) /* Pen Interrupt */

Definition at line 379 of file MC68328.h.

#define ISR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */

Definition at line 366 of file MC68328.h.

#define ISR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */

Definition at line 364 of file MC68328.h.

#define ISR_SPI   ISR_SPIM

Definition at line 385 of file MC68328.h.

#define ISR_SPIM   (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */

Definition at line 360 of file MC68328.h.

#define ISR_SPIS   (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */

Definition at line 380 of file MC68328.h.

#define ISR_TMR   ISR_TMR1

Definition at line 386 of file MC68328.h.

#define ISR_TMR1   (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */

Definition at line 381 of file MC68328.h.

#define ISR_TMR2   (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */

Definition at line 361 of file MC68328.h.

#define ISR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */

Definition at line 362 of file MC68328.h.

#define ISR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */

Definition at line 363 of file MC68328.h.

#define IVR   BYTE_REF(IVR_ADDR)

Definition at line 236 of file MC68328.h.

#define IVR_ADDR   0xfffff300

Definition at line 235 of file MC68328.h.

#define IVR_VECTOR_MASK   0xF8

Definition at line 238 of file MC68328.h.

#define IWR   LONG_REF(IWR_ADDR)

Definition at line 328 of file MC68328.h.

#define IWR_ADDR   0xfffff308

Definition at line 327 of file MC68328.h.

#define IWR_INT0   (1 << INT0_IRQ_NUM) /* External INT0 */

Definition at line 337 of file MC68328.h.

#define IWR_INT1   (1 << INT1_IRQ_NUM) /* External INT1 */

Definition at line 338 of file MC68328.h.

#define IWR_INT2   (1 << INT2_IRQ_NUM) /* External INT2 */

Definition at line 339 of file MC68328.h.

#define IWR_INT3   (1 << INT3_IRQ_NUM) /* External INT3 */

Definition at line 340 of file MC68328.h.

#define IWR_INT4   (1 << INT4_IRQ_NUM) /* External INT4 */

Definition at line 341 of file MC68328.h.

#define IWR_INT5   (1 << INT5_IRQ_NUM) /* External INT5 */

Definition at line 342 of file MC68328.h.

#define IWR_INT6   (1 << INT6_IRQ_NUM) /* External INT6 */

Definition at line 343 of file MC68328.h.

#define IWR_INT7   (1 << INT7_IRQ_NUM) /* External INT7 */

Definition at line 344 of file MC68328.h.

#define IWR_IRQ1   (1 << IRQ1_IRQ_NUM) /* IRQ1 */

Definition at line 345 of file MC68328.h.

#define IWR_IRQ2   (1 << IRQ2_IRQ_NUM) /* IRQ2 */

Definition at line 346 of file MC68328.h.

#define IWR_IRQ3   (1 << IRQ3_IRQ_NUM) /* IRQ3 */

Definition at line 347 of file MC68328.h.

#define IWR_IRQ6   (1 << IRQ6_IRQ_NUM) /* IRQ6 */

Definition at line 348 of file MC68328.h.

#define IWR_IRQ7   (1 << IRQ7_IRQ_NUM) /* IRQ7 */

Definition at line 352 of file MC68328.h.

#define IWR_KB   (1 << KB_IRQ_NUM) /* Keyboard Interrupt */

Definition at line 335 of file MC68328.h.

#define IWR_PEN   (1 << PEN_IRQ_NUM) /* Pen Interrupt */

Definition at line 349 of file MC68328.h.

#define IWR_PWM   (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */

Definition at line 336 of file MC68328.h.

#define IWR_RTC   (1 << RTC_IRQ_NUM) /* RTC interrupt */

Definition at line 334 of file MC68328.h.

#define IWR_SPIM   (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */

Definition at line 330 of file MC68328.h.

#define IWR_SPIS   (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */

Definition at line 350 of file MC68328.h.

#define IWR_TMR1   (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */

Definition at line 351 of file MC68328.h.

#define IWR_TMR2   (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */

Definition at line 331 of file MC68328.h.

#define IWR_UART   (1 << UART_IRQ_NUM) /* UART interrupt */

Definition at line 332 of file MC68328.h.

#define IWR_WDT   (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */

Definition at line 333 of file MC68328.h.

#define KB_IRQ_NUM   6 /* Keyboard Interrupt */

Definition at line 270 of file MC68328.h.

#define LACDRC   BYTE_REF(LACDRC_ADDR)

Definition at line 1106 of file MC68328.h.

#define LACDRC_ACD_MASK   0x0f /* Alternate Crystal Direction Control */

Definition at line 1108 of file MC68328.h.

#define LACDRC_ACD_SHIFT   0

Definition at line 1109 of file MC68328.h.

#define LACDRC_ADDR   0xfffffa23

Definition at line 1105 of file MC68328.h.

#define LBLKC   BYTE_REF(LBLKC_ADDR)

Definition at line 1071 of file MC68328.h.

#define LBLKC_ADDR   0xfffffa1f

Definition at line 1070 of file MC68328.h.

#define LBLKC_BD_MASK   0x7f /* Blink Divisor */

Definition at line 1073 of file MC68328.h.

#define LBLKC_BD_SHIFT   0

Definition at line 1074 of file MC68328.h.

#define LBLKC_BKEN   0x80 /* Blink Enabled */

Definition at line 1075 of file MC68328.h.

#define LCKCON   BYTE_REF(LCKCON_ADDR)

Definition at line 1124 of file MC68328.h.

#define LCKCON_ADDR   0xfffffa27

Definition at line 1123 of file MC68328.h.

#define LCKCON_DMA16   0x40 /* DMA burst length */

Definition at line 1130 of file MC68328.h.

#define LCKCON_DW_MASK   LCKCON_DWS_MASK

Definition at line 1134 of file MC68328.h.

#define LCKCON_DW_SHIFT   LCKCON_DWS_SHIFT

Definition at line 1135 of file MC68328.h.

#define LCKCON_DWIDTH   0x02 /* Display Memory Width */

Definition at line 1127 of file MC68328.h.

#define LCKCON_DWS_MASK   0x3c /* Display Wait-State */

Definition at line 1128 of file MC68328.h.

#define LCKCON_DWS_SHIFT   2

Definition at line 1129 of file MC68328.h.

#define LCKCON_LCDON   0x80 /* Enable LCD Controller */

Definition at line 1131 of file MC68328.h.

#define LCKCON_PCDS   0x01 /* Pixel Clock Divider Source Select */

Definition at line 1126 of file MC68328.h.

#define LCWCH   WORD_REF(LCWCH_ADDR)

Definition at line 1060 of file MC68328.h.

#define LCWCH_ADDR   0xfffffa1c

Definition at line 1059 of file MC68328.h.

#define LCWCH_CH_MASK   0x001f /* Cursor Height */

Definition at line 1062 of file MC68328.h.

#define LCWCH_CH_SHIFT   0

Definition at line 1063 of file MC68328.h.

#define LCWCH_CW_MASK   0x1f00 /* Cursor Width */

Definition at line 1064 of file MC68328.h.

#define LCWCH_CW_SHIFT   8

Definition at line 1065 of file MC68328.h.

#define LCXP   WORD_REF(LCXP_ADDR)

Definition at line 1039 of file MC68328.h.

#define LCXP_ADDR   0xfffffa18

Definition at line 1038 of file MC68328.h.

#define LCXP_CC_BLACK   0x4000

Definition at line 1043 of file MC68328.h.

#define LCXP_CC_MASK   0xc000 /* Cursor Control */

Definition at line 1041 of file MC68328.h.

#define LCXP_CC_REVERSED   0x8000

Definition at line 1044 of file MC68328.h.

#define LCXP_CC_TRAMSPARENT   0x0000

Definition at line 1042 of file MC68328.h.

#define LCXP_CC_WHITE   0xc000

Definition at line 1045 of file MC68328.h.

#define LCXP_CXP_MASK   0x02ff /* Cursor X position */

Definition at line 1046 of file MC68328.h.

#define LCYP   WORD_REF(LCYP_ADDR)

Definition at line 1052 of file MC68328.h.

#define LCYP_ADDR   0xfffffa1a

Definition at line 1051 of file MC68328.h.

#define LCYP_CYP_MASK   0x01ff /* Cursor Y Position */

Definition at line 1054 of file MC68328.h.

#define LFRCM   BYTE_REF(LFRCM_ADDR)

Definition at line 1166 of file MC68328.h.

#define LFRCM_ADDR   0xfffffa31

Definition at line 1165 of file MC68328.h.

#define LFRCM_XMOD_MASK   0xf0 /* Horizontal Modulation */

Definition at line 1170 of file MC68328.h.

#define LFRCM_XMOD_SHIFT   4

Definition at line 1171 of file MC68328.h.

#define LFRCM_YMOD_MASK   0x0f /* Vertical Modulation */

Definition at line 1168 of file MC68328.h.

#define LFRCM_YMOD_SHIFT   0

Definition at line 1169 of file MC68328.h.

#define LGPMR   WORD_REF(LGPMR_ADDR)

Definition at line 1177 of file MC68328.h.

#define LGPMR_ADDR   0xfffffa32

Definition at line 1176 of file MC68328.h.

#define LGPMR_GLEVEL0_MASK   0x0f00

Definition at line 1183 of file MC68328.h.

#define LGPMR_GLEVEL0_SHIFT   8

Definition at line 1184 of file MC68328.h.

#define LGPMR_GLEVEL1_MASK   0xf000

Definition at line 1185 of file MC68328.h.

#define LGPMR_GLEVEL1_SHIFT   12

Definition at line 1186 of file MC68328.h.

#define LGPMR_GLEVEL2_MASK   0x00f0

Definition at line 1181 of file MC68328.h.

#define LGPMR_GLEVEL2_SHIFT   4

Definition at line 1182 of file MC68328.h.

#define LGPMR_GLEVEL3_MASK   0x000f

Definition at line 1179 of file MC68328.h.

#define LGPMR_GLEVEL3_SHIFT   0

Definition at line 1180 of file MC68328.h.

#define LLBAR   BYTE_REF(LLBAR_ADDR)

Definition at line 1141 of file MC68328.h.

#define LLBAR_ADDR   0xfffffa29

Definition at line 1140 of file MC68328.h.

#define LLBAR_LBAR_MASK   0x7f /* Number of memory words to fill 1 line */

Definition at line 1143 of file MC68328.h.

#define LLBAR_LBAR_SHIFT   0

Definition at line 1144 of file MC68328.h.

#define LONG_REF

(

addr

)

(*((volatile unsigned long*)addr))

Definition at line 17 of file MC68328.h.

#define LOTCR   BYTE_REF(LOTCR_ADDR)

Definition at line 1150 of file MC68328.h.

#define LOTCR_ADDR   0xfffffa2b

Definition at line 1149 of file MC68328.h.

#define LPICF   BYTE_REF(LPICF_ADDR)

Definition at line 1081 of file MC68328.h.

#define LPICF_ADDR   0xfffffa20

Definition at line 1080 of file MC68328.h.

#define LPICF_GS_BW   0x00

Definition at line 1084 of file MC68328.h.

#define LPICF_GS_GRAY_4   0x01

Definition at line 1085 of file MC68328.h.

#define LPICF_GS_MASK   0x01 /* Gray-Scale Mode */

Definition at line 1083 of file MC68328.h.

#define LPICF_PBSIZ_1   0x00

Definition at line 1087 of file MC68328.h.

#define LPICF_PBSIZ_2   0x02

Definition at line 1088 of file MC68328.h.

#define LPICF_PBSIZ_4   0x04

Definition at line 1089 of file MC68328.h.

#define LPICF_PBSIZ_MASK   0x06 /* Panel Bus Width */

Definition at line 1086 of file MC68328.h.

#define LPOLCF   BYTE_REF(LPOLCF_ADDR)

Definition at line 1095 of file MC68328.h.

#define LPOLCF_ADDR   0xfffffa21

Definition at line 1094 of file MC68328.h.

#define LPOLCF_FLMPOL   0x04 /* Frame Marker Polarity */

Definition at line 1099 of file MC68328.h.

#define LPOLCF_LCKPOL   0x08 /* LCD Shift Lock Polarity */

Definition at line 1100 of file MC68328.h.

#define LPOLCF_LPPOL   0x02 /* Line Pulse Polarity */

Definition at line 1098 of file MC68328.h.

#define LPOLCF_PIXPOL   0x01 /* Pixel Polarity */

Definition at line 1097 of file MC68328.h.

#define LPOSR   BYTE_REF(LPOSR_ADDR)

Definition at line 1156 of file MC68328.h.

#define LPOSR_ADDR   0xfffffa2d

Definition at line 1155 of file MC68328.h.

#define LPOSR_BOS   0x08 /* Byte offset (for B/W mode only */

Definition at line 1158 of file MC68328.h.

#define LPOSR_POS_MASK   0x07 /* Pixel Offset Code */

Definition at line 1159 of file MC68328.h.

#define LPOSR_POS_SHIFT   0

Definition at line 1160 of file MC68328.h.

#define LPXCD   BYTE_REF(LPXCD_ADDR)

Definition at line 1115 of file MC68328.h.

#define LPXCD_ADDR   0xfffffa25

Definition at line 1114 of file MC68328.h.

#define LPXCD_PCD_MASK   0x3f /* Pixel Clock Divider */

Definition at line 1117 of file MC68328.h.

#define LPXCD_PCD_SHIFT   0

Definition at line 1118 of file MC68328.h.

#define LSSA   LONG_REF(LSSA_ADDR)

Definition at line 1009 of file MC68328.h.

#define LSSA_ADDR   0xfffffa00

Definition at line 1008 of file MC68328.h.

#define LSSA_SSA_MASK   0xfffffffe /* Bit 0 is reserved */

Definition at line 1011 of file MC68328.h.

#define LVPW   BYTE_REF(LVPW_ADDR)

Definition at line 1017 of file MC68328.h.

#define LVPW_ADDR   0xfffffa05

Definition at line 1016 of file MC68328.h.

#define LXMAX   WORD_REF(LXMAX_ADDR)

Definition at line 1023 of file MC68328.h.

#define LXMAX_ADDR   0xfffffa08

Definition at line 1022 of file MC68328.h.

#define LXMAX_XM_MASK   0x02ff /* Bits 0-3 are reserved */

Definition at line 1025 of file MC68328.h.

#define LYMAX   WORD_REF(LYMAX_ADDR)

Definition at line 1031 of file MC68328.h.

#define LYMAX_ADDR   0xfffffa0a

Definition at line 1030 of file MC68328.h.

#define LYMAX_YM_MASK   0x02ff /* Bits 10-15 are reserved */

Definition at line 1033 of file MC68328.h.

#define MRR   LONG_REF(MRR_ADDR)

Definition at line 46 of file MC68328.h.

#define MRR_ADDR   0xfffff004

Definition at line 45 of file MC68328.h.

#define PA

(

x

)

(1 << (x))

Definition at line 439 of file MC68328.h.

#define PA_A

(

x

)

PA((x) - 16) /* This is specific to PA only! */

Definition at line 440 of file MC68328.h.

#define PA_A16   PA(0) /* Use A16 as PA(0) */

Definition at line 442 of file MC68328.h.

#define PA_A17   PA(1) /* Use A17 as PA(1) */

Definition at line 443 of file MC68328.h.

#define PA_A18   PA(2) /* Use A18 as PA(2) */

Definition at line 444 of file MC68328.h.

#define PA_A19   PA(3) /* Use A19 as PA(3) */

Definition at line 445 of file MC68328.h.

#define PA_A20   PA(4) /* Use A20 as PA(4) */

Definition at line 446 of file MC68328.h.

#define PA_A21   PA(5) /* Use A21 as PA(5) */

Definition at line 447 of file MC68328.h.

#define PA_A22   PA(6) /* Use A22 as PA(6) */

Definition at line 448 of file MC68328.h.

#define PA_A23   PA(7) /* Use A23 as PA(7) */

Definition at line 449 of file MC68328.h.

#define PADATA   BYTE_REF(PADATA_ADDR)

Definition at line 436 of file MC68328.h.

#define PADATA_ADDR   0xfffff401 /* Port A data register */

Definition at line 432 of file MC68328.h.

#define PADIR   BYTE_REF(PADIR_ADDR)

Definition at line 435 of file MC68328.h.

#define PADIR_ADDR   0xfffff400 /* Port A direction reg */

Definition at line 431 of file MC68328.h.

#define PASEL   BYTE_REF(PASEL_ADDR)

Definition at line 437 of file MC68328.h.

#define PASEL_ADDR   0xfffff403 /* Port A Select register */

Definition at line 433 of file MC68328.h.

#define PB

(

x

)

(1 << (x))

Definition at line 462 of file MC68328.h.

#define PB_D

(

x

)

PB(x) /* This is specific to port B only */

Definition at line 463 of file MC68328.h.

#define PB_D0   PB(0) /* Use D0 as PB(0) */

Definition at line 465 of file MC68328.h.

#define PB_D1   PB(1) /* Use D1 as PB(1) */

Definition at line 466 of file MC68328.h.

#define PB_D2   PB(2) /* Use D2 as PB(2) */

Definition at line 467 of file MC68328.h.

#define PB_D3   PB(3) /* Use D3 as PB(3) */

Definition at line 468 of file MC68328.h.

#define PB_D4   PB(4) /* Use D4 as PB(4) */

Definition at line 469 of file MC68328.h.

#define PB_D5   PB(5) /* Use D5 as PB(5) */

Definition at line 470 of file MC68328.h.

#define PB_D6   PB(6) /* Use D6 as PB(6) */

Definition at line 471 of file MC68328.h.

#define PB_D7   PB(7) /* Use D7 as PB(7) */

Definition at line 472 of file MC68328.h.

#define PBDATA   BYTE_REF(PBDATA_ADDR)

Definition at line 459 of file MC68328.h.

#define PBDATA_ADDR   0xfffff409 /* Port B data register */

Definition at line 455 of file MC68328.h.

#define PBDIR   BYTE_REF(PBDIR_ADDR)

Definition at line 458 of file MC68328.h.

#define PBDIR_ADDR   0xfffff408 /* Port B direction reg */

Definition at line 454 of file MC68328.h.

#define PBSEL   BYTE_REF(PBSEL_ADDR)

Definition at line 460 of file MC68328.h.

#define PBSEL_ADDR   0xfffff40b /* Port B Select Register */

Definition at line 456 of file MC68328.h.

#define PC

(

x

)

(1 << (x))

Definition at line 485 of file MC68328.h.

#define PC_DTACK   PC(5) /* Use DTACK as PC(5) */

Definition at line 488 of file MC68328.h.

#define PC_IRQ7   PC(4) /* Use IRQ7 as PC(4) */

Definition at line 489 of file MC68328.h.

#define PC_LDS   PC(2) /* Use LDS as PC(2) */

Definition at line 490 of file MC68328.h.

#define PC_MOCLK   PC(0) /* Use MOCLK as PC(0) */

Definition at line 492 of file MC68328.h.

#define PC_UDS   PC(1) /* Use UDS as PC(1) */

Definition at line 491 of file MC68328.h.

#define PC_WE   PC(6) /* Use WE as PC(6) */

Definition at line 487 of file MC68328.h.

#define PCDATA   BYTE_REF(PCDATA_ADDR)

Definition at line 482 of file MC68328.h.

#define PCDATA_ADDR   0xfffff411 /* Port C data register */

Definition at line 478 of file MC68328.h.

#define PCDIR   BYTE_REF(PCDIR_ADDR)

Definition at line 481 of file MC68328.h.

#define PCDIR_ADDR   0xfffff410 /* Port C direction reg */

Definition at line 477 of file MC68328.h.

#define PCSEL   BYTE_REF(PCSEL_ADDR)

Definition at line 483 of file MC68328.h.

#define PCSEL_ADDR   0xfffff413 /* Port C Select Register */

Definition at line 479 of file MC68328.h.

#define PCTRL   BYTE_REF(PCTRL_ADDR)

Definition at line 219 of file MC68328.h.

#define PCTRL_ADDR   0xfffff207

Definition at line 218 of file MC68328.h.

#define PCTRL_PCEN   0x80 /* Power Control Enable */

Definition at line 224 of file MC68328.h.

#define PCTRL_STOP   0x40 /* Enter power-save mode immediately */

Definition at line 223 of file MC68328.h.

#define PCTRL_WIDTH_MASK   0x1f /* CPU Clock bursts width */

Definition at line 221 of file MC68328.h.

#define PCTRL_WIDTH_SHIFT   0

Definition at line 222 of file MC68328.h.

#define PD

(

x

)

(1 << (x))

Definition at line 511 of file MC68328.h.

#define PD_KB

(

x

)

PD(x) /* This is specific for Port D only */

Definition at line 512 of file MC68328.h.

#define PD_KB0   PD(0) /* Use KB0 as PD(0) */

Definition at line 514 of file MC68328.h.

#define PD_KB1   PD(1) /* Use KB1 as PD(1) */

Definition at line 515 of file MC68328.h.

#define PD_KB2   PD(2) /* Use KB2 as PD(2) */

Definition at line 516 of file MC68328.h.

#define PD_KB3   PD(3) /* Use KB3 as PD(3) */

Definition at line 517 of file MC68328.h.

#define PD_KB4   PD(4) /* Use KB4 as PD(4) */

Definition at line 518 of file MC68328.h.

#define PD_KB5   PD(5) /* Use KB5 as PD(5) */

Definition at line 519 of file MC68328.h.

#define PD_KB6   PD(6) /* Use KB6 as PD(6) */

Definition at line 520 of file MC68328.h.

#define PD_KB7   PD(7) /* Use KB7 as PD(7) */

Definition at line 521 of file MC68328.h.

#define PDDATA   BYTE_REF(PDDATA_ADDR)

Definition at line 505 of file MC68328.h.

#define PDDATA_ADDR   0xfffff419 /* Port D data register */

Definition at line 498 of file MC68328.h.

#define PDDIR   BYTE_REF(PDDIR_ADDR)

Definition at line 504 of file MC68328.h.

#define PDDIR_ADDR   0xfffff418 /* Port D direction reg */

Definition at line 497 of file MC68328.h.

#define PDIQEG   BYTE_REF(PDIQEG_ADDR)

Definition at line 509 of file MC68328.h.

#define PDIQEG_ADDR   0xfffff41f /* Port D IRQ Edge Register */

Definition at line 502 of file MC68328.h.

#define PDIRQEN   BYTE_REF(PDIRQEN_ADDR)

Definition at line 508 of file MC68328.h.

#define PDIRQEN_ADDR   0xfffff41d /* Port D IRQ enable register */

Definition at line 501 of file MC68328.h.

#define PDPOL   BYTE_REF(PDPOL_ADDR)

Definition at line 507 of file MC68328.h.

#define PDPOL_ADDR   0xfffff41c /* Port D Polarity Register */

Definition at line 500 of file MC68328.h.

#define PDPUEN   BYTE_REF(PDPUEN_ADDR)

Definition at line 506 of file MC68328.h.

#define PDPUEN_ADDR   0xfffff41a /* Port D Pull-Up enable reg */

Definition at line 499 of file MC68328.h.

#define PE

(

x

)

(1 << (x))

Definition at line 536 of file MC68328.h.

#define PE_CSA1   PE(1) /* Use CSA1 as PE(1) */

Definition at line 538 of file MC68328.h.

#define PE_CSA2   PE(2) /* Use CSA2 as PE(2) */

Definition at line 539 of file MC68328.h.

#define PE_CSA3   PE(3) /* Use CSA3 as PE(3) */

Definition at line 540 of file MC68328.h.

#define PE_CSB0   PE(4) /* Use CSB0 as PE(4) */

Definition at line 541 of file MC68328.h.

#define PE_CSB1   PE(5) /* Use CSB1 as PE(5) */

Definition at line 542 of file MC68328.h.

#define PE_CSB2   PE(6) /* Use CSB2 as PE(6) */

Definition at line 543 of file MC68328.h.

#define PE_CSB3   PE(7) /* Use CSB3 as PE(7) */

Definition at line 544 of file MC68328.h.

#define PEDATA   BYTE_REF(PEDATA_ADDR)

Definition at line 532 of file MC68328.h.

#define PEDATA_ADDR   0xfffff421 /* Port E data register */

Definition at line 527 of file MC68328.h.

#define PEDIR   BYTE_REF(PEDIR_ADDR)

Definition at line 531 of file MC68328.h.

#define PEDIR_ADDR   0xfffff420 /* Port E direction reg */

Definition at line 526 of file MC68328.h.

#define PEN_IRQ_NUM   20 /* Pen Interrupt */

Definition at line 284 of file MC68328.h.

#define PEPUEN   BYTE_REF(PEPUEN_ADDR)

Definition at line 533 of file MC68328.h.

#define PEPUEN_ADDR   0xfffff422 /* Port E Pull-Up enable reg */

Definition at line 528 of file MC68328.h.

#define PESEL   BYTE_REF(PESEL_ADDR)

Definition at line 534 of file MC68328.h.

#define PESEL_ADDR   0xfffff423 /* Port E Select Register */

Definition at line 529 of file MC68328.h.

#define PF

(

x

)

(1 << (x))

Definition at line 559 of file MC68328.h.

#define PF_A

(

x

)

PF((x) - 24) /* This is Port F specific only */

Definition at line 560 of file MC68328.h.

#define PF_A24   PF(0) /* Use A24 as PF(0) */

Definition at line 562 of file MC68328.h.

#define PF_A25   PF(1) /* Use A25 as PF(1) */

Definition at line 563 of file MC68328.h.

#define PF_A26   PF(2) /* Use A26 as PF(2) */

Definition at line 564 of file MC68328.h.

#define PF_A27   PF(3) /* Use A27 as PF(3) */

Definition at line 565 of file MC68328.h.

#define PF_A28   PF(4) /* Use A28 as PF(4) */

Definition at line 566 of file MC68328.h.

#define PF_A29   PF(5) /* Use A29 as PF(5) */

Definition at line 567 of file MC68328.h.

#define PF_A30   PF(6) /* Use A30 as PF(6) */

Definition at line 568 of file MC68328.h.

#define PF_A31   PF(7) /* Use A31 as PF(7) */

Definition at line 569 of file MC68328.h.

#define PFDATA   BYTE_REF(PFDATA_ADDR)

Definition at line 555 of file MC68328.h.

#define PFDATA_ADDR   0xfffff429 /* Port F data register */

Definition at line 550 of file MC68328.h.

#define PFDIR   BYTE_REF(PFDIR_ADDR)

Definition at line 554 of file MC68328.h.

#define PFDIR_ADDR   0xfffff428 /* Port F direction reg */

Definition at line 549 of file MC68328.h.

#define PFPUEN   BYTE_REF(PFPUEN_ADDR)

Definition at line 556 of file MC68328.h.

#define PFPUEN_ADDR   0xfffff42a /* Port F Pull-Up enable reg */

Definition at line 551 of file MC68328.h.

#define PFSEL   BYTE_REF(PFSEL_ADDR)

Definition at line 557 of file MC68328.h.

#define PFSEL_ADDR   0xfffff42b /* Port F Select Register */

Definition at line 552 of file MC68328.h.

#define PG

(

x

)

(1 << (x))

Definition at line 584 of file MC68328.h.

#define PG_PWMOUT   PG(2) /* Use PWMOUT as PG(2) */

Definition at line 588 of file MC68328.h.

#define PG_RTCOUT   PG(7) /* Use RTCOUT as PG(7) */

Definition at line 593 of file MC68328.h.

#define PG_TIN1   PG(6) /* Use TIN1 as PG(6) */

Definition at line 592 of file MC68328.h.

#define PG_TIN2   PG(4) /* Use TIN2 as PG(4) */

Definition at line 590 of file MC68328.h.

#define PG_TOUT1   PG(5) /* Use TOUT1 as PG(5) */

Definition at line 591 of file MC68328.h.

#define PG_TOUT2   PG(3) /* Use TOUT2 as PG(3) */

Definition at line 589 of file MC68328.h.

#define PG_UART_RXD   PG(1) /* Use UART_RXD as PG(1) */

Definition at line 587 of file MC68328.h.

#define PG_UART_TXD   PG(0) /* Use UART_TXD as PG(0) */

Definition at line 586 of file MC68328.h.

#define PGDATA   BYTE_REF(PGDATA_ADDR)

Definition at line 580 of file MC68328.h.

#define PGDATA_ADDR   0xfffff431 /* Port G data register */

Definition at line 575 of file MC68328.h.

#define PGDIR   BYTE_REF(PGDIR_ADDR)

Definition at line 579 of file MC68328.h.

#define PGDIR_ADDR   0xfffff430 /* Port G direction reg */

Definition at line 574 of file MC68328.h.

#define PGPUEN   BYTE_REF(PGPUEN_ADDR)

Definition at line 581 of file MC68328.h.

#define PGPUEN_ADDR   0xfffff432 /* Port G Pull-Up enable reg */

Definition at line 576 of file MC68328.h.

#define PGSEL   BYTE_REF(PGSEL_ADDR)

Definition at line 582 of file MC68328.h.

#define PGSEL_ADDR   0xfffff433 /* Port G Select Register */

Definition at line 577 of file MC68328.h.

#define PJ

(

x

)

(1 << (x))

Definition at line 606 of file MC68328.h.

#define PJ_CSD3   PJ(7) /* Use CSD3 as PJ(7) */

Definition at line 608 of file MC68328.h.

#define PJDATA   BYTE_REF(PJDATA_ADDR)

Definition at line 603 of file MC68328.h.

#define PJDATA_ADDR   0xfffff439 /* Port J data register */

Definition at line 599 of file MC68328.h.

#define PJDIR   BYTE_REF(PJDIR_ADDR)

Definition at line 602 of file MC68328.h.

#define PJDIR_ADDR   0xfffff438 /* Port J direction reg */

Definition at line 598 of file MC68328.h.

#define PJSEL   BYTE_REF(PJSEL_ADDR)

Definition at line 604 of file MC68328.h.

#define PJSEL_ADDR   0xfffff43b /* Port J Select Register */

Definition at line 600 of file MC68328.h.

#define PK

(

x

)

(1 << (x))

Definition at line 623 of file MC68328.h.

#define PKDATA   BYTE_REF(PKDATA_ADDR)

Definition at line 619 of file MC68328.h.

#define PKDATA_ADDR   0xfffff441 /* Port K data register */

Definition at line 614 of file MC68328.h.

#define PKDIR   BYTE_REF(PKDIR_ADDR)

Definition at line 618 of file MC68328.h.

#define PKDIR_ADDR   0xfffff440 /* Port K direction reg */

Definition at line 613 of file MC68328.h.

#define PKPUEN   BYTE_REF(PKPUEN_ADDR)

Definition at line 620 of file MC68328.h.

#define PKPUEN_ADDR   0xfffff442 /* Port K Pull-Up enable reg */

Definition at line 615 of file MC68328.h.

#define PKSEL   BYTE_REF(PKSEL_ADDR)

Definition at line 621 of file MC68328.h.

#define PKSEL_ADDR   0xfffff443 /* Port K Select Register */

Definition at line 616 of file MC68328.h.

#define PLLCR   WORD_REF(PLLCR_ADDR)

Definition at line 189 of file MC68328.h.

#define PLLCR_ADDR   0xfffff200

Definition at line 188 of file MC68328.h.

#define PLLCR_CLKEN   0x0010 /* Clock (CLKO pin) enable */

Definition at line 192 of file MC68328.h.

#define PLLCR_DISPLL   0x0008 /* Disable PLL */

Definition at line 191 of file MC68328.h.

#define PLLCR_LCDCLK_SEL_MASK   PLLCR_PIXCLK_SEL_MASK

Definition at line 199 of file MC68328.h.

#define PLLCR_LCDCLK_SEL_SHIFT   PLLCR_PIXCLK_SEL_SHIFT

Definition at line 200 of file MC68328.h.

#define PLLCR_PIXCLK_SEL_MASK   0x3800 /* LCD Clock Selection */

Definition at line 195 of file MC68328.h.

#define PLLCR_PIXCLK_SEL_SHIFT   11

Definition at line 196 of file MC68328.h.

#define PLLCR_SYSCLK_SEL_MASK   0x0700 /* System Clock Selection */

Definition at line 193 of file MC68328.h.

#define PLLCR_SYSCLK_SEL_SHIFT   8

Definition at line 194 of file MC68328.h.

#define PLLFSR   WORD_REF(PLLFSR_ADDR)

Definition at line 206 of file MC68328.h.

#define PLLFSR_ADDR   0xfffff202

Definition at line 205 of file MC68328.h.

#define PLLFSR_CLK32   0x8000 /* Clock 32 (kHz) */

Definition at line 213 of file MC68328.h.

#define PLLFSR_PC_MASK   0x00ff /* P Count */

Definition at line 208 of file MC68328.h.

#define PLLFSR_PC_SHIFT   0

Definition at line 209 of file MC68328.h.

#define PLLFSR_PROT   0x4000 /* Protect P & Q */

Definition at line 212 of file MC68328.h.

#define PLLFSR_QC_MASK   0x0f00 /* Q Count */

Definition at line 210 of file MC68328.h.

#define PLLFSR_QC_SHIFT   8

Definition at line 211 of file MC68328.h.

#define PM

(

x

)

(1 << (x))

Definition at line 638 of file MC68328.h.

#define PMDATA   BYTE_REF(PMDATA_ADDR)

Definition at line 634 of file MC68328.h.

#define PMDATA_ADDR   0xfffff439 /* Port M data register */

Definition at line 629 of file MC68328.h.

#define PMDIR   BYTE_REF(PMDIR_ADDR)

Definition at line 633 of file MC68328.h.

#define PMDIR_ADDR   0xfffff438 /* Port M direction reg */

Definition at line 628 of file MC68328.h.

#define PMNC_POL   0x0020 /* PWM Output Bit Polarity */

Definition at line 655 of file MC68328.h.

#define PMPUEN   BYTE_REF(PMPUEN_ADDR)

Definition at line 635 of file MC68328.h.

#define PMPUEN_ADDR   0xfffff43a /* Port M Pull-Up enable reg */

Definition at line 630 of file MC68328.h.

#define PMSEL   BYTE_REF(PMSEL_ADDR)

Definition at line 636 of file MC68328.h.

#define PMSEL_ADDR   0xfffff43b /* Port M Select Register */

Definition at line 631 of file MC68328.h.

#define PUT_FIELD	(		field,
			val
	)		(((val) << field##_SHIFT) & field##_MASK)

Definition at line 19 of file MC68328.h.

#define PWM_IRQ_NUM   7 /* Pulse-Width Modulator int. */

Definition at line 271 of file MC68328.h.

#define PWMC   WORD_REF(PWMC_ADDR)

Definition at line 650 of file MC68328.h.

#define PWMC_ADDR   0xfffff500

Definition at line 649 of file MC68328.h.

#define PWMC_CLKSEL_MASK   0x0007 /* Clock Selection */

Definition at line 652 of file MC68328.h.

#define PWMC_CLKSEL_SHIFT   0

Definition at line 653 of file MC68328.h.

#define PWMC_CLKSRC   0x8000 /* Clock Source Select */

Definition at line 659 of file MC68328.h.

#define PWMC_EN   PWMC_PWMEN

Definition at line 662 of file MC68328.h.

#define PWMC_IRQEN   0x4000 /* Interrupt Request Enable */

Definition at line 658 of file MC68328.h.

#define PWMC_LOAD   0x0100 /* Force a new period */

Definition at line 657 of file MC68328.h.

#define PWMC_PIN   0x0080 /* Current PWM output pin status */

Definition at line 656 of file MC68328.h.

#define PWMC_PWMEN   0x0010 /* Enable PWM */

Definition at line 654 of file MC68328.h.

#define PWMCNT   WORD_REF(PWMCNT_ADDR)

Definition at line 680 of file MC68328.h.

#define PWMCNT_ADDR   0xfffff506

Definition at line 679 of file MC68328.h.

#define PWMP   WORD_REF(PWMP_ADDR)

Definition at line 668 of file MC68328.h.

#define PWMP_ADDR   0xfffff502

Definition at line 667 of file MC68328.h.

#define PWMW   WORD_REF(PWMW_ADDR)

Definition at line 674 of file MC68328.h.

#define PWMW_ADDR   0xfffff504

Definition at line 673 of file MC68328.h.

#define RTC_IRQ_NUM   4 /* RTC interrupt */

Definition at line 269 of file MC68328.h.

#define RTCALRM   LONG_REF(RTCALRM_ADDR)

Definition at line 1211 of file MC68328.h.

#define RTCALRM_ADDR   0xfffffb04

Definition at line 1210 of file MC68328.h.

#define RTCALRM_HOURS_MASK   0x1f000000 /* Hours */

Definition at line 1217 of file MC68328.h.

#define RTCALRM_HOURS_SHIFT   24

Definition at line 1218 of file MC68328.h.

#define RTCALRM_MINUTES_MASK   0x003f0000 /* Minutes */

Definition at line 1215 of file MC68328.h.

#define RTCALRM_MINUTES_SHIFT   16

Definition at line 1216 of file MC68328.h.

#define RTCALRM_SECONDS_MASK   0x0000003f /* Seconds */

Definition at line 1213 of file MC68328.h.

#define RTCALRM_SECONDS_SHIFT   0

Definition at line 1214 of file MC68328.h.

#define RTCCTL   WORD_REF(RTCCTL_ADDR)

Definition at line 1224 of file MC68328.h.

#define RTCCTL_384   0x0020 /* Crystal Selection */

Definition at line 1226 of file MC68328.h.

#define RTCCTL_ADDR   0xfffffb0c

Definition at line 1223 of file MC68328.h.

#define RTCCTL_EN   RTCCTL_ENABLE

Definition at line 1231 of file MC68328.h.

#define RTCCTL_ENABLE   0x0080 /* RTC Enable */

Definition at line 1227 of file MC68328.h.

#define RTCCTL_XTL   RTCCTL_384

Definition at line 1230 of file MC68328.h.

#define RTCIENR   WORD_REF(RTCIENR_ADDR)

Definition at line 1249 of file MC68328.h.

#define RTCIENR_1HZ   0x0010 /* 1Hz interrupt enable */

Definition at line 1255 of file MC68328.h.

#define RTCIENR_ADDR   0xfffffb10

Definition at line 1248 of file MC68328.h.

#define RTCIENR_ALM   0x0004 /* Alarm interrupt enable */

Definition at line 1253 of file MC68328.h.

#define RTCIENR_DAY   0x0008 /* 24-hour rollover interrupt enable */

Definition at line 1254 of file MC68328.h.

#define RTCIENR_MIN   0x0002 /* 1-minute interrupt enable */

Definition at line 1252 of file MC68328.h.

#define RTCIENR_SW   0x0001 /* Stopwatch interrupt enable */

Definition at line 1251 of file MC68328.h.

#define RTCISR   WORD_REF(RTCISR_ADDR)

Definition at line 1237 of file MC68328.h.

#define RTCISR_1HZ   0x0010 /* 1Hz interrupt has occurred */

Definition at line 1243 of file MC68328.h.

#define RTCISR_ADDR   0xfffffb0e

Definition at line 1236 of file MC68328.h.

#define RTCISR_ALM   0x0004 /* Alarm interrupt has occurred */

Definition at line 1241 of file MC68328.h.

#define RTCISR_DAY   0x0008 /* 24-hour rollover interrupt has occurred */

Definition at line 1242 of file MC68328.h.

#define RTCISR_MIN   0x0002 /* 1-minute interrupt has occurred */

Definition at line 1240 of file MC68328.h.

#define RTCISR_SW   0x0001 /* Stopwatch timed out */

Definition at line 1239 of file MC68328.h.

#define RTCTIME   LONG_REF(RTCTIME_ADDR)

Definition at line 1198 of file MC68328.h.

#define RTCTIME_ADDR   0xfffffb00

Definition at line 1197 of file MC68328.h.

#define RTCTIME_HOURS_MASK   0x1f000000 /* Hours */

Definition at line 1204 of file MC68328.h.

#define RTCTIME_HOURS_SHIFT   24

Definition at line 1205 of file MC68328.h.

#define RTCTIME_MINUTES_MASK   0x003f0000 /* Minutes */

Definition at line 1202 of file MC68328.h.

#define RTCTIME_MINUTES_SHIFT   16

Definition at line 1203 of file MC68328.h.

#define RTCTIME_SECONDS_MASK   0x0000003f /* Seconds */

Definition at line 1200 of file MC68328.h.

#define RTCTIME_SECONDS_SHIFT   0

Definition at line 1201 of file MC68328.h.

#define SCR   BYTE_REF(SCR_ADDR)

Definition at line 32 of file MC68328.h.

#define SCR_ADDR   0xfffff000

Definition at line 31 of file MC68328.h.

#define SCR_BETEN   0x10 /* Bus-Error Time-Out Enable */

Definition at line 37 of file MC68328.h.

#define SCR_BETO   0x80 /* Bus-Error TimeOut */

Definition at line 40 of file MC68328.h.

#define SCR_DMAP   0x04 /* Double Map */

Definition at line 35 of file MC68328.h.

#define SCR_PRV   0x20 /* Privilege Violation */

Definition at line 38 of file MC68328.h.

#define SCR_SO   0x08 /* Supervisor Only */

Definition at line 36 of file MC68328.h.

#define SCR_WDTH8   0x01 /* 8-Bit Width Select */

Definition at line 34 of file MC68328.h.

#define SCR_WPV   0x40 /* Write Protect Violation */

Definition at line 39 of file MC68328.h.

#define SPI_IRQ_NUM   SPIM_IRQ_NUM

Definition at line 290 of file MC68328.h.

#define SPIM_IRQ_NUM   0 /* SPI Master interrupt */

Definition at line 265 of file MC68328.h.

#define SPIMCONT   WORD_REF(SPIMCONT_ADDR)

Definition at line 841 of file MC68328.h.

#define SPIMCONT_ADDR   0xfffff802

Definition at line 840 of file MC68328.h.

#define SPIMCONT_BIT_COUNT_MASK   0x000f /* Transfer Length in Bytes */

Definition at line 843 of file MC68328.h.

#define SPIMCONT_BIT_COUNT_SHIFT   0

Definition at line 844 of file MC68328.h.

#define SPIMCONT_DATA_RATE_MASK   0xe000 /* SPIM Data Rate */

Definition at line 851 of file MC68328.h.

#define SPIMCONT_DATA_RATE_SHIFT   13

Definition at line 852 of file MC68328.h.

#define SPIMCONT_ENABLE   SPIMCONT_SPIMEN

Definition at line 856 of file MC68328.h.

#define SPIMCONT_IRQ   SPIMCONT_SPIMIRQ

Definition at line 855 of file MC68328.h.

#define SPIMCONT_IRQEN   0x0040 /* IRQ Enable */

Definition at line 847 of file MC68328.h.

#define SPIMCONT_PHA   0x0020 /* Clock/Data phase relationship */

Definition at line 846 of file MC68328.h.

#define SPIMCONT_POL   0x0010 /* SPMCLK Signel Polarity */

Definition at line 845 of file MC68328.h.

#define SPIMCONT_RSPIMEN   0x0200 /* Enable SPIM */

Definition at line 850 of file MC68328.h.

#define SPIMCONT_SPIMIRQ   0x0080 /* Interrupt Request */

Definition at line 848 of file MC68328.h.

#define SPIMCONT_XCH   0x0100 /* Exchange */

Definition at line 849 of file MC68328.h.

#define SPIMDATA   WORD_REF(SPIMDATA_ADDR)

Definition at line 835 of file MC68328.h.

#define SPIMDATA_ADDR   0xfffff800

Definition at line 834 of file MC68328.h.

#define SPIS_IRQ_NUM   21 /* SPI Slave Interrupt */

Definition at line 285 of file MC68328.h.

#define SPISR   WORD_REF(SPISR_ADDR)

Definition at line 809 of file MC68328.h.

#define SPISR_ADDR   0xfffff700

Definition at line 808 of file MC68328.h.

#define SPISR_DATA   BYTE_REF(SPISR_DATA_ADDR)

Definition at line 812 of file MC68328.h.

#define SPISR_DATA_ADDR   0xfffff701

Definition at line 811 of file MC68328.h.

#define SPISR_DATA_MASK   0x00ff /* Shifted data from the external device */

Definition at line 814 of file MC68328.h.

#define SPISR_DATA_SHIFT   0

Definition at line 815 of file MC68328.h.

#define SPISR_DATARDY   0x1000 /* Data ready */

Definition at line 820 of file MC68328.h.

#define SPISR_ENPOL   0x2000 /* Enable Polarity */

Definition at line 821 of file MC68328.h.

#define SPISR_IRQEN   0x4000 /* SPIS IRQ Enable */

Definition at line 822 of file MC68328.h.

#define SPISR_OVWR   0x0800 /* Data buffer has been overwritten */

Definition at line 819 of file MC68328.h.

#define SPISR_PHA   0x0400 /* Phase relationship between SPSCLK & SPSRxD */

Definition at line 818 of file MC68328.h.

#define SPISR_POL   0x0200 /* SPSCLK polarity control */

Definition at line 817 of file MC68328.h.

#define SPISR_SPISEN   0x0100 /* SPIS module enable */

Definition at line 816 of file MC68328.h.

#define SPISR_SPISIRQ   0x8000 /* SPIS IRQ posted */

Definition at line 823 of file MC68328.h.

#define SPTWCH_CNT_SHIFT   0

Definition at line 1264 of file MC68328.h.

#define STPWCH   WORD_REF(STPWCH)

Definition at line 1261 of file MC68328.h.

#define STPWCH_ADDR   0xfffffb12

Definition at line 1260 of file MC68328.h.

#define STPWCH_CNT_MASK   0x00ff /* Stopwatch countdown value */

Definition at line 1263 of file MC68328.h.

#define TCMP   TCMP1

Definition at line 736 of file MC68328.h.

#define TCMP1   WORD_REF(TCMP1_ADDR)

Definition at line 730 of file MC68328.h.

#define TCMP1_ADDR   0xfffff604

Definition at line 729 of file MC68328.h.

#define TCMP2   WORD_REF(TCMP2_ADDR)

Definition at line 732 of file MC68328.h.

#define TCMP2_ADDR   0xfffff610

Definition at line 731 of file MC68328.h.

#define TCMP_ADDR   TCMP1_ADDR

Definition at line 735 of file MC68328.h.

#define TCN   TCN

Definition at line 760 of file MC68328.h.

#define TCN1   WORD_REF(TCN1_ADDR)

Definition at line 754 of file MC68328.h.

#define TCN1_ADDR   0xfffff608

Definition at line 753 of file MC68328.h.

#define TCN2   WORD_REF(TCN2_ADDR)

Definition at line 756 of file MC68328.h.

#define TCN2_ADDR   0xfffff614

Definition at line 755 of file MC68328.h.

#define TCN_ADDR   TCN1_ADDR

Definition at line 759 of file MC68328.h.

#define TCR   TCR1

Definition at line 748 of file MC68328.h.

#define TCR1   WORD_REF(TCR1_ADDR)

Definition at line 742 of file MC68328.h.

#define TCR1_ADDR   0xfffff606

Definition at line 741 of file MC68328.h.

#define TCR2   WORD_REF(TCR2_ADDR)

Definition at line 744 of file MC68328.h.

#define TCR2_ADDR   0xfffff612

Definition at line 743 of file MC68328.h.

#define TCR_ADDR   TCR1_ADDR

Definition at line 747 of file MC68328.h.

#define TCTL   TCTL1

Definition at line 712 of file MC68328.h.

#define TCTL1   WORD_REF(TCTL1_ADDR)

Definition at line 692 of file MC68328.h.

#define TCTL1_ADDR   0xfffff600

Definition at line 691 of file MC68328.h.

#define TCTL2   WORD_REF(TCTL2_ADDR)

Definition at line 694 of file MC68328.h.

#define TCTL2_ADDR   0xfffff60c

Definition at line 693 of file MC68328.h.

#define TCTL_ADDR   TCTL1_ADDR

Definition at line 711 of file MC68328.h.

#define TCTL_CAP_FE   0x0080 /* Capture on falling edge */

Definition at line 707 of file MC68328.h.

#define TCTL_CAP_MASK   0x00c0 /* Capture Edge: */

Definition at line 705 of file MC68328.h.

#define TCTL_CAP_RE   0x0040 /* Capture on rizing edge */

Definition at line 706 of file MC68328.h.

#define TCTL_CLKSOURCE_32KHZ   0x0008 /* 32kHz clock to prescaler */

Definition at line 702 of file MC68328.h.

#define TCTL_CLKSOURCE_MASK   0x000e /* Clock Source: */

Definition at line 697 of file MC68328.h.

#define TCTL_CLKSOURCE_STOP   0x0000 /* Stop count (disabled) */

Definition at line 698 of file MC68328.h.

#define TCTL_CLKSOURCE_SYSCLK   0x0002 /* SYSCLK to prescaler */

Definition at line 699 of file MC68328.h.

#define TCTL_CLKSOURCE_SYSCLK_16   0x0004 /* SYSCLK/16 to prescaler */

Definition at line 700 of file MC68328.h.

#define TCTL_CLKSOURCE_TIN   0x0006 /* TIN to prescaler */

Definition at line 701 of file MC68328.h.

#define TCTL_FRR   0x0010 /* Free-Run Mode */

Definition at line 708 of file MC68328.h.

#define TCTL_IRQEN   0x0010 /* IRQ Enable */

Definition at line 703 of file MC68328.h.

#define TCTL_OM   0x0020 /* Output Mode */

Definition at line 704 of file MC68328.h.

#define TCTL_TEN   0x0001 /* Timer Enable */

Definition at line 696 of file MC68328.h.

#define TMR1_IRQ_NUM   22 /* Timer 1 interrupt */

Definition at line 286 of file MC68328.h.

#define TMR2_IRQ_NUM   1 /* Timer 2 interrupt */

Definition at line 266 of file MC68328.h.

#define TMR_IRQ_NUM   TMR1_IRQ_NUM

Definition at line 291 of file MC68328.h.

#define TPRER   TPRER1

Definition at line 724 of file MC68328.h.

#define TPRER1   WORD_REF(TPRER1_ADDR)

Definition at line 718 of file MC68328.h.

#define TPRER1_ADDR   0xfffff602

Definition at line 717 of file MC68328.h.

#define TPRER2   WORD_REF(TPRER2_ADDR)

Definition at line 720 of file MC68328.h.

#define TPRER2_ADDR   0xfffff60e

Definition at line 719 of file MC68328.h.

#define TPRER_ADDR   TPRER1_ADDR

Definition at line 723 of file MC68328.h.

#define TSTAT   TSTAT1

Definition at line 775 of file MC68328.h.

#define TSTAT1   WORD_REF(TSTAT1_ADDR)

Definition at line 766 of file MC68328.h.

#define TSTAT1_ADDR   0xfffff60a

Definition at line 765 of file MC68328.h.

#define TSTAT2   WORD_REF(TSTAT2_ADDR)

Definition at line 768 of file MC68328.h.

#define TSTAT2_ADDR   0xfffff616

Definition at line 767 of file MC68328.h.

#define TSTAT_ADDR   TSTAT1_ADDR

Definition at line 774 of file MC68328.h.

#define TSTAT_CAPT   0x0001 /* Capture Event occurred */

Definition at line 771 of file MC68328.h.

#define TSTAT_COMP   0x0001 /* Compare Event occurred */

Definition at line 770 of file MC68328.h.

#define UART_IRQ_NUM   2 /* UART interrupt */

Definition at line 267 of file MC68328.h.

#define UBAUD   WORD_REF(UBAUD_ADDR)

Definition at line 903 of file MC68328.h.

#define UBAUD_ADDR   0xfffff902

Definition at line 902 of file MC68328.h.

#define UBAUD_BAUD_SRC   0x0800 /* Baud Rate Source */

Definition at line 909 of file MC68328.h.

#define UBAUD_DIVIDE_MASK   0x0700 /* Baud Rate freq. divizor */

Definition at line 907 of file MC68328.h.

#define UBAUD_DIVIDE_SHIFT   8

Definition at line 908 of file MC68328.h.

#define UBAUD_GPIO   0x4000 /* Current GPIO pin status */

Definition at line 912 of file MC68328.h.

#define UBAUD_GPIODELTA   0x8000 /* GPIO pin value changed */

Definition at line 913 of file MC68328.h.

#define UBAUD_GPIODIR   0x2000 /* GPIO Direction */

Definition at line 911 of file MC68328.h.

#define UBAUD_GPIOSRC   0x1000 /* GPIO source */

Definition at line 910 of file MC68328.h.

#define UBAUD_PRESCALER_MASK   0x003f /* Actual divisor is 65 - PRESCALER */

Definition at line 905 of file MC68328.h.

#define UBAUD_PRESCALER_SHIFT   0

Definition at line 906 of file MC68328.h.

#define UMISC   WORD_REF(UMISC_ADDR)

Definition at line 961 of file MC68328.h.

#define UMISC_ADDR   0xfffff908

Definition at line 960 of file MC68328.h.

#define UMISC_CLKSRC   0x4000 /* Clock Source */

Definition at line 971 of file MC68328.h.

#define UMISC_FORCE_PERR   0x2000 /* Force Parity Error */

Definition at line 970 of file MC68328.h.

#define UMISC_IRDA_EN   0x0020 /* Infra-Red Enable */

Definition at line 966 of file MC68328.h.

#define UMISC_IRDA_LOOP   0x0010 /* IrDA Loopback Enable */

Definition at line 965 of file MC68328.h.

#define UMISC_LOOP   0x1000 /* Serial Loopback Enable */

Definition at line 969 of file MC68328.h.

#define UMISC_RTS   0x0040 /* Set RTS status */

Definition at line 967 of file MC68328.h.

#define UMISC_RTSCONT   0x0080 /* Choose RTS control */

Definition at line 968 of file MC68328.h.

#define UMISC_RX_POL   0x0008 /* Receive Polarity */

Definition at line 964 of file MC68328.h.

#define UMISC_TX_POL   0x0004 /* Transmit Polarity */

Definition at line 963 of file MC68328.h.

#define URX   WORD_REF(URX_ADDR)

Definition at line 919 of file MC68328.h.

#define URX_ADDR   0xfffff904

Definition at line 918 of file MC68328.h.

#define URX_BREAK   0x0200 /* Break Detected */

Definition at line 927 of file MC68328.h.

#define URX_DATA_READY   0x2000 /* Data Ready (FIFO not empty) */

Definition at line 930 of file MC68328.h.

#define URX_FIFO_FULL   0x8000 /* FIFO is Full */

Definition at line 932 of file MC68328.h.

#define URX_FIFO_HALF   0x4000 /* FIFO is Half-Full */

Definition at line 931 of file MC68328.h.

#define URX_FRAME_ERROR   0x0400 /* Framing Error */

Definition at line 928 of file MC68328.h.

#define URX_OVRUN   0x0800 /* Serial Overrun */

Definition at line 929 of file MC68328.h.

#define URX_PARITY_ERROR   0x0100 /* Parity Error */

Definition at line 926 of file MC68328.h.

#define URX_RXDATA   BYTE_REF(URX_RXDATA_ADDR)

Definition at line 922 of file MC68328.h.

#define URX_RXDATA_ADDR   0xfffff905

Definition at line 921 of file MC68328.h.

#define URX_RXDATA_MASK   0x00ff /* Received data */

Definition at line 924 of file MC68328.h.

#define URX_RXDATA_SHIFT   0

Definition at line 925 of file MC68328.h.

#define USTCNT   WORD_REF(USTCNT_ADDR)

Definition at line 867 of file MC68328.h.

#define USTCNT_8_7   0x0100 /* Eight or seven-bit transmission */

Definition at line 877 of file MC68328.h.

#define USTCNT_ADDR   0xfffff900

Definition at line 866 of file MC68328.h.

#define USTCNT_CLKM   USTCNT_CLKMODE

Definition at line 896 of file MC68328.h.

#define USTCNT_CLKMODE   0x1000 /* Clock Mode Select */

Definition at line 881 of file MC68328.h.

#define USTCNT_CTSD   USTCNT_CTSDELTAEN

Definition at line 893 of file MC68328.h.

#define USTCNT_CTSDELTAEN   0x0040 /* CTS Delta Interrupt Enable */

Definition at line 875 of file MC68328.h.

#define USTCNT_GPIODELTAEN   0x0080 /* Old Data Interrupt Enable */

Definition at line 876 of file MC68328.h.

#define USTCNT_ODD   USTCNT_ODD_EVEN

Definition at line 894 of file MC68328.h.

#define USTCNT_ODD_EVEN   0x0400 /* Odd Parity */

Definition at line 879 of file MC68328.h.

#define USTCNT_PARITYEN   0x0800 /* Parity Enable */

Definition at line 880 of file MC68328.h.

#define USTCNT_PEN   USTCNT_PARITYEN

Definition at line 895 of file MC68328.h.

#define USTCNT_RXEN   0x4000 /* Receiver Enable */

Definition at line 883 of file MC68328.h.

#define USTCNT_RXFE   USTCNT_RXFULLEN

Definition at line 892 of file MC68328.h.

#define USTCNT_RXFULLEN   0x0020 /* Receiver Full Interrupt Enable */

Definition at line 874 of file MC68328.h.

#define USTCNT_RXHALFEN   0x0010 /* Receiver Half-Full Int Enable */

Definition at line 873 of file MC68328.h.

#define USTCNT_RXHE   USTCNT_RXHALFEN

Definition at line 891 of file MC68328.h.

#define USTCNT_RXRE   USTCNT_RXREADYEN

Definition at line 890 of file MC68328.h.

#define USTCNT_RXREADYEN   0x0008 /* Receiver Ready Interrupt Enable */

Definition at line 872 of file MC68328.h.

#define USTCNT_STOP   0x0200 /* Stop bit transmission */

Definition at line 878 of file MC68328.h.

#define USTCNT_TXAE   USTCNT_TXAVAILEN

Definition at line 887 of file MC68328.h.

#define USTCNT_TXAVAILEN   0x0001 /* Transmitter Available Int Enable */

Definition at line 869 of file MC68328.h.

#define USTCNT_TXEE   USTCNT_TXEMPTYEN

Definition at line 889 of file MC68328.h.

#define USTCNT_TXEMPTYEN   0x0004 /* Transmitter Empty Int Enable */

Definition at line 871 of file MC68328.h.

#define USTCNT_TXEN   0x2000 /* Transmitter Enable */

Definition at line 882 of file MC68328.h.

#define USTCNT_TXHALFEN   0x0002 /* Transmitter Half Empty Int Enable */

Definition at line 870 of file MC68328.h.

#define USTCNT_TXHE   USTCNT_TXHALFEN

Definition at line 888 of file MC68328.h.

#define USTCNT_UARTEN   0x8000 /* UART Enable */

Definition at line 884 of file MC68328.h.

#define USTCNT_UEN   USTCNT_UARTEN

Definition at line 897 of file MC68328.h.

#define UTX   WORD_REF(UTX_ADDR)

Definition at line 938 of file MC68328.h.

#define UTX_ADDR   0xfffff906

Definition at line 937 of file MC68328.h.

#define UTX_CTS_DELTA   0x0100 /* CTS changed */

Definition at line 945 of file MC68328.h.

#define UTX_CTS_STAT   UTX_CTS_STATUS

Definition at line 954 of file MC68328.h.

#define UTX_CTS_STATUS   0x0200 /* CTS State */

Definition at line 946 of file MC68328.h.

#define UTX_FIFO_EMPTY   0x8000 /* Transmit FIFO is empty */

Definition at line 951 of file MC68328.h.

#define UTX_FIFO_HALF   0x4000 /* Transmit FIFO is half empty */

Definition at line 950 of file MC68328.h.

#define UTX_IGNORE_CTS   0x0800 /* Ignore CTS */

Definition at line 947 of file MC68328.h.

#define UTX_NOCTS   UTX_IGNORE_CTS

Definition at line 955 of file MC68328.h.

#define UTX_SEND_BREAK   0x1000 /* Send a BREAK */

Definition at line 948 of file MC68328.h.

#define UTX_TX_AVAIL   0x2000 /* Transmit FIFO has a slot available */

Definition at line 949 of file MC68328.h.

#define UTX_TXDATA   BYTE_REF(UTX_TXDATA_ADDR)

Definition at line 941 of file MC68328.h.

#define UTX_TXDATA_ADDR   0xfffff907

Definition at line 940 of file MC68328.h.

#define UTX_TXDATA_MASK   0x00ff /* Data to be transmitted */

Definition at line 943 of file MC68328.h.

#define UTX_TXDATA_SHIFT   0

Definition at line 944 of file MC68328.h.

#define WCN   WORD_REF(WCN_ADDR)

Definition at line 787 of file MC68328.h.

#define WCN_ADDR   0xfffff61c

Definition at line 786 of file MC68328.h.

#define WCSR   WORD_REF(WCSR_ADDR)

Definition at line 793 of file MC68328.h.

#define WCSR_ADDR   0xfffff618

Definition at line 792 of file MC68328.h.

#define WCSR_FI   0x0002 /* Forced Interrupt (instead of SW reset)*/

Definition at line 796 of file MC68328.h.

#define WCSR_WDEN   0x0001 /* Watchdog Enable */

Definition at line 795 of file MC68328.h.

#define WCSR_WRST   0x0004 /* Watchdog Reset */

Definition at line 797 of file MC68328.h.

#define WDT_IRQ_NUM   3 /* Watchdog Timer interrupt */

Definition at line 268 of file MC68328.h.

#define WORD_REF

(

addr

)

(*((volatile unsigned short*)addr))

Definition at line 16 of file MC68328.h.

#define WRR   WORD_REF(WRR_ADDR)

Definition at line 781 of file MC68328.h.

#define WRR_ADDR   0xfffff61a

Definition at line 780 of file MC68328.h.