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pci.c
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1 /*
2  * linux/arch/mips/txx9/pci.c
3  *
4  * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
5  * linux/arch/mips/txx9/rbtx4938/setup.c,
6  * and RBTX49xx patch from CELF patch archive.
7  *
8  * Copyright 2001-2005 MontaVista Software Inc.
9  * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle ([email protected])
10  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
11  *
12  * This file is subject to the terms and conditions of the GNU General Public
13  * License. See the file "COPYING" in the main directory of this archive
14  * for more details.
15  */
16 #include <linux/delay.h>
17 #include <linux/jiffies.h>
18 #include <linux/io.h>
19 #include <asm/txx9/generic.h>
20 #include <asm/txx9/pci.h>
21 #ifdef CONFIG_TOSHIBA_FPCIB0
22 #include <linux/interrupt.h>
23 #include <linux/slab.h>
24 #include <asm/i8259.h>
25 #include <asm/txx9/smsc_fdc37m81x.h>
26 #endif
27 
28 static int __init
29 early_read_config_word(struct pci_controller *hose,
30  int top_bus, int bus, int devfn, int offset, u16 *value)
31 {
32  struct pci_dev fake_dev;
33  struct pci_bus fake_bus;
34 
35  fake_dev.bus = &fake_bus;
36  fake_dev.sysdata = hose;
37  fake_dev.devfn = devfn;
38  fake_bus.number = bus;
39  fake_bus.sysdata = hose;
40  fake_bus.ops = hose->pci_ops;
41 
42  if (bus != top_bus)
43  /* Fake a parent bus structure. */
44  fake_bus.parent = &fake_bus;
45  else
46  fake_bus.parent = NULL;
47 
48  return pci_read_config_word(&fake_dev, offset, value);
49 }
50 
51 int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
52  int current_bus)
53 {
54  u32 pci_devfn;
55  unsigned short vid;
56  int cap66 = -1;
57  u16 stat;
58 
59  /* It seems SLC90E66 needs some time after PCI reset... */
60  mdelay(80);
61 
62  printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
63 
64  for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
65  if (PCI_FUNC(pci_devfn))
66  continue;
67  if (early_read_config_word(hose, top_bus, current_bus,
68  pci_devfn, PCI_VENDOR_ID, &vid) !=
69  PCIBIOS_SUCCESSFUL)
70  continue;
71  if (vid == 0xffff)
72  continue;
73 
74  /* check 66MHz capability */
75  if (cap66 < 0)
76  cap66 = 1;
77  if (cap66) {
78  early_read_config_word(hose, top_bus, current_bus,
79  pci_devfn, PCI_STATUS, &stat);
80  if (!(stat & PCI_STATUS_66MHZ)) {
81  printk(KERN_DEBUG
82  "PCI: %02x:%02x not 66MHz capable.\n",
83  current_bus, pci_devfn);
84  cap66 = 0;
85  break;
86  }
87  }
88  }
89  return cap66 > 0;
90 }
91 
92 static struct resource primary_pci_mem_res[2] = {
93  { .name = "PCI MEM" },
94  { .name = "PCI MMIO" },
95 };
96 static struct resource primary_pci_io_res = { .name = "PCI IO" };
97 struct pci_controller txx9_primary_pcic = {
98  .mem_resource = &primary_pci_mem_res[0],
99  .io_resource = &primary_pci_io_res,
100 };
101 
102 #ifdef CONFIG_64BIT
103 int txx9_pci_mem_high __initdata = 1;
104 #else
105 int txx9_pci_mem_high __initdata;
106 #endif
107 
108 /*
109  * allocate pci_controller and resources.
110  * mem_base, io_base: physical address. 0 for auto assignment.
111  * mem_size and io_size means max size on auto assignment.
112  * pcic must be &txx9_primary_pcic or NULL.
113  */
114 struct pci_controller *__init
115 txx9_alloc_pci_controller(struct pci_controller *pcic,
116  unsigned long mem_base, unsigned long mem_size,
117  unsigned long io_base, unsigned long io_size)
118 {
119  struct pcic {
120  struct pci_controller c;
121  struct resource r_mem[2];
122  struct resource r_io;
123  } *new = NULL;
124  int min_size = 0x10000;
125 
126  if (!pcic) {
127  new = kzalloc(sizeof(*new), GFP_KERNEL);
128  if (!new)
129  return NULL;
130  new->r_mem[0].name = "PCI mem";
131  new->r_mem[1].name = "PCI mmio";
132  new->r_io.name = "PCI io";
133  new->c.mem_resource = new->r_mem;
134  new->c.io_resource = &new->r_io;
135  pcic = &new->c;
136  } else
137  BUG_ON(pcic != &txx9_primary_pcic);
138  pcic->io_resource->flags = IORESOURCE_IO;
139 
140  /*
141  * for auto assignment, first search a (big) region for PCI
142  * MEM, then search a region for PCI IO.
143  */
144  if (mem_base) {
145  pcic->mem_resource[0].start = mem_base;
146  pcic->mem_resource[0].end = mem_base + mem_size - 1;
147  if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
148  goto free_and_exit;
149  } else {
150  unsigned long min = 0, max = 0x20000000; /* low 512MB */
151  if (!mem_size) {
152  /* default size for auto assignment */
153  if (txx9_pci_mem_high)
154  mem_size = 0x20000000; /* mem:512M(max) */
155  else
156  mem_size = 0x08000000; /* mem:128M(max) */
157  }
158  if (txx9_pci_mem_high) {
159  min = 0x20000000;
160  max = 0xe0000000;
161  }
162  /* search free region for PCI MEM */
163  for (; mem_size >= min_size; mem_size /= 2) {
164  if (allocate_resource(&iomem_resource,
165  &pcic->mem_resource[0],
166  mem_size, min, max,
167  mem_size, NULL, NULL) == 0)
168  break;
169  }
170  if (mem_size < min_size)
171  goto free_and_exit;
172  }
173 
174  pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
175  if (io_base) {
176  pcic->mem_resource[1].start = io_base;
177  pcic->mem_resource[1].end = io_base + io_size - 1;
178  if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
179  goto release_and_exit;
180  } else {
181  if (!io_size)
182  /* default size for auto assignment */
183  io_size = 0x01000000; /* io:16M(max) */
184  /* search free region for PCI IO in low 512MB */
185  for (; io_size >= min_size; io_size /= 2) {
186  if (allocate_resource(&iomem_resource,
187  &pcic->mem_resource[1],
188  io_size, 0, 0x20000000,
189  io_size, NULL, NULL) == 0)
190  break;
191  }
192  if (io_size < min_size)
193  goto release_and_exit;
194  io_base = pcic->mem_resource[1].start;
195  }
196 
197  pcic->mem_resource[0].flags = IORESOURCE_MEM;
198  if (pcic == &txx9_primary_pcic &&
199  mips_io_port_base == (unsigned long)-1) {
200  /* map ioport 0 to PCI I/O space address 0 */
201  set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
202  pcic->io_resource->start = 0;
203  pcic->io_offset = 0; /* busaddr == ioaddr */
204  pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
205  } else {
206  /* physaddr to ioaddr */
207  pcic->io_resource->start =
208  io_base - (mips_io_port_base - IO_BASE);
209  pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
210  pcic->io_map_base = mips_io_port_base;
211  }
212  pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
213 
214  pcic->mem_offset = 0; /* busaddr == physaddr */
215 
216  printk(KERN_INFO "PCI: IO %pR MEM %pR\n",
217  &pcic->mem_resource[1], &pcic->mem_resource[0]);
218 
219  /* register_pci_controller() will request MEM resource */
220  release_resource(&pcic->mem_resource[0]);
221  return pcic;
222  release_and_exit:
223  release_resource(&pcic->mem_resource[0]);
224  free_and_exit:
225  kfree(new);
226  printk(KERN_ERR "PCI: Failed to allocate resources.\n");
227  return NULL;
228 }
229 
230 static int __init
231 txx9_arch_pci_init(void)
232 {
233  PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */
234  return 0;
235 }
236 arch_initcall(txx9_arch_pci_init);
237 
238 /* IRQ/IDSEL mapping */
239 int txx9_pci_option =
240 #ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
241  TXX9_PCI_OPT_PICMG |
242 #endif
243  TXX9_PCI_OPT_CLK_AUTO;
244 
245 enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
246 
247 #ifdef CONFIG_TOSHIBA_FPCIB0
248 static irqreturn_t i8259_interrupt(int irq, void *dev_id)
249 {
250  int isairq;
251 
252  isairq = i8259_irq();
253  if (unlikely(isairq <= I8259A_IRQ_BASE))
254  return IRQ_NONE;
255  generic_handle_irq(isairq);
256  return IRQ_HANDLED;
257 }
258 
259 static int __devinit
260 txx9_i8259_irq_setup(int irq)
261 {
262  int err;
263 
264  init_i8259_irqs();
265  err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
266  "cascade(i8259)", (void *)(long)irq);
267  if (!err)
268  printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
269  return err;
270 }
271 
272 static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev)
273 {
274  int irq; /* PCI/ISA Bridge interrupt */
275  u8 reg_64;
276  u32 reg_b0;
277  u8 reg_e1;
278  irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
279  if (!irq)
280  return;
281  txx9_i8259_irq_setup(irq);
282  pci_read_config_byte(dev, 0x64, &reg_64);
283  pci_read_config_dword(dev, 0xb0, &reg_b0);
284  pci_read_config_byte(dev, 0xe1, &reg_e1);
285  /* serial irq control */
286  reg_64 = 0xd0;
287  /* serial irq pin */
288  reg_b0 |= 0x00010000;
289  /* ide irq on isa14 */
290  reg_e1 &= 0xf0;
291  reg_e1 |= 0x0d;
292  pci_write_config_byte(dev, 0x64, reg_64);
293  pci_write_config_dword(dev, 0xb0, reg_b0);
294  pci_write_config_byte(dev, 0xe1, reg_e1);
295 
296  smsc_fdc37m81x_init(0x3f0);
297  smsc_fdc37m81x_config_beg();
298  smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
299  SMSC_FDC37M81X_KBD);
300  smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
301  smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
302  smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
303  1);
304  smsc_fdc37m81x_config_end();
305 }
306 
307 static void __devinit quirk_slc90e66_ide(struct pci_dev *dev)
308 {
309  unsigned char dat;
310  int regs[2] = {0x41, 0x43};
311  int i;
312 
313  /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
314  pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
315  pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
316  printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat);
317  /* enable SMSC SLC90E66 IDE */
318  for (i = 0; i < ARRAY_SIZE(regs); i++) {
319  pci_read_config_byte(dev, regs[i], &dat);
320  pci_write_config_byte(dev, regs[i], dat | 0x80);
321  pci_read_config_byte(dev, regs[i], &dat);
322  printk(KERN_CONT " IDETIM%d %02x", i, dat);
323  }
324  pci_read_config_byte(dev, 0x5c, &dat);
325  /*
326  * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
327  *
328  * This line of code is intended to provide the user with a work
329  * around solution to the anomalies cited in SMSC's anomaly sheet
330  * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
331  *
332  * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
333  */
334  dat |= 0x01;
335  pci_write_config_byte(dev, regs[i], dat);
336  pci_read_config_byte(dev, 0x5c, &dat);
337  printk(KERN_CONT " REG5C %02x", dat);
338  printk(KERN_CONT "\n");
339 }
340 #endif /* CONFIG_TOSHIBA_FPCIB0 */
341 
342 static void __devinit tc35815_fixup(struct pci_dev *dev)
343 {
344  /* This device may have PM registers but not they are not suported. */
345  if (dev->pm_cap) {
346  dev_info(&dev->dev, "PM disabled\n");
347  dev->pm_cap = 0;
348  }
349 }
350 
351 static void __devinit final_fixup(struct pci_dev *dev)
352 {
353  unsigned char bist;
354 
355  /* Do build-in self test */
356  if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
357  (bist & PCI_BIST_CAPABLE)) {
358  unsigned long timeout;
359  pci_set_power_state(dev, PCI_D0);
360  printk(KERN_INFO "PCI: %s BIST...", pci_name(dev));
361  pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
362  timeout = jiffies + HZ * 2; /* timeout after 2 sec */
363  do {
364  pci_read_config_byte(dev, PCI_BIST, &bist);
365  if (time_after(jiffies, timeout))
366  break;
367  } while (bist & PCI_BIST_START);
368  if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
369  printk(KERN_CONT "failed. (0x%x)\n", bist);
370  else
371  printk(KERN_CONT "OK.\n");
372  }
373 }
374 
375 #ifdef CONFIG_TOSHIBA_FPCIB0
376 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
378  quirk_slc90e66_bridge);
379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
380  quirk_slc90e66_ide);
381 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
382  quirk_slc90e66_ide);
383 #endif
384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
385  PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
387  PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
388 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
389 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
390 
391 int pcibios_plat_dev_init(struct pci_dev *dev)
392 {
393  return 0;
394 }
395 
396 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
397 {
398  return txx9_board_vec->pci_map_irq(dev, slot, pin);
399 }
400 
401 char * (*txx9_board_pcibios_setup)(char *str) __initdata;
402 
403 char *__init txx9_pcibios_setup(char *str)
404 {
405  if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
406  return NULL;
407  if (!strcmp(str, "picmg")) {
408  /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
409  (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
410  txx9_pci_option |= TXX9_PCI_OPT_PICMG;
411  return NULL;
412  } else if (!strcmp(str, "nopicmg")) {
413  /* non-PICMG compliant backplane (TOSHIBA
414  RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
415  txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
416  return NULL;
417  } else if (!strncmp(str, "clk=", 4)) {
418  char *val = str + 4;
419  txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
420  if (strcmp(val, "33") == 0)
421  txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
422  else if (strcmp(val, "66") == 0)
423  txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
424  else /* "auto" */
425  txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
426  return NULL;
427  } else if (!strncmp(str, "err=", 4)) {
428  if (!strcmp(str + 4, "panic"))
429  txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
430  else if (!strcmp(str + 4, "ignore"))
431  txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
432  return NULL;
433  }
434  return str;
435 }
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