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irq.c
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1 /*
2  * Low-Level PCI Support for PC -- Routing of Interrupts
3  *
4  * (c) 1999--2000 Martin Mares <[email protected]>
5  */
6 
7 #include <linux/types.h>
8 #include <linux/kernel.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/dmi.h>
13 #include <linux/io.h>
14 #include <linux/smp.h>
15 #include <asm/io_apic.h>
16 #include <linux/irq.h>
17 #include <linux/acpi.h>
18 #include <asm/pci_x86.h>
19 
20 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
21 #define PIRQ_VERSION 0x0100
22 
23 static int broken_hp_bios_irq9;
24 static int acer_tm360_irqrouting;
25 
26 static struct irq_routing_table *pirq_table;
27 
28 static int pirq_enable_irq(struct pci_dev *dev);
29 
30 /*
31  * Never use: 0, 1, 2 (timer, keyboard, and cascade)
32  * Avoid using: 13, 14 and 15 (FP error and IDE).
33  * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
34  */
35 unsigned int pcibios_irq_mask = 0xfff8;
36 
37 static int pirq_penalty[16] = {
38  1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
39  0, 0, 0, 0, 1000, 100000, 100000, 100000
40 };
41 
42 struct irq_router {
43  char *name;
45  int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
46  int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
47  int new);
48 };
49 
52  int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
53 };
54 
55 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
57 
58 /*
59  * Check passed address for the PCI IRQ Routing Table signature
60  * and perform checksum verification.
61  */
62 
63 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
64 {
65  struct irq_routing_table *rt;
66  int i;
67  u8 sum;
68 
69  rt = (struct irq_routing_table *) addr;
70  if (rt->signature != PIRQ_SIGNATURE ||
71  rt->version != PIRQ_VERSION ||
72  rt->size % 16 ||
73  rt->size < sizeof(struct irq_routing_table))
74  return NULL;
75  sum = 0;
76  for (i = 0; i < rt->size; i++)
77  sum += addr[i];
78  if (!sum) {
79  DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
80  rt);
81  return rt;
82  }
83  return NULL;
84 }
85 
86 
87 
88 /*
89  * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
90  */
91 
92 static struct irq_routing_table * __init pirq_find_routing_table(void)
93 {
94  u8 *addr;
95  struct irq_routing_table *rt;
96 
97  if (pirq_table_addr) {
98  rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
99  if (rt)
100  return rt;
101  printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
102  }
103  for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
104  rt = pirq_check_routing_table(addr);
105  if (rt)
106  return rt;
107  }
108  return NULL;
109 }
110 
111 /*
112  * If we have a IRQ routing table, use it to search for peer host
113  * bridges. It's a gross hack, but since there are no other known
114  * ways how to get a list of buses, we have to go this way.
115  */
116 
117 static void __init pirq_peer_trick(void)
118 {
119  struct irq_routing_table *rt = pirq_table;
120  u8 busmap[256];
121  int i;
122  struct irq_info *e;
123 
124  memset(busmap, 0, sizeof(busmap));
125  for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
126  e = &rt->slots[i];
127 #ifdef DEBUG
128  {
129  int j;
130  DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
131  for (j = 0; j < 4; j++)
132  DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
133  DBG("\n");
134  }
135 #endif
136  busmap[e->bus] = 1;
137  }
138  for (i = 1; i < 256; i++) {
139  int node;
140  if (!busmap[i] || pci_find_bus(0, i))
141  continue;
142  node = get_mp_bus_to_node(i);
143  if (pci_scan_bus_on_node(i, &pci_root_ops, node))
144  printk(KERN_INFO "PCI: Discovered primary peer "
145  "bus %02x [IRQ]\n", i);
146  }
147  pcibios_last_bus = -1;
148 }
149 
150 /*
151  * Code for querying and setting of IRQ routes on various interrupt routers.
152  */
153 
154 void eisa_set_level_irq(unsigned int irq)
155 {
156  unsigned char mask = 1 << (irq & 7);
157  unsigned int port = 0x4d0 + (irq >> 3);
158  unsigned char val;
159  static u16 eisa_irq_mask;
160 
161  if (irq >= 16 || (1 << irq) & eisa_irq_mask)
162  return;
163 
164  eisa_irq_mask |= (1 << irq);
165  printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
166  val = inb(port);
167  if (!(val & mask)) {
168  DBG(KERN_DEBUG " -> edge");
169  outb(val | mask, port);
170  }
171 }
172 
173 /*
174  * Common IRQ routing practice: nibbles in config space,
175  * offset by some magic constant.
176  */
177 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
178 {
179  u8 x;
180  unsigned reg = offset + (nr >> 1);
181 
182  pci_read_config_byte(router, reg, &x);
183  return (nr & 1) ? (x >> 4) : (x & 0xf);
184 }
185 
186 static void write_config_nybble(struct pci_dev *router, unsigned offset,
187  unsigned nr, unsigned int val)
188 {
189  u8 x;
190  unsigned reg = offset + (nr >> 1);
191 
192  pci_read_config_byte(router, reg, &x);
193  x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
194  pci_write_config_byte(router, reg, x);
195 }
196 
197 /*
198  * ALI pirq entries are damn ugly, and completely undocumented.
199  * This has been figured out from pirq tables, and it's not a pretty
200  * picture.
201  */
202 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
203 {
204  static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
205 
206  WARN_ON_ONCE(pirq > 16);
207  return irqmap[read_config_nybble(router, 0x48, pirq-1)];
208 }
209 
210 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
211 {
212  static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
213  unsigned int val = irqmap[irq];
214 
215  WARN_ON_ONCE(pirq > 16);
216  if (val) {
217  write_config_nybble(router, 0x48, pirq-1, val);
218  return 1;
219  }
220  return 0;
221 }
222 
223 /*
224  * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
225  * just a pointer to the config space.
226  */
227 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
228 {
229  u8 x;
230 
231  pci_read_config_byte(router, pirq, &x);
232  return (x < 16) ? x : 0;
233 }
234 
235 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
236 {
237  pci_write_config_byte(router, pirq, irq);
238  return 1;
239 }
240 
241 /*
242  * The VIA pirq rules are nibble-based, like ALI,
243  * but without the ugly irq number munging.
244  * However, PIRQD is in the upper instead of lower 4 bits.
245  */
246 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
247 {
248  return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
249 }
250 
251 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
252 {
253  write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
254  return 1;
255 }
256 
257 /*
258  * The VIA pirq rules are nibble-based, like ALI,
259  * but without the ugly irq number munging.
260  * However, for 82C586, nibble map is different .
261  */
262 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
263 {
264  static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
265 
266  WARN_ON_ONCE(pirq > 5);
267  return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
268 }
269 
270 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
271 {
272  static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
273 
274  WARN_ON_ONCE(pirq > 5);
275  write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
276  return 1;
277 }
278 
279 /*
280  * ITE 8330G pirq rules are nibble-based
281  * FIXME: pirqmap may be { 1, 0, 3, 2 },
282  * 2+3 are both mapped to irq 9 on my system
283  */
284 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
285 {
286  static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
287 
288  WARN_ON_ONCE(pirq > 4);
289  return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
290 }
291 
292 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
293 {
294  static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
295 
296  WARN_ON_ONCE(pirq > 4);
297  write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
298  return 1;
299 }
300 
301 /*
302  * OPTI: high four bits are nibble pointer..
303  * I wonder what the low bits do?
304  */
305 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
306 {
307  return read_config_nybble(router, 0xb8, pirq >> 4);
308 }
309 
310 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
311 {
312  write_config_nybble(router, 0xb8, pirq >> 4, irq);
313  return 1;
314 }
315 
316 /*
317  * Cyrix: nibble offset 0x5C
318  * 0x5C bits 7:4 is INTB bits 3:0 is INTA
319  * 0x5D bits 7:4 is INTD bits 3:0 is INTC
320  */
321 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
322 {
323  return read_config_nybble(router, 0x5C, (pirq-1)^1);
324 }
325 
326 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
327 {
328  write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
329  return 1;
330 }
331 
332 /*
333  * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
334  * We have to deal with the following issues here:
335  * - vendors have different ideas about the meaning of link values
336  * - some onboard devices (integrated in the chipset) have special
337  * links and are thus routed differently (i.e. not via PCI INTA-INTD)
338  * - different revision of the router have a different layout for
339  * the routing registers, particularly for the onchip devices
340  *
341  * For all routing registers the common thing is we have one byte
342  * per routeable link which is defined as:
343  * bit 7 IRQ mapping enabled (0) or disabled (1)
344  * bits [6:4] reserved (sometimes used for onchip devices)
345  * bits [3:0] IRQ to map to
346  * allowed: 3-7, 9-12, 14-15
347  * reserved: 0, 1, 2, 8, 13
348  *
349  * The config-space registers located at 0x41/0x42/0x43/0x44 are
350  * always used to route the normal PCI INT A/B/C/D respectively.
351  * Apparently there are systems implementing PCI routing table using
352  * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
353  * We try our best to handle both link mappings.
354  *
355  * Currently (2003-05-21) it appears most SiS chipsets follow the
356  * definition of routing registers from the SiS-5595 southbridge.
357  * According to the SiS 5595 datasheets the revision id's of the
358  * router (ISA-bridge) should be 0x01 or 0xb0.
359  *
360  * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
361  * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
362  * They seem to work with the current routing code. However there is
363  * some concern because of the two USB-OHCI HCs (original SiS 5595
364  * had only one). YMMV.
365  *
366  * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
367  *
368  * 0x61: IDEIRQ:
369  * bits [6:5] must be written 01
370  * bit 4 channel-select primary (0), secondary (1)
371  *
372  * 0x62: USBIRQ:
373  * bit 6 OHCI function disabled (0), enabled (1)
374  *
375  * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
376  *
377  * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
378  *
379  * We support USBIRQ (in addition to INTA-INTD) and keep the
380  * IDE, ACPI and DAQ routing untouched as set by the BIOS.
381  *
382  * Currently the only reported exception is the new SiS 65x chipset
383  * which includes the SiS 69x southbridge. Here we have the 85C503
384  * router revision 0x04 and there are changes in the register layout
385  * mostly related to the different USB HCs with USB 2.0 support.
386  *
387  * Onchip routing for router rev-id 0x04 (try-and-error observation)
388  *
389  * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
390  * bit 6-4 are probably unused, not like 5595
391  */
392 
393 #define PIRQ_SIS_IRQ_MASK 0x0f
394 #define PIRQ_SIS_IRQ_DISABLE 0x80
395 #define PIRQ_SIS_USB_ENABLE 0x40
396 
397 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
398 {
399  u8 x;
400  int reg;
401 
402  reg = pirq;
403  if (reg >= 0x01 && reg <= 0x04)
404  reg += 0x40;
405  pci_read_config_byte(router, reg, &x);
406  return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
407 }
408 
409 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
410 {
411  u8 x;
412  int reg;
413 
414  reg = pirq;
415  if (reg >= 0x01 && reg <= 0x04)
416  reg += 0x40;
417  pci_read_config_byte(router, reg, &x);
419  x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
420  pci_write_config_byte(router, reg, x);
421  return 1;
422 }
423 
424 
425 /*
426  * VLSI: nibble offset 0x74 - educated guess due to routing table and
427  * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
428  * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
429  * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
430  * for the busbridge to the docking station.
431  */
432 
433 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
434 {
435  WARN_ON_ONCE(pirq >= 9);
436  if (pirq > 8) {
437  dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
438  return 0;
439  }
440  return read_config_nybble(router, 0x74, pirq-1);
441 }
442 
443 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
444 {
445  WARN_ON_ONCE(pirq >= 9);
446  if (pirq > 8) {
447  dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
448  return 0;
449  }
450  write_config_nybble(router, 0x74, pirq-1, irq);
451  return 1;
452 }
453 
454 /*
455  * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
456  * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
457  * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
458  * register is a straight binary coding of desired PIC IRQ (low nibble).
459  *
460  * The 'link' value in the PIRQ table is already in the correct format
461  * for the Index register. There are some special index values:
462  * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
463  * and 0x03 for SMBus.
464  */
465 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
466 {
467  outb(pirq, 0xc00);
468  return inb(0xc01) & 0xf;
469 }
470 
471 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
472  int pirq, int irq)
473 {
474  outb(pirq, 0xc00);
475  outb(irq, 0xc01);
476  return 1;
477 }
478 
479 /* Support for AMD756 PCI IRQ Routing
480  * Jhon H. Caicedo <[email protected]>
481  * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
482  * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
483  * The AMD756 pirq rules are nibble-based
484  * offset 0x56 0-3 PIRQA 4-7 PIRQB
485  * offset 0x57 0-3 PIRQC 4-7 PIRQD
486  */
487 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
488 {
489  u8 irq;
490  irq = 0;
491  if (pirq <= 4)
492  irq = read_config_nybble(router, 0x56, pirq - 1);
493  dev_info(&dev->dev,
494  "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
495  dev->vendor, dev->device, pirq, irq);
496  return irq;
497 }
498 
499 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
500 {
501  dev_info(&dev->dev,
502  "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
503  dev->vendor, dev->device, pirq, irq);
504  if (pirq <= 4)
505  write_config_nybble(router, 0x56, pirq - 1, irq);
506  return 1;
507 }
508 
509 /*
510  * PicoPower PT86C523
511  */
512 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
513 {
514  outb(0x10 + ((pirq - 1) >> 1), 0x24);
515  return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
516 }
517 
518 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
519  int irq)
520 {
521  unsigned int x;
522  outb(0x10 + ((pirq - 1) >> 1), 0x24);
523  x = inb(0x26);
524  x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
525  outb(x, 0x26);
526  return 1;
527 }
528 
529 #ifdef CONFIG_PCI_BIOS
530 
531 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
532 {
533  struct pci_dev *bridge;
534  int pin = pci_get_interrupt_pin(dev, &bridge);
535  return pcibios_set_irq_routing(bridge, pin - 1, irq);
536 }
537 
538 #endif
539 
540 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
541 {
542  static struct pci_device_id __initdata pirq_440gx[] = {
545  { },
546  };
547 
548  /* 440GX has a proprietary PIRQ router -- don't use it */
549  if (pci_dev_present(pirq_440gx))
550  return 0;
551 
552  switch (device) {
594  r->name = "PIIX/ICH";
595  r->get = pirq_piix_get;
596  r->set = pirq_piix_set;
597  return 1;
598  }
599 
604  || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
608  r->name = "PIIX/ICH";
609  r->get = pirq_piix_get;
610  r->set = pirq_piix_set;
611  return 1;
612  }
613 
614  return 0;
615 }
616 
617 static __init int via_router_probe(struct irq_router *r,
618  struct pci_dev *router, u16 device)
619 {
620  /* FIXME: We should move some of the quirk fixup stuff here */
621 
622  /*
623  * workarounds for some buggy BIOSes
624  */
625  if (device == PCI_DEVICE_ID_VIA_82C586_0) {
626  switch (router->device) {
628  /*
629  * Asus k7m bios wrongly reports 82C686A
630  * as 586-compatible
631  */
632  device = PCI_DEVICE_ID_VIA_82C686;
633  break;
639  device = PCI_DEVICE_ID_VIA_8235;
640  break;
646  device = PCI_DEVICE_ID_VIA_8237;
647  break;
648  }
649  }
650 
651  switch (device) {
653  r->name = "VIA";
654  r->get = pirq_via586_get;
655  r->set = pirq_via586_set;
656  return 1;
663  /* FIXME: add new ones for 8233/5 */
664  r->name = "VIA";
665  r->get = pirq_via_get;
666  r->set = pirq_via_set;
667  return 1;
668  }
669  return 0;
670 }
671 
672 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
673 {
674  switch (device) {
676  r->name = "VLSI 82C534";
677  r->get = pirq_vlsi_get;
678  r->set = pirq_vlsi_set;
679  return 1;
680  }
681  return 0;
682 }
683 
684 
685 static __init int serverworks_router_probe(struct irq_router *r,
686  struct pci_dev *router, u16 device)
687 {
688  switch (device) {
691  r->name = "ServerWorks";
692  r->get = pirq_serverworks_get;
693  r->set = pirq_serverworks_set;
694  return 1;
695  }
696  return 0;
697 }
698 
699 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
700 {
701  if (device != PCI_DEVICE_ID_SI_503)
702  return 0;
703 
704  r->name = "SIS";
705  r->get = pirq_sis_get;
706  r->set = pirq_sis_set;
707  return 1;
708 }
709 
710 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
711 {
712  switch (device) {
714  r->name = "NatSemi";
715  r->get = pirq_cyrix_get;
716  r->set = pirq_cyrix_set;
717  return 1;
718  }
719  return 0;
720 }
721 
722 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
723 {
724  switch (device) {
726  r->name = "OPTI";
727  r->get = pirq_opti_get;
728  r->set = pirq_opti_set;
729  return 1;
730  }
731  return 0;
732 }
733 
734 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
735 {
736  switch (device) {
738  r->name = "ITE";
739  r->get = pirq_ite_get;
740  r->set = pirq_ite_set;
741  return 1;
742  }
743  return 0;
744 }
745 
746 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
747 {
748  switch (device) {
751  r->name = "ALI";
752  r->get = pirq_ali_get;
753  r->set = pirq_ali_set;
754  return 1;
755  }
756  return 0;
757 }
758 
759 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
760 {
761  switch (device) {
763  r->name = "AMD756";
764  break;
766  r->name = "AMD766";
767  break;
769  r->name = "AMD768";
770  break;
771  default:
772  return 0;
773  }
774  r->get = pirq_amd756_get;
775  r->set = pirq_amd756_set;
776  return 1;
777 }
778 
779 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
780 {
781  switch (device) {
783  r->name = "PicoPower PT86C523";
784  r->get = pirq_pico_get;
785  r->set = pirq_pico_set;
786  return 1;
787 
789  r->name = "PicoPower PT86C523 rev. BB+";
790  r->get = pirq_pico_get;
791  r->set = pirq_pico_set;
792  return 1;
793  }
794  return 0;
795 }
796 
797 static __initdata struct irq_router_handler pirq_routers[] = {
798  { PCI_VENDOR_ID_INTEL, intel_router_probe },
799  { PCI_VENDOR_ID_AL, ali_router_probe },
800  { PCI_VENDOR_ID_ITE, ite_router_probe },
801  { PCI_VENDOR_ID_VIA, via_router_probe },
802  { PCI_VENDOR_ID_OPTI, opti_router_probe },
803  { PCI_VENDOR_ID_SI, sis_router_probe },
804  { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
805  { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
806  { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
807  { PCI_VENDOR_ID_AMD, amd_router_probe },
808  { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
809  /* Someone with docs needs to add the ATI Radeon IGP */
810  { 0, NULL }
811 };
812 static struct irq_router pirq_router;
813 static struct pci_dev *pirq_router_dev;
814 
815 
816 /*
817  * FIXME: should we have an option to say "generic for
818  * chipset" ?
819  */
820 
821 static void __init pirq_find_router(struct irq_router *r)
822 {
823  struct irq_routing_table *rt = pirq_table;
824  struct irq_router_handler *h;
825 
826 #ifdef CONFIG_PCI_BIOS
827  if (!rt->signature) {
828  printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
829  r->set = pirq_bios_set;
830  r->name = "BIOS";
831  return;
832  }
833 #endif
834 
835  /* Default unless a driver reloads it */
836  r->name = "default";
837  r->get = NULL;
838  r->set = NULL;
839 
840  DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
841  rt->rtr_vendor, rt->rtr_device);
842 
843  pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn);
844  if (!pirq_router_dev) {
845  DBG(KERN_DEBUG "PCI: Interrupt router not found at "
846  "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
847  return;
848  }
849 
850  for (h = pirq_routers; h->vendor; h++) {
851  /* First look for a router match */
852  if (rt->rtr_vendor == h->vendor &&
853  h->probe(r, pirq_router_dev, rt->rtr_device))
854  break;
855  /* Fall back to a device match */
856  if (pirq_router_dev->vendor == h->vendor &&
857  h->probe(r, pirq_router_dev, pirq_router_dev->device))
858  break;
859  }
860  dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
861  pirq_router.name,
862  pirq_router_dev->vendor, pirq_router_dev->device);
863 
864  /* The device remains referenced for the kernel lifetime */
865 }
866 
867 static struct irq_info *pirq_get_info(struct pci_dev *dev)
868 {
869  struct irq_routing_table *rt = pirq_table;
870  int entries = (rt->size - sizeof(struct irq_routing_table)) /
872  struct irq_info *info;
873 
874  for (info = rt->slots; entries--; info++)
875  if (info->bus == dev->bus->number &&
876  PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
877  return info;
878  return NULL;
879 }
880 
881 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
882 {
883  u8 pin;
884  struct irq_info *info;
885  int i, pirq, newirq;
886  int irq = 0;
887  u32 mask;
888  struct irq_router *r = &pirq_router;
889  struct pci_dev *dev2 = NULL;
890  char *msg = NULL;
891 
892  /* Find IRQ pin */
893  pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
894  if (!pin) {
895  dev_dbg(&dev->dev, "no interrupt pin\n");
896  return 0;
897  }
898 
900  return 0;
901 
902  /* Find IRQ routing entry */
903 
904  if (!pirq_table)
905  return 0;
906 
907  info = pirq_get_info(dev);
908  if (!info) {
909  dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
910  'A' + pin - 1);
911  return 0;
912  }
913  pirq = info->irq[pin - 1].link;
914  mask = info->irq[pin - 1].bitmap;
915  if (!pirq) {
916  dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
917  return 0;
918  }
919  dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
920  'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
921  mask &= pcibios_irq_mask;
922 
923  /* Work around broken HP Pavilion Notebooks which assign USB to
924  IRQ 9 even though it is actually wired to IRQ 11 */
925 
926  if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
927  dev->irq = 11;
928  pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
929  r->set(pirq_router_dev, dev, pirq, 11);
930  }
931 
932  /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
933  if (acer_tm360_irqrouting && dev->irq == 11 &&
934  dev->vendor == PCI_VENDOR_ID_O2) {
935  pirq = 0x68;
936  mask = 0x400;
937  dev->irq = r->get(pirq_router_dev, dev, pirq);
938  pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
939  }
940 
941  /*
942  * Find the best IRQ to assign: use the one
943  * reported by the device if possible.
944  */
945  newirq = dev->irq;
946  if (newirq && !((1 << newirq) & mask)) {
948  newirq = 0;
949  else
950  dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
951  "%#x; try pci=usepirqmask\n", newirq, mask);
952  }
953  if (!newirq && assign) {
954  for (i = 0; i < 16; i++) {
955  if (!(mask & (1 << i)))
956  continue;
957  if (pirq_penalty[i] < pirq_penalty[newirq] &&
959  newirq = i;
960  }
961  }
962  dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
963 
964  /* Check if it is hardcoded */
965  if ((pirq & 0xf0) == 0xf0) {
966  irq = pirq & 0xf;
967  msg = "hardcoded";
968  } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
969  ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
970  msg = "found";
971  eisa_set_level_irq(irq);
972  } else if (newirq && r->set &&
973  (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
974  if (r->set(pirq_router_dev, dev, pirq, newirq)) {
975  eisa_set_level_irq(newirq);
976  msg = "assigned";
977  irq = newirq;
978  }
979  }
980 
981  if (!irq) {
982  if (newirq && mask == (1 << newirq)) {
983  msg = "guessed";
984  irq = newirq;
985  } else {
986  dev_dbg(&dev->dev, "can't route interrupt\n");
987  return 0;
988  }
989  }
990  dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
991 
992  /* Update IRQ for all devices with the same pirq value */
993  for_each_pci_dev(dev2) {
994  pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
995  if (!pin)
996  continue;
997 
998  info = pirq_get_info(dev2);
999  if (!info)
1000  continue;
1001  if (info->irq[pin - 1].link == pirq) {
1002  /*
1003  * We refuse to override the dev->irq
1004  * information. Give a warning!
1005  */
1006  if (dev2->irq && dev2->irq != irq && \
1007  (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1008  ((1 << dev2->irq) & mask))) {
1009 #ifndef CONFIG_PCI_MSI
1010  dev_info(&dev2->dev, "IRQ routing conflict: "
1011  "have IRQ %d, want IRQ %d\n",
1012  dev2->irq, irq);
1013 #endif
1014  continue;
1015  }
1016  dev2->irq = irq;
1017  pirq_penalty[irq]++;
1018  if (dev != dev2)
1019  dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1020  irq, pci_name(dev2));
1021  }
1022  }
1023  return 1;
1024 }
1025 
1027 {
1028  struct pci_dev *dev = NULL;
1029  u8 pin;
1030 
1031  DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1032  for_each_pci_dev(dev) {
1033  /*
1034  * If the BIOS has set an out of range IRQ number, just
1035  * ignore it. Also keep track of which IRQ's are
1036  * already in use.
1037  */
1038  if (dev->irq >= 16) {
1039  dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1040  dev->irq = 0;
1041  }
1042  /*
1043  * If the IRQ is already assigned to a PCI device,
1044  * ignore its ISA use penalty
1045  */
1046  if (pirq_penalty[dev->irq] >= 100 &&
1047  pirq_penalty[dev->irq] < 100000)
1048  pirq_penalty[dev->irq] = 0;
1049  pirq_penalty[dev->irq]++;
1050  }
1051 
1053  return;
1054 
1055  dev = NULL;
1056  for_each_pci_dev(dev) {
1057  pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1058  if (!pin)
1059  continue;
1060 
1061  /*
1062  * Still no IRQ? Try to lookup one...
1063  */
1064  if (!dev->irq)
1065  pcibios_lookup_irq(dev, 0);
1066  }
1067 }
1068 
1069 /*
1070  * Work around broken HP Pavilion Notebooks which assign USB to
1071  * IRQ 9 even though it is actually wired to IRQ 11
1072  */
1073 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1074 {
1075  if (!broken_hp_bios_irq9) {
1076  broken_hp_bios_irq9 = 1;
1077  printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1078  d->ident);
1079  }
1080  return 0;
1081 }
1082 
1083 /*
1084  * Work around broken Acer TravelMate 360 Notebooks which assign
1085  * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1086  */
1087 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1088 {
1089  if (!acer_tm360_irqrouting) {
1090  acer_tm360_irqrouting = 1;
1091  printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1092  d->ident);
1093  }
1094  return 0;
1095 }
1096 
1097 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1098  {
1099  .callback = fix_broken_hp_bios_irq9,
1100  .ident = "HP Pavilion N5400 Series Laptop",
1101  .matches = {
1102  DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1103  DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1105  "HP Pavilion Notebook Model GE"),
1106  DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1107  },
1108  },
1109  {
1110  .callback = fix_acer_tm360_irqrouting,
1111  .ident = "Acer TravelMate 36x Laptop",
1112  .matches = {
1113  DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1114  DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1115  },
1116  },
1117  { }
1118 };
1119 
1121 {
1122  DBG(KERN_DEBUG "PCI: IRQ init\n");
1123 
1124  if (raw_pci_ops == NULL)
1125  return;
1126 
1127  dmi_check_system(pciirq_dmi_table);
1128 
1129  pirq_table = pirq_find_routing_table();
1130 
1131 #ifdef CONFIG_PCI_BIOS
1132  if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
1133  pirq_table = pcibios_get_irq_routing_table();
1134 #endif
1135  if (pirq_table) {
1136  pirq_peer_trick();
1137  pirq_find_router(&pirq_router);
1138  if (pirq_table->exclusive_irqs) {
1139  int i;
1140  for (i = 0; i < 16; i++)
1141  if (!(pirq_table->exclusive_irqs & (1 << i)))
1142  pirq_penalty[i] += 100;
1143  }
1144  /*
1145  * If we're using the I/O APIC, avoid using the PCI IRQ
1146  * routing table
1147  */
1149  pirq_table = NULL;
1150  }
1151 
1152  x86_init.pci.fixup_irqs();
1153 
1155  struct pci_dev *dev = NULL;
1156  /*
1157  * PCI IRQ routing is set up by pci_enable_device(), but we
1158  * also do it here in case there are still broken drivers that
1159  * don't use pci_enable_device().
1160  */
1161  printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1162  for_each_pci_dev(dev)
1163  pirq_enable_irq(dev);
1164  }
1165 }
1166 
1167 static void pirq_penalize_isa_irq(int irq, int active)
1168 {
1169  /*
1170  * If any ISAPnP device reports an IRQ in its list of possible
1171  * IRQ's, we try to avoid assigning it to PCI devices.
1172  */
1173  if (irq < 16) {
1174  if (active)
1175  pirq_penalty[irq] += 1000;
1176  else
1177  pirq_penalty[irq] += 100;
1178  }
1179 }
1180 
1181 void pcibios_penalize_isa_irq(int irq, int active)
1182 {
1183 #ifdef CONFIG_ACPI
1184  if (!acpi_noirq)
1185  acpi_penalize_isa_irq(irq, active);
1186  else
1187 #endif
1188  pirq_penalize_isa_irq(irq, active);
1189 }
1190 
1191 static int pirq_enable_irq(struct pci_dev *dev)
1192 {
1193  u8 pin;
1194 
1195  pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1196  if (pin && !pcibios_lookup_irq(dev, 1)) {
1197  char *msg = "";
1198 
1199  if (!io_apic_assign_pci_irqs && dev->irq)
1200  return 0;
1201 
1203 #ifdef CONFIG_X86_IO_APIC
1204  struct pci_dev *temp_dev;
1205  int irq;
1206  struct io_apic_irq_attr irq_attr;
1207 
1208  irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1209  PCI_SLOT(dev->devfn),
1210  pin - 1, &irq_attr);
1211  /*
1212  * Busses behind bridges are typically not listed in the MP-table.
1213  * In this case we have to look up the IRQ based on the parent bus,
1214  * parent slot, and pin number. The SMP code detects such bridged
1215  * busses itself so we should get into this branch reliably.
1216  */
1217  temp_dev = dev;
1218  while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1219  struct pci_dev *bridge = dev->bus->self;
1220 
1221  pin = pci_swizzle_interrupt_pin(dev, pin);
1222  irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1223  PCI_SLOT(bridge->devfn),
1224  pin - 1, &irq_attr);
1225  if (irq >= 0)
1226  dev_warn(&dev->dev, "using bridge %s "
1227  "INT %c to get IRQ %d\n",
1228  pci_name(bridge), 'A' + pin - 1,
1229  irq);
1230  dev = bridge;
1231  }
1232  dev = temp_dev;
1233  if (irq >= 0) {
1234  io_apic_set_pci_routing(&dev->dev, irq,
1235  &irq_attr);
1236  dev->irq = irq;
1237  dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1238  "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1239  return 0;
1240  } else
1241  msg = "; probably buggy MP table";
1242 #endif
1243  } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1244  msg = "";
1245  else
1246  msg = "; please try using pci=biosirq";
1247 
1248  /*
1249  * With IDE legacy devices the IRQ lookup failure is not
1250  * a problem..
1251  */
1252  if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1253  !(dev->class & 0x5))
1254  return 0;
1255 
1256  dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1257  'A' + pin - 1, msg);
1258  }
1259  return 0;
1260 }